[PATCH] D151397: [3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub

craig.topper added a comment. Do we need to check the immediate range in SemaChecking.cpp? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151397/new/ https://reviews.llvm.org/D151397 ___ cfe-commits maili

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152070/new/ https://reviews.llvm.org/D152070 ___

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

craig.topper added inline comments. Comment at: clang/lib/Support/RISCVVIntrinsicUtils.cpp:730 } + case VectorTypeModifier::Tuple3: { +IsTuple = true; Could maybe merge these into a single case body and use math to compute NF? Repository: rG LLVM Gith

[PATCH] D152071: [3/11][Clang][RISCV] Expand all variants for unit stride segment load

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152071/new/ https://reviews.llvm.org/D152071 ___

[PATCH] D151730: [RISCV] Support target attribute for function

craig.topper added inline comments. Comment at: clang/include/clang/Basic/TargetInfo.h:1401 +return getTriple().isX86() || getTriple().isAArch64() || + getTriple().isRISCV(); } Is this needed for target attribute? The description to me reads like

[PATCH] D152627: [RISCV] Change the immediate argument to Zvk intrinsics/builtins to i8.

craig.topper created this revision. craig.topper added reviewers: asb, reames, kito-cheng, VincentWu, ksyx, achieveartificialintelligence. Herald added subscribers: jobnoorman, luke, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruc

[PATCH] D152628: [RISCV] Add __builtin_riscv_zip/unzip for Zbkb to match gcc.

craig.topper created this revision. craig.topper added reviewers: asb, VincentWu, kito-cheng. Herald added subscribers: jobnoorman, luke, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D152072: [4/11][Clang][RISCV] Expand all variants for unit stride segment store

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152072/new/ https://reviews.llvm.org/D152072 ___

[PATCH] D152073: [5/11][Clang][RISCV] Expand all variants for unit stride fault-first segment load

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152073/new/ https://reviews.llvm.org/D152073 ___

[PATCH] D152117: [RISC-V] Zvk update to 0.9.7, Zvknc/Zvksc

This revision was automatically updated to reflect the committed changes. Closed by commit rGc5a88fe3d071: [RISC-V] Zvk update to 0.9.7, Zvknc/Zvksc (authored by ego, committed by craig.topper). Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github M

[PATCH] D152074: [6/11][Clang][RISCV] Expand all variants for strided segment load

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152074/new/ https://reviews.llvm.org/D152074 ___

[PATCH] D152075: [7/11][Clang][RISCV] Expand all variants for strided segment store

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152075/new/ https://reviews.llvm.org/D152075 ___

[PATCH] D152076: [8/11][Clang][RISCV] Expand all variants for indexed strided segment load

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152076/new/ https://reviews.llvm.org/D152076 ___

[PATCH] D152077: [9/11][Clang][RISCV] Expand all variants for indexed strided segment store

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152077/new/ https://reviews.llvm.org/D152077 ___

[PATCH] D152078: [10/11][Clang][RISCV] Expand all variants for vget on tuple types

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152078/new/ https://reviews.llvm.org/D152078 ___

[PATCH] D152079: [11/11][Clang][RISCV] Expand all variants for vset on tuple types

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152079/new/ https://reviews.llvm.org/D152079 ___

[PATCH] D152627: [RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2f2af2d01763: [RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32. (authored by craig.topper). Repository: rG LLVM Git

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp:105 + +BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRMImm)) +.addImm(FRMImm); Don't we need to restore the original FRM value after t

[PATCH] D151397: [3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. Herald added a subscriber: wangpc. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151397/new/ https://reviews.llvm.org/D151397

[PATCH] D152879: [1/2][RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu

craig.topper added a comment. Herald added a subscriber: wangpc. SemaChecking.cpp? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152879/new/ https://reviews.llvm.org/D152879 ___ cfe-commits mailing list

[PATCH] D152889: [2/2][RISCV] Model vxrm control for vsadd, vsaddu, vssub, and vssubu

craig.topper added a comment. SemaChecking.cpp? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152889/new/ https://reviews.llvm.org/D152889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://

[PATCH] D152889: [2/2][RISCV] Model vxrm control for vsadd, vsaddu, vssub, and vssubu

craig.topper added a comment. These instructions don't read vxrm why do they need to change? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152889/new/ https://reviews.llvm.org/D152889 ___ cfe-commits mai

[PATCH] D152879: [RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:697 +: DefaultAttrsIntrinsic<[llvm_anyvector_ty], +[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty, + LLVMScalarOrSameVectorWidth<0, llvm_i1_t

[PATCH] D152879: [RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152879/new/ https://reviews.llvm.org/D152879 ___

[PATCH] D152879: [RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2269 + +IntrinsicTypes = {ResultType, Ops[Offset]->getType(), Ops[Offset + 1]->getType(), + Ops.back()->getType()}; I think we if we used `LLVMTrun

[PATCH] D152879: [RISCV] Model vxrm control for vsmul, vssra, vssrl, vnclip, and vnclipu

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2269 + +IntrinsicTypes = {ResultType, Ops[Offset]->getType(), Ops[Offset + 1]->getType(), + Ops.back()->getType()}; craig.topper wrote: > I think w

[PATCH] D153161: [RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.

craig.topper created this revision. craig.topper added reviewers: reames, jrtc27, asb, VincentWu. Herald added subscribers: jobnoorman, luke, vkmr, frasercrmck, jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01

[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

craig.topper created this revision. craig.topper added reviewers: jrtc27, asb, kito-cheng, wangpc, reames. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added a comment. In D138807#3962417 , @craig.topper wrote: > Anything that uses OP-P needs to have a DecoderNamespace assigned and > RISCVDisassembler::getInstruction will need to lookup that table when V/Zve > is enabled. Otherwise we wil

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; Shouldn't this also need Feature32B

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:208 +} \ No newline at end of file Add new line Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.ll

[PATCH] D139025: [NFC][RISCV] Extract utility to calculate value through MajorVersion and MinorVersion

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. Herald added a subscriber: StephenFan. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139025/new/ https://reviews.llvm.org/D1390

[PATCH] D139387: [Clang] Support policy function for all vector segment load.

craig.topper added a comment. Title is not clear this is NFC and only adding tests Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139387/new/ https://reviews.llvm.org/D139387 ___ cfe-commits mailing list

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:637 +def : ProcessorModel<"scr1-min", SCR1Model, + [FeatureRV32E, FeatureStdExtC], + [TuneNoDefaultUnroll]>; dnpetrov-sc wrote: > craig.topper w

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827 +{{"zvkb"}, {ImpliedExtsZve64x}}, +{{"zvkg"}, {ImpliedExtsZve32x}}, +{{"zvknha"}, {ImpliedExtsZve32x}}, ego wrote: > What is the reasoning between 32 vs 64 for those

[PATCH] D139627: clang/X86: Don't emit "min-legal-vector-width"="0"

craig.topper added a comment. The attribute is supposed to tell the backend if there were any vectors used in the C source code and how big they were. A value of 0 means the code didn't contain any vectors. The backend assumes lack of the attributes means the IR didn't come from clang and can'

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper added a comment. Should the names be prefixed with "syntacore-". I assume there could be an SCR2, etc. in the future? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302

[PATCH] D139627: clang/X86: Don't emit "min-legal-vector-width"="0"

craig.topper added a comment. In D139627#3982349 , @jdoerfert wrote: > Isn't this (inherently) X86 specific? Yes it is. We could qualify the attribute emission with the targeting being X86? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139627/n

[PATCH] D139387: [NFC][Clang] Add missing test cases for segment load

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139387/new/ https://reviews.llvm.org/D139387 ___ cfe-commits mailing list cfe-commits

[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139302/new/ https://reviews.llvm.org/D139302 ___

[PATCH] D139701: [Clang] Don't emit "min-legal-vector-width"="0" for AMDGPU

craig.topper added a comment. I really think only X86 is using this. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139701/new/ https://reviews.llvm.org/D139701 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D139627: clang/X86: Don't emit "min-legal-vector-width"="0"

craig.topper added a comment. In D139627#3993440 , @arsenm wrote: > In D139627#3983718 , @pengfei wrote: > >>> It also doesn't mean that, because the IR doesn't have to be consistent >>> with the attribute. The I

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

craig.topper added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:105 + : TU(_TU), TA(_TA), MU(_MU), MA(_MA) {} + Policy(bool _TU, bool _TA, bool _MU, bool _MA, bool _IntrinsicWithoutMU) + : TU(_TU), TA(_TA), MU(_MU), MA(_MA), -

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

craig.topper added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:141 +// Just for maintain the old order for quick test. +return std::tie(this->MU, this->MA, this->TA, this->TU) < + std::tie(Other.MU, Other.MA, Other.TA, Other.T

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

craig.topper added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:131 + bool operator==(const Policy &Other) const { +return this->PolicyNone == Other.PolicyNone && this->TU == Other.TU && + this->TA == Other.TA && this->MU == Other

[PATCH] D139701: [Clang] Don't emit "min-legal-vector-width"="0" for AMDGPU

craig.topper added a comment. In D139701#4003209 , @pengfei wrote: > In D139701#3993131 , @craig.topper > wrote: > >> I really think only X86 is using this. > > I'm still not sure of that. Please see the diff in

[PATCH] D28018: AMD family 17h (znver1) enablement

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D28018 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D31034: [X86][AVX512][Clang][Intrinsics] Adding missing intrinsics to Clang .

craig.topper added inline comments. Comment at: lib/Headers/avx512fintrin.h:9633 static __inline __m512i __DEFAULT_FN_ATTRS +_mm512_set_epi8 (char e63, char e62, char e61, char e60, char e59, +char e58, char e57, char e56, char e55, char e54, char e53, char e52,

[PATCH] D31034: [X86][AVX512][Clang][Intrinsics] Adding missing intrinsics to Clang .

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D31034 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D31155: [X86][AVX512] Add _mm512_cvtsd_f64 and _mm512_cvtss_f32 intrinsics (PR32305)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D31155 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D31394: [X86][Clang] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into generic intrinsics.

craig.topper added a comment. Y Comment at: lib/CodeGen/CGBuiltin.cpp:7176 + return CGF.Builder.CreateSExt( + Mask, llvm::VectorType::get(IT, NumberOfElements), "vpmovm2"); +} Why can't we just use DstTy here to create the SExt? https://reviews.llvm.org

[PATCH] D31394: [X86][Clang] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into generic intrinsics.

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:7176 + return CGF.Builder.CreateSExt( + Mask, llvm::VectorType::get(IT, NumberOfElements), "vpmovm2"); +} m_zuckerman wrote: > craig.topper wrote: > > Why can't we just use DstTy here

[PATCH] D31394: [X86][Clang] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into generic intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D31394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D30922: [Builtins] Synchronize the definition of fma/fmaf/fmal in Builtins.def with the implementation in CGBuiltins.cpp

craig.topper added a comment. Ping https://reviews.llvm.org/D30922 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D31766: [Clang][X86][SSE] Update MOVNTDQA non-temporal loads to generic implementation

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D31766 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D31996: Make Gentoo GNU GCC Config override whitespace tolerant

craig.topper added inline comments. Comment at: lib/Driver/ToolChains/Gnu.cpp:2176 for (StringRef Line : Lines) { + StringRef TrimLine = Line.trim(); // CURRENT=triple-version Can we just do Line = Line.trim() so we won't have an extra StringRe

[PATCH] D29386: Clzero flag addition and inclusion under znver1

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM, but i'll make some additional testing changes before committing it. -Add __CLZERO__ checks to test/Preprocessor/predefined-arch-macros.c for znver1 -Add command line testing t

[PATCH] D34842: [X86] Add RDRND to Goldmont. Add MOVBE to all Atom CPUs

craig.topper created this revision. This adds to RDNRND to Goldmont as I believe it has that feature in addition to RDSEED. I don't know how to test the MOVBE part since we don't have a __MOVBE__ macro nor do we need one. The backend will already infer the feature from the CPU name. We do have

[PATCH] D34842: [X86] Add RDRND to Goldmont. Add MOVBE to all Atom CPUs

craig.topper added a comment. There's a separate review for X86.d https://reviews.llvm.org/D34828 https://reviews.llvm.org/D34842 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D35184: X86 Intrinsics: _bit_scan_forward should not be under #ifdef __RDRND__

craig.topper added inline comments. Comment at: lib/Headers/immintrin.h:230 static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd"))) _rdrand64_step(unsigned long long *__p) { Looks like we now aren't removing rdrand64_step. S

[PATCH] D35184: X86 Intrinsics: _bit_scan_forward should not be under #ifdef __RDRND__

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D35184 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D35449: [X86] Implement __builtin_cpu_is

craig.topper created this revision. This patch adds support for __builtin_cpu_is. I've tried to match the strings supported to the latest version of gcc. I've only tested this on my Macbook so far so I'd appreciate if others would test it. An AMD system would be great. https://reviews.llvm.or

[PATCH] D35449: [X86] Implement __builtin_cpu_is

craig.topper added a comment. I think gcc supports __builtin_cpu_supports and __builtin_cpu_is for non-x86. We already have an x86 only implementation of __builtin_cpu_supports so I did the same here. https://reviews.llvm.org/D35449 ___ cfe-commit

[PATCH] D35449: [X86] Implement __builtin_cpu_is

craig.topper added a comment. I'm considering making validateCpuIs return a std::pair with the appropriate value and a tag that indicates invalid/vendor/type/subtype. This way we can remove the target based string decoding from CodeGen by reusing the validate function(with a better name). Sema

[PATCH] D35572: Add isValidCPUName and isValidFeature to TargetInfo

craig.topper added inline comments. Comment at: lib/Basic/Targets.cpp:2931 + + // Fallthrough +case CK_Nocona: Use LLVM_FALLTHROUGH? https://reviews.llvm.org/D35572 ___ cfe-commits mailing list cfe-commits

[PATCH] D35701: Break up Targets.cpp into a header/impl pair per target type[NFCI]

craig.topper added a comment. Just review blank lines between every function. I'm too lazy to keep marking them. Comment at: lib/Basic/Targets/AArch64.cpp:20 +using namespace clang::targets; +const char *const AArch64TargetInfo::GCCRegNames[] = { +// 32-bit Integer registe

[PATCH] D35701: Break up Targets.cpp into a header/impl pair per target type[NFCI]

craig.topper added a comment. I think we should drop "using namespace llvm;" from the cpp files. clang doesn't usually do that except in codegen and it doesn't look like it was required in the original Targets.cpp. https://reviews.llvm.org/D35701

[PATCH] D35701: Break up Targets.cpp into a header/impl pair per target type[NFCI]

craig.topper added inline comments. Comment at: lib/Basic/Targets/OSTargets.h:13 + +//===--===// +// Defines specific to certain operating systems. This comment seems somewhat redundant with the

[PATCH] D35701: Break up Targets.cpp into a header/impl pair per target type[NFCI]

craig.topper added a comment. Please recheck all the cpp file headers. Many of them aren't 80 columns and they should probably mention the target the way the header comments do. Right now it looks like a copy and paste from Targets.cpp with only the file name changed. Clang format seems to hav

[PATCH] D35701: Break up Targets.cpp into a header/impl pair per target type[NFCI]

craig.topper added a comment. LGTM https://reviews.llvm.org/D35701 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41523: xmmintrin.h documentation fixes and updates

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D41523 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D42154: Don't generate inline atomics for i386/i486

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.h:472 +CPUKind Kind = getCPUKind(Opts.CPU); +if (Kind >= CK_i586 || Kind == CK_Generic) + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; efriedma wrote: > What exactly does "CK

[PATCH] D42154: Don't generate inline atomics for i386/i486

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.h:472 +CPUKind Kind = getCPUKind(Opts.CPU); +if (Kind >= CK_i586 || Kind == CK_Generic) + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; craig.topper wrote: > efriedma wrote: >

[PATCH] D42154: Don't generate inline atomics for i386/i486

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.h:472 +CPUKind Kind = getCPUKind(Opts.CPU); +if (Kind >= CK_i586 || Kind == CK_Generic) + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; wmi wrote: > wmi wrote: > > craig.toppe

[PATCH] D42272: [X86] Add rdpid command line option and intrinsics.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, zvi, AndreiGrischenko. This patch adds -mrdpid/-mno-rdpid and the rdpid intrinsic. The corresponding LLVM commit has already been made. https://reviews.llvm.org/D42272 Files: include/clang/Basic/BuiltinsX86.de

[PATCH] D42272: [X86] Add rdpid command line option and intrinsics.

craig.topper updated this revision to Diff 130670. craig.topper added a comment. Add doxygen comment https://reviews.llvm.org/D42272 Files: include/clang/Basic/BuiltinsX86.def include/clang/Driver/Options.td lib/Basic/Targets/X86.cpp lib/Basic/Targets/X86.h lib/Headers/immintrin.h t

[PATCH] D30834: [x86] these aren't the undefs you're looking for (PR32176)

craig.topper added a comment. Have you ran the tests all the way through to assembly and made sure we don't regress? If we do regress, I wouldn't hold up fixing this, but we should at least have bugs for what breaks. Comment at: lib/CodeGen/CGBuiltin.cpp:7384 case X86::BI_

[PATCH] D30922: [Builtins] Synchronize the definition of fma/fmaf/fmal in Builtins.def with the implementation in CGBuiltins.cpp

craig.topper created this revision. The fma libcalls are defined in Builtins.def using the 'e' attribute that says that its only const if -fno-math-errno. It was apparently marked this way because that's what the posix spec says. This determines whether the call gets marked as const or not in S

[PATCH] D32543: [X86] Clang option -fuse-init-array has no effect when generating for MCU target

craig.topper added a comment. Should we add a test to test/CodeGen/X86/constructor.ll that test appears to have been modified when NAcl was added to the line you changed. https://reviews.llvm.org/D32543 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D32543: [X86] Clang option -fuse-init-array has no effect when generating for MCU target

craig.topper added a comment. It looksl ike UseInitArray is connected to -use-ctors command line option to llc so we should be able to test this without a frontend test. https://reviews.llvm.org/D32543 ___ cfe-commits mailing list cfe-commits@lists

[PATCH] D32543: [X86] Clang option -fuse-init-array has no effect when generating for MCU target

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D32543 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D32770: [X86][LWP] Add clang support for LWP instructions.

craig.topper added a comment. Sorry I missed this patch, but shouldn't we had __LWP__ to the relevant processors in test/Preprocessor/predefined-arch-macros.c and the command line switch testing to test/Preprocessor/x86_target_features.c Repository: rL LLVM https://reviews.llvm.org/D32770

[PATCH] D33170: [X86] Adding avx512_vpopcntdq feature set and its intrinsics

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:7526 +llvm::Type *ResultType = ConvertType(E->getType()); +Value *X = EmitScalarExpr(E->getArg(0)); +llvm::Function *F = CGM.getIntrinsic(Intrinsic::ctpop, ResultType); I'm not

[PATCH] D33170: [X86] Adding avx512_vpopcntdq feature set and its intrinsics

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:7526 +llvm::Type *ResultType = ConvertType(E->getType()); +Value *X = EmitScalarExpr(E->getArg(0)); +llvm::Function *F = CGM.getIntrinsic(Intrinsic::ctpop, ResultType); oren_ben

[PATCH] D33170: [X86] Adding avx512_vpopcntdq feature set and its intrinsics

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:7526 +llvm::Type *ResultType = ConvertType(E->getType()); +llvm::Function *F = CGM.getIntrinsic(Intrinsic::ctpop, ResultType); +return Builder.CreateCall(F, Ops); Why did the ca

[PATCH] D33170: [X86] Adding avx512_vpopcntdq feature set and its intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/CodeGen/CGBuiltin.cpp:7526 +llvm::Type *ResultType = ConvertType(E->getType()); +llvm::Function *F = CGM.getIntrinsic(Intrinsic::ctpo

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:907 (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>; +def : Pat<(riscv_fsr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt), + (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>; --

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4246 + case Intrinsic::riscv_fsl: +return DAG.getNode(RISCVISD::FSL, DL, XLenVT, Op.getOperand(1), + Op.getOperand(2), Op.getOperand(3)); The op

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4246 + case Intrinsic::riscv_fsl: +return DAG.getNode(RISCVISD::FSL, DL, XLenVT, Op.getOperand(1), + Op.getOperand(2), Op.getOperand(3)); craig.

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added a comment. Out of curiosity, what is your interest in Zbt? Do you work for a company that is implementing this extension in hardware? Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4246 + case Intrinsic::riscv_fsl: +return DAG.getNode(RISCVISD:

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1499 foreach nf=2-8 in { +// Vector Unit-strided Segment Instructions +def VLSEG#nf#E64_V : The unit-stride and strided with EEW=64 don't require RV64. Just the in

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll:21 +; RV32ZBT: # %bb.0: +; RV32ZBT-NEXT:fsr a0, a1, a0, a2 +; RV32ZBT-NEXT:ret This should have the same register order as the fsl test case. I think the te

[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper added a comment. In D117468#3253879 , @Chenbing.Zheng wrote: > In D117468#3253493 , @craig.topper > wrote: > >> Out of curiosity, what is your interest in Zbt? Do you work for a company >> that is

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:186 + "with maximal 32 EEW and F extension)", + [FeatureStdExtZve32x, FeatureStdExtF]>; +def HasStdExtZve32f : Predicate<"SubTarget->hasStdExtZve32f()">; ---

[PATCH] D117647: [RISCV] Add destination operand for RVV nomask load intrinsics.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1238 unsigned CurOp = 2; + bool IsTU = false; + if ((IntNo != Intrinsic::riscv_vlm && ``` bool IsTU = IntNo != Intrinsic::riscv_vlm && (!Node->getOperand

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2187 +multiclass VPseudoTernaryNoMaskNoPolicyhttps://reviews.llvm.org/D117681/new/ https://reviews.llvm.org/D117681 ___ cfe-commits mailin

[PATCH] D117724: [RISCV] Remove Zvlsseg extension.

craig.topper added inline comments. Comment at: llvm/test/MC/RISCV/rvv/zvlsseg.s:11 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \ # RUN: --mattr=+experimental-zvlsseg %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:744 static const char *ImpliedExtsZfh[] = {"zfhmin"}; +static const char *ImpliedExtsZve64d[] = {"zve64f", "d"}; +static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; I t

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112408/new/ https://reviews.llvm.org/D112408 ___

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+ex

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