craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1238
unsigned CurOp = 2;
+ bool IsTU = false;
+ if ((IntNo != Intrinsic::riscv_vlm &&
----------------
```
bool IsTU = IntNo != Intrinsic::riscv_vlm &&
(!Node->getOperand(CurOp).isUndef() || IsMasked);
```
NOTE: I changed it so IsMask is also only checked when it's not vlm. That makes
the non vlm part of the condition look like the other intrinsic handling
earlier.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1251
addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
- Operands, /*IsLoad=*/true);
+ Operands, /*IsLoad=*/true,
/*IndexVT=*/nullptr);
----------------
Why aren't we using the default value for IndexVT now?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D117647/new/
https://reviews.llvm.org/D117647
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