[PATCH] D150646: [clang][X86] Add __cpuidex function to cpuid.h

craig.topper added a comment. In D150646#4351981 , @aidengrossman wrote: > Thanks for notifying me of this. I've reverted it as I don't have too much > time currently to thoroughly go through things and I don't want to keep you > blocked. Essentially,

[PATCH] D150670: [WebAssembly] Disable generation of fshl/fshr for rotates

craig.topper added a comment. > Preventing the simplification means adding target specific code in > instcombine which seems even worse than adding it here given as @dschuff > pointed out, there's precedent with x86. How harmful is it to avoid breaking rotate patterns even if the target doesn't

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper accepted this revision. craig.topper added inline comments. This revision is now accepted and ready to land. Comment at: clang/lib/CodeGen/CGCall.cpp:3135 STy->getNumElements() > 1) { -uint64_t SrcSize = CGM.getDataLayout().getTypeAllocSize(STy); -

[PATCH] D147731: [3/11][POC][Clang][RISCV] Add typedef of the tuple type and define tuple type variant of vlseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1528 + + unsigned Offset = IsMasked ? 1 : 0; + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; I don't think we need the `Value *` variables here. They're

[PATCH] D147774: [4/11][POC][Clang][RISCV] Define tuple type variant of vsseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1575 + unsigned Offset = IsMasked ? 1 : 0; + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = Ops[Offset]; Similar comment

[PATCH] D147911: [5/11][POC][Clang][RISCV] Define tuple type variant of vlseg2e32ff

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1635 + Operands.push_back(PtrOperand); + if (MaskOperand) +Operands.push_back(MaskOperand); Same comment as previous patch Repository: rG LLVM Github M

[PATCH] D147912: [6/11][POC][Clang][RISCV] Define tuple type variant of vlsseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1693 + unsigned Offset = IsMasked ? 1 : 0; + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; S

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGCall.cpp:3135 STy->getNumElements() > 1) { -uint64_t SrcSize = CGM.getDataLayout().getTypeAllocSize(STy); -llvm::Type *DstTy = Ptr.getElementType(); -uint64_t DstSize = CGM.getD

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGCall.cpp:3156 } else { - AddrToStoreInto = -CreateTempAlloca(STy, Alloca.getAlignment(), "coerce"); -} + uint64_t SrcSize = CGM.getDataLayout().getTypeAllocSize(STy)

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146873/new/ https://reviews.llvm.org/D146873 ___

[PATCH] D147731: [3/11][POC][Clang][RISCV] Add typedef of the tuple type and define tuple type variant of vlseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1531 + Operands.push_back(Ops[Offset]); // Ptr + if (MaskOperand) +Operands.push_back(MaskOperand); MaskOperand can still be simplified. Repository: rG

[PATCH] D147731: [3/11][POC][Clang][RISCV] Add typedef of the tuple type and define tuple type variant of vlseg2e32

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147731/new/ https://reviews.llvm.org/D147731 ___

[PATCH] D147774: [4/11][POC][Clang][RISCV] Define tuple type variant of vsseg2e32

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147774/new/ https://reviews.llvm.org/D147774 ___

[PATCH] D147911: [5/11][POC][Clang][RISCV] Define tuple type variant of vlseg2e32ff

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147911/new/ https://reviews.llvm.org/D147911 ___

[PATCH] D147912: [6/11][POC][Clang][RISCV] Define tuple type variant of vlsseg2e32

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147912/new/ https://reviews.llvm.org/D147912 ___

[PATCH] D147913: [7/11][POC][Clang][RISCV] Define tuple type variant of vssseg2e32

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147913/new/ https://reviews.llvm.org/D147913 ___

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147914/new/ https://reviews.llvm.org/D147914 ___

[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147915/new/ https://reviews.llvm.org/D147915 ___

[PATCH] D147916: [10/11][POC][Clang][RISCV] Define vget for tuple type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2599 + llvm::Value *IndexOperand = Ops[1]; + assert(isa(IndexOperand)); + unsigned Index = cast(IndexOperand)->getZExtValue(); You can drop this a

[PATCH] D147917: [11/11][POC][Clang][RISCV] Define vset for tuple type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2640 + llvm::Value *VOperand = Ops[2]; + assert(isa(IndexOperand)); + Drop this assert Comment at: clang/include/clang/Basic/riscv_vecto

[PATCH] D147916: [10/11][POC][Clang][RISCV] Define vget for tuple type

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147916/new/ https://reviews.llvm.org/D147916 ___

[PATCH] D147917: [11/11][POC][Clang][RISCV] Define vset for tuple type

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D147917/new/ https://reviews.llvm.org/D147917 ___

[PATCH] D148385: [RISCV] Implement KCFI operand bundle lowering for RV64

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:310 +EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI) + .addReg(ScratchRegs[0]) + .addReg(RISCV::X0) --

[PATCH] D148385: [RISCV] Implement KCFI operand bundle lowering for RV64

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:310 +EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI) + .addReg(ScratchRegs[0]) + .addReg(RISCV::X0) --

[PATCH] D148385: [RISCV] Implement KCFI operand bundle lowering for RV64

craig.topper added inline comments. Comment at: llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn:81 "RISCVInstrInfo.cpp", +"RISCVKCFI.cpp", "RISCVMCInstLower.cpp", Isn't this done automatically by the GN Syncbot when CMakeLists.txt is updated?

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/AttrDocs.td:2332 + + #if __RISCV_RVV_VLEN_BITS==512 + typedef vint8m1_t fixed_vint8m1_t __attribute__((riscv_rvv_vector_bits(512))); rjmccall wrote: > This probably needs a `defined(__RI

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4276099 , @rjmccall wrote: > The CodeGen change looks fine. I'm surprised you didn't need any code in > argument/parameter/call/return emission to do the actual fixed<->scalable > coercion; do we already have th

[PATCH] D143364: [RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D143364/new/ https://reviews.llvm.org/D143364 ___

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CodeGenTypes.cpp:632 +#define RVV_TYPE(Name, Id, SingletonId) \ + case BuiltinType::Id: { \ +ASTContext::BuiltinVec

[PATCH] D147731: [3/11][POC][Clang][RISCV] Add typedef of the tuple type and define tuple type variant of vlseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/AST/ASTContext.h:1486 + QualType getScalableVectorTupleType(QualType EltTy, unsigned NumElts, + unsigned Tuple) const; + Use `NF` or `NumFields` instead of `

[PATCH] D147911: [5/11][POC][Clang][RISCV] Define tuple type variant of vlseg2e32ff

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1852 + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; + unsigned NewVLOperandIdx = IsMasked ? 2 : 1; + llvm::Value *NewVLOperand = IsMasked ? Ops[2] : Ops[1]; -

[PATCH] D147912: [6/11][POC][Clang][RISCV] Define tuple type variant of vlsseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1914 + + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; similar comment to what I left on the last

[PATCH] D147913: [7/11][POC][Clang][RISCV] Define tuple type variant of vssseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1962 + // Intrinsic: (val0, val1, ..., ptr, stride, vl) + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; -

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2014 + + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; Same comment as last review Repository:

[PATCH] D147916: [10/11][POC][Clang][RISCV] Define vget for tuple type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2723 + unsigned MaxIndex = cast(VTupleOperand->getType())->getNumElements(); + Index = std::min(Index, MaxIndex); + Does SemaChecking.cpp already guarante

[PATCH] D147917: [11/11][POC][Clang][RISCV] Define vset for tuple type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2763 + unsigned MaxIndex = cast(VTupleOperand->getType())->getNumElements(); + Index = std::min(Index, MaxIndex); + Does SemaChecking already guarantee th

[PATCH] D147916: [10/11][POC][Clang][RISCV] Define vget for tuple type

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:2723 + unsigned MaxIndex = cast(VTupleOperand->getType())->getNumElements(); + Index = std::min(Index, MaxIndex); + craig.topper wrote: > Does SemaCheckin

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/AttrDocs.td:2332 + + #if __RISCV_RVV_VLEN_BITS==512 + typedef vint8m1_t fixed_vint8m1_t __attribute__((riscv_rvv_vector_bits(512))); rjmccall wrote: > craig.topper wrote: > > rjmccall wr

[PATCH] D148680: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td

craig.topper added a comment. Are we running tablegen separately for each vendor extension? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148680/new/ https://reviews.llvm.org/D148680 ___ cfe-commits mail

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_sifive_vector.td:41 + if !find(prototype, "0") then { + def : VCIXBuiltinSet; + } Indent Comment at: clang/include/clang/Basic/riscv_sifive_vector.td:64 +

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:903 +return createStringError(errc::invalid_argument, + "zcmt is not allowed when c is specified"); + Extension names should be in single quotes. Sh

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 ___

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_sifive_vector.td:46 + +multiclass RVVVCIXBuiltinSet range, string prototype, + list intrinsic_types, bit EncodeVtype, We might consider breaking this class

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

craig.topper created this revision. craig.topper added reviewers: kito-cheng, asb, jrtc27, reames. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Ma

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

craig.topper added inline comments. Comment at: clang/test/Driver/riscv-default-build-attributes.s:1 +// Enabled by default for assembly +// RUN: %clang --target=riscv64 -### %s 2>&1 \ jrtc27 wrote: > Do we use /// for non-lit/FileCheck lines like we use ;; in IR

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

craig.topper updated this revision to Diff 515484. craig.topper added a comment. Address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148817/new/ https://reviews.llvm.org/D148817 Files: clang/lib/Driver/ToolChains/Clang.cpp cl

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

craig.topper added inline comments. Comment at: clang/test/Driver/riscv-default-build-attributes.s:3 +// RUN: %clang --target=riscv64 -### %s 2>&1 \ +// RUN:| FileCheck %s -check-prefix CHECK-ENABLED + jrtc27 wrote: > jrtc27 wrote: > > `=` for these > Also ar

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

craig.topper updated this revision to Diff 515511. craig.topper added a comment. Fix more review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148817/new/ https://reviews.llvm.org/D148817 Files: clang/lib/Driver/ToolChains/Clang.cpp c

[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGea0dae096189: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an… (authored by craig.topper). Changed prior to commit: https:/

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

craig.topper created this revision. craig.topper added reviewers: asb, reames, kito-cheng, jrtc27. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Ma

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added a comment. Need to update RISCVUsage.rst Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:969 +case KindTy::Spimm: + OS << "{Spimm: "; + RISCVZC::printSpimm(Spimm.Val, OS); Why curly braces when everything else use

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

craig.topper added a comment. In D147610#4294247 , @joshua-arch1 wrote: > I'm wondering whether it is appropriate to just use FPR16 for the destination > of fcvt.bf16.s? The destination is in BF16 format instead of simple FP16. > Your implemention loo

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

craig.topper added a comment. Forgot to make this dependent on @reames patch D144215 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148962/new/ https://reviews.llvm.org/D148962 ___

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

craig.topper added a comment. In D147610#4294322 , @joshua-arch1 wrote: > In D147610#4294260 , @craig.topper > wrote: > >> In D147610#4294247 , @joshua-arch1 >> wrote:

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper requested changes to this revision. craig.topper added inline comments. This revision now requires changes to proceed. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:853 Error RISCVISAInfo::checkDependency() { + bool HasC = Exts.count("c") != 0; bool HasD = Exts.

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

craig.topper added a comment. In D147610#4297533 , @joshua-arch1 wrote: >> The RVI toolchain SIG is supposed to be setting up a task group to define >> intrinsics for all extensions. > > Where should I discuss this intrinsic issue right now? I guess ht

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:915 +return createStringError(errc::invalid_argument, + "'zcmt' is incompatible with 'c' or 'zcd' " + "extensions when 'd' extensions is s

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1473 +ErrorLoc, +"operand must like {ra [, s0[-sN]]} or {x1 [, x8[-x9][, x18[-xN]]]}"); + } like -> be ``` "operand must be '{ra [, s0[-sN]]}' or

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:916 + "'zcmt' is incompatible with 'c' or 'zcd' " + "extensions when 'd' extensions is set"); + 'd' extensions - > 'd' extens

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG3ce3ee616982: [RISCV] Make Zicntr and Zihpm imply Zicsr. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTIO

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGCall.cpp:3063 + llvm::Type *DstTy = Ptr.getElementType(); + llvm::TypeSize SrcSize = CGM.getDataLayout().getTypeAllocSize(STy); + llvm::TypeSize DstSize = CGM.getDataLayout().getTypeAll

[PATCH] D146873: [2/11][POC][Clang][RISCV] Define RVV tuple types

craig.topper added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:151 + +RVV_VECTOR_TUPLE_INT("__rvv_int32m1x2_t", RvvInt32m1x2, RvvInt32m1x2Ty, 2, 32, 2, true) + Is this macro still needed? Repository: rG LLVM Github Monorepo CHANG

[PATCH] D147731: [3/11][POC][Clang][RISCV] Add typedef of the tuple type and define tuple type variant of vlseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1758 + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; + llvm::Value *VLOperand = IsMasked ? Ops[2] : Ops[1]; -

[PATCH] D147774: [4/11][POC][Clang][RISCV] Define tuple type variant of vsseg2e32

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1802 + llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr; + llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0]; + llvm::Value *VTupleOperand = IsMasked ? Ops[2] : Ops[1

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

craig.topper created this revision. craig.topper added reviewers: jrtc27, kito-cheng. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, e

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

craig.topper updated this revision to Diff 517408. craig.topper added a comment. Add another test case Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149314/new/ https://reviews.llvm.org/D149314 Files: clang/include/clang/Basic/Attr.td clang/li

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG05d0caef6081: [RISCV] Remove support for attribute interrupt("user"). (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SIN

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:3150 + SMLoc Loc = Operands[1]->getStartLoc(); + return Error(Loc, "'rs1' and 'rs2' mast be different."); +} mast -> must Repository: rG LLVM Gith

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

craig.topper added a comment. Release note added in 0e02e5decc732155d8dc4b63ecccbb1477603ecd Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149314/new/ https://reviews.llvm.org/D

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D145088/new/ https://reviews.llvm.org/D145088 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.or

[PATCH] D149401: [Clang][RISCV] Set native half type to legal when has zfh extension

craig.topper added a comment. Is this the same as https://reviews.llvm.org/D145071 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149401/new/ https://reviews.llvm.org/D149401 ___ cfe-commits mailing list

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1048 + static std::unique_ptr createRlist(unsigned RlistEncode, + SMLoc S, bool IsRV64) { +auto Op = std::make_unique(KindTy::

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

craig.topper added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:176 // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:181 + FeatureStdExtZvfh, + FeatureStdExtZba, + FeatureStdExtZbb], ---

[PATCH] D149497: [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149497/new/ https://reviews.llvm.org/D149497 ___

[PATCH] D149498: [RISCV] Add Scheduling information for Zfh to SiFive7 model

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149498/new/ https://reviews.llvm.org/D149498 ___

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4307772 , @akyrtzi wrote: > Hi @craig.topper , this patch is causing a build failure: > > In file included from /llvm-project/clang/lib/Sema/SemaType.cpp:43: > /llvm-project/llvm/include/llvm/TargetParser/RISCV

[PATCH] D149456: Basic documentation of -mrecip=... option

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149456/new/ https://reviews.llvm.org/D149456 ___

[PATCH] D149606: [RISCV] Move RISCV::RVVBitsPerBlock to be a static member of RISCVISAInfo class.

craig.topper created this revision. craig.topper added reviewers: reames, asb, luismarques, frasercrmck, kito-cheng, rogfer01, pcwang-thead. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehou

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4308840 , @akyrtzi wrote: > `CodeGen` has the same issue: > > $ ninja > tools/clang/lib/CodeGen/CMakeFiles/obj.clangCodeGen.dir/TargetInfo.cpp.o > In file included from /llvm-project/clang/lib/CodeGen/TargetIn

[PATCH] D149606: [RISCV] Move RISCV::RVVBitsPerBlock to be a static member of RISCVISAInfo class.

craig.topper abandoned this revision. craig.topper added a comment. fa42e7b made this unnecessary. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149606/new/ https://reviews.llvm

[PATCH] D145088: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

craig.topper added a comment. In D145088#4310464 , @craig.topper wrote: > In D145088#4308840 , @akyrtzi wrote: > >> `CodeGen` has the same issue: >> >> $ ninja >> tools/clang/lib/CodeGen/CMakeFiles/obj.clangCo

[PATCH] D149334: [RISCV] Enable strict fp for RISC-V in clang.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149334/new/ https://reviews.llvm.org/D149334 ___

[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVProcessors.td:169 +def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, + [Feature64Bit, I would prefer that we add sifive-x280 in a si

[PATCH] D149495: [RISCV] Add sifive-x280 processor and support V extension in SiFive7

craig.topper added a comment. All CPU name additions should be mentioned in the RISC-V section of llvm/docs/ReleaseNotes.rst Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149495/new/ https://reviews.llvm.org/D149495 __

[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM with the last 4 few comments addressed. Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h:550 + if (RlistVal == RLISTENCODE::INVALID_RLIST) +

[PATCH] D133863: [RISCV] Add MC support of RISCV zcmt Extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D133863/new/ https://reviews.llvm.org/D133863 ___

[PATCH] D149710: [RISCV] Add sifive-x280 processor with all of its extensions

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149710/new/ https://reviews.llvm.org/D149710 ___ cfe-commits mailing list cfe-commits

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

craig.topper added a comment. In D146054#4314766 , @kito-cheng wrote: > LGTM, consider about the GNU compatibility, I would that has -march=help form > for that. Are you saying gcc supports march=help? Is that recent? Repository: rG LLVM Github Mon

[PATCH] D152070: [2/11][Clang][RISCV] Expand all variants of RVV intrinsic tuple types

craig.topper added inline comments. Comment at: clang/include/clang/Basic/RISCVVTypes.def:224 +RVV_VECTOR_TYPE_INT("__rvv_uint8m4x2_t", RvvUint8m4x2, RvvUint8m4x2Ty, 32, 8, 2, false) +//===- Int16 tuple types --===// +RVV_VECTOR_T

[PATCH] D152071: [3/11][Clang][RISCV] Expand all variants for unit stride segment load

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1533 + + if (NoPassthru) // Push poison into passthru +Operands.append(NF, llvm::PoisonValue::get(ElementVectorType)); `if` should use curly braces if the `else

[PATCH] D152073: [5/11][Clang][RISCV] Expand all variants for unit stride fault-first segment load

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1645 + + if (NoPassthru) // Push poison into passthru +Operands.append(NF, llvm::PoisonValue::get(ElementVectorType)); Curly braces Repository: rG LLVM Gith

[PATCH] D152074: [6/11][Clang][RISCV] Expand all variants for strided segment load

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1719 + + if (NoPassthru) // Push poison into passthru +Operands.append(NF, llvm::PoisonValue::get(ElementVectorType)); Curly braces Repository: rG LLVM Gith

[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

craig.topper added a comment. From the C language perspective with this change, __builtin_clz/ctz is still considered undefined for 0 and code that uses it is ill-formed. `isCLZForZeroUndef` is only intended to prevent the middle end from optimizing based on the undefinedness and creating surpr

[PATCH] D152250: [Clang][RISCV] Add test cases for intrinsics clz/ctz codegen when has extension zbb/xtheadbb

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c:52 +// +long clz_64_generic(long a) { + return __builtin_clzl(a); Should the return type be int to match __builtin_clzl? Comment at: cla

[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

craig.topper added a comment. In D151867#4401952 , @Yunzezhu wrote: > In D151867#4400255 , @craig.topper > wrote: > >> From the C language perspective with this change, __builtin_clz/ctz is still >> considered u

[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

craig.topper added a comment. Ping * 3 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150926/new/ https://reviews.llvm.org/D150926 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llv

[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaType.cpp:8338 // The attribute vector size must match -mrvv-vector-bits. - if (VecSize != VScale->first * MinElts * EltSize) { + unsigned ExpectedSize = VScale->first * MinElts * EltSize; + if (VecSize != Ex

[PATCH] D152415: [RISCV] Add test cases to show that rvv_vectreo-bits attributes is not accepted for vbool or LMUL!=1 RVV types. NFC

craig.topper created this revision. craig.topper added a reviewer: aaron.ballman. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones,

[PATCH] D152415: [RISCV] Add test cases to show that rvv_vector_bits attribute is not accepted for vbool or LMUL!=1 RVV types. NFC

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGe4c1fa734ea7: [RISCV] Add test cases to show that rvv_vector_bits attribute is not accepted… (authored by craig.topper). Repository: rG LLVM Githu

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