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This constant is used by clang and llvm so needs to be shared.
It can't be in RISCVTargetParser.h where it is today because that
file depends on a tablegen output.
I don't want to create a new header file so I figured RISCVISAInfo.h
could be a new home for it.
lld imports RISCVISAInfo.h and lld has a class named llvm::RISCV.
So we can't expose the llvm::RISCV namespace to lld.
Thus this patch to put it inside the RISCVISAInfo class.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D149606
Files:
clang/lib/AST/ASTContext.cpp
clang/lib/AST/Type.cpp
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/CodeGen/TargetInfo.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Sema/CMakeLists.txt
clang/lib/Sema/SemaType.cpp
llvm/include/llvm/Support/RISCVISAInfo.h
llvm/include/llvm/TargetParser/RISCVTargetParser.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -210,15 +210,15 @@
std::optional<unsigned> RISCVTTIImpl::getMaxVScale() const {
if (ST->hasVInstructions())
- return ST->getRealMaxVLen() / RISCV::RVVBitsPerBlock;
+ return ST->getRealMaxVLen() / RISCVISAInfo::RVVBitsPerBlock;
return BaseT::getMaxVScale();
}
std::optional<unsigned> RISCVTTIImpl::getVScaleForTuning() const {
if (ST->hasVInstructions())
if (unsigned MinVLen = ST->getRealMinVLen();
- MinVLen >= RISCV::RVVBitsPerBlock)
- return MinVLen / RISCV::RVVBitsPerBlock;
+ MinVLen >= RISCVISAInfo::RVVBitsPerBlock)
+ return MinVLen / RISCVISAInfo::RVVBitsPerBlock;
return BaseT::getVScaleForTuning();
}
@@ -235,8 +235,8 @@
case TargetTransformInfo::RGK_ScalableVector:
return TypeSize::getScalable(
(ST->hasVInstructions() &&
- ST->getRealMinVLen() >= RISCV::RVVBitsPerBlock)
- ? LMUL * RISCV::RVVBitsPerBlock
+ ST->getRealMinVLen() >= RISCVISAInfo::RVVBitsPerBlock)
+ ? LMUL * RISCVISAInfo::RVVBitsPerBlock
: 0);
}
@@ -1193,7 +1193,8 @@
if (isa<ScalableVectorType>(Ty)) {
const unsigned EltSize = DL.getTypeSizeInBits(Ty->getElementType());
const unsigned MinSize = DL.getTypeSizeInBits(Ty).getKnownMinValue();
- const unsigned VectorBits = *getVScaleForTuning() * RISCV::RVVBitsPerBlock;
+ const unsigned VectorBits =
+ *getVScaleForTuning() * RISCVISAInfo::RVVBitsPerBlock;
return RISCVTargetLowering::computeVLMAX(VectorBits, EltSize, MinSize);
}
return cast<FixedVectorType>(Ty)->getNumElements();
@@ -1673,7 +1674,7 @@
TypeSize Size = DL.getTypeSizeInBits(Ty);
if (Ty->isVectorTy()) {
if (Size.isScalable() && ST->hasVInstructions())
- return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
+ return divideCeil(Size.getKnownMinValue(), RISCVISAInfo::RVVBitsPerBlock);
if (ST->useRVVForFixedLengthVectors())
return divideCeil(Size, ST->getRealMinVLen());
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -140,10 +140,11 @@
Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
if (VScaleRangeAttr.isValid()) {
if (!RVVVectorBitsMinOpt.getNumOccurrences())
- RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
+ RVVBitsMin =
+ VScaleRangeAttr.getVScaleRangeMin() * RISCVISAInfo::RVVBitsPerBlock;
std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
- RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
+ RVVBitsMax = *VScaleMax * RISCVISAInfo::RVVBitsPerBlock;
}
if (RVVBitsMin != -1U) {
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -18,7 +18,6 @@
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
#include <optional>
namespace llvm {
@@ -650,10 +649,10 @@
unsigned MinSize) {
// Original equation:
// VLMAX = (VectorBits / EltSize) * LMUL
- // where LMUL = MinSize / RISCV::RVVBitsPerBlock
+ // where LMUL = MinSize / RISCVISAInfo::RVVBitsPerBlock
// The following equations have been reordered to prevent loss of precision
// when calculating fractional LMUL.
- return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
+ return ((VectorBits / EltSize) * MinSize) / RISCVISAInfo::RVVBitsPerBlock;
};
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -142,19 +142,19 @@
auto addRegClassForRVV = [this](MVT VT) {
// Disable the smallest fractional LMUL types if ELEN is less than
// RVVBitsPerBlock.
- unsigned MinElts = RISCV::RVVBitsPerBlock / Subtarget.getELEN();
+ unsigned MinElts = RISCVISAInfo::RVVBitsPerBlock / Subtarget.getELEN();
if (VT.getVectorMinNumElements() < MinElts)
return;
unsigned Size = VT.getSizeInBits().getKnownMinValue();
const TargetRegisterClass *RC;
- if (Size <= RISCV::RVVBitsPerBlock)
+ if (Size <= RISCVISAInfo::RVVBitsPerBlock)
RC = &RISCV::VRRegClass;
- else if (Size == 2 * RISCV::RVVBitsPerBlock)
+ else if (Size == 2 * RISCVISAInfo::RVVBitsPerBlock)
RC = &RISCV::VRM2RegClass;
- else if (Size == 4 * RISCV::RVVBitsPerBlock)
+ else if (Size == 4 * RISCVISAInfo::RVVBitsPerBlock)
RC = &RISCV::VRM4RegClass;
- else if (Size == 8 * RISCV::RVVBitsPerBlock)
+ else if (Size == 8 * RISCVISAInfo::RVVBitsPerBlock)
RC = &RISCV::VRM8RegClass;
else
llvm_unreachable("Unexpected size");
@@ -2199,8 +2199,8 @@
// narrower types. The smallest fractional LMUL we support is 8/ELEN. Within
// each fractional LMUL we support SEW between 8 and LMUL*ELEN.
unsigned NumElts =
- (VT.getVectorNumElements() * RISCV::RVVBitsPerBlock) / MinVLen;
- NumElts = std::max(NumElts, RISCV::RVVBitsPerBlock / MaxELen);
+ (VT.getVectorNumElements() * RISCVISAInfo::RVVBitsPerBlock) / MinVLen;
+ NumElts = std::max(NumElts, RISCVISAInfo::RVVBitsPerBlock / MaxELen);
assert(isPowerOf2_32(NumElts) && "Expected power of 2 NumElts");
return MVT::getScalableVectorVT(EltVT, NumElts);
}
@@ -3283,8 +3283,8 @@
assert(VT.getVectorElementType().getSizeInBits() <= 64 &&
"Unexpected vector MVT");
return MVT::getScalableVectorVT(
- VT.getVectorElementType(),
- RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits());
+ VT.getVectorElementType(), RISCVISAInfo::RVVBitsPerBlock /
+ VT.getVectorElementType().getSizeInBits());
}
// This function lowers an insert of a scalar operand Scalar into lane
@@ -4500,8 +4500,9 @@
// We define our scalable vector types for lmul=1 to use a 64 bit known
// minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
// vscale as VLENB / 8.
- static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
- if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
+ static_assert(RISCVISAInfo::RVVBitsPerBlock == 64,
+ "Unexpected bits per block!");
+ if (Subtarget.getRealMinVLen() < RISCVISAInfo::RVVBitsPerBlock)
report_fatal_error("Support for VLEN==32 is incomplete.");
// We assume VLENB is a multiple of 8. We manually choose the best shift
// here because SimplifyDemandedBits isn't always able to simplify it.
@@ -7469,7 +7470,7 @@
// Reverse each half, then reassemble them in reverse order.
// NOTE: It's also possible that after splitting that VLMAX no longer
// requires vrgatherei16.vv.
- if (MinSize == (8 * RISCV::RVVBitsPerBlock)) {
+ if (MinSize == (8 * RISCVISAInfo::RVVBitsPerBlock)) {
auto [Lo, Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
auto [LoVT, HiVT] = DAG.GetSplitDestVTs(VecVT);
Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, LoVT, Lo);
@@ -15450,7 +15451,7 @@
// FIXME: This doesn't work for zve32, but that's already broken
// elsewhere for the same reason.
assert(Subtarget.getRealMinVLen() >= 64 && "zve32* unsupported");
- static_assert(RISCV::RVVBitsPerBlock == 64,
+ static_assert(RISCVISAInfo::RVVBitsPerBlock == 64,
"RVVBitsPerBlock changed, audit needed");
return true;
}
Index: llvm/include/llvm/TargetParser/RISCVTargetParser.h
===================================================================
--- llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -23,9 +23,6 @@
namespace RISCV {
-// We use 64 bits as the known part in the scalable vector types.
-static constexpr unsigned RVVBitsPerBlock = 64;
-
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===================================================================
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -90,6 +90,8 @@
static llvm::Expected<std::unique_ptr<RISCVISAInfo>>
postProcessAndChecking(std::unique_ptr<RISCVISAInfo> &&ISAInfo);
+ static constexpr unsigned RVVBitsPerBlock = 64;
+
private:
RISCVISAInfo(unsigned XLen)
: XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0) {}
Index: clang/lib/Sema/SemaType.cpp
===================================================================
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -40,7 +40,7 @@
#include "llvm/ADT/SmallString.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include <bitset>
#include <optional>
@@ -8325,9 +8325,9 @@
// The attribute vector size must match -mrvv-vector-bits.
// FIXME: Add support for types with LMUL!=1. Need to make sure size passed
// to attribute is equal to LMUL*VScaleMin*RVVBitsPerBlock.
- if (VecSize != VScale->first * llvm::RISCV::RVVBitsPerBlock) {
+ if (VecSize != VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock) {
S.Diag(Attr.getLoc(), diag::err_attribute_bad_rvv_vector_size)
- << VecSize << VScale->first * llvm::RISCV::RVVBitsPerBlock;
+ << VecSize << VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock;
Attr.setInvalid();
return;
}
Index: clang/lib/Sema/CMakeLists.txt
===================================================================
--- clang/lib/Sema/CMakeLists.txt
+++ clang/lib/Sema/CMakeLists.txt
@@ -71,7 +71,6 @@
DEPENDS
ClangOpenCLBuiltinsImpl
omp_gen
- RISCVTargetParserTableGen
LINK_LIBS
clangAST
Index: clang/lib/Driver/ToolChains/Clang.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -56,7 +56,6 @@
#include "llvm/Support/YAMLParser.h"
#include "llvm/TargetParser/ARMTargetParserCommon.h"
#include "llvm/TargetParser/Host.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
#include <cctype>
using namespace clang::driver;
@@ -2131,19 +2130,19 @@
// If the value is "zvl", use MinVLen from march. Otherwise, try to parse
// as integer as long as we have a MinVLen.
unsigned Bits = 0;
- if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) {
+ if (Val.equals("zvl") && MinVLen >= llvm::RISCVISAInfo::RVVBitsPerBlock) {
Bits = MinVLen;
} else if (!Val.getAsInteger(10, Bits)) {
// Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that
// at least MinVLen.
- if (Bits < MinVLen || Bits < llvm::RISCV::RVVBitsPerBlock ||
+ if (Bits < MinVLen || Bits < llvm::RISCVISAInfo::RVVBitsPerBlock ||
Bits > 65536 || !llvm::isPowerOf2_32(Bits))
Bits = 0;
}
// If we got a valid value try to use it.
if (Bits != 0) {
- unsigned VScaleMin = Bits / llvm::RISCV::RVVBitsPerBlock;
+ unsigned VScaleMin = Bits / llvm::RISCVISAInfo::RVVBitsPerBlock;
CmdArgs.push_back(
Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin)));
CmdArgs.push_back(
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -32,8 +32,8 @@
#include "llvm/IR/IntrinsicsS390.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
@@ -11364,9 +11364,9 @@
const auto *BT = VT->getElementType()->castAs<BuiltinType>();
unsigned EltSize = getContext().getTypeSize(BT);
- llvm::ScalableVectorType *ResType =
- llvm::ScalableVectorType::get(CGT.ConvertType(VT->getElementType()),
- llvm::RISCV::RVVBitsPerBlock / EltSize);
+ llvm::ScalableVectorType *ResType = llvm::ScalableVectorType::get(
+ CGT.ConvertType(VT->getElementType()),
+ llvm::RISCVISAInfo::RVVBitsPerBlock / EltSize);
return ABIArgInfo::getDirect(ResType);
}
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -203,8 +203,9 @@
auto VScale = getVScaleRange(Opts);
if (VScale && VScale->first && VScale->first == VScale->second)
- Builder.defineMacro("__riscv_v_fixed_vlen",
- Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock));
+ Builder.defineMacro(
+ "__riscv_v_fixed_vlen",
+ Twine(VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock));
}
static constexpr Builtin::Info BuiltinInfo[] = {
@@ -261,8 +262,9 @@
std::optional<std::pair<unsigned, unsigned>>
RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
- // RISCV::RVVBitsPerBlock is 64.
- unsigned VScaleMin = ISAInfo->getMinVLen() / llvm::RISCV::RVVBitsPerBlock;
+ // RISCVISAInfo::RVVBitsPerBlock is 64.
+ unsigned VScaleMin =
+ ISAInfo->getMinVLen() / llvm::RISCVISAInfo::RVVBitsPerBlock;
if (LangOpts.VScaleMin || LangOpts.VScaleMax) {
// Treat Zvl*b as a lower bound on vscale.
@@ -274,7 +276,8 @@
}
if (VScaleMin > 0) {
- unsigned VScaleMax = ISAInfo->getMaxVLen() / llvm::RISCV::RVVBitsPerBlock;
+ unsigned VScaleMax =
+ ISAInfo->getMaxVLen() / llvm::RISCVISAInfo::RVVBitsPerBlock;
return std::make_pair(VScaleMin, VScaleMax);
}
Index: clang/lib/AST/Type.cpp
===================================================================
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -46,7 +46,7 @@
#include "llvm/Support/Casting.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
@@ -2435,9 +2435,10 @@
if (const BuiltinType *BT = getAs<BuiltinType>()) {
switch (BT->getKind()) {
// FIXME: Support more than LMUL 1.
-#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP) \
- case BuiltinType::Id: \
- return NF == 1 && (NumEls * ElBits) == llvm::RISCV::RVVBitsPerBlock;
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, \
+ IsFP) \
+ case BuiltinType::Id: \
+ return NF == 1 && (NumEls * ElBits) == llvm::RISCVISAInfo::RVVBitsPerBlock;
#include "clang/Basic/RISCVVTypes.def"
default:
return false;
Index: clang/lib/AST/ASTContext.cpp
===================================================================
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -84,8 +84,8 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MD5.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
@@ -9576,7 +9576,7 @@
static uint64_t getRVVTypeSize(ASTContext &Context, const BuiltinType *Ty) {
assert(Ty->isRVVVLSBuiltinType() && "Invalid RVV Type");
auto VScale = Context.getTargetInfo().getVScaleRange(Context.getLangOpts());
- return VScale ? VScale->first * llvm::RISCV::RVVBitsPerBlock : 0;
+ return VScale ? VScale->first * llvm::RISCVISAInfo::RVVBitsPerBlock : 0;
}
bool ASTContext::areCompatibleRVVTypes(QualType FirstType,
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