@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+: RISCVExtension<1
@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+: RISCVExtension<1
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/131094
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https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/131094
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dong-miao wrote:
> do you need someone to merge this?
Yes,Please help me merge.
https://github.com/llvm/llvm-project/pull/131094
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>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/36] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/131094
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@@ -0,0 +1,112 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/35] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+: RISCVExtension<1
https://github.com/topperc edited
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@@ -19,31 +19,29 @@
# TODO: more exhaustive testing of immediate encoding.
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
# CHECK-NO-EXT: error: instruction requires the f
@@ -401,6 +408,14 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>;
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store
@@ -780,6 +780,14 @@ Error RISCVISAInfo::checkDependency() {
return getIncompatibleError("xwchc", "zcb");
}
+ if (Exts.count("zclsd") != 0) {
+if (XLen != 32)
+ return getError("'zclsd' is only supported for 'rv32'");
+
+if (Exts.count("zcf") != 0)
+
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/33] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+: RISCVExtension<1
@@ -0,0 +1,12 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+zilsd < %s 2>&1 | FileCheck %s
+
+# Out of range immediates
+## simm12
+ld t1, -2049(a0) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with
%lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 20
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zclsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zclsd< %s \
+# RUN: | llvm-objdump --mattr=+zclsd --no-
@@ -205,6 +206,7 @@ on support follow.
``Zihintntl`` Supported
``Zihintpause`` Assembly Support
``Zihpm`` (`See Note <#riscv-i2p1-note>`__)
+ ``Zilsd`` Supported
christian-herber-nxp wrote:
Supported would indicate ther
https://github.com/wangpc-pp commented:
Please add a ReleaseNote.
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@@ -19,31 +19,29 @@
# TODO: more exhaustive testing of immediate encoding.
-# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
-# CHECK-ASM: encoding: [0x82,0x60]
+# CHECK-ASM-AND-OBJ: c.ldsp s0, 0(sp)
+# CHECK-ASM: encoding: [0x02,0x64]
# CHECK-NO-EXT: error: instruction requires the f
https://github.com/wangpc-pp edited
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@@ -0,0 +1,25 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zilsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zilsd < %s \
+# RUN: | llvm-objdump --mattr=+zilsd --n
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/30] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
@@ -0,0 +1,22 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zclsd < %s 2>&1 | FileCheck %s
+
+## GPRPairC
+c.ld t1, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+c.sd s2, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+
+## GPRPairNoX0
@@ -0,0 +1,25 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zilsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zilsd < %s \
+# RUN: | llvm-objdump --mattr=+zilsd --n
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/29] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/26] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/28] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/27] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/25] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/25] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/dong-miao ready_for_review
https://github.com/llvm/llvm-project/pull/131094
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https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/22] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
dong-miao wrote:
> This should fix your failures
>
> ```
> diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
> b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
> index 214378d4b554..59ab59703ac7 100644
> --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cp
dong-miao wrote:
> commented
Thanks for your help. I have successfully solved the problem.
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https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/25] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/24] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/23] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
topperc wrote:
This should fix your failures
```
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 214378d4b554..59ab59703ac7 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/24] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/23] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
dong-miao wrote:
When I tested with `sudo ninja - C build check lvm` locally, there were two
testing errors that I couldn't solve. For rv32zclsd-valid. s, errors may occur
during the disassembly process because the test file does not report errors
when I remove Check-ASM-AND-OBJ.
[Error
reco
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/11] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/21] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/20] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/topperc edited
https://github.com/llvm/llvm-project/pull/131094
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@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/10] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -401,6 +408,14 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>;
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/19] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/18] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/17] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/16] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/13] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/12] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RIS
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 1/9] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCV
https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 1/8] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCV
https://github.com/dong-miao converted_to_draft
https://github.com/llvm/llvm-project/pull/131094
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github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 8d1e260fc419e31bb11cb5a2f1f872a2b679d217
2c3440f10357b41e9a19ddacf63f161c58bc5f45 --e
https://github.com/dong-miao created
https://github.com/llvm/llvm-project/pull/131094
This commit adds the Load/Store pair instructions (Zilsd) and Compressed
Load/Store pair instructions (Zclsd).
[Specification
link](https://github.com/riscv/riscv-isa-manual/blob/main/src/zilsd.adoc).
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