================
@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+ : RISCVExtension<1, 0,
+ "Load/Store Pair Instructions">;
----------------
dong-miao wrote:
Many instruction sets that are only 32-bit or 64 bit have already been declared
and defined in this format. To reduce some code and disrupt the overall
definition format, it may not be a good choice.
https://github.com/llvm/llvm-project/pull/131094
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