https://github.com/dong-miao updated
https://github.com/llvm/llvm-project/pull/131094
>From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sat, 4 Jan 2025 17:53:58 +0800
Subject: [PATCH 01/16] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 39853cf13a920..41b96e1497e70 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
def : SysReg<"hvip", 0x645>;
def : SysReg<"htinst", 0x64A>;
def : SysReg<"hgeip", 0xE12>;
+def : SysReg<"hedelegh", 0x612>;
//===----------------------------------------------------------------------===//
// Hypervisor Configuration
@@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
+def : SysReg<"medelegh", 0x312>;
//===----------------------------------------------------------------------===//
// Machine Configuration
>From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sat, 4 Jan 2025 18:02:40 +0800
Subject: [PATCH 02/16] Update rv32-hypervisor-csr-names.s
---
llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
index aadee4fb4f3ad..79d87b3f2471c 100644
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
csrrs t1, vsiph, zero
# uimm12
csrrs t2, 0x254, zero
+
+##################################
+# Hypervisor Trap Setup
+##################################
+
+# hedelegh
+# name
+# CHECK-INST: csrrs t1, hedelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t1, hedelegh
+# uimm12
+# CHECK-INST: csrrs t2, hedelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
+# CHECK-INST-ALIAS: csrr t2, hedelegh
+# name
+csrrs t1, hedelegh, zero
+# uimm12
+csrrs t2, 0x612, zero
>From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sat, 4 Jan 2025 18:05:04 +0800
Subject: [PATCH 03/16] Update rv32-machine-csr-names.s
---
llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
index 3d527e382376e..9e929b7eddeed 100644
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
# uimm12
csrrs t2, 0x310, zero
+# medelegh
+# name
+# CHECK-INST: csrrs t1, medelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t1, medelegh
+# uimm12
+# CHECK-INST: csrrs t2, medelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
+# CHECK-INST-ALIAS: csrr t2, medelegh
+# name
+csrrs t1, medelegh, zero
+# uimm12
+csrrs t2, 0x312, zero
+
#########################
# Machine Configuration
#########################
>From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sun, 5 Jan 2025 11:12:53 +0800
Subject: [PATCH 04/16] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 41b96e1497e70..21f912bbc84d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>;
def : SysReg<"hvip", 0x645>;
def : SysReg<"htinst", 0x64A>;
def : SysReg<"hgeip", 0xE12>;
+let isRV32Only = 1 in
def : SysReg<"hedelegh", 0x612>;
//===----------------------------------------------------------------------===//
@@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
+let isRV32Only = 1 in
def : SysReg<"medelegh", 0x312>;
//===----------------------------------------------------------------------===//
>From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sun, 5 Jan 2025 11:30:33 +0800
Subject: [PATCH 05/16] Update rv32-only-csr-names.s
---
llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s
b/llvm/test/MC/RISCV/rv32-only-csr-names.s
index db88eacf9396b..1604469210193 100644
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11:
error: system registe
csrrs t1, htimedeltah, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'htimedeltah' is RV32 only
+csrrs t1, hedelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'hedelegh' is RV32 only
+
csrrs t1, mstatush, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'mstatush' is RV32 only
csrrs t1, menvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'menvcfgh' is RV32 only
csrrs t1, mseccfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'mseccfgh' is RV32 only
+csrrs t1, medelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'medelegh' is RV32 only
+
csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'pmpcfg1' is RV32 only
csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'pmpcfg3' is RV32 only
csrrs t1, pmpcfg5, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system
register 'pmpcfg5' is RV32 only
>From f77d8e363f598da42b7606ae28be3dcd13867856 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Sun, 5 Jan 2025 15:43:31 +0800
Subject: [PATCH 06/16] Update RISCVSystemOperands.td
---
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 21f912bbc84d1..01bb4a61ee013 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -148,6 +148,8 @@ def : SysReg<"hideleg", 0x603>;
def : SysReg<"hie", 0x604>;
def : SysReg<"hcounteren", 0x606>;
def : SysReg<"hgeie", 0x607>;
+let isRV32Only = 1 in
+def : SysReg<"hedelegh", 0x612>;
//===----------------------------------------------------------------------===//
// Hypervisor Trap Handling
@@ -158,8 +160,6 @@ def : SysReg<"hip", 0x644>;
def : SysReg<"hvip", 0x645>;
def : SysReg<"htinst", 0x64A>;
def : SysReg<"hgeip", 0xE12>;
-let isRV32Only = 1 in
-def : SysReg<"hedelegh", 0x612>;
//===----------------------------------------------------------------------===//
// Hypervisor Configuration
@@ -226,8 +226,10 @@ def : SysReg<"mideleg", 0x303>;
def : SysReg<"mie", 0x304>;
def : SysReg<"mtvec", 0x305>;
def : SysReg<"mcounteren", 0x306>;
-let isRV32Only = 1 in
+let isRV32Only = 1 in {
def : SysReg<"mstatush", 0x310>;
+def : SysReg<"medelegh", 0x312>;
+} // isRV32Only
//===----------------------------------------------------------------------===//
// Machine Trap Handling
@@ -241,8 +243,6 @@ def : SysReg<"mbadaddr", 0x343>;
def : SysReg<"mip", 0x344>;
def : SysReg<"mtinst", 0x34A>;
def : SysReg<"mtval2", 0x34B>;
-let isRV32Only = 1 in
-def : SysReg<"medelegh", 0x312>;
//===----------------------------------------------------------------------===//
// Machine Configuration
>From 2c3440f10357b41e9a19ddacf63f161c58bc5f45 Mon Sep 17 00:00:00 2001
From: dong-miao <601183...@qq.com>
Date: Thu, 13 Mar 2025 07:31:13 +0000
Subject: [PATCH 07/16] add extensions
---
$<TARGET_LINKER_FILE:cxx_shared> | 0
.../Driver/print-supported-extensions-riscv.c | 2 +
.../test/Preprocessor/riscv-target-features.c | 18 ++++
llvm/docs/RISCVUsage.rst | 2 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 14 ++-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 26 ++++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 15 ++++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td | 90 +++++++++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td | 36 ++++++++
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 11 ++-
llvm/test/CodeGen/RISCV/attributes.ll | 4 +
llvm/test/MC/RISCV/attribute-arch.s | 6 ++
llvm/test/MC/RISCV/rv32zclsd-invalid.s | 22 +++++
llvm/test/MC/RISCV/rv32zclsd-valid.s | 18 ++++
llvm/test/MC/RISCV/rv32zilsd-invalid.s | 12 +++
llvm/test/MC/RISCV/rv32zilsd-valid.s | 25 ++++++
.../TargetParser/RISCVISAInfoTest.cpp | 2 +
18 files changed, 301 insertions(+), 4 deletions(-)
create mode 100644 $<TARGET_LINKER_FILE:cxx_shared>
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
create mode 100644 llvm/test/MC/RISCV/rv32zclsd-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zclsd-valid.s
create mode 100644 llvm/test/MC/RISCV/rv32zilsd-invalid.s
create mode 100644 llvm/test/MC/RISCV/rv32zilsd-valid.s
diff --git a/$<TARGET_LINKER_FILE:cxx_shared> b/$<TARGET_LINKER_FILE:cxx_shared>
new file mode 100644
index 0000000000000..e69de29bb2d1d
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index 4d6e112f4e387..e5724f51acdc4 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -185,7 +185,9 @@
// CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD))
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
+// CHECK-NEXT: zilsd 1.0 'zilsd' (Load/Store pair
instructions)
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and
Store-Release Instructions)
+// CHECK-NEXT: zclsd 1.0 'zclsd' (Compressed
Load/Store pair instructions)
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless
Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM
instructions for Cryptography)
// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index c219771135275..a2c876f09dbee 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -108,6 +108,7 @@
// CHECK-NOT: __riscv_zcd {{.*$}}
// CHECK-NOT: __riscv_zce {{.*$}}
// CHECK-NOT: __riscv_zcf {{.*$}}
+// CHECK-NOT: __riscv_zclsd {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zcmp {{.*$}}
// CHECK-NOT: __riscv_zcmt {{.*$}}
@@ -133,6 +134,7 @@
// CHECK-NOT: __riscv_zihintntl {{.*$}}
// CHECK-NOT: __riscv_zihintpause {{.*$}}
// CHECK-NOT: __riscv_zihpm {{.*$}}
+// CHECK-NOT: __riscv_zilsd {{.*$}}
// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_zk {{.*$}}
// CHECK-NOT: __riscv_zkn {{.*$}}
@@ -922,6 +924,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_zclsd1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCLSD-EXT %s
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_zclsd1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCLSD-EXT %s
+// CHECK-ZCLSD-EXT: __riscv_zclsd 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32i_zcmop1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
@@ -1118,6 +1128,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHPM-EXT %s
// CHECK-ZIHPM-EXT: __riscv_zihpm 2000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_zilsd1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZILSD-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64i_zilsd1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZILSD-EXT %s
+// CHECK-ZILSD-EXT: __riscv_zilsd 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32i_zimop1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 63185fe67440c..ec3e7ae99902c 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -179,6 +179,7 @@ on support follow.
``Zcb`` Supported
``Zcd`` Supported
``Zcf`` Supported
+ ``Zclsd`` Supported
``Zcmop`` Supported
``Zcmp`` Supported
``Zcmt`` Assembly Support
@@ -205,6 +206,7 @@ on support follow.
``Zihintntl`` Supported
``Zihintpause`` Assembly Support
``Zihpm`` (`See Note <#riscv-i2p1-note>`__)
+ ``Zilsd`` Support
``Zimop`` Supported
``Zkn`` Supported
``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 541979a0f70e8..1e51314f90440 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -219,7 +219,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
ParseStatus parseRegReg(OperandVector &Operands);
ParseStatus parseRetval(OperandVector &Operands);
ParseStatus parseZcmpStackAdj(OperandVector &Operands,
- bool ExpectNegative = false);
+ bool ExpectNegative = false);
ParseStatus parseZcmpNegStackAdj(OperandVector &Operands) {
return parseZcmpStackAdj(Operands, /*ExpectNegative*/ true);
}
@@ -487,6 +487,18 @@ struct RISCVOperand final : public MCParsedAsmOperand {
Reg.RegNum);
}
+ bool isGPRPairC() const {
+ return Kind == KindTy::Register &&
+ RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID].contains(
+ Reg.RegNum);
+ }
+
+ bool isGPRPairNoX0() const {
+ return Kind == KindTy::Register &&
+ RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID].contains(
+ Reg.RegNum);
+ }
+
bool isGPRF16() const {
return Kind == KindTy::Register &&
RISCVMCRegisterClasses[RISCV::GPRF16RegClassID].contains(Reg.RegNum);
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 61deaa827a6df..8631bed8ae5af 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -208,6 +208,32 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst,
uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder)
{
+ if (RegNo >= 8 || RegNo % 2)
+ return MCDisassembler::Fail;
+
+ const RISCVDisassembler *Dis =
+ static_cast<const RISCVDisassembler *>(Decoder);
+ const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
+ MCRegister Reg = RI->getMatchingSuperReg(
+ RISCV::X8 + RegNo, RISCV::sub_gpr_even,
+ &RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t
RegNo,
+ uint64_t Address,
+ const MCDisassembler
*Decoder) {
+ if (RegNo == 0) {
+ return MCDisassembler::Fail;
+ }
+
+ return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
+}
+
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 24828cde28079..6c18680709f78 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -176,6 +176,13 @@ def HasStdExtZicfiss :
Predicate<"Subtarget->hasStdExtZicfiss()">,
"'Zicfiss' (Shadow stack)">;
def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
+def FeatureStdExtZilsd
+ : RISCVExtension<1, 0,
+ "'Zilsd' (Load/Store pair instructions)">;
+def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">,
+ AssemblerPredicate<(all_of FeatureStdExtZilsd),
+ "'Zilsd' (Load/Store pair
instructions)">;
+
// Multiply Extensions
def FeatureStdExtZmmul
@@ -401,6 +408,14 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>;
+def FeatureStdExtZclsd
+ : RISCVExtension<1, 0,
+ "Compressed Load/Store pair instructions",
+ [FeatureStdExtZilsd,FeatureStdExtZca]>;
+def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd() &&
!Subtarget->hasStdExtZcf()">,
+ AssemblerPredicate<(all_of FeatureStdExtZclsd),
+ "'Zclsd' (Compressed Load/Store pair instructions)">;
+
def FeatureStdExtZcmp
: RISCVExtension<1, 0,
"sequenced instructions for code-size reduction",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index a4e420ed8fcf3..8ca5dd382ff70 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2135,12 +2135,14 @@ include "RISCVInstrInfoZvk.td"
include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZcmop.td"
+include "RISCVInstrInfoZclsd.td"
// Integer
include "RISCVInstrInfoZimop.td"
include "RISCVInstrInfoZicbo.td"
include "RISCVInstrInfoZicond.td"
include "RISCVInstrInfoZicfiss.td"
+include "RISCVInstrInfoZilsd.td"
//===----------------------------------------------------------------------===//
// Vendor extensions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
new file mode 100644
index 0000000000000..34786cacdfc41
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -----------------------------*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+ let Name = "GPRPairNoX0RV32";
+ let ParserMethod = "parseGPRPair<false>";
+ let PredicateMethod = "isGPRPairNoX0";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand<GPRPairNoX0> {
+ let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+ let Name = "GPRPairCRV32";
+ let ParserMethod = "parseGPRPair<false>";
+ let PredicateMethod = "isGPRPairC";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand<GPRPairC> {
+ let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad<bits<3> funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+ : RVInst16CI<funct3, 0b10, (outs RC:$rd), (ins SPMem:$rs1, opnd:$imm),
+ OpcodeStr, "$rd, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore<bits<3> funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+ : RVInst16CSS<funct3, 0b10, (outs), (ins RC:$rs2, SPMem:$rs1, opnd:$imm),
+ OpcodeStr, "$rs2, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri<bits<3> funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+ : RVInst16CL<funct3, 0b00, (outs RC:$rd), (ins GPRCMem:$rs1, opnd:$imm),
+ OpcodeStr, "$rd, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri<bits<3> funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+ : RVInst16CS<funct3, 0b00, (outs), (ins RC:$rs2,GPRCMem:$rs1, opnd:$imm),
+ OpcodeStr, "$rs2, ${imm}(${rs1})">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32,
uimm9_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
new file mode 100644
index 0000000000000..e1d7dbe37d9a2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -----------------------------*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r<string opcodestr, DAGOperand RC>
+ : RVInstI<0b011, OPC_LOAD, (outs RC:$rd),
+ (ins GPRMem:$rs1, simm12:$imm12),
+ opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r<string opcodestr, DAGOperand RC>
+ : RVInstS<0b011, OPC_STORE, (outs),
+ (ins RC:$rs2, GPRMem:$rs1, simm12:$imm12),
+ opcodestr, "${rs2}, ${imm12}(${rs1})">;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZilsd, IsRV32], DecoderNamespace = "RV32GPRPair" in
{
+def LD_RV32 : ld_r<"ld", GPRPairRV32>, Sched<[WriteLDD, ReadMemBase]>;
+def SD_RV32 : sd_r<"sd", GPRPairRV32>, Sched<[WriteSTD, ReadStoreData,
ReadMemBase]>;
+} // Predicates = [HasStdExtZilsd, IsRV32]
+
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index a5dfb5ba1a2fc..e507c4d6c7237 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -353,14 +353,19 @@ def GPRPair : RISCVRegisterClass<[XLenPairVT,
XLenPairFVT], 64, (add
X18_X19, X20_X21, X22_X23, X24_X25, X26_X27,
X0_Pair, X2_X3, X4_X5
)>;
+}// let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairRegisterClass"
+let RegInfos = XLenPairRI,
+ DecoderMethod = "DecodeGPRPairNoX0RegisterClass" in {
def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub
GPRPair, X0_Pair)>;
-} // let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairRegisterClass"
-
-let RegInfos = XLenPairRI in
+ }
+
+let RegInfos = XLenPairRI,
+ DecoderMethod = "DecodeGPRPairCRegisterClass" in {
def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
X10_X11, X12_X13, X14_X15, X8_X9
)>;
+} // let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairCRegisterClass"
//===----------------------------------------------------------------------===//
// Floating Point registers
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 29f84dc79b6ae..ea6e4aa9b836e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -124,7 +124,9 @@
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck
--check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck
--check-prefix=RV32ZVFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck
--check-prefix=RV32ZICOND %s
+; RUN: llc -mtriple=riscv32 -mattr=+zilsd %s -o - | FileCheck
--check-prefix=RV32ZILSD %s
; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck
--check-prefix=RV32ZIMOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zclsd %s -o - | FileCheck
--check-prefix=RV32ZCLSD %s
; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck
--check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck
--check-prefixes=CHECK,RV32SSAIA %s
@@ -444,7 +446,9 @@
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV32ZVFH: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
+; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0"
; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0"
+; RV32ZCLSD: .attribute 5, "rv32i2p1_zilsd1p0_zca1p0_zclsd1p0"
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s
b/llvm/test/MC/RISCV/attribute-arch.s
index a8bb9b7e6cef1..574b4cb45437e 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -255,6 +255,9 @@
.attribute arch, "rv32izcb1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcb1p0"
+.attribute arch, "rv32izclsd1p0"
+# CHECK: attribute 5, "rv32i2p1_zilsd1p0_zca1p0_zclsd1p0"
+
.attribute arch, "rv32izcmp1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
@@ -429,6 +432,9 @@
.attribute arch, "rv32i_zicfiss1p0"
# CHECK: .attribute 5, "rv32i2p1_zicfiss1p0_zicsr2p0_zimop1p0"
+.attribute arch, "rv32i_zilsd1p0"
+# CHECK: .attribute 5, "rv32i2p1_zilsd1p0"
+
.attribute arch, "rv64i_xsfvfwmaccqqq"
# CHECK: attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
diff --git a/llvm/test/MC/RISCV/rv32zclsd-invalid.s
b/llvm/test/MC/RISCV/rv32zclsd-invalid.s
new file mode 100644
index 0000000000000..720570e667a75
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zclsd-invalid.s
@@ -0,0 +1,22 @@
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zclsd < %s 2>&1 | FileCheck %s
+
+## GPRPairC
+c.ld t1, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+c.sd s2, 4(sp) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+
+## GPRPairNoX0
+c.ldsp x0, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.ldsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for
instruction
+
+## uimm9_lsb000
+c.ldsp t1, 512(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple
of 8 bytes in the range [0, 504]
+c.sdsp t1, -8(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple
of 8 bytes in the range [0, 504]
+## uimm8_lsb000
+c.ld s0, -8(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple
of 8 bytes in the range [0, 248]
+c.sd s0, 256(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple
of 8 bytes in the range [0, 248]
+
+# Invalid register names
+c.ld a1, 4(sp) # CHECK: :[[@LINE]]:6: error: register must be even
+c.sd a3, 4(sp) # CHECK: :[[@LINE]]:6: error: register must be even
+c.ldsp ra, 4(sp) # CHECK: :[[@LINE]]:8: error: register must be even
+c.ldsp t0, 4(sp) # CHECK: :[[@LINE]]:8: error: register must be even
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/rv32zclsd-valid.s
b/llvm/test/MC/RISCV/rv32zclsd-valid.s
new file mode 100644
index 0000000000000..79bdd53158372
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zclsd-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zclsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zclsd< %s \
+# RUN: | llvm-objdump --mattr=+zclsd --no-print-imm-hex -M no-aliases -d
-r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.ldsp t1, 176(sp)
+# CHECK-ASM: encoding: [0x4a,0x73]
+c.ldsp t1, 176(sp)
+# CHECK-ASM-AND-OBJ: c.sdsp t1, 360(sp)
+# CHECK-ASM: encoding: [0x9a,0xf6]
+c.sdsp t1, 360(sp)
+# CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
+# CHECK-ASM: encoding: [0x98,0x62]
+c.ld a4, 0(a3)
+# CHECK-ASM-AND-OBJ: c.sd s0, 248(a3)
+# CHECK-ASM: encoding: [0xe0,0xfe]
+c.sd s0, 248(a3)
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/rv32zilsd-invalid.s
b/llvm/test/MC/RISCV/rv32zilsd-invalid.s
new file mode 100644
index 0000000000000..80860be549380
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zilsd-invalid.s
@@ -0,0 +1,12 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+zilsd < %s 2>&1 | FileCheck %s
+
+# Out of range immediates
+## simm12
+ld t1, -2049(a0) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with
%lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+sd t1, 2048(a0) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with
%lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
+
+# Invalid register names
+ld t2, (4)a0 # CHECK: :[[@LINE]]:4: error: register must be even
+ld s3, (4)a0 # CHECK: :[[@LINE]]:4: error: register must be even
+sd t2, (10)s2 # CHECK: :[[@LINE]]:4: error: register must be even
+sd a7, (10)s2 # CHECK: :[[@LINE]]:4: error: register must be even
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/rv32zilsd-valid.s
b/llvm/test/MC/RISCV/rv32zilsd-valid.s
new file mode 100644
index 0000000000000..885506e85d4f4
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zilsd-valid.s
@@ -0,0 +1,25 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zilsd -M no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zilsd < %s \
+# RUN: | llvm-objdump --mattr=+zilsd --no-print-imm-hex -M no-aliases -d
-r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: ld t1, 12(a0)
+# CHECK-ASM: encoding: [0x03,0x33,0xc5,0x00]
+ld t1, 12(a0)
+# CHECK-ASM-AND-OBJ: ld a0, 4(a2)
+# CHECK-ASM: encoding: [0x03,0x35,0x46,0x00]
+ld a0, +4(a2)
+# CHECK-ASM-AND-OBJ: ld t1, -2048(a4)
+# CHECK-ASM: encoding: [0x03,0x33,0x07,0x80]
+ld t1, -2048(a4)
+# CHECK-ASM-AND-OBJ: ld t1, 2047(a4)
+# CHECK-ASM: encoding: [0x03,0x33,0xf7,0x7f]
+ld t1, 2047(a4)
+
+# CHECK-ASM-AND-OBJ: sd s0, 2047(a0)
+# CHECK-ASM: encoding: [0xa3,0x3f,0x85,0x7e]
+sd s0, 2047(a0)
+# CHECK-ASM-AND-OBJ: sd a0, -2048(a2)
+# CHECK-ASM: encoding: [0x23,0x30,0xa6,0x80]
+sd a0, -2048(a2)
\ No newline at end of file
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 0ca8add7e85b4..806fa94305e27 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -960,6 +960,7 @@ R"(All available -march extensions for RISC-V
zihintntl 1.0
zihintpause 2.0
zihpm 2.0
+ zilsd 1.0
zimop 1.0
zmmul 1.0
za128rs 1.0
@@ -981,6 +982,7 @@ R"(All available -march extensions for RISC-V
zcd 1.0
zce 1.0
zcf 1.0
+ zclsd 1.0
zcmop 1.0
zcmp 1.0
zcmt 1.0
>From faa59c94969ad4b6675e744185b609ac1b04a133 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:00:02 +0800
Subject: [PATCH 08/16] Update RISCVDisassembler.cpp
---
.../RISCV/Disassembler/RISCVDisassembler.cpp | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 8631bed8ae5af..03289880ca744 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -227,11 +227,17 @@ static DecodeStatus DecodeGPRPairCRegisterClass(MCInst
&Inst, uint32_t RegNo,
static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t
RegNo,
uint64_t Address,
const MCDisassembler
*Decoder) {
- if (RegNo == 0) {
- return MCDisassembler::Fail;
- }
-
- return DecodeGPRPairRegisterClass(Inst, RegNo, Address, Decoder);
+ if (RegNo >= 32 || RegNo % 2 || RegNo == 0)
+ return MCDisassembler::Fail;
+
+ const RISCVDisassembler *Dis =
+ static_cast<const RISCVDisassembler *>(Decoder);
+ const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
+ MCRegister Reg = RI->getMatchingSuperReg(
+ RISCV::X0 + RegNo, RISCV::sub_gpr_even,
+ &RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID]);
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
}
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
>From 4442de03b5c48f28409428bcf03f9df8875d4f56 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:10:51 +0800
Subject: [PATCH 09/16] Delete $<TARGET_LINKER_FILE:cxx_shared>
---
$<TARGET_LINKER_FILE:cxx_shared> | 0
1 file changed, 0 insertions(+), 0 deletions(-)
delete mode 100644 $<TARGET_LINKER_FILE:cxx_shared>
diff --git a/$<TARGET_LINKER_FILE:cxx_shared> b/$<TARGET_LINKER_FILE:cxx_shared>
deleted file mode 100644
index e69de29bb2d1d..0000000000000
>From 20fd842e47a9a04e2f9a8f9df7e83cb38db977df Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:12:18 +0800
Subject: [PATCH 10/16] Update RISCVDisassembler.cpp
---
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 03289880ca744..370f027b9c403 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -235,7 +235,7 @@ static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst
&Inst, uint32_t RegNo,
const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
MCRegister Reg = RI->getMatchingSuperReg(
RISCV::X0 + RegNo, RISCV::sub_gpr_even,
- &RISCVMCRegisterClasses[RISCV::GPRPairNoX0RegClassID]);
+ &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
>From 1fb709c645581fb94876ab4fbf1181eab9b9863f Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:22:47 +0800
Subject: [PATCH 11/16] Update RISCVDisassembler.cpp
---
.../RISCV/Disassembler/RISCVDisassembler.cpp | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 370f027b9c403..56f6b5e1326c2 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -223,23 +223,7 @@ static DecodeStatus DecodeGPRPairCRegisterClass(MCInst
&Inst, uint32_t RegNo,
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
-
-static DecodeStatus DecodeGPRPairNoX0RegisterClass(MCInst &Inst, uint32_t
RegNo,
- uint64_t Address,
- const MCDisassembler
*Decoder) {
- if (RegNo >= 32 || RegNo % 2 || RegNo == 0)
- return MCDisassembler::Fail;
-
- const RISCVDisassembler *Dis =
- static_cast<const RISCVDisassembler *>(Decoder);
- const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
- MCRegister Reg = RI->getMatchingSuperReg(
- RISCV::X0 + RegNo, RISCV::sub_gpr_even,
- &RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
- Inst.addOperand(MCOperand::createReg(Reg));
- return MCDisassembler::Success;
-}
-
+
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
>From 5a6103d8eb827d3cab491e1270ec36f8b75e1c2b Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:27:33 +0800
Subject: [PATCH 12/16] Update RISCVRegisterInfo.td
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index e507c4d6c7237..a3d03f63a5d48 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -353,13 +353,10 @@ def GPRPair : RISCVRegisterClass<[XLenPairVT,
XLenPairFVT], 64, (add
X18_X19, X20_X21, X22_X23, X24_X25, X26_X27,
X0_Pair, X2_X3, X4_X5
)>;
-}// let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairRegisterClass"
-let RegInfos = XLenPairRI,
- DecoderMethod = "DecodeGPRPairNoX0RegisterClass" in {
def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub
GPRPair, X0_Pair)>;
- }
-
+} // let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairRegisterClass"
+
let RegInfos = XLenPairRI,
DecoderMethod = "DecodeGPRPairCRegisterClass" in {
def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
>From f7c4cf4a193e16ba9a5ac7d41209d1dae8e98eeb Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:28:35 +0800
Subject: [PATCH 13/16] Update RISCVAsmParser.cpp
---
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 1e51314f90440..8603cd59ae2bb 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -219,7 +219,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
ParseStatus parseRegReg(OperandVector &Operands);
ParseStatus parseRetval(OperandVector &Operands);
ParseStatus parseZcmpStackAdj(OperandVector &Operands,
- bool ExpectNegative = false);
+ bool ExpectNegative = false);
ParseStatus parseZcmpNegStackAdj(OperandVector &Operands) {
return parseZcmpStackAdj(Operands, /*ExpectNegative*/ true);
}
>From 54780fad46828676935d255c148b77496365ee30 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:44:46 +0800
Subject: [PATCH 14/16] Update riscv-target-features.c
---
clang/test/Preprocessor/riscv-target-features.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index a2c876f09dbee..67e4dfc3db3e9 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -924,9 +924,6 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 1000000{{$}}
-// RUN: %clang --target=riscv32-unknown-linux-gnu \
-// RUN: -march=rv32i_zclsd1p0 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZCLSD-EXT %s
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32i_zclsd1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCLSD-EXT %s
@@ -1131,9 +1128,6 @@
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32i_zilsd1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZILSD-EXT %s
-// RUN: %clang --target=riscv64-unknown-linux-gnu \
-// RUN: -march=rv64i_zilsd1p0 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZILSD-EXT %s
// CHECK-ZILSD-EXT: __riscv_zilsd 1000000{{$}}
// RUN: %clang --target=riscv32-unknown-linux-gnu \
>From 1387e89aa5a513d30e8f690b72591ff9cdcd03cf Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 16:45:27 +0800
Subject: [PATCH 15/16] Update RISCVUsage.rst
---
llvm/docs/RISCVUsage.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index ec3e7ae99902c..1864c14fe75be 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -206,7 +206,7 @@ on support follow.
``Zihintntl`` Supported
``Zihintpause`` Assembly Support
``Zihpm`` (`See Note <#riscv-i2p1-note>`__)
- ``Zilsd`` Support
+ ``Zilsd`` Supported
``Zimop`` Supported
``Zkn`` Supported
``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__)
>From fc5246485a95c073b7cd3708c467273c3caf2a80 Mon Sep 17 00:00:00 2001
From: dong-miao <miaozhendon...@mails.ucas.ac.cn>
Date: Thu, 13 Mar 2025 17:02:42 +0800
Subject: [PATCH 16/16] Update print-supported-extensions-riscv.c
---
clang/test/Driver/print-supported-extensions-riscv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index e5724f51acdc4..f01fafad21592 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -50,6 +50,7 @@
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed
Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zce 1.0 'Zce' (Compressed extensions
for microcontrollers)
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed
Single-Precision Floating-Point Instructions)
+// CHECK-NEXT: zclsd 1.0 'zclsd' (Compressed
Load/Store Pair Instructions)
// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed
May-Be-Operations)
// CHECK-NEXT: zcmp 1.0 'Zcmp' (sequenced
instructions for code-size reduction)
// CHECK-NEXT: zcmt 1.0 'Zcmt' (table jump
instructions for code-size reduction)
@@ -60,6 +61,7 @@
// CHECK-NEXT: zbkc 1.0 'Zbkc' (Carry-less multiply
instructions for Cryptography)
// CHECK-NEXT: zbkx 1.0 'Zbkx' (Crossbar permutation
instructions)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit
Instructions)
+// CHECK-NEXT: zilsd 1.0 'zilsd' (Load/Store Pair
Instructions)
// CHECK-NEXT: zk 1.0 'Zk' (Standard scalar
cryptography extension)
// CHECK-NEXT: zkn 1.0 'Zkn' (NIST Algorithm Suite)
// CHECK-NEXT: zknd 1.0 'Zknd' (NIST Suite: AES
Decryption)
@@ -185,9 +187,7 @@
// CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD))
// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad)
// CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack)
-// CHECK-NEXT: zilsd 1.0 'zilsd' (Load/Store pair
instructions)
// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and
Store-Release Instructions)
-// CHECK-NEXT: zclsd 1.0 'zclsd' (Compressed
Load/Store pair instructions)
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless
Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM
instructions for Cryptography)
// CHECK-NEXT: sdext 1.0 'Sdext' (External debugger)
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