https://github.com/topperc approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/66043
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https://github.com/yetingk edited
https://github.com/llvm/llvm-project/pull/66043
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@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
+static const char *ImpliedExtsZicfiss[] = {"
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -60,12 +60,3 @@ defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010,
"ssamoswap.w">;
let Predicates = [HasStdExtZicfiss, IsRV64] in
defm SSAMOSWAP_D : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
-
-//===--==
@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
+static const char *ImpliedExtsZicfiss[] = {"
@@ -1024,6 +1024,7 @@ static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zhinxmin"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
+static const char *ImpliedExtsZicfiss[] = {"
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 4a73535ec7206951c6b843e11c81e6c0c01cc1d0 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
wangpc-pp wrote:
It seems that the author of Zimop implementation doesn't have commit access.
@yetingk Would you mind to commit it and rebase your PR on that? It will make
this PR simpler.
https://github.com/llvm/llvm-project/pull/66043
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@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRX1X5 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
topperc wrote:
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 01222b781e3a0a925d2cdf793c54c7d6050f82af Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH] [RISCV] Add MC layer support for Zicfiss.
The patch adds the instru
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/4] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/3] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,86 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
llvmbot wrote:
@llvm/pr-subscribers-llvm-support
Changes
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to
support shadow stack for control flow integrity. This patch is based on version
[0.3.1].
[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
yetingk wrote:
Do
https://github.com/yetingk updated
https://github.com/llvm/llvm-project/pull/66043
>From 91bb1d9884276a37f93515a648aa6ece353fdc70 Mon Sep 17 00:00:00 2001
From: Yeting Kuo
Date: Tue, 12 Sep 2023 12:28:00 +0800
Subject: [PATCH 1/2] [RISCV] Add MC layer support for Zicfiss.
The patch adds the in
@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>;
def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9),
(sequence "X%u", 18, 23))>;
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
tclin914 wrote:
I
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Changes
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to
support shadow stack for control flow integrity. This patch is based on version
[0.3.1].
[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
-
llvmbot wrote:
@llvm/pr-subscribers-mc
Changes
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to
support shadow stack for control flow integrity. This patch is based on version
[0.3.1].
[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
--
Patch is
llvmbot wrote:
@llvm/pr-subscribers-clang
Changes
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to
support shadow stack for control flow integrity. This patch is based on version
[0.3.1].
[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
--
Patch
https://github.com/llvmbot labeled
https://github.com/llvm/llvm-project/pull/66043
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https://github.com/yetingk created
https://github.com/llvm/llvm-project/pull/66043:
The patch adds the instructions in Zicfiss extension. Zicfiss extension is to
support shadow stack for control flow integrity. This patch is based on version
[0.3.1].
[0.3.1]: https://github.com/riscv/riscv-cf
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