[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

krasimir added a comment. > I just pushed 6cb42cd6669785f3b611106e1b6b38bbe65733a9 > to > hopefully fix this. Thank you Craig! That fixed it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. Never mind, I see you added a test for that case Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commits@

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. Does a double with `r` for RV32 work with that fix? That's supposed to give the low half of the register. You might need to also deal with the register pair class? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ h

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. In D93298#3355088 , @craig.topper wrote: > In D93298#3354313 , @krasimir wrote: > >> @achieveartificialintelligence thank you for looking into this, sorry for >> the late reply! >> >>

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. In D93298#3354313 , @krasimir wrote: > @achieveartificialintelligence thank you for looking into this, sorry for the > late reply! > > It looks like the latest version addresses @nikic's IR reproducer with > `-mtriple=riscv3

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

krasimir added a comment. @achieveartificialintelligence thank you for looking into this, sorry for the late reply! It looks like the latest version addresses @nikic's IR reproducer with `-mtriple=riscv32`. There seems to be an error trying this out with `-mtriple=riscv64`: % cat test.ll

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/zfinx-types.ll:5 +; RUN:| FileCheck --check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32f < %s \ +; RUN:| FileCheck --check-prefix=RV32IF %s craig.toppe

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG0e38b295435b: [RISCV] add the MC layer support of Zfinx extension (authored by achieveartificialintelligence). Herald added a project: All. Reposito

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 411959. achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added a comment. Address @craig.topper's comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.ll

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/zfinx-types.ll:5 +; RUN:| FileCheck --check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32f < %s \ +; RUN:| FileCheck --check-prefix=RV32IF %s I'm not sur

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Are there any other errors now? @krasimir @nikic Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits ma

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 411734. achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added a comment. Address @jrtc27's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.or

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10923-10924 - return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); + std::pair Res; + Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); + ---

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 411719. achieveartificialintelligence added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Support/RISCVISAIn

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Can you help test if this patch works fine now? @krasimir Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-c

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 411375. achieveartificialintelligence added a comment. Thanks for @craig.topper's patch! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files:

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. Here's a fix that I tested on the original repreoduce. It detects that we picked one of the new register classes and tries to redirect back to the normal GPR register class if the GPR register class has the same width. I also checked for MVT::Other to use the GPR c

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

krasimir added a comment. In D93298#3342480 , @achieveartificialintelligence wrote: > In D93298#3342452 , @krasimir wrote: > >> @achieveartificialintelligence any progress with the problematic IR? Have >> you been

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. In D93298#3342452 , @krasimir wrote: > @achieveartificialintelligence any progress with the problematic IR? Have you > been able to reproduce using nikic's reduced example? Sorry, I don't have a solution rig

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

krasimir added a comment. @achieveartificialintelligence any progress with the problematic IR? Have you been able to reproduce using nikic's reduced example? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

nikic added a comment. Because I happened to also run into this, reduced IR for `-mtriple=riscv32 -mattr=+d` is: define float @test(float %x) { %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.00e+00) ret float 0.00e+00 } Repository: rG

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

xbolva00 added a comment. In D93298#3332058 , @jrtc27 wrote: > In D93298#3332038 , @xbolva00 wrote: > It appears that this is causing an assertion segfault in a rustc test over at our experimental rust +

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. In D93298#3332038 , @xbolva00 wrote: >>> It appears that this is causing an assertion segfault in a rustc test over >>> at our experimental rust + llvm@head bot: > > I dont think that patch author is required to debug this issue fo

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

xbolva00 added a comment. >> It appears that this is causing an assertion segfault in a rustc test over >> at our experimental rust + llvm@head bot: I dont think that patch author is required to debug this issue for "experimental rust + llvm@head" - downstream. >> Since I don't have a rust env

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. In D93298#3332020 , @achieveartificialintelligence wrote: > @krasimir Since I don't have a rust environment, can you help me to test if > D120130 works? Hm, actually, looking at the log, it does

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. @krasimir Since I don't have a rust environment, can you help me to test if D120130 works? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.l

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. In D93298#3331641 , @krasimir wrote: > It appears that this is causing an assertion segfault in a `rustc` test over > at our experimental rust + llvm@head bot: > https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/buil

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

krasimir added a comment. It appears that this is causing an assertion segfault in a `rustc` test over at our experimental rust + llvm@head bot: https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706 The test is https://github.co

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Thanks all! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. achieveartificialintelligence marked an inline comment as done. Closed by commit rG7798ecca9c3d: [RISCV] add the MC layer support of Zfinx extension (authored by achiev

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In that case, LGTM (needs a rebase though). Thanks for your patience on this @achieveartificialintelligence. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. In D93298#3326230 , @asb wrote: > I think all my comments have been addressed. @craig.topper - are you happy > your RegInfo question is addressed? I'm happy. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 _

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557 + +let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in +def GPRPF64 : RegisterClass<"RISCV"

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557 + +let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add Is register pair only on RV32 for used as f64? Reposi

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555 +def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add +X10_PD, X12_PD, X14_PD, X16_PD,

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 407482. achieveartificialintelligence marked 2 inline comments as done. achieveartificialintelligence added a comment. Address comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555 +def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add +X10_PD, X12_PD, X14_PD, X16_PD, Jim wrote: > Is

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

Jim added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555 +def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>; +def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add +X10_PD, X12_PD, X14_PD, X16_PD, Is XLenRI correct for GPR

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. In D93298#3296515 , @luismarques wrote: > Assuming this will be merged soon, do you want to submit a backport request > for the 14.0 branch? Yes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST A

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

luismarques added a comment. Assuming this will be merged soon, do you want to submit a backport request for the 14.0 branch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 404910. achieveartificialintelligence added a comment. Separate the Zhinxmin and Zhinx extensions. Inspired by D118581 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://review

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 402739. achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added a comment. @asb Thank you very much! Could you please take a look at what needs to be modified now? Repository: rG LLVM Githu

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. Not an issue for this MC-layer patch, but I've created https://github.com/riscv/riscv-zfinx/issues/14 to point out what seems to be an incorrect statement about the status quo on the ABI for 32-bit floating point types on RV64 in the Zfinx spec. Repository: rG LLVM Gith

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. Herald added a subscriber: pcwang-thead. Thanks for your work on this. The way you've managed to use multiclasses to handle this with the 'ExtInfo' definitions takes a bit of unpicking to follow, but it does a really good job of keeping the instruction definitions largely u

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 401528. achieveartificialintelligence added a comment. Address @craig.topper's comments. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 F

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:137 + +def GPR : RegisterClass<"RISCV", [XLenVT], 32, GPRAllocationList> { let RegInfos = XLenRI; Does putting this back the way it was and using "(add GPR)" in GPRF16,

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Ping. Any other suggestions? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commi

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 400733. achieveartificialintelligence added a comment. Herald added subscribers: alextsao1999, eopXD. rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.o

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 400256. achieveartificialintelligence added a comment. Rebase Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Support/RISCVISAIn

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 399527. achieveartificialintelligence marked 3 inline comments as done. achieveartificialintelligence added a comment. Address @craig.topper's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.l

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:687 // TODO: This has been removed in later specs, which specify that D implies F if (HasD && !HasF) return createStringError(errc::invalid_argument, Do we need the equiv

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 399270. achieveartificialintelligence added a comment. update Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Support/RISCVISAIn

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Ping. `Zfinx` has been ratified, could we spend some time on this patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 __

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 396373. achieveartificialintelligence added a comment. Update Part of Zfinx Codes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/li

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:489 +let Predicates = [HasStdExtZdinx] in { +def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX GPRF64Op:$rd, GPRF64Op:$rs, GPRF64Op:$rs)>; Aren't these aliases only valid f

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:69 {"zfh", RISCVExtensionVersion{0, 1}}, +{"zfinx", RISCVExtensionVersion{1, 0}}, +{"zdinx", RISCVExtensionVersion{1, 0}}, Do we need to enforce that these can't be mix

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence marked 6 inline comments as done. achieveartificialintelligence added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:164 +static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint64_t RegNo, +

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

MaskRay added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:164 +static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, Use `functionNa

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 379272. achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added a comment. Add arch info Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. In D93298#3020917 , @frasercrmck wrote: > In D93298#3014160 , @jrtc27 wrote: > >> The amount of duplication here really depresses me and is only going to get >> worse

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

frasercrmck added a comment. In D93298#3014160 , @jrtc27 wrote: > The amount of duplication here really depresses me and is only going to get > worse once codegen is added, but TableGen isn't able to have operands that > use different register classes ba

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 374131. achieveartificialintelligence added a comment. Address @jrtc27 's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/l

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:539 +let RegAltNameIndices = [ABIRegAltName] in { + foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, This needs to be coordinated with D95588; you both define GPR p

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. The amount of duplication here really depresses me and is only going to get worse once codegen is added, but TableGen isn't able to have operands that use different register classes based on even HwMode, that I know of, and whilst you could make use of multi classes to g

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. ping. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 373170. achieveartificialintelligence added a comment. fix CI error Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Target/RISCV

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 372866. achieveartificialintelligence added a comment. Updating D93298 : [RISCV] add the MC layer support of Zfinx extension Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://re

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 372863. achieveartificialintelligence added a comment. support zfinx-1.0-rc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Targ

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

StephenFan added a comment. In D93298#2544775 , @asb wrote: > In D93298#2544459 , @StephenFan > wrote: > >> According to @jrtc27 's review that is >> "As for Zfinx itself, well, the idea is fine, but I really det

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. In D93298#2544775 , @asb wrote: > In D93298#2544459 , @StephenFan > wrote: > >> According to @jrtc27 's review that is >> "As for Zfinx itself, well, the idea is fine, but I really detest

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. In D93298#2544459 , @StephenFan wrote: > According to @jrtc27 's review that is > "As for Zfinx itself, well, the idea is fine, but I really detest the way > it's being done as an extension to F/D/Zfh. Running F code on an FZfh core

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

StephenFan added a comment. In D93298#253 , @asb wrote: > I started reviewing this alongside the specification in > https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time > of writing, it seems to define "zfinx" but not "zfhinx

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. I started reviewing this alongside the specification in https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem to be used in this patch. I think intent is that rv32ifd_zfinx

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Herald added a subscriber: vkmr. Ping CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://list

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 314879. achieveartificialintelligence marked 5 inline comments as done. achieveartificialintelligence added a comment. Thanks for suggestions. We updated the code again. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:943 +static MCRegister convertGPRToGPRPD(MCRegister Reg) { + assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && !((Reg - RISCV::X0) & 1) && + "Invalid register");

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

StephenFan added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663 +OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector &Operands) { + switch (getLexer().getKind()) { StephenFan wrote: > jrtc27 wrote: > > Why can

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

StephenFan added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663 +OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector &Operands) { + switch (getLexer().getKind()) { jrtc27 wrote: > Why can't you just use parseR

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. In D93298#2477105 , @jrtc27 wrote: > Your tests look like copies of the F/D/Zfh tests with not all the comments > updated and instances of tests that just don't make sense for Zfinx. I only > skimmed them an

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. Your tests look like copies of the F/D/Zfh tests with not all the comments updated and instances of tests that just don't make sense for Zfinx. I only skimmed them and picked up a few issues, I haven't gone through them thoroughly, please do that yourself. ===

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence marked an inline comment as done. achieveartificialintelligence added a comment. In D93298#2457925 , @kito-cheng wrote: > Do you have implement register pair for rv32ifd_zfinx? I didn't saw the > related implementation, but I

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

StephenFan added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:983 + } + return Match_InvalidOperand; It seems like that this function is not useful. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https:/

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 314349. achieveartificialintelligence marked 2 inline comments as done. achieveartificialintelligence added a comment. Including Zfinx, zdinx. Zfhinx. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llv

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

StephenFan added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:102 +: InstAlias; + use GPR as instruction operand may cause the codegen part of zfinx report errors. Because the GPR has data type i32 or i64, However, the zfinx will

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence added a comment. Thanks. I've updated it. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cg

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 312444. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCV.td llvm/lib/Target/RISCV/RISCVIns

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence updated this revision to Diff 312395. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 Files: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RI

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

kito-cheng added a comment. Do you have implement register pair for rv32ifd_zfinx? I didn't saw the related implementation, but I could be wrong since I am not LLVM expert, in case you have implemented, you need a test case for that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST AC

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.h:40 : TargetInfo(Triple), HasM(false), HasA(false), HasF(false), HasD(false), -HasC(false), HasB(false), HasV(false), HasZfh(false) { LongDoubleWidth = 128; We real

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

jrtc27 added a comment. Firstly, please generate your diffs with full context (-U with a sufficiently-large number). Secondly, can we avoid having to do a bunch of duplication with some clever use of multiclasses for F/D/Zfh and pseudos? Though maybe it's small enough that the duplication is ea

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

achieveartificialintelligence created this revision. achieveartificialintelligence added reviewers: HsiangKai, rkruppe, kito-cheng, craig.topper, jrtc27, luismarques. Herald added subscribers: frasercrmck, NickHung, evandro, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, j