craig.topper added inline comments.
================
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:687
// TODO: This has been removed in later specs, which specify that D implies F
if (HasD && !HasF)
return createStringError(errc::invalid_argument,
----------------
Do we need the equivalent of this for Zfinx and Zdinx?
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:228
+let Predicates = [HasStdExtZdinx] in {
+def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs,
FPR64INX:$rs)>;
----------------
Don't we need IN32X aliases too?
================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:552
+
+def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add
+ (sequence "X%u", 10, 17),
----------------
Is possible to reference GPR here to avoid listing the allocation order again?
Similar to how GPRNoX0 does (sub GPR, X0). Not sure if there is a way to be
exactly another list.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D93298/new/
https://reviews.llvm.org/D93298
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