jrtc27 added a comment. In D93298#3331641 <https://reviews.llvm.org/D93298#3331641>, @krasimir wrote:
> It appears that this is causing an assertion segfault in a `rustc` test over > at our experimental rust + llvm@head bot: > https://buildkite.com/llvm-project/rust-llvm-integrate-prototype/builds/8430#167e6de5-2dd5-41c3-87d7-b6e3f3908371/262-706 > The test is > https://github.com/rust-lang/rust/blob/master/src/test/assembly/asm/riscv-types.rs. > These two lines appear to cause it (code compiles fine when removed): > > - `check_reg!(a0_f32 f32 "a0" "mv");` > https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L178 > - `check_reg!(a0_f64 f64 "a0" "mv");` > https://github.com/rust-lang/rust/blob/f838a425e3134d036a7d9632935111a569ac7446/src/test/assembly/asm/riscv-types.rs#L192 > > The assertion: > > Impossible reg-to-reg copy > UNREACHABLE executed at > [...]/rust/src/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:350 > > ... This is just MC layer support. Inline assembly interacts with CodeGen; I assume the register classes/constraints still need updating to support Zfinx. ================ Comment at: llvm/test/MC/RISCV/rv32i-invalid.s:1 -# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s ---------------- This is an unrelated change Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
