[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+ex

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112408/new/ https://reviews.llvm.org/D112408 ___

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

eopXD added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimen

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

achieveartificialintelligence added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=r

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:744 static const char *ImpliedExtsZfh[] = {"zfhmin"}; +static const char *ImpliedExtsZve64d[] = {"zve64f", "d"}; +static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; I t

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:186 + "with maximal 32 EEW and F extension)", + [FeatureStdExtZve32x, FeatureStdExtF]>; +def HasStdExtZve32f : Predicate<"SubTarget->hasStdExtZve32f()">; ---

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

eopXD added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1499 foreach nf=2-8 in { +// Vector Unit-strided Segment Instructions +def VLSEG#nf#E64_V : craig.topper wrote: > The unit-stride and strided with EEW=64 don't require RV

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1499 foreach nf=2-8 in { +// Vector Unit-strided Segment Instructions +def VLSEG#nf#E64_V : The unit-stride and strided with EEW=64 don't require RV64. Just the in

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

eopXD added a comment. We can land non-macro related code for zve first and continue on proceeding patches. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112408/new/ https://reviews.llvm.org/D112408 ___

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

eopXD marked an inline comment as not done. eopXD added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:184 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); +Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew)); +Builder.defineMacro("__ris

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:184 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); +Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew)); +Builder.defineMacro("__riscv_v_max_eew_fp", Twine(MaxEewFp)); -

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

eopXD marked 7 inline comments as done. eopXD added inline comments. Comment at: clang/lib/Basic/Targets/RISCV.cpp:184 Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); +Builder.defineMacro("__riscv_v_max_eew", Twine(MaxEew)); +Builder.defineMacro("__riscv_v

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:224 + +def HasStdExtVIntegerEEW32 +: Predicate<"Subtarget->hasStdExtV() || SubTarget->hasStdExtZve32x()">, Can we add the AssemblerPredicate to HasVInstructions and use that? Or we

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCV.td:225 +def HasStdExtVIntegerEEW32 +: Predicate<"Subtarget->hasStdExtV() || SubTarget->hasStdExtZve32x()">, + AssemblerPredicate< StdExtV depends on Zve64d which depends on Featu

[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:170 // D and Zfh imply F. bool hasVInstructionsAnyF() const { return HasStdExtV && hasStdExtF(); } unsigned getMaxInterleaveFactor() const { This needs to be the same