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Closed by commit rGd77cba6d474a: [Clang][DebugInfo] Emit narrower base types
for structured binding declarations… (authored by vhscampos).
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vhscampos marked an inline comment as done.
vhscampos added a comment.
@aprantl We have discussed internally a few options to implement correct debug
information in this case. But this will be future work.
For the time being, we believe it is better to have no debug information rather
than wron
vhscampos updated this revision to Diff 550298.
vhscampos added a comment.
- Redone test to cover only what's needed.
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vhscampos marked 3 inline comments as done.
vhscampos added inline comments.
Comment at: clang/test/CodeGenCXX/debug-info-structured-binding-bitfield.cpp:6
+ unsigned int y : 16;
+};
+
tmatheson wrote:
> This would be easier to check if the structs had meaningfu
vhscampos updated this revision to Diff 549359.
vhscampos added a comment.
- Addressed the one comment regarding code.
- Changed the test to use update_cc_test
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In cases where a structured binding declaration is made to a struct with
bitfields:
struct A {
unsigned int x : 16;
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vhscampos updated this revision to Diff 474029.
vhscampos added a comment.
Rebasing and conflict resolution
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@tschuett Do you want me to put the note about 'native' detection for
neoverse-v2 back?
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vhscampos updated this revision to Diff 472583.
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Added SSBS
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vhscampos marked an inline comment as done.
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Comment at: clang/docs/ReleaseNotes.rst:696
-- Add driver and tuning support for Neoverse V2 via the flag
``-mcpu=neoverse-v2``.
- Native detection is also supported via ``-mcpu=native``.
---
vhscampos updated this revision to Diff 472567.
vhscampos added a comment.
Added AEK_FLAM to the list of features for Cortex-X3
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vhscampos added inline comments.
Comment at: clang/docs/ReleaseNotes.rst:699
+
+ * Arm cortex-A715 (cortex-a715).
Please capitalise the first cortex-A715. It should be "Arm Cortex-A715".
Comment at: llvm/docs/ReleaseNotes.rst:84
+* Added s
vhscampos updated this revision to Diff 472001.
vhscampos added a comment.
Combining release notes of Cortex-X3 and Neoverse V2.
Make cortex-x3 use neoverse-v2 model.
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We found an issue in the list of target features for v9-A. This patch will be
affected.
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vhscampos added inline comments.
Comment at: llvm/docs/ReleaseNotes.rst:84
+* Added support for the Cortex-X3 CPU.
+
vhscampos wrote:
> dmgreen wrote:
> > Can you add a reference to neoverse-v2 too.
> I could do this in another patch, but I prefer to restrict t
vhscampos added inline comments.
Comment at: llvm/docs/ReleaseNotes.rst:84
+* Added support for the Cortex-X3 CPU.
+
dmgreen wrote:
> Can you add a reference to neoverse-v2 too.
I could do this in another patch, but I prefer to restrict this one to X3.
Reposi
vhscampos updated this revision to Diff 470449.
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Comments addressed
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Cortex-X3 is an Armv9-A AArch64 CPU.
This patch i
vhscampos added a comment.
For reference, another small reproducer of the crash, but with a different
stack trace than the first example posted here:
// Must compile with -std=c++03 to crash
#include
int main(int, char**)
{
int i[3] = {1, 2, 3};
int j[3] = {4, 5, 6};
std:
vhscampos added inline comments.
Comment at: clang/lib/CodeGen/CGExprConstant.cpp:2217
assert(E->isFileScope() && "not a file-scope compound literal expr");
- return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+ ConstantEmitter emitter(*this, nullptr);
+ return tryEmit
vhscampos added inline comments.
Comment at: clang/lib/CodeGen/CGExprConstant.cpp:2217
assert(E->isFileScope() && "not a file-scope compound literal expr");
- return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+ ConstantEmitter emitter(*this, nullptr);
+ return tryEmit
vhscampos accepted this revision.
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This revision is now accepted and ready to land.
LGTM, thanks
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This revision is now accepted and ready to land.
LGTM
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I don't see any problem with the patch, but we should wait on @SjoerdMeijer.
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Comment at: clang/lib/Basic/Targets/ARM.cpp:929-949
+ if (ArchKind == llvm::ARM::ArchKind::ARMV8A ||
+ ArchKind == llvm::ARM::ArchKind::ARMV8R ||
+ ArchKind == llvm::ARM::ArchKind::ARMV8_1A ||
+ ArchKind == llvm::ARM::ArchKind::ARM
vhscampos accepted this revision.
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This revision is now accepted and ready to land.
LGTM.
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Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:2979
+def warn_unsupported_branch_protection_spec : Warning<
+ "unsupported branch protection specification '%0'">,
InGroup;
+
Still need to remove extraneous whitesp
vhscampos added inline comments.
Comment at: clang/lib/Basic/Targets/AArch64.cpp:134-135
StringRef &Err) const {
- llvm::AArch64::ParsedBranchProtection PBP;
- if (!llvm::AArch64::parseBranchProtection(Spec, PBP, Err))
+ llvm::
vhscampos added inline comments.
Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:4083
def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>;
+def : t2InstAlias<"pacbti$p r12,lr,sp", (t2HINT 13, pred:$p), 1>;
+def : t2InstAlias<"bti$p", (t2HINT 15, pred:$p), 1>;
--
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To the relevant persons I have just added to the review: @srhines
@nickdesaulniers @llozano
The cryptographic extensions will **//NOT//** be enabled by default on Armv9-A
and on Armv9-A ARM CPUs.
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vhscampos updated this revision to Diff 376228.
vhscampos edited the summary of this revision.
vhscampos added a comment.
1. Disable the cryptographic extensions by default.
2. Small fix in TargetParserTest.cpp to include different spellings of the
-march values.
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vhscampos updated this revision to Diff 374207.
vhscampos added a comment.
Added 'the' for better phrasing.
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vhscampos updated this revision to Diff 374162.
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Add missing . to end of sentences in comments.
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Sorry @SjoerdMeijer , I found a bug in the implementation (as described in the
latest comment). Therefore I kindly ask another round of review, please.
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vhscampos updated this revision to Diff 373943.
vhscampos added a comment.
1. Fix bug in "+sve2" feature position in the target features list. It was
being inserted at the end, which made it impossible to disable it using
+nosve2, as the positive option would always be placed after the negative
vhscampos added inline comments.
Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:413
- auto V8_6Pos = llvm::find(Features, "+v8.6a");
- if (V8_6Pos != std::end(Features))
-V8_6Pos = Features.insert(std::next(V8_6Pos), {"+i8mm", "+bf16"});
+ const char *Archs[] =
vhscampos updated this revision to Diff 372473.
vhscampos marked 3 inline comments as done.
vhscampos added a comment.
1. Enable the SVE2 extension as default.
2. Remove out of date comments in tests.
3. Remove unrelated change.
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armv9-a, armv9.1-a and armv9.2-a can be targeted using the -march o
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Thanks Peter. Since one week has passed, I plan to commit these changes by the
end of the day if nothing surfaces.
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vhscampos updated this revision to Diff 337723.
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Add a clarifying comment.
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Clang only defines __VFP_FP__ when the FPU is enabled. However, gcc
defines it unconditionally.
vhscampos added a comment.
@Tyker This is causing another build failure in another example:
[2858/4034] Building CXX object
tools/clang/examples/Attribute/CMakeFiles/Attribute.dir/Attribute.cpp.o
FAILED:
tools/clang/examples/Attribute/CMakeFiles/Attribute.dir/Attribute.cpp.o
CCACHE_CPP2=
vhscampos added a comment.
Not really. Closing it
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Closed by commit rGd1a3396bfbc6: [Driver][ARM] Disable unsupported features
when nofp arch extension is used (authored by vhscampos).
Changed prior to commit:
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vhscampos updated this revision to Diff 280072.
vhscampos added a comment.
1. Add comment explaining the MVE-Integer detail.
2. Add another test to check the disabled features.
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Ping.
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vhscampos updated this revision to Diff 275392.
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1. Merged the second patch into this (handle bf16).
2. Do the same treatment for -mcpu.
3. Instead of doing string search once again, return t
vhscampos marked 2 inline comments as done.
vhscampos added inline comments.
Comment at: clang/lib/Driver/ToolChains/Arch/ARM.cpp:292-297
+ auto checkFPDisabledInArchName = [](const StringRef &ArchName) {
+SmallVector Split;
+ArchName.split(Split, '+', -1, false);
+r
vhscampos marked 2 inline comments as done.
vhscampos added a comment.
I will merge the two patches into one.
Please also see my inline responses.
Comment at: clang/lib/Driver/ToolChains/Arch/ARM.cpp:288
+static void appendNoFPUnsupportedFeatures(const arm::FloatABI ABI,
+
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A list of target features
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vhscampos retitled this revision from "Disable bf16 when hardware FP support is
missing" to "[Driver][ARM] Disable bf16 when hardware FP support is missing".
vhscampos edited the summary of this
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A list of target features is disabled when there is no hardware
floating-point support. This is the case when one of the following
op
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Whenever Neon is not supported, a generic message is printed:
error: "NEON support not enabled"
Followed by a series of other err
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Add support for vcadd_* family of intrinsics. This set of intrinsics is
available in Armv8.3-A.
The fp16 versions require the FP16 extension, which h
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Closed by commit rGf6e11a36c49c: [ARM][AArch64] Implement __cls, __clsl and
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Closed by commit rG5d35b7d9e1a3: [ARM][AArch64] Implement __arm_rsrf,
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vhscampos marked an inline comment as done.
vhscampos added a comment.
Added support for `__clsll` as requested.
Comment at: clang/lib/Headers/arm_acle.h:150
+__clsl(unsigned long __t) {
+#if __SIZEOF_LONG__ == 4
+ return __builtin_arm_cls(__t);
compnerd wrote
vhscampos updated this revision to Diff 226430.
vhscampos added a comment.
Add support for __clsll.
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vhscampos updated this revision to Diff 226406.
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Use __builtin_bit_cast to perform the relevant bitcasts.
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Comment at: clang/lib/Headers/arm_acle.h:150
+__clsl(unsigned long __t) {
+#if __SIZEOF_LONG__ == 4
+ return __builtin_arm_cls(__t);
compnerd wrote:
> vhscampos wrote:
> > compnerd wrot
vhscampos updated this revision to Diff 226015.
vhscampos added a comment.
Run clang-format
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Adding support for ACLE intrinsics.
Patch by Michael Platings.
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Comment at: clang/lib/Headers/arm_acle.h:150
+__clsl(unsigned long __t) {
+#if __SIZEOF_LONG__ == 4
+ return __builtin_arm_cls(__t);
compnerd wrote:
> I don't see a pattern match for th
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Writing support for two ACLE functions:
unsigned int __cls(uint32_t x)
unsigned int __clsl(unsigned long x)
CLS stands for "Count number of lead
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