@@ -386,13 +386,29 @@ llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(
if (ContainedTy.isNull())
return nullptr;
-assert(!ResAttrs.RawBuffer &&
- "Raw buffers handles are not implemented for SPIR-V yet");
assert(!ResAttrs.IsROV &&
@@ -711,13 +711,14 @@
BuiltinTypeDeclBuilder::addHandleAccessFunction(DeclarationName &Name,
using PH = BuiltinTypeMethodBuilder::PlaceHolder;
QualType ElemTy = getHandleElementType();
- // TODO: Map to an hlsl_device address space.
- QualType ElemPtrTy = AST.getPointer
@@ -386,13 +386,22 @@ llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(
if (ContainedTy.isNull())
return nullptr;
-assert(!ResAttrs.RawBuffer &&
- "Raw buffers handles are not implemented for SPIR-V yet");
assert(!ResAttrs.IsROV &&
@@ -57,22 +58,37 @@ void main(unsigned GI : SV_GroupIndex) {
// CHECK: define void @main()
// CHECK-NEXT: entry:
// Verify destructor is emitted
-// NOINLINE-NEXT: call void @_GLOBAL__sub_I_GlobalDestructors.hlsl()
-// NOINLINE-NEXT: %0 = call i32 @llvm.dx.flattened.th
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/133468
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@@ -386,13 +386,22 @@ llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(
if (ContainedTy.isNull())
return nullptr;
-assert(!ResAttrs.RawBuffer &&
- "Raw buffers handles are not implemented for SPIR-V yet");
assert(!ResAttrs.IsROV &&
https://github.com/Keenuts approved this pull request.
minor comments, otherwise OK
https://github.com/llvm/llvm-project/pull/133468
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https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/133469
Destructor calls were emitted without convergence
intrinsics when building for SPIR-V, which means invalid IR since we mixed
controlled and non-controlled convergence.
From 339d410e981b5172c57d9802e0a0fcc117575
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/133464
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Keenuts wrote:
> Is there a reason we can't do this in Sema? It would probably be ideal to
> have the AST represent the address spaces of values accurately.
Hello! So I didn't recalled the details on why, so I made another PR which
implements this in sema (https://github.com/llvm/llvm-project/
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/133464
In SPIR-V, private global variables have the Private storage class. This PR
adds a new address space which allows frontend to emit variable with this
storage class when targeting this backend.
This is covered
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/122103
From c11ace708fab316f422e12cf9785a5a362d7250c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Thu, 28 Nov 2024 15:00:56 +0100
Subject: [PATCH 1/3] [SPIR-V] Add hlsl_private address space for
@@ -5386,6 +5386,23 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const
VarDecl *D) {
if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS))
return AS;
}
+
+ if (LangOpts.HLSL) {
+if (D == nullptr)
+ return LangAS::hlsl_private;
+
+// Except
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -std=hlsl202x
-emit-llvm -o - -disable-llvm-passes %s | FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -triple spirv-pc-vulkan1.3-compute -std=hlsl202x -emit-llvm
-o - -disable-llvm-passes %s |
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/130672
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@@ -0,0 +1,501 @@
+//===- LowerGPUIntrinsic.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/122103
From c11ace708fab316f422e12cf9785a5a362d7250c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Thu, 28 Nov 2024 15:00:56 +0100
Subject: [PATCH 1/2] [SPIR-V] Add hlsl_private address space for
Keenuts wrote:
Hi all!
This PR was dormant for a while because proposals had to be made & merged.
The HLSL proposal which covers `hlsl_private` is now merged:
https://github.com/llvm/wg-hlsl/commit/4c9e11aa50727c53b10d232195fb88fd5376f19c
https://github.com/llvm/llvm-project/pull/122103
__
@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
Hi again! It's been a while, but this now went through an HLSL proposal.
https://github.com/llvm/wg-hlsl/commit/4c9e11aa507
@@ -5362,6 +5362,23 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const
VarDecl *D) {
if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS))
return AS;
}
+
+ if (LangOpts.HLSL) {
+if (D == nullptr)
+ return LangAS::hlsl_private;
+
+// Except
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/121961
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@@ -1468,9 +1468,14 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) {
// Set specific Vulkan version if applicable.
if (const Arg *A = Args.getLastArg(options::OPT_fspv_target_env_EQ)) {
- const llvm::StringSet<> ValidValues = {"vulkan1.2",
@@ -83,6 +84,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_private
---
@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
This being a small stepping stone for the larger change bringing
hlsl_input/hlsl_output, I haven't wrote a specific HLSL s
https://github.com/Keenuts approved this pull request.
SPIR-V failure is unrelated, known issue with ccache
https://github.com/llvm/llvm-project/pull/122105
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@@ -83,6 +84,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_private
---
@@ -83,6 +84,7 @@ const LangASMap AMDGPUTargetInfo::AMDGPUDefIsPrivMap = {
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr32_uptr
llvm::AMDGPUAS::FLAT_ADDRESS, // ptr64
llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_groupshared
+llvm::AMDGPUAS::FLAT_ADDRESS, // hlsl_private
---
@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
That's correct, slightly reworded the description.
The thing is, only SPIR-V will be using this for now (same as the few ot
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/122103
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https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/122103
In SPIR-V, private global variables have the `Private` storage class. This PR
adds a new address space which allows frontend to emit variable with this
storage class.
Before this change, global variable were e
@@ -1468,9 +1468,14 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) {
// Set specific Vulkan version if applicable.
if (const Arg *A = Args.getLastArg(options::OPT_fspv_target_env_EQ)) {
- const llvm::StringSet<> ValidValues = {"vulkan1.2",
https://github.com/Keenuts approved this pull request.
Maybe the renaming shall be done in another PR for both DXIL and SPV, but if
it's a small change, might want to do it now no?
https://github.com/llvm/llvm-project/pull/121963
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@@ -118,6 +118,10 @@ let TargetPrefix = "spv" in {
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty, llvm_i8_ty],
[IntrInaccessibleMemOrArgMemOnly]>;
+ def int_spv_resource_getpointer
Keenuts wrote:
Shall it be `int_spv
https://github.com/Keenuts edited
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@@ -0,0 +1,59 @@
+//===- SemaSPIRV.cpp - Semantic Analysis for SPIRV constructs
+//---===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/121598
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@@ -20440,6 +20442,26 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
}
}
+Value *CodeGenFunction::EmitSPIRVBuiltinExpr(unsigned BuiltinID,
+ const CallExpr *E) {
+ switch (BuiltinID) {
+ case SPIRV::BI__bui
https://github.com/Keenuts approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/121738
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@@ -1229,8 +1248,15 @@ FunctionPass *llvm::createSPIRVStructurizerPass() {
PreservedAnalyses SPIRVStructurizerWrapper::run(Function &F,
FunctionAnalysisManager &AF) {
- FunctionPass *StructurizerPass = createSPIRVStructurizerPas
https://github.com/Keenuts closed
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https://github.com/Keenuts approved this pull request.
LGTM on the SPIR-V side. Just a superfluous loop thing.
For the structurizer, seems like this is OK, worst case we might end-up with a
new condition which has no Flatten/Dontflatten attachment but should be fine.
https://github.com/llvm/llv
@@ -2776,19 +2776,35 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
}
return MIB.constrainAllUses(TII, TRI, RBI);
}
- case Intrinsic::spv_loop_merge:
- case Intrinsic::spv_selection_merge: {
-const auto Opcode = IID == Intrinsic::spv_select
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116331
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@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm
-O3 -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -triple spirv-vulkan-compute -x hlsl -emit-llvm -O3 -o - %s
| FileCheck %s --check-prefixes=CHECK,CHECK
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116331
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@@ -2694,19 +2694,49 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
}
return MIB.constrainAllUses(TII, TRI, RBI);
}
- case Intrinsic::spv_loop_merge:
- case Intrinsic::spv_selection_merge: {
-const auto Opcode = IID == Intrinsic::spv_select
https://github.com/Keenuts commented:
Thanks, answered the question for the intrinsic.
As Chris said, this would definitely needs to have some tests in the spir-v
backend.
Especially given that the structurizer assumes the selection control mask was
always `None`.
When splitting edges, or movin
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/118651
Before this patch, there was a calling-convention mismatch between the
constructors and the actual call emitted for the entrypoint wrapper.
Such mismatch causes the InstCombine pass to replace this call with an
@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
We hoped to split the PRs between back-end and FE, shall I land both at the
same time?
https://github.com/llvm/llvm-proje
@@ -58,6 +58,7 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ hlsl_private,
Keenuts wrote:
Oh didn't knew I could modify the target's AS maps without also modifying this.
I'll revert/re-land this PR (given the othe
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116636
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@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+@PrivInternal = internal addrspace(10) global i32 456
+; CHE
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/118312
This reverts commit aa7fe1c10e5d6d0d3aacdb345fed995de413e142.
From e8c3d6da73e95fd03e5ccdf8e08bdc99ff52e6f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 2 Dec 2024 16:50:47 +0100
Su
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/116636
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https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/118312
From e8c3d6da73e95fd03e5ccdf8e08bdc99ff52e6f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Mon, 2 Dec 2024 16:50:47 +0100
Subject: [PATCH 1/2] Revert "[SPIR-V] Fixup storage class for glo
https://github.com/Keenuts closed
https://github.com/llvm/llvm-project/pull/118312
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From 30bdda1649c1c9480968f830c326554f76eabdb6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Thu, 28 Nov 2024 15:00:56 +0100
Subject: [PATCH 1/2] [SPIR-V] Add hlsl_private address space for
@@ -3388,6 +3398,13 @@ bool SPIRVInstructionSelector::selectGlobalValue(
GVType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
}
+ const unsigned AddrSpace = GV->getAddressSpace();
+ SPIRV::StorageClass::StorageClass StorageClass =
+ addressSpaceToSto
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o -
| FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+@PrivInternal = internal addrspace(10) global i32 456
+; CHE
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/116636
From 30bdda1649c1c9480968f830c326554f76eabdb6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Thu, 28 Nov 2024 15:00:56 +0100
Subject: [PATCH] [SPIR-V] Add hlsl_private address space for SPI
Keenuts wrote:
@llvm-beanz : FYI for the added address space.
https://github.com/llvm/llvm-project/pull/116636
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Keenuts wrote:
Hello all!
Changed the PR to use a new AS emitted by the FE. This way there are no more
weird storage class switch.
However, this required to support a new `addrspacecast` operation from
`Function` to `Private` and the other way around.
The FE change will be in another PR (can b
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/115902
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@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#bool:]] = OpTypeBool
+; CHECK-DAG: %[[#uint:]]
@@ -86,6 +86,7 @@ let TargetPrefix = "spv" in {
def int_spv_dot4add_i8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_spv_dot4add_u8packed : DefaultAttrsIntrinsic<[llvm_i32_ty],
[llvm_i32_ty, llvm_i32_ty, llvm_i3
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/115902
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https://github.com/Keenuts commented:
Thanks for this addition! Sorry late review,missed that
https://github.com/llvm/llvm-project/pull/115902
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@@ -59,6 +59,9 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ // Vulkan specific address spaces.
+ vulkan_private,
+
Keenuts wrote:
It breaks 1 test, but the test seems wrong anyway: test for
SPV_INTEL_function_p
@@ -59,6 +59,9 @@ enum class LangAS : unsigned {
// HLSL specific address spaces.
hlsl_groupshared,
+ // Vulkan specific address spaces.
+ vulkan_private,
+
Keenuts wrote:
My understanding is we have 2 ways to convey this information from the FE to
the
@@ -379,6 +380,18 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<>
&B,
const ParmVarDecl &D,
llvm::Type *Ty) {
assert(D.hasAttrs() && "Entry parameter missing annotation a
@@ -204,7 +204,11 @@ addressSpaceToStorageClass(unsigned AddrSpace, const
SPIRVSubtarget &STI) {
? SPIRV::StorageClass::HostOnlyINTEL
: SPIRV::StorageClass::CrossWorkgroup;
case 7:
+return SPIRV::StorageClass::Private;
+ case 8:
return
@@ -43,7 +43,7 @@ void neg() {
template
void tooBig() {
- __attribute__((address_space(I))) int *bounds; // expected-error {{address
space is larger than the maximum supported (8388586)}}
+ __attribute__((address_space(I))) int *bounds; // expected-error {{address
space i
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/116393
Draft PR to explore adding semantics & inline SPIR-V for builtins. This PR is
an alternative to #115187 which does not requires a spec change as we keep the
variables as `static [const]`.
In addition, it tried
https://github.com/Keenuts updated
https://github.com/llvm/llvm-project/pull/115187
From 357f8e613e030967f6a95ccbeffe03c0f5f8c186 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Nathan=20Gau=C3=ABr?=
Date: Wed, 6 Nov 2024 17:48:13 +0100
Subject: [PATCH] [SPIR-V] DRAFT: ext_builtin_input/ext_builtin_ou
https://github.com/Keenuts created
https://github.com/llvm/llvm-project/pull/115187
Draft PR to explore adding semantics & inline SPIR-V for builtins.
Current usage is
```hlsl
// RUN: %clang --driver-mode=dxc -T cs_6_6 -spirv %s -O3 -E main
[[vk::ext_builtin_input(/* NumWorkGroups */ 24)]]
ext
@@ -323,6 +327,83 @@ llvm::Type
*CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
return nullptr;
}
+llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
+ const Type *Ty) const {
+ auto
@@ -323,6 +327,82 @@ llvm::Type
*CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
return nullptr;
}
+llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
+ const Type *Ty) const {
+ auto
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/114273
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@@ -323,6 +327,83 @@ llvm::Type
*CommonSPIRTargetCodeGenInfo::getOpenCLType(CodeGenModule &CGM,
return nullptr;
}
+llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(CodeGenModule &CGM,
+ const Type *Ty) const {
+ auto
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/112757
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@@ -0,0 +1,40 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o
- | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
+// RUN: %clang_cc1 -std=hlsl2021 -fincl
https://github.com/Keenuts commented:
Thanks for this! Some minor changes, otherwise looks good 😊
https://github.com/llvm/llvm-project/pull/111010
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@@ -2653,6 +2653,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
+ case Intrinsic::spv_wave_read_lane_at: {
+assert(I.getNumOperands() == 4);
https://github.com/Keenuts edited
https://github.com/llvm/llvm-project/pull/111010
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https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/110275
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@@ -415,6 +415,7 @@ void CGHLSLRuntime::emitEntryFunction(const FunctionDecl
*FD,
}
CallInst *CI = B.CreateCall(FunctionCallee(Fn), Args);
+ CI->setCallingConv(Fn->getCallingConv());
(void)CI;
Keenuts wrote:
nit: `(void)CI` can now be removed.
https
https://github.com/Keenuts approved this pull request.
https://github.com/llvm/llvm-project/pull/110306
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https://github.com/Keenuts closed
https://github.com/llvm/llvm-project/pull/107408
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Keenuts wrote:
rebased. Will merge tomorrow morning if CI is green.
https://github.com/llvm/llvm-project/pull/107408
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Keenuts wrote:
Thanks! No worries!
Applied the few changes. And yes, there will be iterations on this. For
example, merge-exit pass is not completely finished, and other specific
scenarios. But this will be done through smaller PRs.
I also need to look into how to test this since people want me
@@ -0,0 +1,1242 @@
+//===-- SPIRVStructurizer.cpp --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH
@@ -0,0 +1,1242 @@
+//===-- SPIRVStructurizer.cpp --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH
@@ -0,0 +1,1242 @@
+//===-- SPIRVStructurizer.cpp --*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH
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