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>From 51bd7b1ff944032e9aba5da1fd1a61bec0dafddd Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Wed, 13 Mar 2024 12:15:33 +
Subject: [PATCH] [clang][AArch64] Enable fp128 for aarch64 linux target
-
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MDevereau wrote:
/cherry-pick d9c20e437fe110fb79b5ca73a52762e5b930b361
https://github.com/llvm/llvm-project/pull/79276
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>From 79bf1ffc720d97e96bda477b445502d2cbe71369 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 11 Jan 2024 17:21:10 +
Subject: [PATCH] [AArch64][SME2] Refactor arm_sme.td into multiclasses
Create s
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/78169
>From aa9b6e584e5f469d5ed5d8ceaa56c3b424a98b02 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 11 Jan 2024 17:21:10 +
Subject: [PATCH] [AArch64][SME2] Refactor arm_sme.td into multiclasses
Create s
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https://github.com/llvm/llvm-project/pull/79276
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@@ -10702,6 +10702,14 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
parseConstraintCode(Constraint) != AArch64CC::Invalid)
return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
+ if (StringRef("{za}").equals_insensitive(Constraint)) {
@@ -507,6 +507,10 @@ bool AArch64RegisterInfo::isAsmClobberable(const
MachineFunction &MF,
MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
return true;
+ // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
+ if (PhysReg.id() == AArch64
@@ -10702,6 +10702,14 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
parseConstraintCode(Constraint) != AArch64CC::Invalid)
return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
+ if (StringRef("{za}").equals_insensitive(Constraint)) {
+
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/79276
>From e98987ebb48839ea652d63dfaa62ed841b426e46 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 18 Jan 2024 15:41:25 +
Subject: [PATCH 1/4] [AArch64][SME] Implement inline-asm clobbers for za/zt0
Th
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/79276
>From e98987ebb48839ea652d63dfaa62ed841b426e46 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 18 Jan 2024 15:41:25 +
Subject: [PATCH 1/3] [AArch64][SME] Implement inline-asm clobbers for za/zt0
Th
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/79276
>From e98987ebb48839ea652d63dfaa62ed841b426e46 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 18 Jan 2024 15:41:25 +
Subject: [PATCH 1/2] [AArch64][SME] Implement inline-asm clobbers for za/zt0
Th
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/79276
This enables specifing "za" or "zt0" to the clobber list for inline asm. This
complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276
>From e98987ebb48839ea
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/78961
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>From 5b7d0d25709cb13840845af67409ec74083a96c6 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 22 Jan 2024 11:24:59 +
Subject: [PATCH] [AArch64][SME] Take arm_sme.h out of draft
---
clang/li
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/77947
>From 83374edb041c2440f6bfb9413f62882d6e7b6b19 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 12 Jan 2024 14:01:10 +
Subject: [PATCH 1/2] [AArch64][SME2] Refine fcvtu/fcvts/scvtf/ucvtf
Rename intr
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https://github.com/llvm/llvm-project/pull/77947
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@@ -10056,7 +10056,7 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags
&TypeFlags,
llvm::Type *DefaultType = getSVEType(TypeFlags);
- if (TypeFlags.isOverloadWhile())
+ if (TypeFlags.isOverloadWhile() || TypeFlags.isOverloadMultiVecCvt())
MDever
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/77947
>From 5b2206518e380e8a5ee020f8ff12137cdda4cfa2 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 12 Jan 2024 14:01:10 +
Subject: [PATCH 1/2] [AArch64][SME2] Refine fcvtu/fcvts/scvtf/ucvtf
Rename intr
@@ -136,10 +136,10 @@ defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd",
"aarch64_sme_writeq",
let TargetGuard = "sme" in {
def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone,
"aarch64_sme_zero",
- [IsOverloadNone, IsStreami
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/78258
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https://github.com/llvm/llvm-project/pull/78258
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@@ -342,331 +342,331 @@ let TargetGuard = "sme2" in {
//
let TargetGuard = "sme2" in {
- def SVSMOPA : Inst<"svmopa_za32[_{d}]_m", "viPPdd", "s", MergeNone,
"aarch64_sme_smopa_za32", [IsSharedZA, IsStreaming], [ImmCheck<0,
ImmCheck0_3>]>;
- def SVUSMOPA : Inst<"svmopa_za3
@@ -1720,21 +1720,29 @@ void SVEEmitter::createBuiltinZAState(raw_ostream &OS) {
for (auto *R : RV)
createIntrinsic(R, Defs);
- std::map> DefsZAState;
-
- uint64_t IsSharedZAFlag = getEnumValueForFlag("IsSharedZA");
+ std::map> IntrinsicsPerState;
for (auto &Def :
@@ -3005,6 +3005,15 @@ enum ArmStreamingType {
ArmStreamingOrSVE2p1
};
+enum ArmSMEState : unsigned {
+ ArmNoState = 0,
+
+ ArmInZA = 0b01,
+ ArmOutZA = 0b10,
+ ArmInOutZA = 0b11,
+ ArmZAMask = 0b11,
MDevereau wrote:
```suggestion
ArmZAMask = ArmInOu
@@ -102,3 +102,8 @@ svint8_t missing_za(svint8_t zd, svbool_t pg, uint32_t
slice_base) __arm_streami
// expected-warning@+1 {{builtin call is not valid when calling from a
function without active ZA state}}
return svread_hor_za8_s8_m(zd, pg, 0, slice_base);
}
+
+__arm_n
@@ -1720,21 +1720,29 @@ void SVEEmitter::createBuiltinZAState(raw_ostream &OS) {
for (auto *R : RV)
createIntrinsic(R, Defs);
- std::map> DefsZAState;
-
- uint64_t IsSharedZAFlag = getEnumValueForFlag("IsSharedZA");
+ std::map> IntrinsicsPerState;
for (auto &Def :
@@ -136,10 +136,10 @@ defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd",
"aarch64_sme_writeq",
let TargetGuard = "sme" in {
def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone,
"aarch64_sme_zero",
- [IsOverloadNone, IsStreami
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/78169
Create some multiclasses for FMLA/FMLS, MLAL and MLSL to reduce the size of
arm_sme.td
>From 651facb641b57d8cd019b35d0912499d558bdc08 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 11 Jan 2024 17:21:
@@ -812,6 +819,24 @@ Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF,
Address VAListAddr,
/*allowHigherAlign*/ false);
}
+void AArch64TargetCodeGenInfo::checkFunctionCallABI(
+CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDec
@@ -0,0 +1,12 @@
+// RUN: %clang --target=aarch64-none-linux-gnu -march=armv9-a+sme -O3 -S
-Xclang -verify %s
+
+// Conflicting attributes when using always_inline
+__attribute__((always_inline)) __arm_locally_streaming
+int inlined_fn_local(void) {
+return 42;
+}
---
@@ -279,6 +279,8 @@ def err_builtin_needs_feature : Error<"%0 needs target
feature %1">;
def err_function_needs_feature : Error<
"always_inline function %1 requires target feature '%2', but would "
"be inlined into function %0 that is compiled without support for '%2'">;
+
@@ -812,6 +819,23 @@ Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF,
Address VAListAddr,
/*allowHigherAlign*/ false);
}
+void AArch64TargetCodeGenInfo::checkFunctionCallABI(
+CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDec
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/77947
Rename intrinsics for fcvtu to fcvtzu and fcvts to fcvtzs.
Use llvm_anyvector_ty for both multi vector returns and operands, therefore the
return and operands can be specified in the intrinsic call, e.g.
@llv
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/76711
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>From 67be98b05d771dabe11af54b69532641fa548fb1 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Wed, 10 Jan 2024 17:58:30 +
Subject: [PATCH 1/3] [AArch64][SME] Fix multi vector cvt builtins
This fixes cv
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/77656
>From 67be98b05d771dabe11af54b69532641fa548fb1 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Wed, 10 Jan 2024 17:58:30 +
Subject: [PATCH 1/3] [AArch64][SME] Fix multi vector cvt builtins
This fixes cv
@@ -34,118 +34,118 @@ define
@multi_vector_cvt_x2_bf16( %unu
;
; FCVTZS
;
-define {, }
@multi_vector_cvt_x2_f32_s32( %unused,
%zn0, %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:
+define {, }
@multi_vector_cvt_x2_s32_f32( %unused,
%zn0, %zn1) {
+; CHECK-LABEL:
@@ -34,118 +34,118 @@ define
@multi_vector_cvt_x2_bf16( %unu
;
; FCVTZS
;
-define {, }
@multi_vector_cvt_x2_f32_s32( %unused,
%zn0, %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:
+define {, }
@multi_vector_cvt_x2_s32_f32( %unused,
%zn0, %zn1) {
+; CHECK-LABEL:
@@ -3095,23 +3095,23 @@ let TargetPrefix = "aarch64" in {
[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
- class SME2_CVT_FtoI_VG2_Intrinsic
+ class SME2_CVT_ItoF_VG2_Intrinsic
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/77656
>From 67be98b05d771dabe11af54b69532641fa548fb1 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Wed, 10 Jan 2024 17:58:30 +
Subject: [PATCH 1/2] [AArch64][SME] Fix multi vector cvt builtins
This fixes cv
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/77656
This fixes cvt multi vector builtins that erroneously had inverted return
vectors and vector parameters. This caused the incorrect instructions to be
emitted.
>From 67be98b05d771dabe11af54b69532641fa548fb1 Mo
@@ -494,7 +494,7 @@ void test_svmls_lane1_f16(uint32_t slice_base, svfloat16_t
zn, svfloat16_t zm) _
//
void test_svmls_lane1_bf16(uint32_t slice_base, svbfloat16_t zn, svbfloat16_t
zm) __arm_streaming __arm_shared_za
{
- SVE_ACLE_FUNC(svmls_lane_za32,,_bf16,,_vg2x1)(slice_
@@ -460,7 +460,7 @@ void test_svmla_single4_u16(uint32_t slice_base,
svuint16x4_t zn, svuint16_t zm)
//
void test_svmla_single4_s16(uint32_t slice_base, svint16x4_t zn, svint16_t zm)
__arm_streaming __arm_shared_za
{
- SVE_ACLE_FUNC(svmla_single_za32,,_s16,,_vg2x4)(slice_ba
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/76711
>From 908da224bd01e4758392a98ba2191185d7296c6a Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Tue, 2 Jan 2024 11:36:33 +
Subject: [PATCH 1/4] [AArch64][SME2] Fix SME2 mla/mls tests
The ACLE defines the
https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/76711
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@@ -460,7 +460,7 @@ void test_svmla_single4_u16(uint32_t slice_base,
svuint16x4_t zn, svuint16_t zm)
//
void test_svmla_single4_s16(uint32_t slice_base, svint16x4_t zn, svint16_t zm)
__arm_streaming __arm_shared_za
{
- SVE_ACLE_FUNC(svmla_single_za32,,_s16,,_vg2x4)(slice_ba
@@ -246,7 +246,7 @@ void test_svmls_single2_f64(uint32_t slice_base,
svfloat64x2_t zn, svfloat64_t z
// CPP-CHECK-NEXT:ret void
//
void test_svmls_single4_f64(uint32_t slice_base, svfloat64x4_t zn, svfloat64_t
zm) __arm_streaming __arm_shared_za {
- SVE_ACLE_FUNC(svmls_s
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/76711
>From 908da224bd01e4758392a98ba2191185d7296c6a Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Tue, 2 Jan 2024 11:36:33 +
Subject: [PATCH 1/3] [AArch64][SME2] Fix SME2 mla/mls tests
The ACLE defines the
@@ -246,7 +246,7 @@ void test_svmls_single2_f64(uint32_t slice_base,
svfloat64x2_t zn, svfloat64_t z
// CPP-CHECK-NEXT:ret void
//
void test_svmls_single4_f64(uint32_t slice_base, svfloat64x4_t zn, svfloat64_t
zm) __arm_streaming __arm_shared_za {
- SVE_ACLE_FUNC(svmls_s
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/76711
>From 908da224bd01e4758392a98ba2191185d7296c6a Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Tue, 2 Jan 2024 11:36:33 +
Subject: [PATCH 1/2] [AArch64][SME2] Fix SME2 mla/mls tests
The ACLE defines the
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/76711
The ACLE defines these builtins as svmla[_single]_za32[_f32]_vg1x2, which means
the SVE_ACLE_FUNC macro should test the overloaded forms as
SVE_ACLE_FUNC(svmla,_single,_za32,_f32,_vg1x2)
https://github.com/AR
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https://github.com/llvm/llvm-project/pull/71953
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>From aaf7270f50c7deaebb34acab636cd1e40e872477 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/4] [SME2] Add LUTI2 and LUTI4 single Builtins and Intrinsics
@@ -15,7 +17,7 @@
// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
// CPP-CHECK-NEXT:ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c8(void) {
+svcount_t test_svptrue_c8(void) __arm_streaming_compatibl
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71953
>From cb6e6b5c6fe76a2b4a3bd1d78f4f7cec82d84067 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 10 Nov 2023 13:40:31 +
Subject: [PATCH 1/4] Add SME2 builtins for pfalse and ptrue
Extend pfalse and p
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/74450
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@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
@@ -1981,6 +1979,11 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i",
"QcQsQiQl", MergeNone, "aarch64_sv
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
}
+let TargetGuard = "sve2p1|sme2" in {
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl",
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71953
>From cb6e6b5c6fe76a2b4a3bd1d78f4f7cec82d84067 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Fri, 10 Nov 2023 13:40:31 +
Subject: [PATCH 1/3] Add SME2 builtins for pfalse and ptrue
Extend pfalse and p
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/73305
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>From aaf7270f50c7deaebb34acab636cd1e40e872477 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 20 Nov 2023 15:50:28 +
Subject: [PATCH 1/4] [SME2] Add LUTI2 and LUTI4 single Builtins and Intrinsics
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/73317
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@@ -0,0 +1,1889 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llv
@@ -0,0 +1,1889 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llv
@@ -1864,6 +1866,35 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+unsigned Nu
@@ -0,0 +1,233 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/74450
Adds builtins for:
- FCVT
- BFCVT
- FCVTZS
- FCVTZU
- SCVTF
- UCVTF
- BFCVTN
- FCVTN
- SQCVT
- SQCVTU
- UQCVT
- SQCVTN
- SQCVTUN
- UQCVTN
See https://github.com/ARM-software/acle/pull/217
>From 07244773d073390
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/74303
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@@ -0,0 +1,280 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
@@ -321,9 +321,18 @@ let TargetGuard = "sme2" in {
let TargetGuard = "sme2" in {
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
def SVSTR_ZT : Ins
MDevereau wrote:
> This looks good to me, but I think it needs rebasing after
> https://github.com/llvm/llvm-project/pull/72849 landed. It also looks like
> @sdesmalen-arm left a comment about renaming ImmToTile - perhaps that could
> be done in this patch?
I've rebased it and changed the fun
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/74303
>From de96ce8075385a3404a24e6cb7d81e46e23f8089 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 4 Dec 2023 10:55:24 +
Subject: [PATCH 1/3] [AArch64][SME2] Remove IsPreservesZA from ldr_zt builtin
--
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/74303
>From de96ce8075385a3404a24e6cb7d81e46e23f8089 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 4 Dec 2023 10:55:24 +
Subject: [PATCH 1/2] [AArch64][SME2] Remove IsPreservesZA from ldr_zt builtin
--
@@ -298,3 +298,11 @@ multiclass ZAAddSub {
defm SVADD : ZAAddSub<"add">;
defm SVSUB : ZAAddSub<"sub">;
+
+//
+// Spill and fill of ZT0
+//
+let TargetGuard = "sme2" in {
+ def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamin
https://github.com/MDevereau created
https://github.com/llvm/llvm-project/pull/74303
None
>From de96ce8075385a3404a24e6cb7d81e46e23f8089 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Mon, 4 Dec 2023 10:55:24 +
Subject: [PATCH] [AArch64][SME2] Remove IsPreservesZA from ldr_zt builtin
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+template
MDevereau wrote:
Done
https://github.com/llvm/llvm-project/pull/73317
___
@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/72274
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@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/72274
>From 86c61659cf99486965dffe201385b28420e93f41 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 16:08:57 +
Subject: [PATCH 1/4] Add SME2 builtins for zero { zt0 }
Patch by: Kerry McLaughl
@@ -2746,19 +2746,25 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
- MachineBasicBlock
*
@@ -2746,19 +2746,25 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI,
MachineBasicBlock *BB) const {
return BB;
}
-MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
- MachineBasicBlock
*
@@ -305,4 +305,9 @@ defm SVSUB : ZAAddSub<"sub">;
let TargetGuard = "sme2" in {
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt",
[IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
[ImmCheck<0, ImmCheck0_0>]>;
def SVSTR_ZT : Inst
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/72274
>From 86c61659cf99486965dffe201385b28420e93f41 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 9 Nov 2023 16:08:57 +
Subject: [PATCH 1/3] Add SME2 builtins for zero { zt0 }
Patch by: Kerry McLaughl
https://github.com/MDevereau closed
https://github.com/llvm/llvm-project/pull/72849
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https://github.com/MDevereau edited
https://github.com/llvm/llvm-project/pull/73317
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@@ -1859,6 +1867,34 @@ void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N,
unsigned NumVecs,
SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
+
@@ -0,0 +1,280 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2
-target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-ll
MDevereau wrote:
> It looks like a few other pull requests are changing the same code around
> ImmToTile. Might be good to land this smaller patch first so you can rebase
> the others and reduce the diffs!
The idea was that the changes to `ImmToTile` were small and any of my in-flight
PRs cou
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