================
@@ -34,118 +34,118 @@ define <vscale x 8 x bfloat>
@multi_vector_cvt_x2_bf16(<vscale x 4 x float> %unu
;
; FCVTZS
;
-define {<vscale x 4 x float>, <vscale x 4 x float>}
@multi_vector_cvt_x2_f32_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32>
%zn0, <vscale x 4 x i32> %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:
+define {<vscale x 4 x i32>, <vscale x 4 x i32>}
@multi_vector_cvt_x2_s32_f32(<vscale x 4 x float> %unused, <vscale x 4 x float>
%zn0, <vscale x 4 x float> %zn1) {
+; CHECK-LABEL: multi_vector_cvt_x2_s32_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z3.d, z2.d
; CHECK-NEXT: mov z2.d, z1.d
; CHECK-NEXT: fcvtzs { z0.s, z1.s }, { z2.s, z3.s }
; CHECK-NEXT: ret
- %res = call {<vscale x 4 x float>, <vscale x 4 x float>}
@llvm.aarch64.sve.fcvts.x2.nxv4f32(<vscale x 4 x i32>%zn0, <vscale x 4 x
i32>%zn1)
- ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
+ %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>}
@llvm.aarch64.sve.fcvts.x2.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x
float> %zn1)
+ ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
}
-define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>,
<vscale x 4 x float>} @multi_vector_cvt_x4_f32_s32(<vscale x 4 x i32> %unused,
<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2,
<vscale x 4 x i32> %zn3) {
-; CHECK-LABEL: multi_vector_cvt_x4_f32_s32:
+define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4
x i32>} @multi_vector_cvt_x4_s32_f32(<vscale x 4 x float> %unused, <vscale x 4
x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x
4 x float> %zn3) {
+; CHECK-LABEL: multi_vector_cvt_x4_s32_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z7.d, z4.d
; CHECK-NEXT: mov z6.d, z3.d
; CHECK-NEXT: mov z5.d, z2.d
; CHECK-NEXT: mov z4.d, z1.d
; CHECK-NEXT: fcvtzs { z0.s - z3.s }, { z4.s - z7.s }
; CHECK-NEXT: ret
- %res = call {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x
float>, <vscale x 4 x float>} @llvm.aarch64.sve.fcvts.x4.nxv4f32(<vscale x 4 x
i32>%zn0, <vscale x 4 x i32>%zn1, <vscale x 4 x i32>%zn2, <vscale x 4 x
i32>%zn3)
- ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>} %res
+ %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>,
<vscale x 4 x i32>} @llvm.aarch64.sve.fcvts.x4.nxv4f32(<vscale x 4 x float>
%zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x
float> %zn3)
+ ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
x i32>} %res
}
;
; FCVTZU
;
-define {<vscale x 4 x float>, <vscale x 4 x float>}
@multi_vector_cvt_x2_f32_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32>
%zn0, <vscale x 4 x i32> %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_f32_u32:
+define {<vscale x 4 x i32>, <vscale x 4 x i32>}
@multi_vector_cvt_x2_u32_f32(<vscale x 4 x float> %unused, <vscale x 4 x float>
%zn0, <vscale x 4 x float> %zn1) {
+; CHECK-LABEL: multi_vector_cvt_x2_u32_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z3.d, z2.d
; CHECK-NEXT: mov z2.d, z1.d
; CHECK-NEXT: fcvtzu { z0.s, z1.s }, { z2.s, z3.s }
; CHECK-NEXT: ret
- %res = call {<vscale x 4 x float>, <vscale x 4 x float>}
@llvm.aarch64.sve.fcvtu.x2.nxv4f32(<vscale x 4 x i32>%zn0, <vscale x 4 x
i32>%zn1)
- ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
+ %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>}
@llvm.aarch64.sve.fcvtu.x2.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x
float> %zn1)
+ ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
}
-define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>} @multi_vector_cvt_x4_f32_u32(<vscale x 4 x i32> %unused,
<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2,
<vscale x 4 x i32> %zn3) {
-; CHECK-LABEL: multi_vector_cvt_x4_f32_u32:
+define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x
4 x i32>} @multi_vector_cvt_x4_u32_f32(<vscale x 4 x float> %unused, <vscale x
4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale
x 4 x float> %zn3) {
+; CHECK-LABEL: multi_vector_cvt_x4_u32_f32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z7.d, z4.d
; CHECK-NEXT: mov z6.d, z3.d
; CHECK-NEXT: mov z5.d, z2.d
; CHECK-NEXT: mov z4.d, z1.d
; CHECK-NEXT: fcvtzu { z0.s - z3.s }, { z4.s - z7.s }
; CHECK-NEXT: ret
- %res = call {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x
float>, <vscale x 4 x float>} @llvm.aarch64.sve.fcvtu.x4.nxv4f32(<vscale x 4 x
i32>%zn0, <vscale x 4 x i32>%zn1, <vscale x 4 x i32>%zn2, <vscale x 4 x
i32>%zn3)
- ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>} %res
+ %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>,
<vscale x 4 x i32>} @llvm.aarch64.sve.fcvtu.x4.nxv4f32(<vscale x 4 x float>
%zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x
float> %zn3)
+ ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4
x i32>} %res
}
;
; SCVTF
;
-define {<vscale x 4 x i32>, <vscale x 4 x i32>}
@multi_vector_cvt_x2_s32_f32(<vscale x 4 x float>%unused, <vscale x 4 x float>
%zn0, <vscale x 4 x float> %zn1) {
-; CHECK-LABEL: multi_vector_cvt_x2_s32_f32:
+define {<vscale x 4 x float>, <vscale x 4 x float>}
@multi_vector_cvt_x2_f32_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32>
%zn0, <vscale x 4 x i32> %zn1) {
+; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z3.d, z2.d
; CHECK-NEXT: mov z2.d, z1.d
; CHECK-NEXT: scvtf { z0.s, z1.s }, { z2.s, z3.s }
; CHECK-NEXT: ret
- %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>}
@llvm.aarch64.sve.scvtf.x2.nxv4f32(<vscale x 4 x float>%zn0, <vscale x 4 x
float>%zn1)
- ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res
+ %res = call {<vscale x 4 x float>, <vscale x 4 x float>}
@llvm.aarch64.sve.scvtf.x2.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32>
%zn1)
----------------
MDevereau wrote:
I agree it makes sense to suffix them as .nxv4f32 since it corresponds to the
`llvm_anyvector_ty` in the intrinsics definition
https://github.com/llvm/llvm-project/pull/77656
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