================
@@ -136,10 +136,10 @@ defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlhbfd",
"aarch64_sme_writeq",
let TargetGuard = "sme" in {
def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone,
"aarch64_sme_zero",
- [IsOverloadNone, IsStreamingCompatible,
IsSharedZA],
+ [IsOverloadNone, IsStreamingCompatible,
IsInOutZA],
[ImmCheck<0, ImmCheck0_255>]>;
def SVZERO_ZA : SInst<"svzero_za", "v", "", MergeNone,
"aarch64_sme_zero",
- [IsOverloadNone, IsStreamingCompatible,
IsSharedZA]>;
+ [IsOverloadNone, IsStreamingCompatible, IsOutZA]>;
----------------
MDevereau wrote:
I thought that was the case. Thanks for clearing it up.
https://github.com/llvm/llvm-project/pull/78258
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