https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/5] [clang][RISCV] Set default CPU for vendor
---
clang/
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/4] [clang][RISCV] Set default CPU for vendor
---
clang/
@@ -115,6 +115,20 @@
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zba"
// MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb"
+// RUN: %clang --target=riscv64-mti-linux-gnu -### -c %s 2>&1| FileCheck
-check-prefix=MCPU-MTI-P8700 %s
djtodoro wrote:
Sure.
https://
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor
---
clang/
djtodoro wrote:
> No tests?
@topperc Added.
https://github.com/llvm/llvm-project/pull/134065
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https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/3] [clang][RISCV] Set default CPU for vendor
---
clang/
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor
---
clang/
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/134065
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor
---
clang/
https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/134065
Add support for MipsTechnologies for RISC-V targets.
>From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Wed, 26 Mar 2025 09:24:29 +0100
Subject: [PATCH 1/2] [
https://github.com/djtodoro approved this pull request.
https://github.com/llvm/llvm-project/pull/133366
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https://github.com/llvm/llvm-project/pull/133215
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https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/133215
Reverts llvm/llvm-project#132907 due to some test failures.
>From 9c22bc410d3e157686ae5fd76f8c000e65949a9e Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Thu, 27 Mar 2025 09:04:45 +0100
Subject: [PATCH
https://github.com/djtodoro closed
https://github.com/llvm/llvm-project/pull/132907
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https://github.com/djtodoro approved this pull request.
https://github.com/llvm/llvm-project/pull/132907
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@@ -0,0 +1,6 @@
+// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 |
FileCheck --allow-empty %s
+// CHECK-NOT: {{.*}} is not a recognized feature for this target
+
djtodoro wrote:
nit: no need for 2 newlines here
https://github.com/llvm/llvm
https://github.com/djtodoro closed
https://github.com/llvm/llvm-project/pull/117865
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djtodoro wrote:
Lets wait another day or two, since someone may have additional comments.
Thanks @mgoudar!
https://github.com/llvm/llvm-project/pull/130587
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https://github.com/djtodoro approved this pull request.
https://github.com/llvm/llvm-project/pull/130587
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@@ -47,14 +47,16 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
.Case("mips64r6", true)
.Case("octeon", true)
.Case("octeon+", true)
+ .Case("i6400", true)
+ .Case("i6500", true)
.Default(false);
}
static constexpr llvm::StringLi
@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
"MipsSubtarget::CPU::P5600",
"The P5600 Processor", [FeatureMips32r5]>;
+// I6500 is multicluster version of I6400. Both are based on s
https://github.com/djtodoro requested changes to this pull request.
Thanks for working on this.
https://github.com/llvm/llvm-project/pull/130587
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@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};
- enum class CPU { P5600 };
+ enum class CPU { P5600, I6400 };
djtodoro wrote:
do we need "i6500" here as well
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};
- enum class CPU { P5600 };
+ enum class CPU { P5600, I6400 };
djtodoro wrote:
So, we do not use this in this
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
CPUName == "mips64r5" || CPUName == "octeon" ||
CPUName == "octeon+",
"-march=mips64r2", Flags);
- addMultilibFlag(CPUName == "mips64r6",
https://github.com/djtodoro edited
https://github.com/llvm/llvm-project/pull/130587
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@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExten
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExten
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExten
djtodoro wrote:
@topperc Is it ok now? :)
https://github.com/llvm/llvm-project/pull/121394
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djolertrk wrote:
@topperc looks ok now?
https://github.com/llvm/llvm-project/pull/121394
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@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394
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@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394
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djtodoro wrote:
@lenary thanks!
>You still have a whitespace change to this file?
No, the whitespaces are there on `main` branch. I applied `clang-format`
initially, and that is why it was included in one of my previous patches.
https://github.com/llvm/llvm-project/pull/121394
___
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
djt
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-23} = imm7{6-3};
+ let Inst{22-20} = 0b000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals :
SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+
+def FeatureVendorMIPSCMove
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
djt
djtodoro wrote:
@topperc Thanks for the comments!
> This still isn't broken down enough. We usually like to see assembler support
> in separate patches from code generation.
I have removed `RISCVLoadStoreOptimizer` Pass, and will add it in a separate
PR/commit.
> Missing tests in test/MC/RIS
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,370 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -389,6 +390,13 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusi
@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> {
}];
}
+// A 7-bit unsigned immediate where the least significant two bits are zero.
djtodoro wrote:
No need any more, thanks
https://github.com/llvm/llvm-project/pull/121394
_
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"]
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/121394
>From 29d22560f2987e81ea66e4c7dea42f594bda709f Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions
Adding two extensions for MIPS
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Pre
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/121394
>From f833498eb48595cc6b2bd5dd0c1b05d941313877 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions
Adding two extensions for MIPS
@@ -426,6 +426,12 @@ The current vendor extensions supported are:
``Xwchc``
LLVM implements `the custom compressed opcodes present in some QingKe cores`
by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes
by the name "XW".
+``xmipscmove``
@@ -367,6 +372,16 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusi
@@ -62,6 +62,20 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
djtodoro wrote:
Well, I do not think so.
https://gith
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -2710,6 +2713,45 @@ MachineInstr
*RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
.setMemRefs(MemI.memoperands())
.setMIFlags(MemI.getFlags());
}
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+ switch (Opc) {
+ default:
+return false;
+
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Pre
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
djtodoro wrote:
Addressed in https://github.com/llvm/llvm-project/pull/121394
https://github.
@@ -514,6 +514,78 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394
https://github.com/llvm/llvm-project/pull/117865
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@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
+ /// Return true if pairing the given load or store may be paired with
another.
+ static bool isPairableLdStInstOpc(unsigned Op
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/121394
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
>From a2e1fd5ffab4fe64a160571a9dffaa
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1477,6 +1477,10 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
https://github.com/djtodoro closed
https://github.com/llvm/llvm-project/pull/119882
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@@ -252,9 +252,17 @@ static const char *getLDMOption(const llvm::Triple &T,
const ArgList &Args) {
case llvm::Triple::ppc64le:
return "elf64lppc";
case llvm::Triple::riscv32:
-return "elf32lriscv";
- case llvm::Triple::riscv64:
-return "elf64lriscv";
+ case l
https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/119885
Depends on https://github.com/llvm/llvm-project/pull/119882.
>From 6e17be47f6a36f417547d9bff2f31b8c421ee03b Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Mon, 9 Dec 2024 13:01:11 +0100
Subject: [PATCH
@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on
RV64I
def WriteJmp: SchedWrite;// Jump
def WriteJal: SchedWrite;// Jump and link
def WriteJalr : SchedWrite;// Jump and link register
+def WriteJmpReg : SchedWrit
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/119882
The P8700 is a high-performance processor from MIPS designed to meet the
demands of modern workloads, offering exceptional scalability and efficiency.
It builds on MIPS's established architectural strengths wh
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/djtodoro edited
https://github.com/llvm/llvm-project/pull/117865
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djtodoro wrote:
> Extensions belong in their own PRs, ditto CPU/scheduler, driver and any
> additional passes. Each PR is one commit and this is not one commit's worth
> of changes.
@jrtc27 Yes! I agree. That is why I marked it as `Draft`. The next step is to
divide it into multiple commits.
https://github.com/djtodoro converted_to_draft
https://github.com/llvm/llvm-project/pull/117865
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https://github.com/djtodoro closed
https://github.com/llvm/llvm-project/pull/70024
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Author: Nikola Tesic
Date: 2022-07-06T17:07:20+02:00
New Revision: b5b6d3a41b4eba23b604f37942b892a382caae57
URL:
https://github.com/llvm/llvm-project/commit/b5b6d3a41b4eba23b604f37942b892a382caae57
DIFF:
https://github.com/llvm/llvm-project/commit/b5b6d3a41b4eba23b604f37942b892a382caae57.diff
Author: Djordje Todorovic
Date: 2022-03-22T12:14:00+01:00
New Revision: 73777b4c35a390617cce0f6b4516e98fe5a88df1
URL:
https://github.com/llvm/llvm-project/commit/73777b4c35a390617cce0f6b4516e98fe5a88df1
DIFF:
https://github.com/llvm/llvm-project/commit/73777b4c35a390617cce0f6b4516e98fe5a88df1.d
Author: Djordje Todorovic
Date: 2021-03-25T05:29:42-07:00
New Revision: 8420a5332486c682c1aaddbcb58a571869d19832
URL:
https://github.com/llvm/llvm-project/commit/8420a5332486c682c1aaddbcb58a571869d19832
DIFF:
https://github.com/llvm/llvm-project/commit/8420a5332486c682c1aaddbcb58a571869d19832.d
Author: Djordje Todorovic
Date: 2020-06-01T09:10:05+02:00
New Revision: 40a3fcb05c83c41862038277aa667c956e7cac82
URL:
https://github.com/llvm/llvm-project/commit/40a3fcb05c83c41862038277aa667c956e7cac82
DIFF:
https://github.com/llvm/llvm-project/commit/40a3fcb05c83c41862038277aa667c956e7cac82.d
Author: Djordje Todorovic
Date: 2020-05-15T10:13:15+02:00
New Revision: 170ac4be3392201d5f5e124e8a1b7d78de3f82c8
URL:
https://github.com/llvm/llvm-project/commit/170ac4be3392201d5f5e124e8a1b7d78de3f82c8
DIFF:
https://github.com/llvm/llvm-project/commit/170ac4be3392201d5f5e124e8a1b7d78de3f82c8.d
Author: Djordje Todorovic
Date: 2020-03-19T13:57:30+01:00
New Revision: d9b962100942c71a4c26debaa716f7ab0c4ea8a1
URL:
https://github.com/llvm/llvm-project/commit/d9b962100942c71a4c26debaa716f7ab0c4ea8a1
DIFF:
https://github.com/llvm/llvm-project/commit/d9b962100942c71a4c26debaa716f7ab0c4ea8a1.d
Author: Djordje Todorovic
Date: 2020-03-10T09:15:06+01:00
New Revision: 5aa5c943f7da155b95564058cd5d50a93eabfc89
URL:
https://github.com/llvm/llvm-project/commit/5aa5c943f7da155b95564058cd5d50a93eabfc89
DIFF:
https://github.com/llvm/llvm-project/commit/5aa5c943f7da155b95564058cd5d50a93eabfc89.d
Author: Djordje Todorovic
Date: 2020-03-09T12:12:44+01:00
New Revision: c15c68abdc6f1afece637bdedba808676191a8e6
URL:
https://github.com/llvm/llvm-project/commit/c15c68abdc6f1afece637bdedba808676191a8e6
DIFF:
https://github.com/llvm/llvm-project/commit/c15c68abdc6f1afece637bdedba808676191a8e6.d
Author: Djordje Todorovic
Date: 2020-02-20T14:41:39+01:00
New Revision: 2f215cf36adced6bf1abda4bdbbc6422c1369353
URL:
https://github.com/llvm/llvm-project/commit/2f215cf36adced6bf1abda4bdbbc6422c1369353
DIFF:
https://github.com/llvm/llvm-project/commit/2f215cf36adced6bf1abda4bdbbc6422c1369353.d
Author: Djordje Todorovic
Date: 2020-02-19T11:12:26+01:00
New Revision: faff707db82d7db12fcd9f7826b8741261230e63
URL:
https://github.com/llvm/llvm-project/commit/faff707db82d7db12fcd9f7826b8741261230e63
DIFF:
https://github.com/llvm/llvm-project/commit/faff707db82d7db12fcd9f7826b8741261230e63.d
Author: Djordje Todorovic
Date: 2020-02-18T16:38:11+01:00
New Revision: 2bf44d11cb42a952bdeb778210d8b3e737f0b96e
URL:
https://github.com/llvm/llvm-project/commit/2bf44d11cb42a952bdeb778210d8b3e737f0b96e
DIFF:
https://github.com/llvm/llvm-project/commit/2bf44d11cb42a952bdeb778210d8b3e737f0b96e.d
Author: Djordje Todorovic
Date: 2020-02-18T14:41:08+01:00
New Revision: a82d3e8a6e67473c94a5ce6345372748e9b61718
URL:
https://github.com/llvm/llvm-project/commit/a82d3e8a6e67473c94a5ce6345372748e9b61718
DIFF:
https://github.com/llvm/llvm-project/commit/a82d3e8a6e67473c94a5ce6345372748e9b61718.d
Author: Djordje Todorovic
Date: 2020-02-12T11:59:04+01:00
New Revision: 97ed706a962af7c6835c7b6716207c4072011ac1
URL:
https://github.com/llvm/llvm-project/commit/97ed706a962af7c6835c7b6716207c4072011ac1
DIFF:
https://github.com/llvm/llvm-project/commit/97ed706a962af7c6835c7b6716207c4072011ac1.d
Author: Djordje Todorovic
Date: 2020-02-12T10:25:14+01:00
New Revision: 9f6ff07f8a396dfc736c4cb6f9fba9a203531329
URL:
https://github.com/llvm/llvm-project/commit/9f6ff07f8a396dfc736c4cb6f9fba9a203531329
DIFF:
https://github.com/llvm/llvm-project/commit/9f6ff07f8a396dfc736c4cb6f9fba9a203531329.d
Best regards,
> Djordje
>
> On 26.12.19. 22:33, David Blaikie wrote:
> >
> >
> > On Wed, Nov 20, 2019 at 1:08 AM Djordje Todorovic via cfe-commits
> mailto:cfe-commits@lists.llvm.org>
> <mailto:cfe-commits@lists.llvm.
good point for improvements.
Best regards,
Djordje
On 26.12.19. 22:33, David Blaikie wrote:
>
>
> On Wed, Nov 20, 2019 at 1:08 AM Djordje Todorovic via cfe-commits
> mailto:cfe-commits@lists.llvm.org>> wrote:
>
>
> Author: Djordje Todorovic
> Date:
Author: Djordje Todorovic
Date: 2019-11-20T10:08:07+01:00
New Revision: ce1f95a6e077693f93d8869245f911aff3eb7e4c
URL:
https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c
DIFF:
https://github.com/llvm/llvm-project/commit/ce1f95a6e077693f93d8869245f911aff3eb7e4c.d
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