[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-15 Thread Djordje Todorovic via cfe-commits
@@ -48,62 +48,64 @@ class Triple { enum ArchType { UnknownArch, -arm,// ARM (little endian): arm, armv.*, xscale -armeb, // ARM (big endian): armeb -aarch64,// AArch64 (little endian): aarch64 -aarch64_be, // AArch64 (big

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-15 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH 1/7] [llvm-objcopy][libObject] Add RISC-V big-endian support

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-14 Thread Djordje Todorovic via cfe-commits
@@ -48,62 +48,64 @@ class Triple { enum ArchType { UnknownArch, -arm,// ARM (little endian): arm, armv.*, xscale -armeb, // ARM (big endian): armeb -aarch64,// AArch64 (little endian): aarch64 -aarch64_be, // AArch64 (big

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-10 Thread Djordje Todorovic via cfe-commits
@@ -48,62 +48,64 @@ class Triple { enum ArchType { UnknownArch, -arm,// ARM (little endian): arm, armv.*, xscale -armeb, // ARM (big endian): armeb -aarch64,// AArch64 (little endian): aarch64 -aarch64_be, // AArch64 (big

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-09 Thread Djordje Todorovic via cfe-commits
@@ -63,6 +63,10 @@ StringRef Triple::getArchTypeName(ArchType Kind) { case renderscript64: return "renderscript64"; case riscv32:return "riscv32"; case riscv64:return "riscv64"; + case riscv32be: djtodoro wrote: Indeed... https://githu

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-09 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH 1/6] [llvm-objcopy][libObject] Add RISC-V big-endian support

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-09 Thread Djordje Todorovic via cfe-commits
@@ -63,6 +63,10 @@ StringRef Triple::getArchTypeName(ArchType Kind) { case renderscript64: return "renderscript64"; case riscv32:return "riscv32"; case riscv64:return "riscv64"; + case riscv32be: djtodoro wrote: Let me try, but I think t

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH 1/5] [llvm-objcopy][libObject] Add RISC-V big-endian support

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH 1/4] [llvm-objcopy][libObject] Add RISC-V big-endian support

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH 1/3] [llvm-objcopy][libObject] Add RISC-V big-endian support

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
@@ -2053,6 +2086,8 @@ bool Triple::isLittleEndian() const { case Triple::renderscript64: case Triple::riscv32: case Triple::riscv64: + case Triple::riscv32be: + case Triple::riscv64be: djtodoro wrote: Ouch, fixed. https://github.com/llvm/llvm-project/

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
@@ -74,8 +74,10 @@ class Triple { ppc64le,// PPC64LE: powerpc64le r600, // R600: AMD GPUs HD2XXX - HD6XXX amdgcn, // AMDGCN: AMD GCN GPUs -riscv32,// RISC-V (32-bit): riscv32 -riscv64,// RISC-V (64-bit): riscv64 +

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
@@ -452,6 +457,8 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { .Case("amdgcn", amdgcn) .Case("riscv32", riscv32) .Case("riscv64", riscv64) +.Case("riscv32be", riscv32be) djtodoro wrote: yeah... I agree https://github.co

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-04 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH 1/2] [llvm-objcopy][libObject] Add RISC-V big-endian support

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-03 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146913 >From a3b50d1a95f4ae76af98e25502a7bdb950592d38 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 3 Jul 2025 14:03:14 +0200 Subject: [PATCH] [llvm-objcopy][libObject] Add RISC-V big-endian support Add

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-03 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: > llvm-objcopy and libObject changes look fine to me. If you split the > llvm-objcopy changes into a separate PR, I'd be happy to approve directly. Done as https://github.com/llvm/llvm-project/pull/146913. I will rebase this PR on top of that one. https://github.com/llvm/llvm-p

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-03 Thread Djordje Todorovic via cfe-commits
@@ -48,62 +48,64 @@ class Triple { enum ArchType { UnknownArch, -arm,// ARM (little endian): arm, armv.*, xscale -armeb, // ARM (big endian): armeb -aarch64,// AArch64 (little endian): aarch64 -aarch64_be, // AArch64 (big

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-03 Thread Djordje Todorovic via cfe-commits
@@ -48,62 +48,64 @@ class Triple { enum ArchType { UnknownArch, -arm,// ARM (little endian): arm, armv.*, xscale -armeb, // ARM (big endian): armeb -aarch64,// AArch64 (little endian): aarch64 -aarch64_be, // AArch64 (big

[clang] [llvm] [llvm-objcopy][libObject] Add RISC-V big-endian support (PR #146913)

2025-07-03 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/146913 Add support for big-endian RISC-V ELF files: - Add riscv32be/riscv64be target architectures to Triple - Support elf32-bigriscv and elf64-bigriscv output targets in llvm-objcopy - Update ELFObjectFile to ha

[clang] [llvm] [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (PR #145647)

2025-07-03 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/145647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-03 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: > What is your intention here around the LLVM 21 release cycle, knowing this is > a big feature and we are ~2 weeks from the branch date Hey @lenary, thank for mentioning that. I agree it is a big feature, so no need to rush to include it in the release. https://github.com/ll

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-02 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: > How are we going to verify the correctness? Does qemu support big-endian > riscv64? Good question. We have an initial support for it developed internally inside MIPS, for both qemu and Linux kernel, but team from Codethink is trying to upstream similar effort already, so ple

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-01 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: Support for `clang`, `lld` and `lldb` will be added in later PRs. All together support can be found at https://github.com/djtodoro/llvm-project/tree/pr/riscv-be-support. Basically, this brings into life the https://reviews.llvm.org/D128612. https://github.com/llvm/llvm-projec

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-01 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/146534 >From 89eca90133c885afec008d19a71e46550c8d78ab Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Mon, 2 Jun 2025 14:07:16 +0200 Subject: [PATCH] [RISCV] Add big-endian support to RISC-V backend Initial bi

[clang] [llvm] [RISCV] Add big-endian support to RISC-V backend (PR #146534)

2025-07-01 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/146534 Initial big-endian RISC-V support: - Add riscv32be/riscv64be target triples - Implement BE-aware codegen patterns - Handle endianness in load/store operations - Add BE target feature and subtarget info

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-22 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: I will postpone this PR until I prepare big endian support, thank you all for the comments! https://github.com/llvm/llvm-project/pull/134065 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-22 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/134065 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Fix xmipscmov extension name (PR #135647)

2025-04-15 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/135647 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NFC] Fix xmipscmov extension name (PR #135647)

2025-04-14 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/135647 The right name was used in riscv-toolchain-conventions docs. >From 86eef6e45b92a8601d2873d89b1b7b153a587bb3 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Mon, 14 Apr 2025 11:22:28 +0200 Subject: [PATC

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-10 Thread Djordje Todorovic via cfe-commits
@@ -337,13 +337,17 @@ std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args, // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac` // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`) if (Triple.isRISCV32()) { -if (Triple.getOS

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-10 Thread Djordje Todorovic via cfe-commits
@@ -1874,15 +1894,26 @@ static void findRISCVMultilibs(const Driver &D, MultilibBuilder("lib64/lp64f").flag("-m64").flag("-mabi=lp64f"); MultilibBuilder Lp64d = MultilibBuilder("lib64/lp64d").flag("-m64").flag("-mabi=lp64d"); + + SmallVector Endian; + if (Target

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-08 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: > There's a lot going on here that has absolutely no explanation (no comments > in the code, and the commit message is a single sentence that tells me > nothing of use), and it's doing multiple different things. There's changing > default arch strings, which makes some sense (w

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-07 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/5] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-07 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/4] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-07 Thread Djordje Todorovic via cfe-commits
@@ -115,6 +115,20 @@ // MCPU-MIPS-P8700-SAME: "-target-feature" "+zba" // MCPU-MIPS-P8700-SAME: "-target-feature" "+zbb" +// RUN: %clang --target=riscv64-mti-linux-gnu -### -c %s 2>&1| FileCheck -check-prefix=MCPU-MTI-P8700 %s djtodoro wrote: Sure. https://

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-04 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-03 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: > No tests? @topperc Added. https://github.com/llvm/llvm-project/pull/134065 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-03 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/3] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-02 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-02 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/134065 >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [clang][RISCV] Set default CPU for vendor --- clang/

[clang] [llvm] Add clang driver changes to support MTI RISC-V (PR #134065)

2025-04-02 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/134065 Add support for MipsTechnologies for RISC-V targets. >From 513b1ae05ed6049586a23acab6c0a2f7dbb48454 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Wed, 26 Mar 2025 09:24:29 +0100 Subject: [PATCH 1/2] [

[clang] [llvm] Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907) (PR #133366)

2025-03-28 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro approved this pull request. https://github.com/llvm/llvm-project/pull/133366 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Reland [MIPS] Define SubTargetFeature for i6500 cpu (#132907) (PR #133366)

2025-03-28 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/133366 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Revert "[MIPS] Define SubTargetFeature for i6500 cpu" (PR #133215)

2025-03-27 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/133215 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] Revert "[MIPS] Define SubTargetFeature for i6500 cpu" (PR #133215)

2025-03-27 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/133215 Reverts llvm/llvm-project#132907 due to some test failures. >From 9c22bc410d3e157686ae5fd76f8c000e65949a9e Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 27 Mar 2025 09:04:45 +0100 Subject: [PATCH

[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

2025-03-27 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/132907 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

2025-03-27 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro approved this pull request. https://github.com/llvm/llvm-project/pull/132907 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Define SubTargetFeature for i6500 cpu (PR #132907)

2025-03-25 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,6 @@ +// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 | FileCheck --allow-empty %s +// CHECK-NOT: {{.*}} is not a recognized feature for this target + djtodoro wrote: nit: no need for 2 newlines here https://github.com/llvm/llvm

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2025-03-19 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/117865 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-19 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: Lets wait another day or two, since someone may have additional comments. Thanks @mgoudar! https://github.com/llvm/llvm-project/pull/130587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-19 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro approved this pull request. https://github.com/llvm/llvm-project/pull/130587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-12 Thread Djordje Todorovic via cfe-commits
@@ -47,14 +47,16 @@ bool MipsTargetInfo::processorSupportsGPR64() const { .Case("mips64r6", true) .Case("octeon", true) .Case("octeon+", true) + .Case("i6400", true) + .Case("i6500", true) .Default(false); } static constexpr llvm::StringLi

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-12 Thread Djordje Todorovic via cfe-commits
@@ -238,13 +238,10 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", "MipsSubtarget::CPU::P5600", "The P5600 Processor", [FeatureMips32r5]>; +// I6500 is multicluster version of I6400. Both are based on s

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-11 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro requested changes to this pull request. Thanks for working on this. https://github.com/llvm/llvm-project/pull/130587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-11 Thread Djordje Todorovic via cfe-commits
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo { Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 }; - enum class CPU { P5600 }; + enum class CPU { P5600, I6400 }; djtodoro wrote: do we need "i6500" here as well

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-11 Thread Djordje Todorovic via cfe-commits
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo { Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 }; - enum class CPU { P5600 }; + enum class CPU { P5600, I6400 }; djtodoro wrote: So, we do not use this in this

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-10 Thread Djordje Todorovic via cfe-commits
@@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D, CPUName == "mips64r5" || CPUName == "octeon" || CPUName == "octeon+", "-march=mips64r2", Flags); - addMultilibFlag(CPUName == "mips64r6",

[clang] [llvm] [MIPS] Add MIPS i6400 and i6500 processors (PR #130587)

2025-03-10 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro edited https://github.com/llvm/llvm-project/pull/130587 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">, AssemblerPredicate<(all_of FeatureVendorXCVbi), "'XCVbi' (CORE-V Immediate Branching)">; +// MIPS Extensions + +def FeatureVendorXMIPSCMove +: RISCVExten

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">, AssemblerPredicate<(all_of FeatureVendorXCVbi), "'XCVbi' (CORE-V Immediate Branching)">; +// MIPS Extensions + +def FeatureVendorXMIPSCMove +: RISCVExten

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">, AssemblerPredicate<(all_of FeatureVendorXCVbi), "'XCVbi' (CORE-V Immediate Branching)">; +// MIPS Extensions + +def FeatureVendorXMIPSCMove +: RISCVExten

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: @topperc Is it ok now? :) https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
djolertrk wrote: @topperc looks ok now? https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
https://github.com/djolertrk deleted https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-27 Thread Djordje Todorovic via cfe-commits
@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-24 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: @lenary thanks! >You still have a whitespace change to this file? No, the whitespaces are there on `main` branch. I applied `clang-format` initially, and that is why it was included in one of my previous patches. https://github.com/llvm/llvm-project/pull/121394 ___

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-20 Thread Djordje Todorovic via cfe-commits
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries( "riscv-min-jump-table-entries", cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on RISCV")); +static cl::opt +UseLoadStorePairsOpt("riscv-load-store-pairs", djt

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-20 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,82 @@ +//===-- RISCVInstrInfoXMips.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-20 Thread Djordje Todorovic via cfe-commits
@@ -514,6 +514,78 @@ class RVInstJ +: RVInst { + bits<7> imm7; + bits<5> rs1; + bits<5> rd1; + bits<5> rd2; + + let Inst{31-27} = rd2; + let Inst{26-23} = imm7{6-3}; + let Inst{22-20} = 0b000; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b100; + let Inst{11-7} = rd1

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-17 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,82 @@ +//===-- RISCVInstrInfoXMips.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-17 Thread Djordje Todorovic via cfe-commits
@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "AllowTaggedGlobals", "true", "Use an instruction sequence for taking the address of a global " "that allows a memory tag in the upper address bits">; + +def FeatureVendorMIPSCMove

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-15 Thread Djordje Todorovic via cfe-commits
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries( "riscv-min-jump-table-entries", cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on RISCV")); +static cl::opt +UseLoadStorePairsOpt("riscv-load-store-pairs", djt

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-15 Thread Djordje Todorovic via cfe-commits
djtodoro wrote: @topperc Thanks for the comments! > This still isn't broken down enough. We usually like to see assembler support > in separate patches from code generation. I have removed `RISCVLoadStoreOptimizer` Pass, and will add it in a separate PR/commit. > Missing tests in test/MC/RIS

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-15 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,82 @@ +//===-- RISCVInstrInfoXMips.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-15 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,370 @@ +//===- RISCVLoadStoreOptimizer.cpp ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-15 Thread Djordje Todorovic via cfe-commits
@@ -389,6 +390,13 @@ class RISCVPassConfig : public TargetPassConfig { DAG->addMutation(createStoreClusterDAGMutation( DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true)); } + +const RISCVSubtarget &ST = C->MF->getSubtarget(); +if (!ST.getMacroFusi

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-15 Thread Djordje Todorovic via cfe-commits
@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> { }]; } +// A 7-bit unsigned immediate where the least significant two bits are zero. djtodoro wrote: No need any more, thanks https://github.com/llvm/llvm-project/pull/121394 _

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2025-01-03 Thread Djordje Todorovic via cfe-commits
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, Group, def mno_save_restore : Flag<["-"], "mno-save-restore">, Group, HelpText<"Disable using library calls for save and restore">; } // let Flags = [TargetSpecific] +def mload_store_pairs : Flag<["-"]

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2024-12-31 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/121394 >From 29d22560f2987e81ea66e4c7dea42f594bda709f Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 26 Dec 2024 09:09:24 +0100 Subject: [PATCH] [RISCV] Add MIPS extensions Adding two extensions for MIPS

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1, (AddiPair:$rs2)), } //===--===// + +// MIPS extensions +//===--===// + +let Pre

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2024-12-31 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro updated https://github.com/llvm/llvm-project/pull/121394 >From f833498eb48595cc6b2bd5dd0c1b05d941313877 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Thu, 26 Dec 2024 09:09:24 +0100 Subject: [PATCH] [RISCV] Add MIPS extensions Adding two extensions for MIPS

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -426,6 +426,12 @@ The current vendor extensions supported are: ``Xwchc`` LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW". +``xmipscmove``

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -367,6 +372,16 @@ class RISCVPassConfig : public TargetPassConfig { DAG->addMutation(createStoreClusterDAGMutation( DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true)); } + +const RISCVSubtarget &ST = C->MF->getSubtarget(); +if (!ST.getMacroFusi

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -62,6 +62,20 @@ static cl::opt RISCVMinimumJumpTableEntries( "riscv-min-jump-table-entries", cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on RISCV")); +static cl::opt djtodoro wrote: Well, I do not think so. https://gith

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; +def TuneMIPSP8700 +: SubtargetFeature<"m

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -2710,6 +2713,45 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI, .setMemRefs(MemI.memoperands()) .setMIFlags(MemI.getFlags()); } +bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) { + switch (Opc) { + default: +return false; +

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; +def TuneMIPSP8700 +: SubtargetFeature<"m

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1, (AddiPair:$rs2)), } //===--===// + +// MIPS extensions +//===--===// + +let Pre

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1, (AddiPair:$rs2)), } //===--===// + djtodoro wrote: Addressed in https://github.com/llvm/llvm-project/pull/121394 https://github.

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -514,6 +514,78 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394 https://github.com/llvm/llvm-project/pull/117865 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override; + /// Return true if pairing the given load or store may be paired with another. + static bool isPairableLdStInstOpc(unsigned Op

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,371 @@ +//===- RISCVLoadStoreOptimizer.cpp ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,371 @@ +//===- RISCVLoadStoreOptimizer.cpp ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,371 @@ +//===- RISCVLoadStoreOptimizer.cpp ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

2024-12-31 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,371 @@ +//===- RISCVLoadStoreOptimizer.cpp ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)

2024-12-31 Thread Djordje Todorovic via cfe-commits
https://github.com/djtodoro created https://github.com/llvm/llvm-project/pull/121394 Adding two extensions for MIPS p8700 CPU: 1. cmove (conditional move) 2. lsp (load/store pair) The official product page here: https://mips.com/products/hardware/p8700 >From a2e1fd5ffab4fe64a160571a9dffaa

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-16 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-16 Thread Djordje Todorovic via cfe-commits
@@ -0,0 +1,290 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

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