[llvm-branch-commits] [llvm] a19747e - Fix type in DenseMap to match V.size()

2021-08-16 Thread Renato Golin via llvm-branch-commits 

Author: Renato Golin
Date: 2021-08-16T15:32:04+01:00
New Revision: a19747ea7395dd470345e4703f13bbb74647b019

URL: 
https://github.com/llvm/llvm-project/commit/a19747ea7395dd470345e4703f13bbb74647b019
DIFF: 
https://github.com/llvm/llvm-project/commit/a19747ea7395dd470345e4703f13bbb74647b019.diff

LOG: Fix type in DenseMap to match V.size()

Differential Revision: https://reviews.llvm.org/D108124

Added: 


Modified: 
llvm/include/llvm/ADT/SmallBitVector.h

Removed: 




diff  --git a/llvm/include/llvm/ADT/SmallBitVector.h 
b/llvm/include/llvm/ADT/SmallBitVector.h
index f570bac23ad51..c70bc88fb1f24 100644
--- a/llvm/include/llvm/ADT/SmallBitVector.h
+++ b/llvm/include/llvm/ADT/SmallBitVector.h
@@ -721,7 +721,7 @@ template <> struct DenseMapInfo {
   }
   static unsigned getHashValue(const SmallBitVector &V) {
 uintptr_t Store;
-return DenseMapInfo>>::getHashValue(
+return DenseMapInfo>>::getHashValue(
 std::make_pair(V.size(), V.getData(Store)));
   }
   static bool isEqual(const SmallBitVector &LHS, const SmallBitVector &RHS) {



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[llvm-branch-commits] [llvm-branch] r245568 - Revert "[SimplifyCFG] Be more aggressive" on branch_37

2015-08-20 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Thu Aug 20 10:05:48 2015
New Revision: 245568

URL: http://llvm.org/viewvc/llvm-project?rev=245568&view=rev
Log:
Revert "[SimplifyCFG] Be more aggressive" on branch_37

This reverts commit r229099 in branch 37 only, because it caused PR24292.
I'll continue investigating and will fix on trunk, but being an optimization
change, we can let the rest of the release go without this one.


Modified:
llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll
llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll

Modified: llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp?rev=245568&r1=245567&r2=245568&view=diff
==
--- llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp Thu Aug 20 
10:05:48 2015
@@ -53,13 +53,9 @@ using namespace PatternMatch;
 
 #define DEBUG_TYPE "simplifycfg"
 
-// Chosen as 2 so as to be cheap, but still to have enough power to fold
-// a select, so the "clamp" idiom (of a min followed by a max) will be caught.
-// To catch this, we need to fold a compare and a select, hence '2' being the
-// minimum reasonable default.
 static cl::opt
-PHINodeFoldingThreshold("phi-node-folding-threshold", cl::Hidden, cl::init(2),
-   cl::desc("Control the amount of phi node folding to perform (default = 
2)"));
+PHINodeFoldingThreshold("phi-node-folding-threshold", cl::Hidden, cl::init(1),
+   cl::desc("Control the amount of phi node folding to perform (default = 
1)"));
 
 static cl::opt
 DupRet("simplifycfg-dup-ret", cl::Hidden, cl::init(false),

Modified: llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll?rev=245568&r1=245567&r2=245568&view=diff
==
--- llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll (original)
+++ llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll Thu Aug 20 
10:05:48 2015
@@ -1,9 +1,9 @@
 ; RUN: llc -O3 -mcpu=cortex-a57 < %s | FileCheck %s 
 
-; CHECK-LABEL: @test
-; CHECK: and 
-; CHECK: csel
-; CHECK: csel
+; CHECK-LABLE: @test
+; CHECK: tst [[CMP:x[0-9]+]], #0x8000
+; CHECK: csel [[R0:x[0-9]+]], [[S0:x[0-9]+]], [[S1:x[0-9]+]], eq
+; CHECK: csel [[R1:x[0-9]+]], [[S2:x[0-9]+]], [[S3:x[0-9]+]], eq
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "arm64--linux-gnueabi"
 

Modified: llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll?rev=245568&r1=245567&r2=245568&view=diff
==
--- llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll 
(original)
+++ llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll Thu 
Aug 20 10:05:48 2015
@@ -135,13 +135,39 @@ define <16 x i8> @test5(<16 x i8> %arg,
 ; In stress mode, constant vector are promoted
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
-; PROMOTED: ldr
-; PROMOTED-NOT: ldr
-; PROMOTED: ret
+; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
+; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
+; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
+; Next BB
+; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
+; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]]
+; Next BB
+; PROMOTED-NEXT: [[LABEL]]:
+; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]]
+; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
+; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
+; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
+; PROMOTED-NEXT: ret
 
 ; REGULAR-LABEL: test5:
-; REGULAR: ldr
-; REGULAR: ret
+; REGULAR: cbz w0, [[LABELelse:LBB.*]]
+; Next BB
+; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
+; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], 
[[CSTLABEL]]@PAGEOFF]
+; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
+; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]]
+; REGULAR-NEXT: b [[LABELend:LBB.*]]
+; Next BB
+; REGULAR-NEXT: [[LABELelse]]
+; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
+; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
+; Next BB
+; REGULAR-NEXT: [[LABELend]]:
+; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]]
+; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
+; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
+; REGULAR-N

[llvm-branch-commits] [llvm-branch] r245570 - Reapply "[SimplifyCFG] Be more aggressive" on branch_37

2015-08-20 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Thu Aug 20 10:49:34 2015
New Revision: 245570

URL: http://llvm.org/viewvc/llvm-project?rev=245570&view=rev
Log:
Reapply "[SimplifyCFG] Be more aggressive" on branch_37

I have underestimated the importance of this patch, and
James has got a fix for it in the making. Sorry for the noise.

Modified:
llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll
llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll

Modified: llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp?rev=245570&r1=245569&r2=245570&view=diff
==
--- llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/branches/release_37/lib/Transforms/Utils/SimplifyCFG.cpp Thu Aug 20 
10:49:34 2015
@@ -53,9 +53,13 @@ using namespace PatternMatch;
 
 #define DEBUG_TYPE "simplifycfg"
 
+// Chosen as 2 so as to be cheap, but still to have enough power to fold
+// a select, so the "clamp" idiom (of a min followed by a max) will be caught.
+// To catch this, we need to fold a compare and a select, hence '2' being the
+// minimum reasonable default.
 static cl::opt
-PHINodeFoldingThreshold("phi-node-folding-threshold", cl::Hidden, cl::init(1),
-   cl::desc("Control the amount of phi node folding to perform (default = 
1)"));
+PHINodeFoldingThreshold("phi-node-folding-threshold", cl::Hidden, cl::init(2),
+   cl::desc("Control the amount of phi node folding to perform (default = 
2)"));
 
 static cl::opt
 DupRet("simplifycfg-dup-ret", cl::Hidden, cl::init(false),

Modified: llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll?rev=245570&r1=245569&r2=245570&view=diff
==
--- llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll (original)
+++ llvm/branches/release_37/test/CodeGen/AArch64/analyzecmp.ll Thu Aug 20 
10:49:34 2015
@@ -1,9 +1,9 @@
 ; RUN: llc -O3 -mcpu=cortex-a57 < %s | FileCheck %s 
 
-; CHECK-LABLE: @test
-; CHECK: tst [[CMP:x[0-9]+]], #0x8000
-; CHECK: csel [[R0:x[0-9]+]], [[S0:x[0-9]+]], [[S1:x[0-9]+]], eq
-; CHECK: csel [[R1:x[0-9]+]], [[S2:x[0-9]+]], [[S3:x[0-9]+]], eq
+; CHECK-LABEL: @test
+; CHECK: and 
+; CHECK: csel
+; CHECK: csel
 target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 target triple = "arm64--linux-gnueabi"
 

Modified: llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll?rev=245570&r1=245569&r2=245570&view=diff
==
--- llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll 
(original)
+++ llvm/branches/release_37/test/CodeGen/AArch64/arm64-promote-const.ll Thu 
Aug 20 10:49:34 2015
@@ -135,39 +135,13 @@ define <16 x i8> @test5(<16 x i8> %arg,
 ; In stress mode, constant vector are promoted
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
-; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]]
-; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
-; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
-; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
-; PROMOTED-NEXT: ret
+; PROMOTED: ldr
+; PROMOTED-NOT: ldr
+; PROMOTED: ret
 
 ; REGULAR-LABEL: test5:
-; REGULAR: cbz w0, [[LABELelse:LBB.*]]
-; Next BB
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], 
[[CSTLABEL]]@PAGEOFF]
-; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]]
-; REGULAR-NEXT: b [[LABELend:LBB.*]]
-; Next BB
-; REGULAR-NEXT: [[LABELelse]]
-; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; Next BB
-; REGULAR-NEXT: [[LABELend]]:
-; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]]
-; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
-; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
-; REGULAR-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
-; REGULAR-NEXT: ret
+; REGULAR: ldr
+; REGULAR: ret
 entry:
   %tobool = icmp eq i32 %path,

Re: [llvm-branch-commits] [llvm-branch] r245570 - Reapply "[SimplifyCFG] Be more aggressive" on branch_37

2015-08-20 Thread Renato Golin via llvm-branch-commits 
On 20 August 2015 at 16:52, Hans Wennborg  wrote:
> The revert also broke the Transforms/SimplifyCFG/clamp.ll test for
> some reason, but not it looks good again.

Yes, that was a bad call. James has told me how crucial that patch was
to many other optimizations and even correctness issues in all
back-ends.

He's on a fix and we should wait until it comes, backport it and then
get RC3 after that.

Sorry again,
--renato
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[llvm-branch-commits] [llvm-branch] r245578 - Merge r245577 into branch_37

2015-08-20 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Thu Aug 20 11:41:22 2015
New Revision: 245578

URL: http://llvm.org/viewvc/llvm-project?rev=245578&view=rev
Log:
Merge r245577 into branch_37

[ARM] Don't try and custom lower a vNi64 SETCC.

It won't go well. We've already marked 64-bit SETCCs as non-Custom, but it's
just possible that a SETCC has a legal result type but an illegal operand
type. If this happens, bail out before we create unselectable nodes.

Fixes PR24292. I tried to create a testcase but in 99% of cases we can't
trigger this - not surprising that this bug has been latent since 2009.

Modified:
llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp?rev=245578&r1=245577&r2=245578&view=diff
==
--- llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_37/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 20 
11:41:22 2015
@@ -4583,6 +4583,12 @@ static SDValue LowerVSETCC(SDValue Op, S
   ISD::CondCode SetCCOpcode = cast(CC)->get();
   SDLoc dl(Op);
 
+  if (CmpVT.getVectorElementType() == MVT::i64)
+// 64-bit comparisons are not legal. We've marked SETCC as non-Custom,
+// but it's possible that our operands are 64-bit but our result is 32-bit.
+// Bail in this case.
+return SDValue();
+
   if (Op1.getValueType().isFloatingPoint()) {
 switch (SetCCOpcode) {
 default: llvm_unreachable("Illegal FP comparison");


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[llvm-branch-commits] [llvm-branch] r252456 - Merging r249165:

2015-11-09 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Mon Nov  9 03:59:23 2015
New Revision: 252456

URL: http://llvm.org/viewvc/llvm-project?rev=252456&view=rev
Log:
Merging r249165:

r249165 | rdivacky | 2015-10-02 19:25:25 +0100 (Fri, 02 Oct 2015) | 2 lines

Actually switch the arch when we see .arch. PR21695

Added:
llvm/branches/release_37/test/MC/ARM/directive-arch-semantic-action.s
Modified:
llvm/branches/release_37/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/branches/release_37/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=252456&r1=252455&r2=252456&view=diff
==
--- llvm/branches/release_37/lib/Target/ARM/AsmParser/ARMAsmParser.cpp 
(original)
+++ llvm/branches/release_37/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Nov  
9 03:59:23 2015
@@ -15,6 +15,7 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAssembler.h"
@@ -9104,6 +9105,10 @@ bool ARMAsmParser::parseDirectiveArch(SM
 return false;
   }
 
+  Triple T;
+  STI.setDefaultFeatures(T.getARMCPUForArch(Arch));
+  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+
   getTargetStreamer().emitArch(ID);
   return false;
 }

Added: llvm/branches/release_37/test/MC/ARM/directive-arch-semantic-action.s
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/MC/ARM/directive-arch-semantic-action.s?rev=252456&view=auto
==
--- llvm/branches/release_37/test/MC/ARM/directive-arch-semantic-action.s 
(added)
+++ llvm/branches/release_37/test/MC/ARM/directive-arch-semantic-action.s Mon 
Nov  9 03:59:23 2015
@@ -0,0 +1,12 @@
+@ RUN: not llvm-mc -triple arm-gnueabi-linux -filetype asm %s 2>&1 | FileCheck 
%s
+
+.arch  armv6
+dsb
+@ CHECK: error: instruction requires: data-barriers
+
+.arch   armv7
+dsb
+@ CHECK-NOT: error: instruction requires: data-barriers
+
+.arch   invalid_architecture_name
+@ CHECK: error: Unknown arch name


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[llvm-branch-commits] [llvm-branch] r258326 - Merging r258308: [AArch64] Fix two bugs in the .inst directive

2016-01-20 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Wed Jan 20 12:01:05 2016
New Revision: 258326

URL: http://llvm.org/viewvc/llvm-project?rev=258326&view=rev
Log:
Merging r258308: [AArch64] Fix two bugs in the .inst directive

Modified:

llvm/branches/release_38/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
llvm/branches/release_38/test/MC/AArch64/inst-directive.s

Modified: 
llvm/branches/release_38/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp?rev=258326&r1=258325&r2=258326&view=diff
==
--- 
llvm/branches/release_38/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp 
(original)
+++ 
llvm/branches/release_38/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp 
Wed Jan 20 12:01:05 2016
@@ -112,9 +112,21 @@ public:
 MCELFStreamer::EmitInstruction(Inst, STI);
   }
 
+  /// Emit a 32-bit value as an instruction. This is only used for the .inst
+  /// directive, EmitInstruction should be used in other cases.
   void emitInst(uint32_t Inst) {
+char Buffer[4];
+
+// We can't just use EmitIntValue here, as that will emit a data mapping
+// symbol, and swap the endianness on big-endian systems (instructions are
+// always little-endian).
+for (unsigned I = 0; I < 4; ++I) {
+  Buffer[I] = uint8_t(Inst);
+  Inst >>= 8;
+}
+
 EmitA64MappingSymbol();
-MCELFStreamer::EmitIntValue(Inst, 4);
+MCELFStreamer::EmitBytes(StringRef(Buffer, 4));
   }
 
   /// This is one of the functions used to emit data into an ELF section, so 
the

Modified: llvm/branches/release_38/test/MC/AArch64/inst-directive.s
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/MC/AArch64/inst-directive.s?rev=258326&r1=258325&r2=258326&view=diff
==
--- llvm/branches/release_38/test/MC/AArch64/inst-directive.s (original)
+++ llvm/branches/release_38/test/MC/AArch64/inst-directive.s Wed Jan 20 
12:01:05 2016
@@ -1,7 +1,14 @@
 // RUN: llvm-mc %s -triple=aarch64-none-linux-gnu -filetype=asm -o - \
 // RUN:   | FileCheck %s --check-prefix=CHECK-ASM
-// RUN: llvm-mc %s -triple=aarch64-none-linux-gnu -filetype=obj -o - \
-// RUN:   | llvm-readobj -s -sd | FileCheck %s  --check-prefix=CHECK-OBJ
+// RUN: llvm-mc %s -triple=aarch64-none-linux-gnu -filetype=obj -o %t
+// RUN: llvm-readobj -s -sd %t | FileCheck %s  --check-prefix=CHECK-OBJ
+// RUN: llvm-objdump -t %t | FileCheck %s  --check-prefix=CHECK-SYMS
+
+// RUN: llvm-mc %s -triple=aarch64_be-none-linux-gnu -filetype=asm -o - \
+// RUN:   | FileCheck %s --check-prefix=CHECK-ASM
+// RUN: llvm-mc %s -triple=aarch64_be-none-linux-gnu -filetype=obj -o %t
+// RUN: llvm-readobj -s -sd %t | FileCheck %s  --check-prefix=CHECK-OBJ
+// RUN: llvm-objdump -t %t | FileCheck %s  --check-prefix=CHECK-SYMS
 
 .section.inst.aarch64_inst
 
@@ -22,3 +29,7 @@ aarch64_inst:
 // CHECK-OBJ:   SectionData (
 // CHECK-OBJ-NEXT: : 2040105E
 // CHECK-OBJ-NEXT: )
+
+// CHECK-SYMS-NOT:  .inst.aarch64_inst  
 $d
+// CHECK-SYMS:  .inst.aarch64_inst  
 $x
+// CHECK-SYMS-NOT:  .inst.aarch64_inst  
 $d


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[llvm-branch-commits] [llvm-branch] r260684 - [ARM/AArch64] 3.8.0 release notes changes

2016-02-12 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Fri Feb 12 09:29:34 2016
New Revision: 260684

URL: http://llvm.org/viewvc/llvm-project?rev=260684&view=rev
Log:
[ARM/AArch64] 3.8.0 release notes changes

Modified:
llvm/branches/release_38/docs/ReleaseNotes.rst

Modified: llvm/branches/release_38/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/docs/ReleaseNotes.rst?rev=260684&r1=260683&r2=260684&view=diff
==
--- llvm/branches/release_38/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_38/docs/ReleaseNotes.rst Fri Feb 12 09:29:34 2016
@@ -109,10 +109,32 @@ Non-comprehensive list of changes in thi
Makes programs 10x faster by doing Special New Thing.
 
 
-Changes to the ARM Backend
---
+Changes to the ARM Backends
+---
 
- During this release ...
+During this release the AArch64 target has:
+
+* Added support for more sanitizers (MSAN, TSAN) and made them compatible with
+  all VMA kernel configurations (kurrently tested on 39 and 42 bits).
+* Gained initial LLD support in the new ELF back-end
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+  made earlier.
+* Expanded LLDB support, including watchpoints, native building, Renderscript,
+  LLDB-server, debugging 32-bit applications.
+* Added support for the ``Exynos M1`` chip.
+
+During this release the ARM target has:
+
+* Gained massive performance improvements on embedded benchmarks due to finally
+  running the stride vectorizer in full form, incrementing the performance 
gains
+  that we already had in the previous releases with limited stride 
vectorization.
+* Expanded LLDB support, including watchpoints, unwind tables
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+  made earlier.
+* Gained some code size improvements, though there's still a long road ahead,
+  especially for older cores.
+* Added some EABI floating point comparison functions to Compiler-RT
+* Added support for Windows+GNU triple, +features in -mcpu/-march options.
 
 
 Changes to the MIPS Target


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[llvm-branch-commits] [llvm-branch] r261341 - Merge r261331: avoid out of bounds loads for interleaved access vectorization

2016-02-19 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Fri Feb 19 11:35:27 2016
New Revision: 261341

URL: http://llvm.org/viewvc/llvm-project?rev=261341&view=rev
Log:
Merge r261331: avoid out of bounds loads for interleaved access vectorization

Modified:
llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp

llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll

llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll

Modified: llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=261341&r1=261340&r2=261341&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp 
(original)
+++ llvm/branches/release_38/lib/Transforms/Vectorize/LoopVectorize.cpp Fri Feb 
19 11:35:27 2016
@@ -4636,6 +4636,8 @@ void InterleavedAccessInfo::analyzeInter
 
   // Holds all interleaved store groups temporarily.
   SmallSetVector StoreGroups;
+  // Holds all interleaved load groups temporarily.
+  SmallSetVector LoadGroups;
 
   // Search the load-load/write-write pair B-A in bottom-up order and try to
   // insert B into the interleave group of A according to 3 rules:
@@ -4663,6 +4665,8 @@ void InterleavedAccessInfo::analyzeInter
 
 if (A->mayWriteToMemory())
   StoreGroups.insert(Group);
+else
+  LoadGroups.insert(Group);
 
 for (auto II = std::next(I); II != E; ++II) {
   Instruction *B = II->first;
@@ -4710,6 +4714,12 @@ void InterleavedAccessInfo::analyzeInter
   for (InterleaveGroup *Group : StoreGroups)
 if (Group->getNumMembers() != Group->getFactor())
   releaseGroup(Group);
+
+  // Remove interleaved load groups that don't have the first and last member.
+  // This guarantees that we won't do speculative out of bounds loads.
+  for (InterleaveGroup *Group : LoadGroups)
+if (!Group->getMember(0) || !Group->getMember(Group->getFactor() - 1))
+  releaseGroup(Group);
 }
 
 LoopVectorizationCostModel::VectorizationFactor

Modified: 
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll?rev=261341&r1=261340&r2=261341&view=diff
==
--- 
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
 (original)
+++ 
llvm/branches/release_38/test/Transforms/LoopVectorize/PowerPC/stride-vectorization.ll
 Fri Feb 19 11:35:27 2016
@@ -16,9 +16,15 @@ for.cond.cleanup:
 for.body: ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %0 = shl nsw i64 %indvars.iv, 1
+  %odd.idx = add nsw i64 %0, 1
+
   %arrayidx = getelementptr inbounds double, double* %b, i64 %0
+  %arrayidx.odd = getelementptr inbounds double, double* %b, i64 %odd.idx
+
   %1 = load double, double* %arrayidx, align 8
-  %add = fadd double %1, 1.00e+00
+  %2 = load double, double* %arrayidx.odd, align 8
+
+  %add = fadd double %1, %2
   %arrayidx2 = getelementptr inbounds double, double* %a, i64 %indvars.iv
   store double %add, double* %arrayidx2, align 8
   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1

Modified: 
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll?rev=261341&r1=261340&r2=261341&view=diff
==
--- 
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll 
(original)
+++ 
llvm/branches/release_38/test/Transforms/LoopVectorize/interleaved-accesses.ll 
Fri Feb 19 11:35:27 2016
@@ -292,10 +292,8 @@ for.body:
 ; }
 
 ; CHECK-LABEL: @even_load(
-; CHECK: %wide.vec = load <8 x i32>, <8 x i32>* %{{.*}}, align 4
-; CHECK: %strided.vec = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 
x i32> 
-; CHECK-NOT: shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> 

-; CHECK: shl nsw <4 x i32> %strided.vec, 
+; CHECK-NOT: %wide.vec = load <8 x i32>, <8 x i32>* %{{.*}}, align 4
+; CHECK-NOT: %strided.vec = shufflevector <8 x i32> %wide.vec, <8 x i32> 
undef, <4 x i32> 
 
 define void @even_load(i32* noalias nocapture readonly %A, i32* noalias 
nocapture %B) {
 entry:


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[llvm-branch-commits] [cfe-branch] r261343 - Merge r261309: ARM: fix VFP asm constraints

2016-02-19 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Fri Feb 19 11:40:14 2016
New Revision: 261343

URL: http://llvm.org/viewvc/llvm-project?rev=261343&view=rev
Log:
Merge r261309: ARM: fix VFP asm constraints

Modified:
cfe/branches/release_38/lib/Basic/Targets.cpp

Modified: cfe/branches/release_38/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_38/lib/Basic/Targets.cpp?rev=261343&r1=261342&r2=261343&view=diff
==
--- cfe/branches/release_38/lib/Basic/Targets.cpp (original)
+++ cfe/branches/release_38/lib/Basic/Targets.cpp Fri Feb 19 11:40:14 2016
@@ -4915,8 +4915,8 @@ public:
 default: break;
 case 'l': // r0-r7
 case 'h': // r8-r15
-case 'w': // VFP Floating point register single precision
-case 'P': // VFP Floating point register double precision
+case 't': // VFP Floating point register single precision
+case 'w': // VFP Floating point register double precision
   Info.setAllowsRegister();
   return true;
 case 'I':


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[llvm-branch-commits] [cfe-branch] r261357 - Merge r261310: Add test for ARM: fix VFP asm constraints

2016-02-19 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Fri Feb 19 13:36:35 2016
New Revision: 261357

URL: http://llvm.org/viewvc/llvm-project?rev=261357&view=rev
Log:
Merge r261310: Add test for ARM: fix VFP asm constraints

Added:
cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c

Added: cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c?rev=261357&view=auto
==
--- cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c (added)
+++ cfe/branches/release_38/test/CodeGen/arm-vfp-asm-constraint.c Fri Feb 19 
13:36:35 2016
@@ -0,0 +1,36 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple armv7-unknown-unknown -mfpmath vfp -emit-llvm -o - 
%s | FileCheck %s
+
+// CHECK-NOT: error:
+
+double fabs(double x) { // CHECK-LABEL: @fabs(
+  // CHECK: call double asm "vabs.f64 ${0:P}, ${1:P}", "=w,w"(double
+  __asm__("vabs.f64 %P0, %P1"
+  : "=w"(x)
+  : "w"(x));
+  return x;
+}
+
+float fabsf(float x) { // CHECK-LABEL: @fabsf(
+  // CHECK: call float asm "vabs.f32 $0, $1", "=t,t"(float
+  __asm__("vabs.f32 %0, %1"
+  : "=t"(x)
+  : "t"(x));
+  return x;
+}
+
+double sqrt(double x) { // CHECK-LABEL: @sqrt(
+  // CHECK: call double asm "vsqrt.f64 ${0:P}, ${1:P}", "=w,w"(double
+  __asm__("vsqrt.f64 %P0, %P1"
+  : "=w"(x)
+  : "w"(x));
+  return x;
+}
+
+float sqrtf(float x) { // CHECK-LABEL: @sqrtf(
+  // CHECK: call float asm "vsqrt.f32 $0, $1", "=t,t"(float
+  __asm__("vsqrt.f32 %0, %1"
+  : "=t"(x)
+  : "t"(x));
+  return x;
+}


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Re: [llvm-branch-commits] [cfe-branch] r261343 - Merge r261309: ARM: fix VFP asm constraints

2016-02-19 Thread Renato Golin via llvm-branch-commits 
On 19 February 2016 at 19:13, Hans Wennborg  wrote:
> Thanks! Can you take r261310 too?

Sure! r261357.

Thanks!
--renato
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[llvm-branch-commits] [llvm-branch] r265243 - Merging r263118: ARM: correct __builtin_longjmp on WoA

2016-04-02 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Sat Apr  2 15:31:15 2016
New Revision: 265243

URL: http://llvm.org/viewvc/llvm-project?rev=265243&view=rev
Log:
Merging r263118: ARM: correct __builtin_longjmp on WoA



Added:
llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll
Modified:
llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp?rev=265243&r1=265242&r2=265243&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp Sat Apr  2 
15:31:15 2016
@@ -1843,8 +1843,10 @@ void ARMAsmPrinter::EmitInstruction(cons
 // ldr $scratch, [$src, #4]
 // ldr r7, [$src]
 // bx $scratch
+const Triple &TT = TM.getTargetTriple();
 unsigned SrcReg = MI->getOperand(0).getReg();
 unsigned ScratchReg = MI->getOperand(1).getReg();
+
 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
   .addReg(ScratchReg)
   .addReg(SrcReg)
@@ -1871,7 +1873,7 @@ void ARMAsmPrinter::EmitInstruction(cons
   .addReg(0));
 
 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
-  .addReg(ARM::R7)
+  .addReg(TT.isOSWindows() ? ARM::R11 : ARM::R7)
   .addReg(SrcReg)
   .addImm(0)
   // Predicate.

Added: llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll?rev=265243&view=auto
==
--- llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll (added)
+++ llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll Sat 
Apr  2 15:31:15 2016
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck 
%s
+
+declare void @llvm.eh.sjlj.longjmp(i8*)
+
+define arm_aapcs_vfpcc void @test___builtin_longjump(i8* %b) {
+entry:
+  tail call void @llvm.eh.sjlj.longjmp(i8* %b)
+  unreachable
+}
+
+; CHECK: ldr r[[SP:[0-9]+]], [r0, #8]
+; CHECK: mov sp, r[[SP]]
+; CHECK: ldr r[[PC:[0-9]+]], [r0, #4]
+; CHECK: ldr r11, [r0]
+; CHECK: bx  r[[PC]]
+


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[llvm-branch-commits] [llvm-branch] r265244 - Merging r263123: ARM: follow up improvements for SVN r263118

2016-04-02 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Sat Apr  2 15:32:54 2016
New Revision: 265244

URL: http://llvm.org/viewvc/llvm-project?rev=265244&view=rev
Log:
Merging r263123: ARM: follow up improvements for SVN r263118

Modified:
llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll

Modified: llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp Sat Apr  2 
15:32:54 2016
@@ -1837,13 +1837,13 @@ void ARMAsmPrinter::EmitInstruction(cons
   .addReg(0));
 return;
   }
-  case ARM::tInt_eh_sjlj_longjmp: {
+  case ARM::tInt_eh_sjlj_longjmp:
+  case ARM::tInt_WIN_eh_sjlj_longjmp: {
 // ldr $scratch, [$src, #8]
 // mov sp, $scratch
 // ldr $scratch, [$src, #4]
 // ldr r7, [$src]
 // bx $scratch
-const Triple &TT = TM.getTargetTriple();
 unsigned SrcReg = MI->getOperand(0).getReg();
 unsigned ScratchReg = MI->getOperand(1).getReg();
 
@@ -1873,7 +1873,7 @@ void ARMAsmPrinter::EmitInstruction(cons
   .addReg(0));
 
 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
-  .addReg(TT.isOSWindows() ? ARM::R11 : ARM::R7)
+  .addReg(Opc == ARM::tInt_WIN_eh_sjlj_longjmp ? ARM::R11 : ARM::R7)
   .addReg(SrcReg)
   .addImm(0)
   // Predicate.

Modified: llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Apr  2 
15:32:54 2016
@@ -632,6 +632,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeIn
   case ARM::Int_eh_sjlj_longjmp:
 return 16;
   case ARM::tInt_eh_sjlj_longjmp:
+  case ARM::tInt_WIN_eh_sjlj_longjmp:
 return 10;
   case ARM::Int_eh_sjlj_setjmp:
   case ARM::Int_eh_sjlj_setjmp_nofp:

Modified: llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td Sat Apr  2 15:32:54 
2016
@@ -279,6 +279,8 @@ def IsARM: Predicate<"!Subta
 def IsMachO  : Predicate<"Subtarget->isTargetMachO()">;
 def IsNotMachO   : Predicate<"!Subtarget->isTargetMachO()">;
 def IsNaCl   : Predicate<"Subtarget->isTargetNaCl()">;
+def IsWindows: Predicate<"Subtarget->isTargetWindows()">;
+def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">;
 def UseNaClTrap  : Predicate<"Subtarget->useNaClTrap()">,
  AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
 def DontUseNaClTrap  : Predicate<"!Subtarget->useNaClTrap()">;

Modified: llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td?rev=265244&r1=265243&r2=265244&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td Sat Apr  2 
15:32:54 2016
@@ -1310,7 +1310,14 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (i
   AddrModeNone, 0, IndexModeNone,
   Pseudo, NoItinerary, "", "",
   [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
- Requires<[IsThumb]>;
+ Requires<[IsThumb,IsNotWindows]>;
+
+let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
+Defs = [ R11, LR, SP ] in
+def tInt_WIN_eh_sjlj_longjmp
+  : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone,
+   Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, 
GPR:$scratch)]>,
+Requires<[IsThumb,IsWindows]>;
 
 
//===--===//
 // Non-Instruction Patterns

Modified: llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llv

[llvm-branch-commits] [llvm-branch] r265245 - Merging r263714: ARM: Revert SVN r253865, 254158, fix windows division

2016-04-02 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Sat Apr  2 15:36:55 2016
New Revision: 265245

URL: http://llvm.org/viewvc/llvm-project?rev=265245&view=rev
Log:
Merging r263714: ARM: Revert SVN r253865, 254158, fix windows division

Added:
llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll
Removed:
llvm/branches/release_38/test/CodeGen/ARM/Windows/overflow.ll
Modified:
llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_38/test/CodeGen/ARM/Windows/division.ll

Modified: llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp?rev=265245&r1=265244&r2=265245&view=diff
==
--- llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_38/lib/Target/ARM/ARMISelLowering.cpp Sat Apr  2 
15:36:55 2016
@@ -390,10 +390,6 @@ ARMTargetLowering::ARMTargetLowering(con
   { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
   { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
   { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::SDIV_I32, "__rt_sdiv",   CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::UDIV_I32, "__rt_udiv",   CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::SDIV_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS_VFP },
-  { RTLIB::UDIV_I64, "__rt_udiv64", CallingConv::ARM_AAPCS_VFP },
 };
 
 for (const auto &LC : LibraryCalls) {
@@ -780,6 +776,14 @@ ARMTargetLowering::ARMTargetLowering(con
 setOperationAction(ISD::UDIV,  MVT::i32, LibCall);
   }
 
+  if (Subtarget->isTargetWindows() && !Subtarget->hasDivide()) {
+setOperationAction(ISD::SDIV, MVT::i32, Custom);
+setOperationAction(ISD::UDIV, MVT::i32, Custom);
+
+setOperationAction(ISD::SDIV, MVT::i64, Custom);
+setOperationAction(ISD::UDIV, MVT::i64, Custom);
+  }
+
   setOperationAction(ISD::SREM,  MVT::i32, Expand);
   setOperationAction(ISD::UREM,  MVT::i32, Expand);
   // Register based DivRem for AEABI (RTABI 4.2)
@@ -6956,8 +6960,14 @@ SDValue ARMTargetLowering::LowerOperatio
   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
   case ISD::FLT_ROUNDS_:   return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::MUL:   return LowerMUL(Op, DAG);
-  case ISD::SDIV:  return LowerSDIV(Op, DAG);
-  case ISD::UDIV:  return LowerUDIV(Op, DAG);
+  case ISD::SDIV:
+if (Subtarget->isTargetWindows())
+  return LowerDIV_Windows(Op, DAG, /* Signed */ true);
+return LowerSDIV(Op, DAG);
+  case ISD::UDIV:
+if (Subtarget->isTargetWindows())
+  return LowerDIV_Windows(Op, DAG, /* Signed */ false);
+return LowerUDIV(Op, DAG);
   case ISD::ADDC:
   case ISD::ADDE:
   case ISD::SUBC:
@@ -7947,7 +7957,7 @@ ARMTargetLowering::EmitLowered__dbzchk(M
   MF->push_back(ContBB);
   ContBB->splice(ContBB->begin(), MBB,
  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
-  MBB->addSuccessor(ContBB);
+  ContBB->transferSuccessorsAndUpdatePHIs(MBB);
 
   MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
   MF->push_back(TrapBB);
@@ -7957,6 +7967,7 @@ ARMTargetLowering::EmitLowered__dbzchk(M
   BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ))
   .addReg(MI->getOperand(0).getReg())
   .addMBB(TrapBB);
+  MBB->addSuccessor(ContBB);
 
   MI->eraseFromParent();
   return ContBB;

Added: llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll?rev=265245&view=auto
==
--- llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll (added)
+++ llvm/branches/release_38/test/CodeGen/ARM/Windows/dbzchk.ll Sat Apr  2 
15:36:55 2016
@@ -0,0 +1,80 @@
+; RUN: llc -mtriple thumbv7--windows-itanium 
-print-machineinstrs=expand-isel-pseudos -o /dev/null %s 2>&1 | FileCheck %s 
-check-prefix CHECK-DIV
+
+; int f(int n, int d) {
+;   if (n / d)
+; return 1;
+;   return 0;
+; }
+
+define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) {
+entry:
+  %retval = alloca i32, align 4
+  %n.addr = alloca i32, align 4
+  %d.addr = alloca i32, align 4
+  store i32 %n, i32* %n.addr, align 4
+  store i32 %d, i32* %d.addr, align 4
+  %0 = load i32, i32* %n.addr, align 4
+  %1 = load i32, i32* %d.addr, align 4
+  %div = sdiv i32 %0, %1
+  %tobool = icmp ne i32 %div, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+  store i32 1, i32* %retval, align 4
+  br label %return
+
+if.end:
+  store i32 0, i32* %retval, align 4
+  br label %return
+
+return:
+  %2 = load i32, i32* %retval, align 4
+  ret i32 %2
+}
+
+; CHECK-DIV-DAG: BB#0
+; CHECK-DIV-DAG: Successors according to CFG: BB#5({{.*}}) BB#4
+; CHECK-DIV-DAG: BB#1
+; CHECK-DIV-DAG: Successors according to CFG: BB#3
+; CHECK-DIV-DAG: BB#2
+; CHECK-DIV-

[llvm-branch-commits] [llvm-branch] r277440 - Merging r276701 and r277439

2016-08-02 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Tue Aug  2 05:26:08 2016
New Revision: 277440

URL: http://llvm.org/viewvc/llvm-project?rev=277440&view=rev
Log:
Merging r276701 and r277439

The saturation instructions appeared in v6T2 / DSP extensions, but they
were being accepted / generated on any, with the new introduction of the
saturation detection in the back-end. This commit restricts the usage to
v6T2 / DSP-enable only cores.

Fixes PR28607.

Added:
llvm/branches/release_39/test/CodeGen/ARM/ssat-v4t.ll
llvm/branches/release_39/test/CodeGen/ARM/usat-v4t.ll
Modified:
llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/release_39/test/CodeGen/ARM/ssat.ll
llvm/branches/release_39/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt

Modified: llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp?rev=277440&r1=277439&r2=277440&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp Tue Aug  2 
05:26:08 2016
@@ -3857,7 +3857,8 @@ SDValue ARMTargetLowering::LowerSELECT_C
   // Try to convert two saturating conditional selects into a single SSAT
   SDValue SatValue;
   uint64_t SatConstant;
-  if (isSaturatingConditional(Op, SatValue, SatConstant))
+  if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || 
Subtarget->isThumb2()) &&
+  isSaturatingConditional(Op, SatValue, SatConstant))
 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
DAG.getConstant(countTrailingOnes(SatConstant), dl, 
VT));
 

Modified: llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td?rev=277440&r1=277439&r2=277440&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td Tue Aug  2 05:26:08 
2016
@@ -3650,7 +3650,8 @@ def USADA8 : AI<(outs GPR:$Rd), (ins GPR
 
 def SSAT : AI<(outs GPRnopc:$Rd),
   (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
-  SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
+  SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
+  Requires<[IsARM,HasV6]>{
   bits<4> Rd;
   bits<5> sat_imm;
   bits<4> Rn;
@@ -3666,7 +3667,8 @@ def SSAT : AI<(outs GPRnopc:$Rd),
 
 def SSAT16 : AI<(outs GPRnopc:$Rd),
 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
-NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
+NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
+Requires<[IsARM,HasV6]>{
   bits<4> Rd;
   bits<4> sat_imm;
   bits<4> Rn;
@@ -3679,7 +3681,8 @@ def SSAT16 : AI<(outs GPRnopc:$Rd),
 
 def USAT : AI<(outs GPRnopc:$Rd),
   (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
-  SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
+  SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
+  Requires<[IsARM,HasV6]> {
   bits<4> Rd;
   bits<5> sat_imm;
   bits<4> Rn;
@@ -3695,7 +3698,8 @@ def USAT : AI<(outs GPRnopc:$Rd),
 
 def USAT16 : AI<(outs GPRnopc:$Rd),
 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
-NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
+NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
+Requires<[IsARM,HasV6]>{
   bits<4> Rd;
   bits<4> sat_imm;
   bits<4> Rn;

Modified: llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td?rev=277440&r1=277439&r2=277440&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td Tue Aug  2 
05:26:08 2016
@@ -2240,7 +2240,8 @@ class T2SatI {
+  NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
+  Requires<[IsThumb2]> {
   let Inst{31-27} = 0b0;
   let Inst{25-22} = 0b1100;
   let Inst{20} = 0;
@@ -2251,7 +2252,7 @@ def t2SSAT: T2SatI<
 def t2SSAT16: T2SatI<
 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
 "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
-  Requires<[IsThumb2, HasDSP]> {
+Requires<[IsThumb2, HasDSP]> {
   let Inst{31-27} = 0b0;
   let Inst{25-22} = 0b1100;
   let Inst{20} = 0;
@@ -2265,7 +2266,8 @@ def t2SSAT16: T2SatI<
 def

[llvm-branch-commits] [llvm-branch] r277587 - [docs] Release Notes 3.9.0: GCC ABI Tag

2016-08-03 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Wed Aug  3 06:07:48 2016
New Revision: 277587

URL: http://llvm.org/viewvc/llvm-project?rev=277587&view=rev
Log:
[docs] Release Notes 3.9.0: GCC ABI Tag

Adding a short explanation of the GCC ABI Tag discussion and issues, with
links and considerations.

Modified:
llvm/branches/release_39/docs/ReleaseNotes.rst

Modified: llvm/branches/release_39/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/docs/ReleaseNotes.rst?rev=277587&r1=277586&r2=277587&view=diff
==
--- llvm/branches/release_39/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_39/docs/ReleaseNotes.rst Wed Aug  3 06:07:48 2016
@@ -93,6 +93,32 @@ Non-comprehensive list of changes in thi
 
Makes programs 10x faster by doing Special New Thing.
 
+GCC ABI Tag
+---
+
+Recently, many of the Linux distributions (ex. `Fedora 
`_,
+`Debian `_, `Ubuntu 
`_)
+have moved on to use the new `GCC ABI 
`_
+to work around `C++11 incompatibilities in libstdc++ 
`_.
+This caused `incompatibility problems 
`_
+with other compilers (ex. Clang), which needed to be fixed, but due to the
+experimental nature of GCC's own implementation, it took a long time for it to
+land in LLVM (`here `_ and
+`here `_), not in time for the 3.8 release.
+
+Those patches are now present in the 3.9.0 release and should be working on the
+majority of cases, as they have been tested thoroughly. However, some bugs were
+`filled in GCC `_ and have 
not
+yet been fixed, so there may be corner cases not covered by either GCC or 
Clang.
+Bug fixes to those problems should be reported in Bugzilla (either LLVM or 
GCC),
+and patches to LLVM's trunk are very likely to be back-ported to future 3.9.x
+releases (depends on how destructive it is).
+
+Unfortunately, these patches won't be back-ported to 3.8.x or earlier, so we
+strongly recommend people to use 3.9.x when GCC ABI cases are at stake.
+
+For a more in-depth view of the issue, check our `Bugzilla entry 
`_.
+
 Changes to the LLVM IR
 --
 


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[llvm-branch-commits] [llvm-branch] r277591 - [docs] Release notes 3.9.0: Adding ARM target changes

2016-08-03 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Wed Aug  3 07:52:40 2016
New Revision: 277591

URL: http://llvm.org/viewvc/llvm-project?rev=277591&view=rev
Log:
[docs] Release notes 3.9.0: Adding ARM target changes

Modified:
llvm/branches/release_39/docs/ReleaseNotes.rst

Modified: llvm/branches/release_39/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/docs/ReleaseNotes.rst?rev=277591&r1=277590&r2=277591&view=diff
==
--- llvm/branches/release_39/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_39/docs/ReleaseNotes.rst Wed Aug  3 07:52:40 2016
@@ -139,7 +139,7 @@ behavior.  See `PR26774

[llvm-branch-commits] [llvm-branch] r277593 - [code] Fix release notes typo

2016-08-03 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Wed Aug  3 08:20:58 2016
New Revision: 277593

URL: http://llvm.org/viewvc/llvm-project?rev=277593&view=rev
Log:
[code] Fix release notes typo

Modified:
llvm/branches/release_39/docs/ReleaseNotes.rst

Modified: llvm/branches/release_39/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/docs/ReleaseNotes.rst?rev=277593&r1=277592&r2=277593&view=diff
==
--- llvm/branches/release_39/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_39/docs/ReleaseNotes.rst Wed Aug  3 08:20:58 2016
@@ -165,7 +165,7 @@ Changes to the ARM Targets
 * Initial ARM/Thumb support was added to LLD.
 * The ExecutionEngine now supports COFF/ARM
 * Swift calling convention was ported to ARM
-* A large number of cddegen fixes around ARMv8, DSP, correct sub-target 
support,
+* A large number of codegen fixes around ARMv8, DSP, correct sub-target 
support,
   relocations, EABI, EHABI, Windows on ARM, atomics.
 * Improved assembler support for Linux/Android/Chromium sub-projects.
 * Initial support for MUSL (libc) on ARM


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[llvm-branch-commits] [llvm-branch] r277606 - [docs] release notes: self-host clang+lld on aarch64, stops

2016-08-03 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Wed Aug  3 11:09:12 2016
New Revision: 277606

URL: http://llvm.org/viewvc/llvm-project?rev=277606&view=rev
Log:
[docs] release notes: self-host clang+lld on aarch64, stops

Modified:
llvm/branches/release_39/docs/ReleaseNotes.rst

Modified: llvm/branches/release_39/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/docs/ReleaseNotes.rst?rev=277606&r1=277605&r2=277606&view=diff
==
--- llvm/branches/release_39/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_39/docs/ReleaseNotes.rst Wed Aug  3 11:09:12 2016
@@ -142,17 +142,18 @@ Changes to the ARM Targets
 **During this release the AArch64 backend has:**
 
 * Gained support for Qualcomm's Kryo and Broadcom's Vulcan CPUs, including
-  scheduling models
-* Landed a scheduling model for Samsung's Exynos M1
-* Seen a lot of work on GlobalISel
+  scheduling models.
+* Landed a scheduling model for Samsung's Exynos M1.
+* Seen a lot of work on GlobalISel.
 * Learned a few more useful combines (fadd and fmul into fmadd, adjustments to 
the
-  stack pointer for callee-save stack memory and local stack memory etc)
-* Gained support for the Swift calling convention
+  stack pointer for callee-save stack memory and local stack memory etc).
+* Gained support for the Swift calling convention.
 * Switched to using SubtargetFeatures rather than testing for specific CPUs and
-  to using TableGen for handling system instruction operands
+  to using TableGen for handling system instruction operands.
 * Like ARM, AArch64 is now using the TargetParser, so no more StringSwitches
   matching CPU, FPU or feature names will be accepted in normal code.
-* Gained a big batch of tests from Halide
+* Clang can now self-host itself using LLD on AArch64.
+* Gained a big batch of tests from Halide.
 
  Furthermore, LLDB now supports AArch64 compact unwind tables, as used on iOS,
  tvos and watchos.
@@ -160,17 +161,17 @@ Changes to the ARM Targets
 **During this release the ARM target has:**
 
 * ARMv8.2-A can now be targeted directly via Clang flags.
-* Adding preliminary support for Cortex-R8
+* Adding preliminary support for Cortex-R8.
 * LLDB can now parse EABI attributes for an ELF input.
 * Initial ARM/Thumb support was added to LLD.
-* The ExecutionEngine now supports COFF/ARM
-* Swift calling convention was ported to ARM
+* The ExecutionEngine now supports COFF/ARM.
+* Swift calling convention was ported to ARM.
 * A large number of codegen fixes around ARMv8, DSP, correct sub-target 
support,
-  relocations, EABI, EHABI, Windows on ARM, atomics.
+  relocations, EABI, EHABI, Windows on ARM, atomics..
 * Improved assembler support for Linux/Android/Chromium sub-projects.
-* Initial support for MUSL (libc) on ARM
-* Support for Thumb1 targets in libunwind
-* Gained a big batch of tests from Halide
+* Initial support for MUSL (libc) on ARM.
+* Support for Thumb1 targets in libunwind.
+* Gained a big batch of tests from Halide.
 
 
 Changes to the MIPS Target


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[llvm-branch-commits] [llvm-branch] r281634 - [3.9.1] Merging r281319 [ARM] Support ldr.w in pseudo instruction ldr rd, =immediate

2016-09-15 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Thu Sep 15 13:10:44 2016
New Revision: 281634

URL: http://llvm.org/viewvc/llvm-project?rev=281634&view=rev
Log:
[3.9.1] Merging r281319 [ARM] Support ldr.w in pseudo instruction ldr 
rd,=immediate

Added:
llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s
Modified:
llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td?rev=281634&r1=281633&r2=281634&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td Thu Sep 15 
13:10:44 2016
@@ -4819,6 +4819,10 @@ def : t2InstAlias<"add${p} $Rd, pc, $imm
 def t2LDRConstPool
   : t2AsmPseudo<"ldr${p} $Rt, $immediate",
 (ins GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
+// Version w/ the .w suffix.
+def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
+  (t2LDRConstPool GPRnopc:$Rt,
+  const_pool_asm_imm:$immediate, pred:$p)>;
 
 // PLD/PLDW/PLI with alternate literal form.
 def : t2InstAlias<"pld${p} $addr",

Modified: llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=281634&r1=281633&r2=281634&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp 
(original)
+++ llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Sep 
15 13:10:44 2016
@@ -6933,6 +6933,9 @@ bool ARMAsmParser::processInstruction(MC
 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
   TmpInst.setOpcode(ARM::t2LDRpci);
 const ARMOperand &PoolOperand =
+  (static_cast(*Operands[2]).isToken() &&
+   static_cast(*Operands[2]).getToken() == ".w") ?
+  static_cast(*Operands[4]) :
   static_cast(*Operands[3]);
 const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
 // If SubExprVal is a constant we may be able to use a MOV

Added: llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s?rev=281634&view=auto
==
--- llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s (added)
+++ llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s Thu Sep 15 13:10:44 
2016
@@ -0,0 +1,71 @@
+@ Test case for PR30352
+@ Check that ldr.w is:
+@ accepted and ignored for ARM
+@ accepted and propagated for Thumb2
+@ rejected as needing Thumb2 for Thumb
+
+@RUN: llvm-mc -triple armv5-unknown-linux-gnueabi %s | FileCheck 
--check-prefix=CHECK-ARM --check-prefix=CHECK %s
+@RUN: llvm-mc -triple   armv7-base-apple-darwin %s | FileCheck 
--check-prefix=CHECK-DARWIN-ARM --check-prefix=CHECK-DARWIN %s
+@RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s | FileCheck 
--check-prefix=CHECK-THUMB2 --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv7-base-apple-darwin %s | FileCheck 
--check-prefix=CHECK-DARWIN-THUMB2 --check-prefix=CHECK-DARWIN %s
+@RUN: not llvm-mc -triple thumbv6-unknown-linux-gnueabi %s 2>&1 | FileCheck 
--check-prefix=CHECK-THUMB %s
+@RUN: not llvm-mc -triple thumbv6-base-apple-darwin %s 2>&1 | FileCheck 
--check-prefix=CHECK-THUMB %s
+@ CHECK-LABEL: f1:
+f1:
+  ldr r0, =0x10002
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP0:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp0
+@ CHECK-THUMB2: ldr r0, .Ltmp[[TMP0:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr r0, Ltmp0
+
+  ldr.w r0, =0x10002
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP1:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp1
+@ CHECK-THUMB2: ldr.w r0, .Ltmp[[TMP1:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr.w r0, Ltmp1
+@ CHECK-THUMB: error: instruction requires: thumb2
+@ CHECK-THUMB-NEXT:  ldr.w r0, =0x10002
+
+@ CHECK-LABEL: f2:
+f2:
+  ldr r0, =foo
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP2:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp2
+@ CHECK-THUMB2: ldr r0, .Ltmp[[TMP2:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr r0, Ltmp2
+
+  ldr.w r0, =foo
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP3:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp3
+@ CHECK-THUMB2: ldr.w r0, .Ltmp[[TMP3:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr.w r0, Ltmp3
+@ CHECK-THUMB: error: instruction requires: thumb2
+@ CHECK-THUMB-NEXT:  ldr.w r0, =foo
+
+@ CHECK-LABEL: f3:
+f3:
+  ldr.w r1, =0x1
+@ CHECK-ARM: mov r1, #1
+@ CHECK-DARWIN-ARM: mov r1, #1
+@ CHECK-THUMB2: mov.w r1, #1
+@ CHECK-DARWIN-THUMB2: mov.w r1, #1
+@ CHECK-THUMB: error: instruction requires: thumb2
+@ CHECK-THUMB-NEXT:  ldr.w r1, =0x1
+
+@ CHECK: .Ltmp0:
+@ CHECK-NEXT: .long   65538
+@ CHECK: .Ltmp1:
+@ CHECK-NEXT: .long   65538
+@ CHECK: .Ltmp2:
+@ CHECK-NEXT: .l

[llvm-branch-commits] [compiler-rt-branch] r287441 - [3.9.1] Merging r287359:

2016-11-19 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Sat Nov 19 08:00:50 2016
New Revision: 287441

URL: http://llvm.org/viewvc/llvm-project?rev=287441&view=rev
Log:
[3.9.1] Merging r287359:

builtins: repair the builtins build with clang 3.8

When the C unwinding personality was corrected to match the ARM EHABI
specification, the unwind header in clang was updated with necessary
declarations.  However, when building with an older compiler, we would not have
the necessary declarations.  This would result in a build failure.  Provide a
supplementary header to ensure that the necessary declarations are present for
the build of the C unwinding personality.

Note that this is NOT an ABI break.  It merely is a compile time failure due to
the constants not being present.  The constants here are reproduced
equivalently.  This header should permit building with clang[<3.9] as well as
gcc.

Addresses PR31035!

Added:
compiler-rt/branches/release_39/lib/builtins/unwind-ehabi-helpers.h
Modified:
compiler-rt/branches/release_39/lib/builtins/gcc_personality_v0.c

Modified: compiler-rt/branches/release_39/lib/builtins/gcc_personality_v0.c
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_39/lib/builtins/gcc_personality_v0.c?rev=287441&r1=287440&r2=287441&view=diff
==
--- compiler-rt/branches/release_39/lib/builtins/gcc_personality_v0.c (original)
+++ compiler-rt/branches/release_39/lib/builtins/gcc_personality_v0.c Sat Nov 
19 08:00:50 2016
@@ -12,6 +12,17 @@
 #include "int_lib.h"
 
 #include 
+#if defined(__arm__) && !defined(__ARM_DWARF_EH__) && 
!defined(__USING_SJLJ_EXCEPTIONS__)
+/*
+ * When building with older compilers (e.g. clang <3.9), it is possible that we
+ * have a version of unwind.h which does not provide the EHABI declarations
+ * which are quired for the C personality to conform to the specification.  In
+ * order to provide forward compatibility for such compilers, we re-declare the
+ * necessary interfaces in the helper to permit a standalone compilation of the
+ * builtins (which contains the C unwinding personality for historical 
reasons).
+ */
+#include "unwind-ehabi-helpers.h"
+#endif
 
 /*
  * Pointer encodings documented at:

Added: compiler-rt/branches/release_39/lib/builtins/unwind-ehabi-helpers.h
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_39/lib/builtins/unwind-ehabi-helpers.h?rev=287441&view=auto
==
--- compiler-rt/branches/release_39/lib/builtins/unwind-ehabi-helpers.h (added)
+++ compiler-rt/branches/release_39/lib/builtins/unwind-ehabi-helpers.h Sat Nov 
19 08:00:50 2016
@@ -0,0 +1,55 @@
+/* ===-- arm-ehabi-helpers.h - Supplementary ARM EHABI declarations ===
+ *
+ * The LLVM Compiler Infrastructure
+ *
+ * This file is dual licensed under the MIT and the University of Illinois Open
+ * Source Licenses. See LICENSE.TXT for details.
+ *
+ * ====== 
*/
+
+#ifndef UNWIND_EHABI_HELPERS_H
+#define UNWIND_EHABI_HELPERS_H
+
+#include 
+/* NOTE: see reasoning for this inclusion below */
+#include 
+
+#if !defined(__ARM_EABI_UNWINDER__)
+
+/*
+ * NOTE: _URC_OK, _URC_FAILURE must be present as preprocessor tokens.  This
+ * allows for a substitution of a constant which can be cast into the
+ * appropriate enumerated type.  This header is expected to always be included
+ * AFTER unwind.h (which is why it is forcefully included above).  This ensures
+ * that we do not overwrite the token for the enumeration.  Subsequent uses of
+ * the token would be clean to rewrite with constant values.
+ *
+ * The typedef redeclaration should be safe.  Due to the protection granted to
+ * us by the `__ARM_EABI_UNWINDER__` above, we are guaranteed that we are in a
+ * header not vended by gcc.  The HP unwinder (being an itanium unwinder) does
+ * not support EHABI, and the GNU unwinder, derived from the HP unwinder, also
+ * does not support EHABI as of the introduction of this header.  As such, we
+ * are fairly certain that we are in the LLVM case.  Here, _Unwind_State is a
+ * typedef, and so we can get away with a redeclaration.
+ *
+ * Guarded redefinitions of the needed unwind state prevent the redefinition of
+ * those states.
+ */
+
+#define _URC_OK   0
+#define _URC_FAILURE  9
+
+typedef uint32_t _Unwind_State;
+
+#if !defined(_US_UNWIND_FRAME_STARTING)
+#define _US_UNWIND_FRAME_STARTING ((_Unwind_State)1)
+#endif
+
+#if !defined(_US_ACTION_MASK)
+#define _US_ACTION_MASK ((_Unwind_State)3)
+#endif
+
+#endif
+
+#endif
+


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[llvm-branch-commits] [compiler-rt-branch] r288513 - [ARM|RT] Merging r24766 into 3.9.1

2016-12-02 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Fri Dec  2 11:33:09 2016
New Revision: 288513

URL: http://llvm.org/viewvc/llvm-project?rev=288513&view=rev
Log:
[ARM|RT] Merging r24766 into 3.9.1

Fixes a bug encountered in RC2 validation.

Modified:

compiler-rt/branches/release_39/test/sanitizer_common/TestCases/Linux/sem_init_glibc.cc

Modified: 
compiler-rt/branches/release_39/test/sanitizer_common/TestCases/Linux/sem_init_glibc.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_39/test/sanitizer_common/TestCases/Linux/sem_init_glibc.cc?rev=288513&r1=288512&r2=288513&view=diff
==
--- 
compiler-rt/branches/release_39/test/sanitizer_common/TestCases/Linux/sem_init_glibc.cc
 (original)
+++ 
compiler-rt/branches/release_39/test/sanitizer_common/TestCases/Linux/sem_init_glibc.cc
 Fri Dec  2 11:33:09 2016
@@ -17,6 +17,21 @@ typedef uint64_t semval_t;
 typedef unsigned semval_t;
 #endif
 
+// glibc 2.21 has introduced some changes in the way the semaphore value is
+// handled for 32-bit platforms, but since these changes are not ABI-breaking
+// they are not versioned. On newer platforms such as ARM, there is only one
+// version of the symbol, so it's enough to check the glibc version. However,
+// for old platforms such as i386, glibc contains two or even three versions of
+// the sem_init symbol, and the sanitizers always pick the oldest one.
+// Therefore, it is not enough to rely on the __GLIBC_PREREQ macro - we should
+// instead check the platform as well to make sure we only expect the new
+// behavior on platforms where the older symbols do not exist.
+#if defined(__arm__) && __GLIBC_PREREQ(2, 21)
+#define GET_SEM_VALUE(V) ((V) >> 1)
+#else
+#define GET_SEM_VALUE(V) (V)
+#endif
+
 void my_sem_init(bool priv, int value, semval_t *a, unsigned char *b) {
   sem_t sem;
   memset(&sem, 0xAB, sizeof(sem));
@@ -34,10 +49,10 @@ int main() {
   unsigned char b;
 
   my_sem_init(false, 42, &a, &b);
-  assert(a == 42);
+  assert(GET_SEM_VALUE(a) == 42);
   assert(b != 0xAB);
 
   my_sem_init(true, 43, &a, &b);
-  assert(a == 43);
+  assert(GET_SEM_VALUE(a) == 43);
   assert(b != 0xAB);
 }


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[llvm-branch-commits] [llvm-branch] r297090 - [notes] adding vulcan rename to release notes

2017-03-06 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Mon Mar  6 16:56:55 2017
New Revision: 297090

URL: http://llvm.org/viewvc/llvm-project?rev=297090&view=rev
Log:
[notes] adding vulcan rename to release notes

Modified:
llvm/branches/release_40/docs/ReleaseNotes.rst

Modified: llvm/branches/release_40/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/docs/ReleaseNotes.rst?rev=297090&r1=297089&r2=297090&view=diff
==
--- llvm/branches/release_40/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_40/docs/ReleaseNotes.rst Mon Mar  6 16:56:55 2017
@@ -225,6 +225,10 @@ Changes to the ARM Targets
 A lot of work has also been done in LLD for ARM, which now supports more
 relocations and TLS.
 
+Note: From the next release (5.0), the "vulcan" target will be renamed to
+"thunderx2t99", including command line options, assembly directives, etc. This
+release (4.0) will be the last one to accept "vulcan" as its name.
+
 Changes to the AVR Target
 -
 


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[llvm-branch-commits] [compiler-rt-branch] r303146 - Merging rr302639:

2017-05-16 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Tue May 16 01:57:03 2017
New Revision: 303146

URL: http://llvm.org/viewvc/llvm-project?rev=303146&view=rev
Log:
Merging rr302639:

r302639 | azanella | 2017-05-10 13:18:25 +0100 (Wed, 10 May 2017) | 11 lines

[msan] Fix getmntent{_r} for empty /etc/fstab

Some configuration (for instance default docker ubuntu images) uses
a default empty and invalid /etc/fstab configuration file.  It makes
any call to getmntent return NULL and it leads to failures on
Msan-aarch64{-with-call}-Test/MemorySanitizer.getmntent{_r}.

This patch fixes it by creating a temporary file with some valid
entries (although not valid for the system) to use along with
setmntent/getmntent.



Modified:
compiler-rt/branches/release_40/   (props changed)
compiler-rt/branches/release_40/lib/msan/tests/msan_test.cc

Propchange: compiler-rt/branches/release_40/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue May 16 01:57:03 2017
@@ -1 +1 @@
-/compiler-rt/trunk:292257,292517,292729,293120,293536,294425,294806,294886
+/compiler-rt/trunk:292257,292517,292729,293120,293536,294425,294806,294886,302639

Modified: compiler-rt/branches/release_40/lib/msan/tests/msan_test.cc
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_40/lib/msan/tests/msan_test.cc?rev=303146&r1=303145&r2=303146&view=diff
==
--- compiler-rt/branches/release_40/lib/msan/tests/msan_test.cc (original)
+++ compiler-rt/branches/release_40/lib/msan/tests/msan_test.cc Tue May 16 
01:57:03 2017
@@ -2124,10 +2124,51 @@ TEST(MemorySanitizer, localtime_r) {
   EXPECT_NE(0U, strlen(time.tm_zone));
 }
 
+#if !defined(__FreeBSD__)
+/* Creates a temporary file with contents similar to /etc/fstab to be used
+   with getmntent{_r}.  */
+class TempFstabFile {
+ public:
+   TempFstabFile() : fd (-1) { }
+   ~TempFstabFile() {
+ if (fd >= 0)
+   close (fd);
+   }
+
+   bool Create(void) {
+ snprintf(tmpfile, sizeof(tmpfile), "/tmp/msan.getmntent.tmp.XX");
+
+ fd = mkstemp(tmpfile);
+ if (fd == -1)
+   return false;
+
+ const char entry[] = "/dev/root / ext4 errors=remount-ro 0 1";
+ size_t entrylen = sizeof(entry);
+
+ size_t bytesWritten = write(fd, entry, entrylen);
+ if (entrylen != bytesWritten)
+   return false;
+
+ return true;
+   }
+
+   const char* FileName(void) {
+ return tmpfile;
+   }
+
+ private:
+  char tmpfile[128];
+  int fd;
+};
+#endif
+
 // There's no getmntent() on FreeBSD.
 #if !defined(__FreeBSD__)
 TEST(MemorySanitizer, getmntent) {
-  FILE *fp = setmntent("/etc/fstab", "r");
+  TempFstabFile fstabtmp;
+  ASSERT_TRUE(fstabtmp.Create());
+  FILE *fp = setmntent(fstabtmp.FileName(), "r");
+
   struct mntent *mnt = getmntent(fp);
   ASSERT_TRUE(mnt != NULL);
   ASSERT_NE(0U, strlen(mnt->mnt_fsname));
@@ -2143,7 +2184,10 @@ TEST(MemorySanitizer, getmntent) {
 // There's no getmntent_r() on FreeBSD.
 #if !defined(__FreeBSD__)
 TEST(MemorySanitizer, getmntent_r) {
-  FILE *fp = setmntent("/etc/fstab", "r");
+  TempFstabFile fstabtmp;
+  ASSERT_TRUE(fstabtmp.Create());
+  FILE *fp = setmntent(fstabtmp.FileName(), "r");
+
   struct mntent mntbuf;
   char buf[1000];
   struct mntent *mnt = getmntent_r(fp, &mntbuf, buf, sizeof(buf));


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[llvm-branch-commits] [llvm-branch] r311578 - [ARM] more release notes updates for 5.0

2017-08-23 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Wed Aug 23 10:04:59 2017
New Revision: 311578

URL: http://llvm.org/viewvc/llvm-project?rev=311578&view=rev
Log:
[ARM] more release notes updates for 5.0

Modified:
llvm/branches/release_50/docs/ReleaseNotes.rst

Modified: llvm/branches/release_50/docs/ReleaseNotes.rst
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/docs/ReleaseNotes.rst?rev=311578&r1=311577&r2=311578&view=diff
==
--- llvm/branches/release_50/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_50/docs/ReleaseNotes.rst Wed Aug 23 10:04:59 2017
@@ -82,14 +82,24 @@ Changes to the Arm Targets
 
 During this release the AArch64 target has:
 
+* A much improved Global ISel at O0.
+* Support for ARMv8.1 8.2 and 8.3 instructions.
+* New scheduler information for ThunderX2.
+* Some SVE type changes but not much more than that.
 * Made instruction fusion more aggressive, resulting in speedups
   for code making use of AArch64 AES instructions. AES fusion has been
   enabled for most Cortex-A cores and the AArch64MacroFusion pass was moved
   to the generic MacroFusion pass.
 * Added preferred function alignments for most Cortex-A cores.
+* OpenMP "offload-to-self" base support.
 
 During this release the ARM target has:
 
+* Improved, but still mostly broken, Global ISel.
+* Scheduling models update, new schedule for Cortex-A57.
+* Hardware breakpoint support in LLDB.
+* New assembler error handling, with spelling corrections and multiple
+  suggestions on how to fix problems.
 * Improved mixed ARM/Thumb code generation. Some cases in which wrong
   relocations were emitted have been fixed.
 * Added initial support for mixed ARM/Thumb link-time optimization, using the


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[llvm-branch-commits] [llvm-branch] r314796 - [release_50] Merging r313916

2017-10-03 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Tue Oct  3 06:13:34 2017
New Revision: 314796

URL: http://llvm.org/viewvc/llvm-project?rev=314796&view=rev
Log:
[release_50] Merging r313916

[AArch64] Fix bug in store of vector 0 DAGCombine.

Summary:
Avoid using XZR/WZR directly as operands to split stores of zero
vectors.  Doing so can lead to the XZR/WZR being used by an instruction
that doesn't allow it (e.g. add).

Fixes bug 34674.

Reviewers: t.p.northover, efriedma, MatzeB

Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, 
kristof.beyls

Differential Revision: https://reviews.llvm.org/D38146

PR34695.


Modified:
llvm/branches/release_50/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/branches/release_50/test/CodeGen/AArch64/arm64-memset-inline.ll
llvm/branches/release_50/test/CodeGen/AArch64/fastcc.ll
llvm/branches/release_50/test/CodeGen/AArch64/ldst-opt.ll

Modified: llvm/branches/release_50/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=314796&r1=314795&r2=314796&view=diff
==
--- llvm/branches/release_50/lib/Target/AArch64/AArch64ISelLowering.cpp 
(original)
+++ llvm/branches/release_50/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Oct 
 3 06:13:34 2017
@@ -9347,11 +9347,20 @@ static SDValue replaceZeroVectorStore(Se
   return SDValue();
   }
 
-  // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from
-  // undoing this transformation.
-  SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32
- ? DAG.getRegister(AArch64::WZR, MVT::i32)
- : DAG.getRegister(AArch64::XZR, MVT::i64);
+  // Use a CopyFromReg WZR/XZR here to prevent
+  // DAGCombiner::MergeConsecutiveStores from undoing this transformation.
+  SDLoc DL(&St);
+  unsigned ZeroReg;
+  EVT ZeroVT;
+  if (VT.getVectorElementType().getSizeInBits() == 32) {
+ZeroReg = AArch64::WZR;
+ZeroVT = MVT::i32;
+  } else {
+ZeroReg = AArch64::XZR;
+ZeroVT = MVT::i64;
+  }
+  SDValue SplatVal =
+  DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
   return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
 }
 

Modified: llvm/branches/release_50/test/CodeGen/AArch64/arm64-memset-inline.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AArch64/arm64-memset-inline.ll?rev=314796&r1=314795&r2=314796&view=diff
==
--- llvm/branches/release_50/test/CodeGen/AArch64/arm64-memset-inline.ll 
(original)
+++ llvm/branches/release_50/test/CodeGen/AArch64/arm64-memset-inline.ll Tue 
Oct  3 06:13:34 2017
@@ -12,9 +12,9 @@ entry:
 define void @t2() nounwind ssp {
 entry:
 ; CHECK-LABEL: t2:
+; CHECK: stp xzr, xzr, [sp, #16]
 ; CHECK: strh wzr, [sp, #32]
-; CHECK: stp xzr, xzr, [sp, #8]
-; CHECK: str xzr, [sp, #24]
+; CHECK: str xzr, [sp, #8]
   %buf = alloca [26 x i8], align 1
   %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)

Modified: llvm/branches/release_50/test/CodeGen/AArch64/fastcc.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/AArch64/fastcc.ll?rev=314796&r1=314795&r2=314796&view=diff
==
--- llvm/branches/release_50/test/CodeGen/AArch64/fastcc.ll (original)
+++ llvm/branches/release_50/test/CodeGen/AArch64/fastcc.ll Tue Oct  3 06:13:34 
2017
@@ -21,9 +21,11 @@ define fastcc void @func_stack0() {
   call fastcc void @func_stack8([8 x i32] undef, i32 42)
 ; CHECK:  bl func_stack8
 ; CHECK-NOT: sub sp, sp,
+; CHECK-NOT: [sp, #{{[-0-9]+}}]!
+; CHECK-NOT: [sp], #{{[-0-9]+}}
 
 ; CHECK-TAIL: bl func_stack8
-; CHECK-TAIL: sub sp, sp, #16
+; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
 
 
   call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
@@ -72,10 +74,12 @@ define fastcc void @func_stack8([8 x i32
   call fastcc void @func_stack8([8 x i32] undef, i32 42)
 ; CHECK:  bl func_stack8
 ; CHECK-NOT: sub sp, sp,
+; CHECK-NOT: [sp, #{{[-0-9]+}}]!
+; CHECK-NOT: [sp], #{{[-0-9]+}}
 
 
 ; CHECK-TAIL: bl func_stack8
-; CHECK-TAIL: sub sp, sp, #16
+; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
 
 
   call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
@@ -116,9 +120,11 @@ define fastcc void @func_stack32([8 x i3
   call fastcc void @func_stack8([8 x i32] undef, i32 42)
 ; CHECK:  bl func_stack8
 ; CHECK-NOT: sub sp, sp,
+; CHECK-NOT: [sp, #{{[-0-9]+}}]!
+; CHECK-NOT: [sp], #{{[-0-9]+}}
 
 ; CHECK-TAIL: bl func_stack8
-; CHECK-TAIL: sub sp, sp, #16
+; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
 
 
   call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)

Modified: llvm/branches/release_50/test/CodeGen/AArch64/ldst-opt.ll
URL: 
http://llvm.

[llvm-branch-commits] [libunwind] r316664 - Merging r316657: fixing libunwind tests

2017-10-26 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Thu Oct 26 06:53:36 2017
New Revision: 316664

URL: http://llvm.org/viewvc/llvm-project?rev=316664&view=rev
Log:
Merging r316657: fixing libunwind tests

Modified:
libunwind/branches/release_50/test/libunwind/test/config.py

Modified: libunwind/branches/release_50/test/libunwind/test/config.py
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/branches/release_50/test/libunwind/test/config.py?rev=316664&r1=316663&r2=316664&view=diff
==
--- libunwind/branches/release_50/test/libunwind/test/config.py (original)
+++ libunwind/branches/release_50/test/libunwind/test/config.py Thu Oct 26 
06:53:36 2017
@@ -43,10 +43,11 @@ class Configuration(LibcxxConfiguration)
 
 def configure_compile_flags(self):
 self.cxx.compile_flags += ['-DLIBUNWIND_NO_TIMER']
-if self.get_lit_bool('enable_exceptions', True):
-self.cxx.compile_flags += ['-funwind-tables']
-else:
+if not self.get_lit_bool('enable_exceptions', True):
 self.cxx.compile_flags += ['-fno-exceptions', 
'-DLIBUNWIND_HAS_NO_EXCEPTIONS']
+# Stack unwinding tests need unwinding tables and these are not
+# generated by default on all Targets.
+self.cxx.compile_flags += ['-funwind-tables']
 if not self.get_lit_bool('enable_threads', True):
 self.cxx.compile_flags += ['-D_LIBUNWIND_HAS_NO_THREADS']
 self.config.available_features.add('libunwind-no-threads')


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[llvm-branch-commits] [libunwind] r316991 - Merge r311574: ARM: explicitly specify the 8-byte alignment

2017-10-31 Thread Renato Golin via llvm-branch-commits 
Author: rengolin
Date: Tue Oct 31 05:21:32 2017
New Revision: 316991

URL: http://llvm.org/viewvc/llvm-project?rev=316991&view=rev
Log:
Merge r311574: ARM: explicitly specify the 8-byte alignment

Fixing the last libunwind failure on ARM.



Modified:
libunwind/branches/release_50/include/unwind.h
libunwind/branches/release_50/test/alignment.pass.cpp

Modified: libunwind/branches/release_50/include/unwind.h
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/branches/release_50/include/unwind.h?rev=316991&r1=316990&r2=316991&view=diff
==
--- libunwind/branches/release_50/include/unwind.h (original)
+++ libunwind/branches/release_50/include/unwind.h Tue Oct 31 05:21:32 2017
@@ -100,7 +100,7 @@ struct _Unwind_Control_Block {
   } pr_cache;
 
   long long int :0; /* Enforce the 8-byte alignment */
-};
+} __attribute__((__aligned__(8)));
 
 typedef _Unwind_Reason_Code (*_Unwind_Stop_Fn)
   (_Unwind_State state,

Modified: libunwind/branches/release_50/test/alignment.pass.cpp
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/branches/release_50/test/alignment.pass.cpp?rev=316991&r1=316990&r2=316991&view=diff
==
--- libunwind/branches/release_50/test/alignment.pass.cpp (original)
+++ libunwind/branches/release_50/test/alignment.pass.cpp Tue Oct 31 05:21:32 
2017
@@ -13,8 +13,16 @@
 
 #include 
 
-struct MaxAligned {} __attribute__((aligned));
-static_assert(alignof(_Unwind_Exception) == alignof(MaxAligned), "");
+// EHABI  : 8-byte aligned
+// itanium: largest supported alignment for the system
+#if defined(_LIBUNWIND_ARM_EHABI)
+static_assert(alignof(_Unwind_Control_Block) == 8,
+  "_Unwind_Control_Block must be double-word aligned");
+#else
+struct MaxAligned {} __attribute__((__aligned__));
+static_assert(alignof(_Unwind_Exception) == alignof(MaxAligned),
+  "_Unwind_Exception must be maximally aligned");
+#endif
 
 int main()
 {


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[llvm-branch-commits] [mlir] [mlir][linalg] Simplify `createWriteOrMaskedWrite` (NFC) (PR #141567)

2025-05-29 Thread Renato Golin via llvm-branch-commits 

https://github.com/rengolin approved this pull request.

Nice clean up, thanks!

https://github.com/llvm/llvm-project/pull/141567
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[llvm-branch-commits] [mlir] [mlir] Nominate Tensor Compiler maintainers (PR #149488)

2025-07-18 Thread Renato Golin via llvm-branch-commits 

https://github.com/rengolin approved this pull request.


https://github.com/llvm/llvm-project/pull/149488
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