Author: rengolin Date: Sat Apr 2 15:32:54 2016 New Revision: 265244 URL: http://llvm.org/viewvc/llvm-project?rev=265244&view=rev Log: Merging r263123: ARM: follow up improvements for SVN r263118
Modified: llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll Modified: llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp?rev=265244&r1=265243&r2=265244&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/branches/release_38/lib/Target/ARM/ARMAsmPrinter.cpp Sat Apr 2 15:32:54 2016 @@ -1837,13 +1837,13 @@ void ARMAsmPrinter::EmitInstruction(cons .addReg(0)); return; } - case ARM::tInt_eh_sjlj_longjmp: { + case ARM::tInt_eh_sjlj_longjmp: + case ARM::tInt_WIN_eh_sjlj_longjmp: { // ldr $scratch, [$src, #8] // mov sp, $scratch // ldr $scratch, [$src, #4] // ldr r7, [$src] // bx $scratch - const Triple &TT = TM.getTargetTriple(); unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); @@ -1873,7 +1873,7 @@ void ARMAsmPrinter::EmitInstruction(cons .addReg(0)); EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) - .addReg(TT.isOSWindows() ? ARM::R11 : ARM::R7) + .addReg(Opc == ARM::tInt_WIN_eh_sjlj_longjmp ? ARM::R11 : ARM::R7) .addReg(SrcReg) .addImm(0) // Predicate. Modified: llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=265244&r1=265243&r2=265244&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/branches/release_38/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Apr 2 15:32:54 2016 @@ -632,6 +632,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeIn case ARM::Int_eh_sjlj_longjmp: return 16; case ARM::tInt_eh_sjlj_longjmp: + case ARM::tInt_WIN_eh_sjlj_longjmp: return 10; case ARM::Int_eh_sjlj_setjmp: case ARM::Int_eh_sjlj_setjmp_nofp: Modified: llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td?rev=265244&r1=265243&r2=265244&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/branches/release_38/lib/Target/ARM/ARMInstrInfo.td Sat Apr 2 15:32:54 2016 @@ -279,6 +279,8 @@ def IsARM : Predicate<"!Subta def IsMachO : Predicate<"Subtarget->isTargetMachO()">; def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; +def IsWindows : Predicate<"Subtarget->isTargetWindows()">; +def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, AssemblerPredicate<"FeatureNaClTrap", "NaCl">; def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; Modified: llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td?rev=265244&r1=265243&r2=265244&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/branches/release_38/lib/Target/ARM/ARMInstrThumb.td Sat Apr 2 15:32:54 2016 @@ -1310,7 +1310,14 @@ def tInt_eh_sjlj_longjmp : XI<(outs), (i AddrModeNone, 0, IndexModeNone, Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, - Requires<[IsThumb]>; + Requires<[IsThumb,IsNotWindows]>; + +let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, + Defs = [ R11, LR, SP ] in +def tInt_WIN_eh_sjlj_longjmp + : XI<(outs), (ins GPR:$src, GPR:$scratch), AddrModeNone, 0, IndexModeNone, + Pseudo, NoItinerary, "", "", [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, + Requires<[IsThumb,IsWindows]>; //===----------------------------------------------------------------------===// // Non-Instruction Patterns Modified: llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll?rev=265244&r1=265243&r2=265244&view=diff ============================================================================== --- llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll (original) +++ llvm/branches/release_38/test/CodeGen/ARM/Windows/builtin_longjmp.ll Sat Apr 2 15:32:54 2016 @@ -8,6 +8,7 @@ entry: unreachable } +; CHECK: push.w {r11, lr} ; CHECK: ldr r[[SP:[0-9]+]], [r0, #8] ; CHECK: mov sp, r[[SP]] ; CHECK: ldr r[[PC:[0-9]+]], [r0, #4] _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits