[llvm-branch-commits] [llvm] [BOLT] Make DataflowAnalysis::getStateBefore() const (NFC) (PR #133308)
llvmbot wrote:
@llvm/pr-subscribers-bolt
Author: Anatoly Trosinenko (atrosinenko)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/133308.diff
2 Files Affected:
- (modified) bolt/include/bolt/Passes/DataflowAnalysis.h (+7-4)
- (modified) bolt/lib/Passes/PAuthGadgetScanner.cpp (+1-1)
``diff
diff --git a/bolt/include/bolt/Passes/DataflowAnalysis.h
b/bolt/include/bolt/Passes/DataflowAnalysis.h
index 2afaa6d3043a6..f6ca39cf6f860 100644
--- a/bolt/include/bolt/Passes/DataflowAnalysis.h
+++ b/bolt/include/bolt/Passes/DataflowAnalysis.h
@@ -292,14 +292,17 @@ class DataflowAnalysis {
/// Relies on a ptr map to fetch the previous instruction and then retrieve
/// state. WARNING: Watch out for invalidated pointers. Do not use this
/// function if you invalidated pointers after the analysis has been
completed
- ErrorOr getStateBefore(const MCInst &Point) {
-return getStateAt(PrevPoint[&Point]);
+ ErrorOr getStateBefore(const MCInst &Point) const {
+auto It = PrevPoint.find(&Point);
+if (It == PrevPoint.end())
+ return make_error_code(std::errc::result_out_of_range);
+return getStateAt(It->getSecond());
}
- ErrorOr getStateBefore(ProgramPoint Point) {
+ ErrorOr getStateBefore(ProgramPoint Point) const {
if (Point.isBB())
return getStateAt(*Point.getBB());
-return getStateAt(PrevPoint[Point.getInst()]);
+return getStateBefore(*Point.getInst());
}
/// Remove any state annotations left by this analysis
diff --git a/bolt/lib/Passes/PAuthGadgetScanner.cpp
b/bolt/lib/Passes/PAuthGadgetScanner.cpp
index 16da08551a34d..86897937c95fe 100644
--- a/bolt/lib/Passes/PAuthGadgetScanner.cpp
+++ b/bolt/lib/Passes/PAuthGadgetScanner.cpp
@@ -448,7 +448,7 @@ class PacRetAnalysis
public:
std::vector
getLastClobberingInsts(const MCInst &Inst, BinaryFunction &BF,
- const ArrayRef UsedDirtyRegs) {
+ const ArrayRef UsedDirtyRegs) const {
if (RegsToTrackInstsFor.empty())
return {};
auto MaybeState = getStateBefore(Inst);
``
https://github.com/llvm/llvm-project/pull/133308
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[llvm-branch-commits] [llvm] [BOLT] Make DataflowAnalysis::getStateBefore() const (NFC) (PR #133308)
atrosinenko wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/133308?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#133308** https://app.graphite.dev/github/pr/llvm/llvm-project/133308?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/133308?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#132540** https://app.graphite.dev/github/pr/llvm/llvm-project/132540?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#131899** https://app.graphite.dev/github/pr/llvm/llvm-project/131899?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#131898** https://app.graphite.dev/github/pr/llvm/llvm-project/131898?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#131897** https://app.graphite.dev/github/pr/llvm/llvm-project/131897?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#131896** https://app.graphite.dev/github/pr/llvm/llvm-project/131896?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#131895** https://app.graphite.dev/github/pr/llvm/llvm-project/131895?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/133308 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [llvm] [ctxprof] root autodetection mechanism (PR #133147)
https://github.com/mtrofin updated
https://github.com/llvm/llvm-project/pull/133147
>From 7d0b3a12a500cb0080f94aa6db1d427e1501083c Mon Sep 17 00:00:00 2001
From: Mircea Trofin
Date: Mon, 24 Mar 2025 12:01:10 -0700
Subject: [PATCH] RootAutodetect
---
compiler-rt/lib/ctx_profile/CMakeLists.txt| 2 +-
.../lib/ctx_profile/CtxInstrContextNode.h | 1 +
.../lib/ctx_profile/CtxInstrProfiling.cpp | 119 +++
.../lib/ctx_profile/CtxInstrProfiling.h | 2 +-
.../lib/ctx_profile/RootAutoDetector.cpp | 83
.../lib/ctx_profile/RootAutoDetector.h| 31 +++
.../TestCases/autodetect-roots.cpp| 188 ++
.../TestCases/generate-context.cpp| 5 +-
.../llvm/ProfileData/CtxInstrContextNode.h| 1 +
.../Instrumentation/PGOCtxProfLowering.cpp| 26 ++-
.../PGOProfile/ctx-instrumentation.ll | 20 +-
11 files changed, 416 insertions(+), 62 deletions(-)
create mode 100644 compiler-rt/test/ctx_profile/TestCases/autodetect-roots.cpp
diff --git a/compiler-rt/lib/ctx_profile/CMakeLists.txt
b/compiler-rt/lib/ctx_profile/CMakeLists.txt
index bb606449c61b1..446ebc96408dd 100644
--- a/compiler-rt/lib/ctx_profile/CMakeLists.txt
+++ b/compiler-rt/lib/ctx_profile/CMakeLists.txt
@@ -27,7 +27,7 @@ endif()
add_compiler_rt_runtime(clang_rt.ctx_profile
STATIC
ARCHS ${CTX_PROFILE_SUPPORTED_ARCH}
- OBJECT_LIBS RTSanitizerCommon RTSanitizerCommonLibc
+ OBJECT_LIBS RTSanitizerCommon RTSanitizerCommonLibc
RTSanitizerCommonSymbolizer
CFLAGS ${EXTRA_FLAGS}
SOURCES ${CTX_PROFILE_SOURCES}
ADDITIONAL_HEADERS ${CTX_PROFILE_HEADERS}
diff --git a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
index a42bf9ebb01ea..aa052bc7eea6c 100644
--- a/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
+++ b/compiler-rt/lib/ctx_profile/CtxInstrContextNode.h
@@ -127,6 +127,7 @@ class ContextNode final {
/// MUTEXDECL takes one parameter, the name of a field that is a mutex.
#define CTXPROF_FUNCTION_DATA(PTRDECL, VOLATILE_PTRDECL, MUTEXDECL)
\
PTRDECL(FunctionData, Next)
\
+ PTRDECL(void, EntryAddress)
\
VOLATILE_PTRDECL(ContextRoot, CtxRoot)
\
VOLATILE_PTRDECL(ContextNode, FlatCtx)
\
MUTEXDECL(Mutex)
diff --git a/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
b/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
index da291e0bbabdd..09ed607cde3aa 100644
--- a/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
+++ b/compiler-rt/lib/ctx_profile/CtxInstrProfiling.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "CtxInstrProfiling.h"
+#include "RootAutoDetector.h"
#include "sanitizer_common/sanitizer_allocator_internal.h"
#include "sanitizer_common/sanitizer_atomic.h"
#include "sanitizer_common/sanitizer_atomic_clang.h"
@@ -43,6 +44,12 @@ Arena *FlatCtxArena = nullptr;
__thread bool IsUnderContext = false;
__sanitizer::atomic_uint8_t ProfilingStarted = {};
+__sanitizer::atomic_uintptr_t RootDetector = {};
+RootAutoDetector *getRootDetector() {
+ return reinterpret_cast(
+ __sanitizer::atomic_load_relaxed(&RootDetector));
+}
+
// utility to taint a pointer by setting the LSB. There is an assumption
// throughout that the addresses of contexts are even (really, they should be
// align(8), but "even"-ness is the minimum assumption)
@@ -201,7 +208,7 @@ ContextNode *getCallsiteSlow(GUID Guid, ContextNode
**InsertionPoint,
return Ret;
}
-ContextNode *getFlatProfile(FunctionData &Data, GUID Guid,
+ContextNode *getFlatProfile(FunctionData &Data, void *Callee, GUID Guid,
uint32_t NumCounters) {
if (ContextNode *Existing = Data.FlatCtx)
return Existing;
@@ -232,6 +239,7 @@ ContextNode *getFlatProfile(FunctionData &Data, GUID Guid,
auto *Ret = allocContextNode(AllocBuff, Guid, NumCounters, 0);
Data.FlatCtx = Ret;
+Data.EntryAddress = Callee;
Data.Next = reinterpret_cast(
__sanitizer::atomic_load_relaxed(&AllFunctionsData));
while (!__sanitizer::atomic_compare_exchange_strong(
@@ -277,8 +285,29 @@ ContextRoot *FunctionData::getOrAllocateContextRoot() {
return Root;
}
-ContextNode *getUnhandledContext(FunctionData &Data, GUID Guid,
- uint32_t NumCounters) {
+ContextNode *tryStartContextGivenRoot(ContextRoot *Root, GUID Guid,
+ uint32_t Counters, uint32_t Callsites)
+SANITIZER_NO_THREAD_SAFETY_ANALYSIS {
+ IsUnderContext = true;
+ __sanitizer::atomic_fetch_add(&Root->TotalEntries, 1,
+__sanitizer::memory_order_relaxed);
+
+ if (!Root->FirstMemBlock) {
+setupContext(Root, Guid, Counters, Callsites);
+ }
+ if (Root->Taken.TryL
[llvm-branch-commits] [mlir] [CI] Add rich build information for github workflows (PR #133197)
boomanaiden154 wrote: (MLIR changes are just for testing everything, forgot the bot would add the label). https://github.com/llvm/llvm-project/pull/133197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Make DataflowAnalysis::getStateBefore() const (NFC) (PR #133308)
https://github.com/atrosinenko ready_for_review https://github.com/llvm/llvm-project/pull/133308 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: Detect address materialization and arithmetics (PR #132540)
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/132540
>From 3455bfdf3f8b117ebbb4ce1d5a9536028b0d94ba Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Thu, 20 Mar 2025 20:15:07 +0300
Subject: [PATCH 1/2] [BOLT] Gadget scanner: Detect address materialization and
arithmetics
In addition to authenticated pointers, consider the contents of a
register safe if it was
* written by PC-relative address computation
* updated by an arithmetic instruction whose input address is safe
---
bolt/include/bolt/Core/MCPlusBuilder.h| 16 ++
bolt/lib/Passes/PAuthGadgetScanner.cpp| 92 +--
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 30 +++
.../AArch64/gs-pacret-autiasp.s | 15 --
.../gs-pauth-address-materialization.s| 228 ++
.../binary-analysis/AArch64/lit.local.cfg | 3 +-
6 files changed, 345 insertions(+), 39 deletions(-)
create mode 100644
bolt/test/binary-analysis/AArch64/gs-pauth-address-materialization.s
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h
b/bolt/include/bolt/Core/MCPlusBuilder.h
index 8b6dc14121480..e94f82d00349a 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -587,6 +587,22 @@ class MCPlusBuilder {
return getNoRegister();
}
+ virtual MCPhysReg getSafelyMaterializedAddressReg(const MCInst &Inst) const {
+llvm_unreachable("not implemented");
+return getNoRegister();
+ }
+
+ /// Analyzes if this instruction can safely perform address arithmetics.
+ ///
+ /// If the first element of the returned pair is no-register, this
instruction
+ /// is considered unknown. Otherwise, (output, input) pair is returned,
+ /// so that output is as trusted as input is.
+ virtual std::pair
+ analyzeSafeAddressArithmetics(const MCInst &Inst) const {
+llvm_unreachable("not implemented");
+return std::make_pair(getNoRegister(), getNoRegister());
+ }
+
virtual bool isTerminator(const MCInst &Inst) const;
virtual bool isNoop(const MCInst &Inst) const {
diff --git a/bolt/lib/Passes/PAuthGadgetScanner.cpp
b/bolt/lib/Passes/PAuthGadgetScanner.cpp
index a3b320c545734..16da08551a34d 100644
--- a/bolt/lib/Passes/PAuthGadgetScanner.cpp
+++ b/bolt/lib/Passes/PAuthGadgetScanner.cpp
@@ -335,6 +335,50 @@ class PacRetAnalysis
});
}
+ BitVector getClobberedRegs(const MCInst &Point) const {
+BitVector Clobbered(NumRegs, false);
+// Assume a call can clobber all registers, including callee-saved
+// registers. There's a good chance that callee-saved registers will be
+// saved on the stack at some point during execution of the callee.
+// Therefore they should also be considered as potentially modified by an
+// attacker/written to.
+// Also, not all functions may respect the AAPCS ABI rules about
+// caller/callee-saved registers.
+if (BC.MIB->isCall(Point))
+ Clobbered.set();
+else
+ BC.MIB->getClobberedRegs(Point, Clobbered);
+return Clobbered;
+ }
+
+ // Returns all registers that can be treated as if they are written by an
+ // authentication instruction.
+ SmallVector getAuthenticatedRegs(const MCInst &Point,
+ const State &Cur) const {
+SmallVector Regs;
+const MCPhysReg NoReg = BC.MIB->getNoRegister();
+
+// A signed pointer can be authenticated, or
+ErrorOr AutReg = BC.MIB->getAuthenticatedReg(Point);
+if (AutReg && *AutReg != NoReg)
+ Regs.push_back(*AutReg);
+
+// ... a safe address can be materialized, or
+MCPhysReg NewAddrReg = BC.MIB->getSafelyMaterializedAddressReg(Point);
+if (NewAddrReg != NoReg)
+ Regs.push_back(NewAddrReg);
+
+// ... an address can be updated in a safe manner, producing the result
+// which is as trusted as the input address.
+MCPhysReg ArithResult, ArithSrc;
+std::tie(ArithResult, ArithSrc) =
+BC.MIB->analyzeSafeAddressArithmetics(Point);
+if (ArithResult != NoReg && Cur.SafeToDerefRegs[ArithSrc])
+ Regs.push_back(ArithResult);
+
+return Regs;
+ }
+
State computeNext(const MCInst &Point, const State &Cur) {
PacStatePrinter P(BC);
LLVM_DEBUG({
@@ -355,19 +399,20 @@ class PacRetAnalysis
return State();
}
+// First, compute various properties of the instruction, taking the state
+// before its execution into account, if necessary.
+
+BitVector Clobbered = getClobberedRegs(Point);
+// Compute the set of registers that can be considered as written by
+// an authentication instruction. This includes operations that are
+// *strictly better* than authentication, such as materializing a
+// PC-relative constant.
+SmallVector AuthenticatedOrBetter =
+getAuthenticatedRegs(Point, Cur);
+
+// Then, compute the state after this instruction is executed.
State Next = Cur;
-BitVector Clobbered(NumRegs, false);
-// Assume a call can
[llvm-branch-commits] [clang] [lld] [llvm] release/20.x: [hexagon] Bump the default version to v68 (#132304) (PR #132499)
llvmbot wrote:
@llvm/pr-subscribers-backend-hexagon
Author: None (llvmbot)
Changes
Backport 759ef5811e22 c0b2c10e9f3a
Requested by: @androm3da
---
Patch is 32.08 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/132499.diff
23 Files Affected:
- (modified) clang/lib/Driver/ToolChains/Hexagon.cpp (+1-3)
- (added) clang/test/Driver/hexagon-cpu-default.c (+4)
- (modified) lld/ELF/Arch/Hexagon.cpp (+1-1)
- (modified) lld/docs/ReleaseNotes.rst (+5)
- (modified) lld/test/ELF/emulation-hexagon.s (+2-2)
- (modified) lld/test/ELF/hexagon-eflag.s (+3-2)
- (modified) llvm/docs/ReleaseNotes.md (+4)
- (modified) llvm/include/llvm/BinaryFormat/ELF.h (+10)
- (modified) llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
(+1-1)
- (modified) llvm/test/CodeGen/Hexagon/arg-copy-elison.ll (+11-12)
- (modified) llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll (+1-3)
- (modified) llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll (+6-6)
- (modified) llvm/test/CodeGen/Hexagon/bank-conflict.mir (+1-1)
- (modified) llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll (+3-2)
- (modified) llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll (+28-22)
- (modified) llvm/test/CodeGen/Hexagon/isel/logical.ll (+26-26)
- (modified) llvm/test/CodeGen/Hexagon/isel/select-i1.ll (+3-9)
- (modified) llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir (+2-2)
- (modified) llvm/test/CodeGen/Hexagon/setmemrefs.ll (+1-1)
- (modified) llvm/test/MC/Hexagon/arch-support.s (+4)
- (modified) llvm/test/MC/Hexagon/hexagon_attributes.s (+8-4)
- (modified)
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected
(+12-13)
- (modified)
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected
(+12-13)
``diff
diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 76cedf312d68a..7ca5ab9af8810 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -802,9 +802,7 @@ bool HexagonToolChain::isAutoHVXEnabled(const
llvm::opt::ArgList &Args) {
// Returns the default CPU for Hexagon. This is the default compilation target
// if no Hexagon processor is selected at the command-line.
//
-StringRef HexagonToolChain::GetDefaultCPU() {
- return "hexagonv60";
-}
+StringRef HexagonToolChain::GetDefaultCPU() { return "hexagonv68"; }
StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) {
Arg *CpuArg = nullptr;
diff --git a/clang/test/Driver/hexagon-cpu-default.c
b/clang/test/Driver/hexagon-cpu-default.c
new file mode 100644
index 0..31fb839f21656
--- /dev/null
+++ b/clang/test/Driver/hexagon-cpu-default.c
@@ -0,0 +1,4 @@
+// CHECK: "-target-cpu" "hexagonv68"
+
+// RUN: %clang -c %s -### --target=hexagon-unknown-elf \
+// RUN: 2>&1 | FileCheck %s
diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp
index 23b60672f6317..4ba61db2733c2 100644
--- a/lld/ELF/Arch/Hexagon.cpp
+++ b/lld/ELF/Arch/Hexagon.cpp
@@ -68,7 +68,7 @@ uint32_t Hexagon::calcEFlags() const {
if (!ret || eflags > *ret)
ret = eflags;
}
- return ret.value_or(/* Default Arch Rev: */ 0x60);
+ return ret.value_or(/* Default Arch Rev: */ EF_HEXAGON_MACH_V68);
}
static uint32_t applyMask(uint32_t mask, uint32_t data) {
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index e13b0cf0678ce..b8604611e286e 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -76,6 +76,11 @@ ELF Improvements
* Supported relocation types for LoongArch target:
``R_LARCH_TLS_{LD,GD,DESC}_PCREL20_S2``.
(`#100105 `_)
+* The default Hexagon architecture version in ELF object files produced by
+ lld is changed to v68. This change is only effective when the version is
+ not provided in the command line by the user and cannot be inferred from
+ inputs.
+
Breaking changes
diff --git a/lld/test/ELF/emulation-hexagon.s b/lld/test/ELF/emulation-hexagon.s
index a8a02d4c428b5..5bdd88941c269 100644
--- a/lld/test/ELF/emulation-hexagon.s
+++ b/lld/test/ELF/emulation-hexagon.s
@@ -1,5 +1,5 @@
# REQUIRES: hexagon
-# RUN: llvm-mc -filetype=obj -triple=hexagon %s -o %t.o
+# RUN: llvm-mc -filetype=obj -triple=hexagon --mcpu=hexagonv73 %s -o %t.o
# RUN: ld.lld %t.o -o %t
# RUN: llvm-readelf --file-headers %t | FileCheck --check-prefix=CHECK %s
# RUN: ld.lld -m hexagonelf %t.o -o %t
@@ -26,7 +26,7 @@
# CHECK-NEXT:Entry point address: 0x200B4
# CHECK-NEXT:Start of program headers: 52 (bytes into file)
# CHECK-NEXT:Start of section headers:
-# CHECK-NEXT:Flags: 0x60
+# CHECK-NEXT:Flags: 0x73
# CHECK-NEXT:Size of this header: 52 (bytes)
# CHECK-NEXT:Size of program
[llvm-branch-commits] [llvm] release/20.x: workflows: Add missing apt-get update to abi tests (#133264) (PR #133336)
llvmbot wrote: @boomanaiden154 What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/16 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [hexagon] Enable --eh-frame-hdr (#130225) (PR #130678)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/130678 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [clang-tools-extra] WIP: [clang] Template Specialization Resugaring - Expressions (PR #132446)
https://github.com/mizvekov created
https://github.com/llvm/llvm-project/pull/132446
This adds some additional users of the resugaring transform, around
expressions. This makes function calls work for example.
While probably not the largest patch in the series, this could use some further
splitting up.
Differential Revision: https://reviews.llvm.org/D137200
>From 29d057eaa86c50e1f60fb2f948887622be6c2b96 Mon Sep 17 00:00:00 2001
From: Matheus Izvekov
Date: Mon, 30 May 2022 01:46:31 +0200
Subject: [PATCH] WIP: [clang] Template Specialization Resugaring - Expressions
This adds some additional users of the resugaring transform,
around expressions. This makes function calls work for example.
While probably not the largest patch in the series,
this could use some further splitting up.
Differential Revision: https://reviews.llvm.org/D137200
---
.../clangd/unittests/InlayHintTests.cpp | 60 ++---
clang/include/clang/Sema/Sema.h | 16 +-
clang/lib/Sema/SemaChecking.cpp | 15 +-
clang/lib/Sema/SemaCoroutine.cpp | 2 +-
clang/lib/Sema/SemaDecl.cpp | 1 +
clang/lib/Sema/SemaDeclAttr.cpp | 1 +
clang/lib/Sema/SemaDeclCXX.cpp| 14 +-
clang/lib/Sema/SemaExpr.cpp | 30 ++-
clang/lib/Sema/SemaExprMember.cpp | 130 +-
clang/lib/Sema/SemaHLSL.cpp | 3 +-
clang/lib/Sema/SemaInit.cpp | 5 +-
clang/lib/Sema/SemaOverload.cpp | 87 +--
clang/lib/Sema/SemaTemplate.cpp | 110 +
clang/lib/Sema/SemaTemplateDeduction.cpp | 15 +-
clang/lib/Sema/TreeTransform.h| 4 +-
.../test/AST/ast-dump-for-range-lifetime.cpp | 66 ++---
clang/test/Analysis/cast-value-notes.cpp | 38 +--
clang/test/Analysis/cast-value-state-dump.cpp | 6 +-
.../Analysis/lifetime-extended-regions.cpp| 8 +-
.../CXX/class.derived/class.abstract/p3.cpp | 2 +-
clang/test/CXX/drs/cwg23xx.cpp| 4 +-
clang/test/CXX/drs/cwg26xx.cpp| 2 +-
clang/test/CXX/drs/cwg4xx.cpp | 8 +-
clang/test/CXX/drs/cwg6xx.cpp | 2 +-
clang/test/Index/print-type.cpp | 6 +-
.../test/Misc/diag-template-diffing-cxx11.cpp | 6 +-
clang/test/Sema/Resugar/resugar-expr.cpp | 227 ++
clang/test/SemaTemplate/attributes.cpp| 3 +-
clang/unittests/Tooling/StencilTest.cpp | 3 +-
29 files changed, 669 insertions(+), 205 deletions(-)
create mode 100644 clang/test/Sema/Resugar/resugar-expr.cpp
diff --git a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
index 77d78b8777fe3..81a342cdcf58e 100644
--- a/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
+++ b/clang-tools-extra/clangd/unittests/InlayHintTests.cpp
@@ -1290,8 +1290,8 @@ TEST(TypeHints, Lambda) {
assertTypeHints(R"cpp(
void f() {
int cap = 42;
- auto $L[[L]] = [cap, $init[[init]] = 1 + 1](int a$ret[[)]] {
-return a + cap + init;
+ auto $L[[L]] = [cap, $init[[init]] = 1 + 1](int a$ret[[)]] {
+return a + cap + init;
};
}
)cpp",
@@ -1367,7 +1367,7 @@ TEST(TypeHints, StructuredBindings_TupleLike) {
TEST(TypeHints, StructuredBindings_NoInitializer) {
assertTypeHints(R"cpp(
// No initializer (ill-formed).
-// Do not show useless "NULL TYPE" hint.
+// Do not show useless "NULL TYPE" hint.
auto [x, y]; /*error-ok*/
)cpp");
}
@@ -1670,15 +1670,16 @@ TEST(TypeHints, SubstTemplateParameterAliases) {
auto $end[[end]] = array.end();
)cpp";
- assertHintsWithHeader(
- InlayHintKind::Type, VectorIntPtr, Header,
- ExpectedHint{": int *", "no_modifier"},
- ExpectedHint{": int **", "ptr_modifier"},
- ExpectedHint{": int *&", "ref_modifier"},
- ExpectedHint{": int *const &", "at"}, ExpectedHint{": int **", "data"},
- ExpectedHint{": allocator", "allocator"},
- ExpectedHint{": size_type", "size"}, ExpectedHint{": iterator", "begin"},
- ExpectedHint{": non_template_iterator", "end"});
+ assertHintsWithHeader(InlayHintKind::Type, VectorIntPtr, Header,
+ExpectedHint{": int *", "no_modifier"},
+ExpectedHint{": int **", "ptr_modifier"},
+ExpectedHint{": int *&", "ref_modifier"},
+ExpectedHint{": const value_type &", "at"},
+ExpectedHint{": pointer", "data"},
+ExpectedHint{": allocator_type", "allocator"},
+ExpectedHint{": size_type", "size"},
+ExpectedHint{": iterator", "begin"},
+ExpectedHint{": non_template_iterator", "end"});
llvm::StringRef VectorInt = R"cpp(
vector array;
@@ -1694,15 +1695,16 @@ TEST(TypeHints, SubstTemplateParameterAliases
[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/133279
>From a5a5ebdd21229284459349970deac401a1f2945d Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Wed, 19 Mar 2025 10:19:57 -0400
Subject: [PATCH 1/2] [PowerPC] Support conversion between f16 and f128
(#130158)
Enables conversion between f16 and f128.
Expanding on pre-Power9 targets and using HW instructions on Power9.
Fixes https://github.com/llvm/llvm-project/issues/92866
Commandeer of: https://github.com/llvm/llvm-project/pull/97677
-
Co-authored-by: esmeyi
(cherry picked from commit ade22fc1d9616c95bd1aa4ea658a21ddb073b73c)
---
llvm/lib/IR/RuntimeLibcalls.cpp | 1 +
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +
llvm/lib/Target/PowerPC/PPCInstrVSX.td | 4 +
llvm/test/CodeGen/PowerPC/f128-conv.ll | 487
llvm/test/CodeGen/PowerPC/fp128-libcalls.ll | 17 +
5 files changed, 215 insertions(+), 300 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index e38fce764b640..085a3bc0586b6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -82,6 +82,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
setLibcallName(RTLIB::POWI_F128, "__powikf2");
setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
+setLibcallName(RTLIB::FPROUND_F128_F16, "__trunckfhf2");
setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 21ff6f050817a..16491a145a5b9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -223,13 +223,19 @@ PPCTargetLowering::PPCTargetLowering(const
PPCTargetMachine &TM,
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}
+ setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+ setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
if (Subtarget.isISA3_0()) {
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
setTruncStoreAction(MVT::f64, MVT::f16, Legal);
setTruncStoreAction(MVT::f32, MVT::f16, Legal);
} else {
// No extending loads from f16 or HW conversions back and forth.
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
+setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 8e400bc63b785..a8724ea125140 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3997,6 +3997,8 @@ defm : ScalToVecWPermute<
(SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
// Load/convert and convert/store patterns for f16.
+def : Pat<(f128 (extloadf16 ForceXForm:$src)),
+ (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src>;
def : Pat<(f64 (extloadf16 ForceXForm:$src)),
(f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4005,6 +4007,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)),
VSSRC))>;
def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
(STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)),
ForceXForm:$dst)>;
+def : Pat<(f128 (f16_to_fp i32:$A)),
+ (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A>;
def : Pat<(f64 (f16_to_fp i32:$A)),
(f64 (XSCVHPDP (MTVSRWZ $A)))>;
def : Pat<(f32 (f16_to_fp i32:$A)),
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index d8eed1fb4092c..f8b2861156db4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -10,11 +10,11 @@
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
-@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16
0], align 2
-@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
+@uhwMem = global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
+@ubMem = global [5 x i8] c"\05\02\03\04\00", align 1
; Function Attrs: norecurse nounwind
-define void @sdwConv2qp(ptr nocapture %a, i64 %b) {
+define void @sdwConv2qp(ptr nocapture %a, i64 %b) nounwind {
;
[llvm-branch-commits] [llvm] af9ec23 - Revert "[X86] combineINSERT_SUBVECTOR - fold insert_subvector(base,extract_su…"
Author: Walter Lee
Date: 2025-03-27T19:13:12-04:00
New Revision: af9ec23840d3355ab78f4d82e558732337d382cb
URL:
https://github.com/llvm/llvm-project/commit/af9ec23840d3355ab78f4d82e558732337d382cb
DIFF:
https://github.com/llvm/llvm-project/commit/af9ec23840d3355ab78f4d82e558732337d382cb.diff
LOG: Revert "[X86] combineINSERT_SUBVECTOR - fold
insert_subvector(base,extract_su…"
This reverts commit 491d3dfc761e3a03c6bd187533f4684d6864a8cb.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 81c75a2f98079..72977923bac2b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58823,8 +58823,6 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N,
SelectionDAG &DAG,
uint64_t IdxVal = N->getConstantOperandVal(2);
MVT SubVecVT = SubVec.getSimpleValueType();
- int VecNumElts = OpVT.getVectorNumElements();
- int SubVecNumElts = SubVecVT.getVectorNumElements();
if (Vec.isUndef() && SubVec.isUndef())
return DAG.getUNDEF(OpVT);
@@ -58884,9 +58882,10 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N,
SelectionDAG &DAG,
SubVec.getOperand(0).getSimpleValueType() == OpVT &&
(IdxVal != 0 ||
!(Vec.isUndef() || ISD::isBuildVectorAllZeros(Vec.getNode() {
-SDValue ExtSrc = SubVec.getOperand(0);
int ExtIdxVal = SubVec.getConstantOperandVal(1);
if (ExtIdxVal != 0) {
+ int VecNumElts = OpVT.getVectorNumElements();
+ int SubVecNumElts = SubVecVT.getVectorNumElements();
SmallVector Mask(VecNumElts);
// First create an identity shuffle mask.
for (int i = 0; i != VecNumElts; ++i)
@@ -58894,24 +58893,8 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N,
SelectionDAG &DAG,
// Now insert the extracted portion.
for (int i = 0; i != SubVecNumElts; ++i)
Mask[i + IdxVal] = i + ExtIdxVal + VecNumElts;
- return DAG.getVectorShuffle(OpVT, dl, Vec, ExtSrc, Mask);
-}
-// If we're broadcasting, see if we can use a blend instead of
-// extract/insert pair. For subvector broadcasts, we must ensure that the
-// subvector is aligned with the insertion/extractions.
-if (ExtSrc.getOpcode() == X86ISD::VBROADCAST ||
-ExtSrc.getOpcode() == X86ISD::VBROADCAST_LOAD ||
-(ExtSrc.getOpcode() == X86ISD::SUBV_BROADCAST_LOAD &&
- (ExtIdxVal % SubVecNumElts) == 0 && (IdxVal % SubVecNumElts) == 0 &&
- cast(ExtSrc)->getMemoryVT() == SubVecVT)) {
- SmallVector Mask(VecNumElts);
- // First create an identity shuffle mask.
- for (int i = 0; i != VecNumElts; ++i)
-Mask[i] = i;
- // Now blend the broadcast.
- for (int i = 0; i != SubVecNumElts; ++i)
-Mask[i + IdxVal] = i + IdxVal + VecNumElts;
- return DAG.getVectorShuffle(OpVT, dl, Vec, ExtSrc, Mask);
+
+ return DAG.getVectorShuffle(OpVT, dl, Vec, SubVec.getOperand(0), Mask);
}
}
@@ -58959,7 +58942,7 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N,
SelectionDAG &DAG,
// If we're splatting the lower half subvector of a full vector load into the
// upper half, attempt to create a subvector broadcast.
// TODO: Drop hasOneUse checks.
- if (IdxVal == (VecNumElts / 2) &&
+ if (IdxVal == (OpVT.getVectorNumElements() / 2) &&
Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits()) &&
(Vec.hasOneUse() || SubVec.hasOneUse())) {
auto *VecLd = dyn_cast(Vec);
diff --git a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
index ce62d7a278b1a..2dfa515d9f05c 100644
--- a/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
+++ b/llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
@@ -2837,7 +2837,8 @@ define void
@vec384_i8_widen_to_i48_factor6_broadcast_to_v8i48_factor8(ptr %in.v
; AVX512F-NEXT:vpalignr {{.*#+}} xmm1 =
xmm1[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],xmm0[0]
; AVX512F-NEXT:vpshufb {{.*#+}} xmm1 =
xmm1[15,0,1,2,3,4,15,6,7,8,9,10,15,12,13,14]
; AVX512F-NEXT:vpbroadcastb %xmm0, %ymm0
-; AVX512F-NEXT:vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; AVX512F-NEXT:vinserti64x4 $1, %ymm0, %zmm0, %zmm0
+; AVX512F-NEXT:vinserti128 $1, %xmm0, %ymm1, %ymm1
; AVX512F-NEXT:vpaddb (%rdx), %ymm1, %ymm1
; AVX512F-NEXT:vpaddb 32(%rdx), %ymm0, %ymm0
; AVX512F-NEXT:vmovdqa %ymm0, 32(%rcx)
@@ -2854,7 +2855,8 @@ define void
@vec384_i8_widen_to_i48_factor6_broadcast_to_v8i48_factor8(ptr %in.v
; AVX512DQ-NEXT:vpalignr {{.*#+}} xmm1 =
xmm1[1,2,3,4,5,6,
[llvm-branch-commits] [llvm] release/20.x: workflows: Add missing apt-get update to abi tests (#133264) (PR #133336)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/16
Backport a10a9134023539ee6ab3d166518487f40e368334
Requested by: @tstellar
>From 9946d1b45faccd9e4030aa2d7f19c0b875f183c5 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 16:01:35 -0700
Subject: [PATCH] workflows: Add missing apt-get update to abi tests (#133264)
(cherry picked from commit a10a9134023539ee6ab3d166518487f40e368334)
---
.github/workflows/libclang-abi-tests.yml | 5 -
.github/workflows/llvm-tests.yml | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index 41b3075288d2d..ff8f38b43098e 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -103,6 +103,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -154,7 +155,9 @@ jobs:
path: build-latest
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 9b3d49d4e99b9..92debf2a8a269 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -91,6 +91,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -163,7 +164,9 @@ jobs:
path: symbol-list
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
if [ -s symbol-list/llvm.symbols ]; then
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/131270
>From d60baf3d47863083079e840efc8912d37399076f Mon Sep 17 00:00:00 2001
From: aankit-ca
Date: Thu, 13 Mar 2025 12:48:31 -0700
Subject: [PATCH] [HEXAGON] Fix semantics of ordered FP compares (#131089)
For the ordered FP compare bitcode instructions, the Hexagon backend was
assuming that no operand could be a NaN. This assumption is flawed. This
patch fixes the code-generation to produce fpcmp.uo and and appropriate
bit comparison operators to account for the case when an operand to a FP
compare is a NaN.
Fix for https://github.com/llvm/llvm-project/issues/129391
Co-authored-by: aankit-quic
(cherry picked from commit d642eec78fc94ef3c5266dc0b10b8c51ea046e7a)
---
llvm/lib/Target/Hexagon/HexagonPatterns.td | 38 +++--
llvm/test/CodeGen/Hexagon/fcmp-nan.ll | 189 +
2 files changed, 213 insertions(+), 14 deletions(-)
create mode 100644 llvm/test/CodeGen/Hexagon/fcmp-nan.ll
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td
b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index cba5ff1ab0d9b..244f204539c89 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -721,11 +721,6 @@ def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F32>;
-def: OpR_RR_pat, i1, F32>;
def: OpR_RR_pat, i1, F32>;
def: OpR_RR_pat, i1, F32>;
def: OpR_RR_pat;
@@ -733,11 +728,6 @@ def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F64>;
-def: OpR_RR_pat, i1, F64>;
def: OpR_RR_pat, i1, F64>;
def: OpR_RR_pat, i1, F64>;
def: OpR_RR_pat;
@@ -900,15 +890,35 @@ def: OpmR_RR_pat, RevCmp, i1,
F64>;
def: OpmR_RR_pat, RevCmp, i1, F64>;
def: OpmR_RR_pat, setune, i1, F64>;
-def: OpmR_RR_pat, setone, i1, F32>;
-def: OpmR_RR_pat, setne, i1, F32>;
+class T4
+ : OutPatFrag<(ops node:$Rs, node:$Rt),
+ (MI1 (MI2 (MI3 $Rs, $Rt), (MI4 $Rs, $Rt)))>;
-def: OpmR_RR_pat, setone, i1, F64>;
-def: OpmR_RR_pat, setne, i1, F64>;
+class Cmpof: T3;
+class Cmpod: T3;
+
+class Cmpofn: T4;
+class Cmpodn: T4;
+
+def: OpmR_RR_pat, setoeq, i1, F32>;
+def: OpmR_RR_pat, setoge, i1, F32>;
+def: OpmR_RR_pat, setogt, i1, F32>;
+def: OpmR_RR_pat, RevCmp, i1, F32>;
+def: OpmR_RR_pat, RevCmp, i1, F32>;
+def: OpmR_RR_pat, setone, i1, F32>;
+
+def: OpmR_RR_pat, setoeq, i1, F64>;
+def: OpmR_RR_pat, setoge, i1, F64>;
+def: OpmR_RR_pat, setogt, i1, F64>;
+def: OpmR_RR_pat, RevCmp, i1, F64>;
+def: OpmR_RR_pat, RevCmp, i1, F64>;
+def: OpmR_RR_pat, setone, i1, F64>;
def: OpmR_RR_pat, seto, i1, F32>;
def: OpmR_RR_pat, seto, i1, F64>;
+def: OpmR_RR_pat, setne, i1, F32>;
+def: OpmR_RR_pat, setne, i1, F64>;
// --(6) Select --
//
diff --git a/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
new file mode 100644
index 0..1469402911601
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
@@ -0,0 +1,189 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Test that all FP ordered compare instructions generate the correct
+; post-processing to accommodate NaNs.
+;
+; Specifically for ordered FP compares, we have to check if one of
+; the operands was a NaN to comform to the semantics of the ordered
+; fcmp bitcode instruction
+;
+target triple = "hexagon"
+
+;
+; Functions for float:
+;
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_oeq_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+ %cmpinf = fcmp oeq float %val, %val2
+ %0 = zext i1 %cmpinf to i32
+ ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = or([[REG0]],[[REG1]])
+; CHECK: r0 = mux([[REG2]],#0,#1)
+;
+define i32 @compare_one_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+ %cmpinf = fcmp one float %val, %val2
+ %0 = zext i1 %cmpinf to i32
+ ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_ogt_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+ %cmpinf = fcmp ogt float %val, %val2
+ %0 = zext i1 %cmpinf to i32
+ ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r1,r0)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r1,r0)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_ole_f(float %val,
[llvm-branch-commits] [llvm] d60baf3 - [HEXAGON] Fix semantics of ordered FP compares (#131089)
Author: aankit-ca
Date: 2025-03-27T16:26:27-07:00
New Revision: d60baf3d47863083079e840efc8912d37399076f
URL:
https://github.com/llvm/llvm-project/commit/d60baf3d47863083079e840efc8912d37399076f
DIFF:
https://github.com/llvm/llvm-project/commit/d60baf3d47863083079e840efc8912d37399076f.diff
LOG: [HEXAGON] Fix semantics of ordered FP compares (#131089)
For the ordered FP compare bitcode instructions, the Hexagon backend was
assuming that no operand could be a NaN. This assumption is flawed. This
patch fixes the code-generation to produce fpcmp.uo and and appropriate
bit comparison operators to account for the case when an operand to a FP
compare is a NaN.
Fix for https://github.com/llvm/llvm-project/issues/129391
Co-authored-by: aankit-quic
(cherry picked from commit d642eec78fc94ef3c5266dc0b10b8c51ea046e7a)
Added:
llvm/test/CodeGen/Hexagon/fcmp-nan.ll
Modified:
llvm/lib/Target/Hexagon/HexagonPatterns.td
Removed:
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td
b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index cba5ff1ab0d9b..244f204539c89 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -721,11 +721,6 @@ def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F32>;
-def: OpR_RR_pat, i1, F32>;
def: OpR_RR_pat, i1, F32>;
def: OpR_RR_pat, i1, F32>;
def: OpR_RR_pat;
@@ -733,11 +728,6 @@ def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat;
-def: OpR_RR_pat, i1, F64>;
-def: OpR_RR_pat, i1, F64>;
def: OpR_RR_pat, i1, F64>;
def: OpR_RR_pat, i1, F64>;
def: OpR_RR_pat;
@@ -900,15 +890,35 @@ def: OpmR_RR_pat, RevCmp, i1,
F64>;
def: OpmR_RR_pat, RevCmp, i1, F64>;
def: OpmR_RR_pat, setune, i1, F64>;
-def: OpmR_RR_pat, setone, i1, F32>;
-def: OpmR_RR_pat, setne, i1, F32>;
+class T4
+ : OutPatFrag<(ops node:$Rs, node:$Rt),
+ (MI1 (MI2 (MI3 $Rs, $Rt), (MI4 $Rs, $Rt)))>;
-def: OpmR_RR_pat, setone, i1, F64>;
-def: OpmR_RR_pat, setne, i1, F64>;
+class Cmpof: T3;
+class Cmpod: T3;
+
+class Cmpofn: T4;
+class Cmpodn: T4;
+
+def: OpmR_RR_pat, setoeq, i1, F32>;
+def: OpmR_RR_pat, setoge, i1, F32>;
+def: OpmR_RR_pat, setogt, i1, F32>;
+def: OpmR_RR_pat, RevCmp, i1, F32>;
+def: OpmR_RR_pat, RevCmp, i1, F32>;
+def: OpmR_RR_pat, setone, i1, F32>;
+
+def: OpmR_RR_pat, setoeq, i1, F64>;
+def: OpmR_RR_pat, setoge, i1, F64>;
+def: OpmR_RR_pat, setogt, i1, F64>;
+def: OpmR_RR_pat, RevCmp, i1, F64>;
+def: OpmR_RR_pat, RevCmp, i1, F64>;
+def: OpmR_RR_pat, setone, i1, F64>;
def: OpmR_RR_pat, seto, i1, F32>;
def: OpmR_RR_pat, seto, i1, F64>;
+def: OpmR_RR_pat, setne, i1, F32>;
+def: OpmR_RR_pat, setne, i1, F64>;
// --(6) Select --
//
diff --git a/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
new file mode 100644
index 0..1469402911601
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/fcmp-nan.ll
@@ -0,0 +1,189 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+;
+; Test that all FP ordered compare instructions generate the correct
+; post-processing to accommodate NaNs.
+;
+; Specifically for ordered FP compares, we have to check if one of
+; the operands was a NaN to comform to the semantics of the ordered
+; fcmp bitcode instruction
+;
+target triple = "hexagon"
+
+;
+; Functions for float:
+;
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_oeq_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+ %cmpinf = fcmp oeq float %val, %val2
+ %0 = zext i1 %cmpinf to i32
+ ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.eq(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = or([[REG0]],[[REG1]])
+; CHECK: r0 = mux([[REG2]],#0,#1)
+;
+define i32 @compare_one_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+ %cmpinf = fcmp one float %val, %val2
+ %0 = zext i1 %cmpinf to i32
+ ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.gt(r0,r1)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r0,r1)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
+define i32 @compare_ogt_f(float %val, float %val2) local_unnamed_addr #0 {
+entry:
+ %cmpinf = fcmp ogt float %val, %val2
+ %0 = zext i1 %cmpinf to i32
+ ret i32 %0
+}
+
+
+;
+; CHECK-DAG: [[REG0:p([0-3])]] = sfcmp.ge(r1,r0)
+; CHECK-DAG: [[REG1:p([0-3])]] = sfcmp.uo(r1,r0)
+; CHECK: [[REG2:p([0-3])]] = and([[REG0]],![[REG1]])
+; CHECK: r0 = mux([[REG2]],#1,#0)
+;
[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)
github-actions[bot] wrote: @androm3da (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/131270 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [HEXAGON] Fix semantics of ordered FP compares (#131089) (PR #131270)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/131270 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [hexagon] Enable --eh-frame-hdr (#130225) (PR #130678)
github-actions[bot] wrote: @androm3da (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/130678 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 3e2801e - [PowerPC] Support conversion between f16 and f128 (#130158)
Author: Lei Huang
Date: 2025-03-27T16:34:46-07:00
New Revision: 3e2801eb634e6010ee783ea7c93718bbb6ed4c35
URL:
https://github.com/llvm/llvm-project/commit/3e2801eb634e6010ee783ea7c93718bbb6ed4c35
DIFF:
https://github.com/llvm/llvm-project/commit/3e2801eb634e6010ee783ea7c93718bbb6ed4c35.diff
LOG: [PowerPC] Support conversion between f16 and f128 (#130158)
Enables conversion between f16 and f128.
Expanding on pre-Power9 targets and using HW instructions on Power9.
Fixes https://github.com/llvm/llvm-project/issues/92866
Commandeer of: https://github.com/llvm/llvm-project/pull/97677
-
Co-authored-by: esmeyi
(cherry picked from commit ade22fc1d9616c95bd1aa4ea658a21ddb073b73c)
Added:
Modified:
llvm/lib/IR/RuntimeLibcalls.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/f128-conv.ll
llvm/test/CodeGen/PowerPC/fp128-libcalls.ll
Removed:
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index e38fce764b640..085a3bc0586b6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -82,6 +82,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
setLibcallName(RTLIB::POWI_F128, "__powikf2");
setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
+setLibcallName(RTLIB::FPROUND_F128_F16, "__trunckfhf2");
setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 21ff6f050817a..16491a145a5b9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -223,13 +223,19 @@ PPCTargetLowering::PPCTargetLowering(const
PPCTargetMachine &TM,
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}
+ setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+ setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
if (Subtarget.isISA3_0()) {
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
setTruncStoreAction(MVT::f64, MVT::f16, Legal);
setTruncStoreAction(MVT::f32, MVT::f16, Legal);
} else {
// No extending loads from f16 or HW conversions back and forth.
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
+setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 8e400bc63b785..a8724ea125140 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3997,6 +3997,8 @@ defm : ScalToVecWPermute<
(SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
// Load/convert and convert/store patterns for f16.
+def : Pat<(f128 (extloadf16 ForceXForm:$src)),
+ (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src>;
def : Pat<(f64 (extloadf16 ForceXForm:$src)),
(f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4005,6 +4007,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)),
VSSRC))>;
def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
(STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)),
ForceXForm:$dst)>;
+def : Pat<(f128 (f16_to_fp i32:$A)),
+ (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A>;
def : Pat<(f64 (f16_to_fp i32:$A)),
(f64 (XSCVHPDP (MTVSRWZ $A)))>;
def : Pat<(f32 (f16_to_fp i32:$A)),
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index d8eed1fb4092c..f8b2861156db4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -10,11 +10,11 @@
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
-@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16
0], align 2
-@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
+@uhwMem = global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
+@ubMem = global [5 x i8] c"\05\02\03\04\00", align 1
; Function Attrs: norecurse nounwind
-define void @sdwConv2qp(ptr nocapture %a, i
[llvm-branch-commits] [clang] [lld] [llvm] release/20.x: [hexagon] Bump the default version to v68 (#132304) (PR #132499)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/132499 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] d1f5a9f - [hexagon] Bump the default version to v68 (#132304)
Author: Alexey Karyakin
Date: 2025-03-27T16:37:38-07:00
New Revision: d1f5a9f66ee237eabe35a1adf88edabd9783
URL:
https://github.com/llvm/llvm-project/commit/d1f5a9f66ee237eabe35a1adf88edabd9783
DIFF:
https://github.com/llvm/llvm-project/commit/d1f5a9f66ee237eabe35a1adf88edabd9783.diff
LOG: [hexagon] Bump the default version to v68 (#132304)
Set the default processor version to v68 when the user does not specify
one in the command line. This includes changes in the LLVM backed and
linker (lld). Since lld normally sets the version based on inputs, this
change will only affect cases when there are no inputs.
Fixes #127558
(cherry picked from commit c0b2c10e9f3a939c227a26aec3ba377f7cc25667)
Added:
Modified:
lld/ELF/Arch/Hexagon.cpp
lld/docs/ReleaseNotes.rst
lld/test/ELF/emulation-hexagon.s
lld/test/ELF/hexagon-eflag.s
llvm/docs/ReleaseNotes.md
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/test/CodeGen/Hexagon/arg-copy-elison.ll
llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll
llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll
llvm/test/CodeGen/Hexagon/bank-conflict.mir
llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll
llvm/test/CodeGen/Hexagon/isel/logical.ll
llvm/test/CodeGen/Hexagon/isel/select-i1.ll
llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir
llvm/test/CodeGen/Hexagon/setmemrefs.ll
llvm/test/MC/Hexagon/arch-support.s
llvm/test/MC/Hexagon/hexagon_attributes.s
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected
Removed:
diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp
index 23b60672f6317..4ba61db2733c2 100644
--- a/lld/ELF/Arch/Hexagon.cpp
+++ b/lld/ELF/Arch/Hexagon.cpp
@@ -68,7 +68,7 @@ uint32_t Hexagon::calcEFlags() const {
if (!ret || eflags > *ret)
ret = eflags;
}
- return ret.value_or(/* Default Arch Rev: */ 0x60);
+ return ret.value_or(/* Default Arch Rev: */ EF_HEXAGON_MACH_V68);
}
static uint32_t applyMask(uint32_t mask, uint32_t data) {
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index e13b0cf0678ce..b8604611e286e 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -76,6 +76,11 @@ ELF Improvements
* Supported relocation types for LoongArch target:
``R_LARCH_TLS_{LD,GD,DESC}_PCREL20_S2``.
(`#100105 `_)
+* The default Hexagon architecture version in ELF object files produced by
+ lld is changed to v68. This change is only effective when the version is
+ not provided in the command line by the user and cannot be inferred from
+ inputs.
+
Breaking changes
diff --git a/lld/test/ELF/emulation-hexagon.s
b/lld/test/ELF/emulation-hexagon.s
index a8a02d4c428b5..5bdd88941c269 100644
--- a/lld/test/ELF/emulation-hexagon.s
+++ b/lld/test/ELF/emulation-hexagon.s
@@ -1,5 +1,5 @@
# REQUIRES: hexagon
-# RUN: llvm-mc -filetype=obj -triple=hexagon %s -o %t.o
+# RUN: llvm-mc -filetype=obj -triple=hexagon --mcpu=hexagonv73 %s -o %t.o
# RUN: ld.lld %t.o -o %t
# RUN: llvm-readelf --file-headers %t | FileCheck --check-prefix=CHECK %s
# RUN: ld.lld -m hexagonelf %t.o -o %t
@@ -26,7 +26,7 @@
# CHECK-NEXT:Entry point address: 0x200B4
# CHECK-NEXT:Start of program headers: 52 (bytes into file)
# CHECK-NEXT:Start of section headers:
-# CHECK-NEXT:Flags: 0x60
+# CHECK-NEXT:Flags: 0x73
# CHECK-NEXT:Size of this header: 52 (bytes)
# CHECK-NEXT:Size of program headers: 32 (bytes)
diff --git a/lld/test/ELF/hexagon-eflag.s b/lld/test/ELF/hexagon-eflag.s
index dbe8604f69fda..ac9123832ac8a 100644
--- a/lld/test/ELF/hexagon-eflag.s
+++ b/lld/test/ELF/hexagon-eflag.s
@@ -3,10 +3,11 @@
# RUN: llvm-mc -filetype=obj -mv60 -triple=hexagon-unknown-elf
%S/Inputs/hexagon.s -o %t2
# RUN: ld.lld %t2 %t -o %t3
# RUN: llvm-readelf -h %t3 | FileCheck %s
-# Verify that the largest arch in the input list is selected.
+## Verify that the largest arch in the input list is selected.
# CHECK: Flags: 0x62
+## Verify the arch version when it cannot be inferred from inputs.
# RUN: llvm-ar rcsD %t4
# RUN: ld.lld -m hexagonelf %t4 -o %t5
# RUN: llvm-readelf -h %t5 | FileCheck --check-prefix=CHECK-EMPTYARCHIVE %s
-# CHECK-EMPTYARCHIVE: Flags: 0x60
+# CHECK-EMPTYARCHIVE: Flags: 0x68
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 958b7adbc4c36..f34003eaf0fe2 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -202,6 +202,10 @@ Changes to the DirectX Backend
[llvm-branch-commits] [clang] [lld] [llvm] release/20.x: [hexagon] Bump the default version to v68 (#132304) (PR #132499)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/132499
>From 90cc9ca8bcb2b96463dd1b2bb9c43380dbf67f87 Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar
Date: Fri, 31 Jan 2025 11:59:39 -0600
Subject: [PATCH 1/2] [Hexagon] Set the default compilation target to V68
(#125239)
Set the default compilation target to V68 if no Hexagon processor is
specified at the command-line.
Add the elf header changes for v81/v83/v85 architectures.
(cherry picked from commit 759ef5811e2297f2cbe7578f7c118668e3467c6a)
---
clang/lib/Driver/ToolChains/Hexagon.cpp | 4 +---
clang/test/Driver/hexagon-cpu-default.c | 4
llvm/include/llvm/BinaryFormat/ELF.h| 10 ++
3 files changed, 15 insertions(+), 3 deletions(-)
create mode 100644 clang/test/Driver/hexagon-cpu-default.c
diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 772a9827cb211..6ea701a7882d1 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -803,9 +803,7 @@ bool HexagonToolChain::isAutoHVXEnabled(const
llvm::opt::ArgList &Args) {
// Returns the default CPU for Hexagon. This is the default compilation target
// if no Hexagon processor is selected at the command-line.
//
-StringRef HexagonToolChain::GetDefaultCPU() {
- return "hexagonv60";
-}
+StringRef HexagonToolChain::GetDefaultCPU() { return "hexagonv68"; }
StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) {
Arg *CpuArg = nullptr;
diff --git a/clang/test/Driver/hexagon-cpu-default.c
b/clang/test/Driver/hexagon-cpu-default.c
new file mode 100644
index 0..31fb839f21656
--- /dev/null
+++ b/clang/test/Driver/hexagon-cpu-default.c
@@ -0,0 +1,4 @@
+// CHECK: "-target-cpu" "hexagonv68"
+
+// RUN: %clang -c %s -### --target=hexagon-unknown-elf \
+// RUN: 2>&1 | FileCheck %s
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h
b/llvm/include/llvm/BinaryFormat/ELF.h
index 48ae0db80f43e..8853c4a88b0b5 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -619,6 +619,7 @@ enum {
EF_HEXAGON_MACH_V5 = 0x0004, // Hexagon V5
EF_HEXAGON_MACH_V55 = 0x0005, // Hexagon V55
EF_HEXAGON_MACH_V60 = 0x0060, // Hexagon V60
+ EF_HEXAGON_MACH_V61 = 0x0061, // Hexagon V61
EF_HEXAGON_MACH_V62 = 0x0062, // Hexagon V62
EF_HEXAGON_MACH_V65 = 0x0065, // Hexagon V65
EF_HEXAGON_MACH_V66 = 0x0066, // Hexagon V66
@@ -630,7 +631,11 @@ enum {
EF_HEXAGON_MACH_V71T = 0x8071, // Hexagon V71T
EF_HEXAGON_MACH_V73 = 0x0073, // Hexagon V73
EF_HEXAGON_MACH_V75 = 0x0075, // Hexagon V75
+ EF_HEXAGON_MACH_V77 = 0x0077, // Hexagon V77
EF_HEXAGON_MACH_V79 = 0x0079, // Hexagon V79
+ EF_HEXAGON_MACH_V81 = 0x0081, // Hexagon V81
+ EF_HEXAGON_MACH_V83 = 0x0083, // Hexagon V83
+ EF_HEXAGON_MACH_V85 = 0x0085, // Hexagon V85
EF_HEXAGON_MACH = 0x03ff, // Hexagon V..
// Highest ISA version flags
@@ -642,6 +647,7 @@ enum {
EF_HEXAGON_ISA_V5 = 0x0040, // Hexagon V5 ISA
EF_HEXAGON_ISA_V55 = 0x0050, // Hexagon V55 ISA
EF_HEXAGON_ISA_V60 = 0x0060, // Hexagon V60 ISA
+ EF_HEXAGON_ISA_V61 = 0x0061, // Hexagon V61 ISA
EF_HEXAGON_ISA_V62 = 0x0062, // Hexagon V62 ISA
EF_HEXAGON_ISA_V65 = 0x0065, // Hexagon V65 ISA
EF_HEXAGON_ISA_V66 = 0x0066, // Hexagon V66 ISA
@@ -651,7 +657,11 @@ enum {
EF_HEXAGON_ISA_V71 = 0x0071, // Hexagon V71 ISA
EF_HEXAGON_ISA_V73 = 0x0073, // Hexagon V73 ISA
EF_HEXAGON_ISA_V75 = 0x0075, // Hexagon V75 ISA
+ EF_HEXAGON_ISA_V77 = 0x0077, // Hexagon V77 ISA
EF_HEXAGON_ISA_V79 = 0x0079, // Hexagon V79 ISA
+ EF_HEXAGON_ISA_V81 = 0x0081, // Hexagon V81 ISA
+ EF_HEXAGON_ISA_V83 = 0x0083, // Hexagon V83 ISA
+ EF_HEXAGON_ISA_V85 = 0x0085, // Hexagon V85 ISA
EF_HEXAGON_ISA = 0x03ff, // Hexagon V.. ISA
};
>From d1f5a9f66ee237eabe35a1adf88edabd9783 Mon Sep 17 00:00:00 2001
From: Alexey Karyakin
Date: Fri, 21 Mar 2025 20:08:45 -0500
Subject: [PATCH 2/2] [hexagon] Bump the default version to v68 (#132304)
Set the default processor version to v68 when the user does not specify
one in the command line. This includes changes in the LLVM backed and
linker (lld). Since lld normally sets the version based on inputs, this
change will only affect cases when there are no inputs.
Fixes #127558
(cherry picked from commit c0b2c10e9f3a939c227a26aec3ba377f7cc25667)
---
lld/ELF/Arch/Hexagon.cpp | 2 +-
lld/docs/ReleaseNotes.rst | 5 ++
lld/test/ELF/emulation-hexagon.s | 4 +-
lld/test/ELF/hexagon-eflag.s | 5 +-
llvm/docs/ReleaseNotes.md | 4 ++
.../MCTargetDesc/HexagonMCTargetDesc.cpp | 2 +-
llvm/test/CodeGen/Hexagon/arg-copy-elison.ll | 23
.../Hexagon/atomicrmw-cond-sub-clamp.ll | 4 +
[llvm-branch-commits] [clang] 90cc9ca - [Hexagon] Set the default compilation target to V68 (#125239)
Author: Ikhlas Ajbar
Date: 2025-03-27T16:37:38-07:00
New Revision: 90cc9ca8bcb2b96463dd1b2bb9c43380dbf67f87
URL:
https://github.com/llvm/llvm-project/commit/90cc9ca8bcb2b96463dd1b2bb9c43380dbf67f87
DIFF:
https://github.com/llvm/llvm-project/commit/90cc9ca8bcb2b96463dd1b2bb9c43380dbf67f87.diff
LOG: [Hexagon] Set the default compilation target to V68 (#125239)
Set the default compilation target to V68 if no Hexagon processor is
specified at the command-line.
Add the elf header changes for v81/v83/v85 architectures.
(cherry picked from commit 759ef5811e2297f2cbe7578f7c118668e3467c6a)
Added:
clang/test/Driver/hexagon-cpu-default.c
Modified:
clang/lib/Driver/ToolChains/Hexagon.cpp
llvm/include/llvm/BinaryFormat/ELF.h
Removed:
diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 772a9827cb211..6ea701a7882d1 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -803,9 +803,7 @@ bool HexagonToolChain::isAutoHVXEnabled(const
llvm::opt::ArgList &Args) {
// Returns the default CPU for Hexagon. This is the default compilation target
// if no Hexagon processor is selected at the command-line.
//
-StringRef HexagonToolChain::GetDefaultCPU() {
- return "hexagonv60";
-}
+StringRef HexagonToolChain::GetDefaultCPU() { return "hexagonv68"; }
StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) {
Arg *CpuArg = nullptr;
diff --git a/clang/test/Driver/hexagon-cpu-default.c
b/clang/test/Driver/hexagon-cpu-default.c
new file mode 100644
index 0..31fb839f21656
--- /dev/null
+++ b/clang/test/Driver/hexagon-cpu-default.c
@@ -0,0 +1,4 @@
+// CHECK: "-target-cpu" "hexagonv68"
+
+// RUN: %clang -c %s -### --target=hexagon-unknown-elf \
+// RUN: 2>&1 | FileCheck %s
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h
b/llvm/include/llvm/BinaryFormat/ELF.h
index 48ae0db80f43e..8853c4a88b0b5 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -619,6 +619,7 @@ enum {
EF_HEXAGON_MACH_V5 = 0x0004, // Hexagon V5
EF_HEXAGON_MACH_V55 = 0x0005, // Hexagon V55
EF_HEXAGON_MACH_V60 = 0x0060, // Hexagon V60
+ EF_HEXAGON_MACH_V61 = 0x0061, // Hexagon V61
EF_HEXAGON_MACH_V62 = 0x0062, // Hexagon V62
EF_HEXAGON_MACH_V65 = 0x0065, // Hexagon V65
EF_HEXAGON_MACH_V66 = 0x0066, // Hexagon V66
@@ -630,7 +631,11 @@ enum {
EF_HEXAGON_MACH_V71T = 0x8071, // Hexagon V71T
EF_HEXAGON_MACH_V73 = 0x0073, // Hexagon V73
EF_HEXAGON_MACH_V75 = 0x0075, // Hexagon V75
+ EF_HEXAGON_MACH_V77 = 0x0077, // Hexagon V77
EF_HEXAGON_MACH_V79 = 0x0079, // Hexagon V79
+ EF_HEXAGON_MACH_V81 = 0x0081, // Hexagon V81
+ EF_HEXAGON_MACH_V83 = 0x0083, // Hexagon V83
+ EF_HEXAGON_MACH_V85 = 0x0085, // Hexagon V85
EF_HEXAGON_MACH = 0x03ff, // Hexagon V..
// Highest ISA version flags
@@ -642,6 +647,7 @@ enum {
EF_HEXAGON_ISA_V5 = 0x0040, // Hexagon V5 ISA
EF_HEXAGON_ISA_V55 = 0x0050, // Hexagon V55 ISA
EF_HEXAGON_ISA_V60 = 0x0060, // Hexagon V60 ISA
+ EF_HEXAGON_ISA_V61 = 0x0061, // Hexagon V61 ISA
EF_HEXAGON_ISA_V62 = 0x0062, // Hexagon V62 ISA
EF_HEXAGON_ISA_V65 = 0x0065, // Hexagon V65 ISA
EF_HEXAGON_ISA_V66 = 0x0066, // Hexagon V66 ISA
@@ -651,7 +657,11 @@ enum {
EF_HEXAGON_ISA_V71 = 0x0071, // Hexagon V71 ISA
EF_HEXAGON_ISA_V73 = 0x0073, // Hexagon V73 ISA
EF_HEXAGON_ISA_V75 = 0x0075, // Hexagon V75 ISA
+ EF_HEXAGON_ISA_V77 = 0x0077, // Hexagon V77 ISA
EF_HEXAGON_ISA_V79 = 0x0079, // Hexagon V79 ISA
+ EF_HEXAGON_ISA_V81 = 0x0081, // Hexagon V81 ISA
+ EF_HEXAGON_ISA_V83 = 0x0083, // Hexagon V83 ISA
+ EF_HEXAGON_ISA_V85 = 0x0085, // Hexagon V85 ISA
EF_HEXAGON_ISA = 0x03ff, // Hexagon V.. ISA
};
___
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[llvm-branch-commits] [clang] [lld] [llvm] release/20.x: [hexagon] Bump the default version to v68 (#132304) (PR #132499)
github-actions[bot] wrote: @androm3da (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/132499 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 1a76c29 - [hexagon] Enable --eh-frame-hdr (#130225)
Author: Brian Cain
Date: 2025-03-27T16:23:20-07:00
New Revision: 1a76c29a9ba877c85acf455f05af47039607958b
URL:
https://github.com/llvm/llvm-project/commit/1a76c29a9ba877c85acf455f05af47039607958b
DIFF:
https://github.com/llvm/llvm-project/commit/1a76c29a9ba877c85acf455f05af47039607958b.diff
LOG: [hexagon] Enable --eh-frame-hdr (#130225)
The missing `PT_GNU_EH_FRAME` was causing C++ exception handling test
failures in llvm-test-suite. We should unconditionally add this argument
like the other drivers do.
Discovered-by: Alexey Karyakin
Fixes: #129745
(cherry picked from commit 6657769199ad625ea0cb7f7c054d4f6a27806080)
Added:
Modified:
clang/lib/Driver/ToolChains/Hexagon.cpp
clang/test/Driver/hexagon-toolchain-elf.c
clang/test/Driver/hexagon-toolchain-linux.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 76cedf312d68a..772a9827cb211 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -313,6 +313,7 @@ constructHexagonLinkArgs(Compilation &C, const JobAction
&JA,
// handled somewhere else.
Args.ClaimAllArgs(options::OPT_static_libgcc);
+ CmdArgs.push_back("--eh-frame-hdr");
//
//
//
diff --git a/clang/test/Driver/hexagon-toolchain-elf.c
b/clang/test/Driver/hexagon-toolchain-elf.c
index be812dda40d57..de2ebfeeda26c 100644
--- a/clang/test/Driver/hexagon-toolchain-elf.c
+++ b/clang/test/Driver/hexagon-toolchain-elf.c
@@ -555,6 +555,7 @@
// RUN: -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \
// RUN: -mcpu=hexagonv60 \
// RUN: -fuse-ld=lld %s 2>&1 | FileCheck -check-prefix=CHECK382 %s
+// CHECK382: "--eh-frame-hdr
// CHECK382-NOT: "-march=
// CHECK382-NOT: "-mcpu=
//
-
diff --git a/clang/test/Driver/hexagon-toolchain-linux.c
b/clang/test/Driver/hexagon-toolchain-linux.c
index 6f7f3b20f9141..e791353cca07f 100644
--- a/clang/test/Driver/hexagon-toolchain-linux.c
+++ b/clang/test/Driver/hexagon-toolchain-linux.c
@@ -127,6 +127,7 @@
// RUN:--target=hexagon-unknown-linux-musl %s -### 2>&1 \
// RUN:| FileCheck -check-prefix=CHECK011 %s
// CHECK011: InstalledDir: [[INSTALLED_DIR:.+]]
+// CHECK011: "--eh-frame-hdr"
// CHECK011: crt1.o
// CHECK011-NOT: "-lunwind"
// CHECK011-NOT: "-lgcc_eh"
___
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[llvm-branch-commits] [llvm] release/20.x: workflows: Add missing apt-get update to abi tests (#133264) (PR #133336)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/16 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)
https://github.com/petar-avramovic edited https://github.com/llvm/llvm-project/pull/132383 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [CI] Add rich build information for github workflows (PR #133197)
DavidSpickett wrote: TIL that https://docs.github.com/en/actions/writing-workflows/choosing-what-your-workflow-does/workflow-commands-for-github-actions#adding-a-job-summary exists, very cool. The title of the PR implies that you are adding more than test results, but the PR description says you are deliberately not adding anything more than test results right now. I would clarify the title. I agree with the strategy, have 2 distinct entry points for a time, stick to test results only. Once Buildkite is removed you can start using all sorts of GitHub data to link log files and whatever we want to do. Without worrying about Buildkite. https://github.com/llvm/llvm-project/pull/133197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [CI] Add rich build information for github workflows (PR #133197)
@@ -0,0 +1,23 @@
+# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+"""Script to generate a build report for Github."""
+
+import argparse
+
+import generate_test_report_lib
+
+if __name__ == "__main___":
+parser = argparse.ArgumentParser()
+parser.add_argument(
+"title", help="Title of the test report, without Markdown formatting."
+)
+parser.add_argument("return_code", help="The build's return code.",
type=int)
+parser.add_argument("junit_files", help="Paths to JUnit report files.",
nargs="*")
+args = parser.parse_args()
+
+report, style = generate_test_report_lib.generate_report_from_files(
DavidSpickett wrote:
Minor thing: use `_` for `style`, to be clear it is deliberately not used here.
https://github.com/llvm/llvm-project/pull/133197
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[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (PR #132382)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 4e74a7e91e4b8638b30f3bd13437b7a149e7a1a1 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:42:48 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and
XOR
Uniform S1 is lowered to S32.
Divergent S1 is selected as VCC(S1) instruction select will select
SALU instruction based on wavesize (S32 or S64).
S16 are selected as is. There are register classes for vgpr S16.
Since some isel patterns check for sgpr S16 we don't lower to S32.
For 32 and 64 bit types we use B32/B64 rules that cover scalar vector
and pointers types.
SALU B32 and B64 and VALU B32 instructions are available.
Divergent B64 is lowered to B32.
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 32 ---
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 10 ++-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 2 +
.../AMDGPU/GlobalISel/regbankselect-and.mir | 33 ---
.../AMDGPU/GlobalISel/regbankselect-or.mir| 85 +--
.../AMDGPU/GlobalISel/regbankselect-xor.mir | 84 +-
7 files changed, 134 insertions(+), 113 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index e2f664396c16d..57ad43cfb8fa9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -242,6 +242,22 @@ void RegBankLegalizeHelper::lowerUni_BFE(MachineInstr &MI)
{
return;
}
+void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst) == V4S16 ? V2S16 : S32;
+ auto Op1 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(1).getReg());
+ auto Op2 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(2).getReg());
+ unsigned Opc = MI.getOpcode();
+ auto Flags = MI.getFlags();
+ auto Lo =
+ B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(0), Op2.getReg(0)}, Flags);
+ auto Hi =
+ B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(1), Op2.getReg(1)}, Flags);
+ B.buildMergeLikeInstr(MI.getOperand(0).getReg(), {Lo, Hi});
+ MI.eraseFromParent();
+ return;
+}
+
void RegBankLegalizeHelper::lower(MachineInstr &MI,
const RegBankLLTMapping &Mapping,
SmallSet &WaterfallSgprs) {
@@ -330,20 +346,12 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
MI.eraseFromParent();
return;
}
- case SplitTo32: {
-auto Op1 = B.buildUnmerge(VgprRB_S32, MI.getOperand(1).getReg());
-auto Op2 = B.buildUnmerge(VgprRB_S32, MI.getOperand(2).getReg());
-unsigned Opc = MI.getOpcode();
-auto Lo = B.buildInstr(Opc, {VgprRB_S32}, {Op1.getReg(0), Op2.getReg(0)});
-auto Hi = B.buildInstr(Opc, {VgprRB_S32}, {Op1.getReg(1), Op2.getReg(1)});
-B.buildMergeLikeInstr(MI.getOperand(0).getReg(), {Lo, Hi});
-MI.eraseFromParent();
-break;
- }
case Div_BFE:
return lowerDiv_BFE(MI);
case Uni_BFE:
return lowerUni_BFE(MI);
+ case SplitTo32:
+return lowerSplitTo32(MI);
case SplitLoad: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = DstTy.getSizeInBits();
@@ -403,6 +411,7 @@ LLT
RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case UniInVcc:
return LLT::scalar(1);
case Sgpr16:
+ case Vgpr16:
return LLT::scalar(16);
case Sgpr32:
case Sgpr32Trunc:
@@ -522,6 +531,7 @@
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Sgpr32AExtBoolInReg:
case Sgpr32SExt:
return SgprRB;
+ case Vgpr16:
case Vgpr32:
case Vgpr64:
case VgprP0:
@@ -565,6 +575,7 @@ void RegBankLegalizeHelper::applyMappingDst(
case SgprP4:
case SgprP5:
case SgprV4S32:
+case Vgpr16:
case Vgpr32:
case Vgpr64:
case VgprP0:
@@ -696,6 +707,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
break;
}
// vgpr scalars, pointers and vectors
+case Vgpr16:
case Vgpr32:
case Vgpr64:
case VgprP0:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
index f91a1e2fa4771..a518c708a07b3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
@@ -111,6 +111,7 @@ class RegBankLegalizeHelper {
void lowerDiv_BFE(MachineInstr &MI);
void lowerUni_BFE(MachineInstr &MI);
+ void lowerSplitTo32(MachineInstr &MI);
};
} // end namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 7959bf30ca27d..96bc969dd1f40 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -106,6 +106,8 @@ bool
[llvm-branch-commits] [llvm] 4Abi debug 20 (PR #133266)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/133266
>From b2b05ff2f84cb7963093752b9e0d3fe93a6cd021 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:11:08 -0700
Subject: [PATCH 1/4] workflows: Add missing apt-get update to abi tests
---
.github/workflows/libclang-abi-tests.yml | 5 -
.github/workflows/llvm-tests.yml | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index 41b3075288d2d..ff8f38b43098e 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -103,6 +103,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -154,7 +155,9 @@ jobs:
path: build-latest
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 9b3d49d4e99b9..92debf2a8a269 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -91,6 +91,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -163,7 +164,9 @@ jobs:
path: symbol-list
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
if [ -s symbol-list/llvm.symbols ]; then
>From f6c1c53267b35855cfdc450cc88761b2116ae050 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:20:25 -0700
Subject: [PATCH 2/4] [workflows] Use -g instead of -g1 for the abi tests
This should improve the debuginfo and hopefully make the abi tests
more accurate.
---
.github/workflows/libclang-abi-tests.yml | 2 +-
.github/workflows/llvm-tests.yml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ff8f38b43098e..b740e5696350b 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -120,7 +120,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
- name: Build
run: ninja -C build/ ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}
install-clang-headers
- name: Dump ABI
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 92debf2a8a269..43cdccedfc894 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -108,7 +108,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DCMAKE_C_FLAGS_DEBUG="-g1 -Og" -DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g
-Og" -DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install
llvm
- name: Build
# Need to run install-LLVM twice to ensure the symlink is installed
(this is a bug).
run: |
>From 12036ba96b6efc54973d895cd1db5ee6143e2804 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:25:56 -0700
Subject: [PATCH 3/4] [workfows] Run abi checks in the ci container
This has a faster compiler and should help reduce build times.
---
.github/workflows/libclang-abi-tests.yml | 2 ++
.github/workflows/llvm-tests.yml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/.github/workflows/libclang-abi-t
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
@@ -0,0 +1,141 @@ +; RUN: llc -mtriple=aarch64 -enable-split-machine-functions \ snehasish wrote: Yeah, it makes sense to rely on a more precise profile due to the fine grained nature of this optimization. Refactoring out the requirement as a condition common to MFS and SDS sounds good. https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][StaticDataSplitter]Support constant pool partitioning (PR #129781)
https://github.com/snehasish approved this pull request. https://github.com/llvm/llvm-project/pull/129781 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] release/20.x: XFAIL malloc_zone.cpp for darwin/lsan (#131234) (PR #133006)
@@ -17,6 +17,8 @@ // UBSan does not install a malloc zone. // XFAIL: ubsan // +// Curently fails on darwin/lsan rdar://145873843 tstellar wrote: This will need to be fixed in main and backported along with this patch. https://github.com/llvm/llvm-project/pull/133006 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [BOLT] Gadget scanner: reformulate the state for data-flow analysis (PR #131898)
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/131898
>From 479bf6822797ba5e65b1697d9b7ff065014205a4 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 17 Mar 2025 22:27:53 +0300
Subject: [PATCH] [BOLT] Gadget scanner: reformulate the state for data-flow
analysis
In preparation for implementing support for detection of non-protected
call instructions, refine the definition of state which is computed for
each register by data-flow analysis.
Explicitly marking the registers which are known to be trusted at
function entry is crucial for finding non-protected calls. In addition,
it fixes less-common false negatives for pac-ret, such as `ret x1` in
`f_nonx30_ret_non_auted` test case.
---
bolt/include/bolt/Core/MCPlusBuilder.h| 10 ++
bolt/include/bolt/Passes/PAuthGadgetScanner.h | 7 +-
bolt/lib/Passes/PAuthGadgetScanner.cpp| 129 +++---
.../Target/AArch64/AArch64MCPlusBuilder.cpp | 4 +
.../AArch64/gs-pacret-autiasp.s | 19 ++-
.../AArch64/gs-pacret-multi-bb.s | 3 +-
.../AArch64/gs-pauth-debug-output.s | 72 +-
7 files changed, 139 insertions(+), 105 deletions(-)
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h
b/bolt/include/bolt/Core/MCPlusBuilder.h
index b285138b77fe7..76ea2489e7038 100644
--- a/bolt/include/bolt/Core/MCPlusBuilder.h
+++ b/bolt/include/bolt/Core/MCPlusBuilder.h
@@ -551,6 +551,16 @@ class MCPlusBuilder {
return Analysis->isReturn(Inst);
}
+ /// Returns the registers that are trusted at function entry.
+ ///
+ /// Each register should be treated as if a successfully authenticated
+ /// pointer was written to it before entering the function (i.e. the
+ /// pointer is safe to jump to as well as to be signed).
+ virtual SmallVector getTrustedLiveInRegs() const {
+llvm_unreachable("not implemented");
+return {};
+ }
+
virtual ErrorOr getAuthenticatedReg(const MCInst &Inst) const {
llvm_unreachable("not implemented");
return getNoRegister();
diff --git a/bolt/include/bolt/Passes/PAuthGadgetScanner.h
b/bolt/include/bolt/Passes/PAuthGadgetScanner.h
index 1a8abffa09c46..700059b814ab9 100644
--- a/bolt/include/bolt/Passes/PAuthGadgetScanner.h
+++ b/bolt/include/bolt/Passes/PAuthGadgetScanner.h
@@ -212,7 +212,7 @@ struct GadgetReport : public Report {
// The particular kind of gadget that is detected.
const GadgetKind &Kind;
// The set of registers related to this gadget report (possibly empty).
- SmallVector AffectedRegisters;
+ SmallVector AffectedRegisters;
// The instructions that clobber the affected registers.
// There is no one-to-one correspondence with AffectedRegisters: for example,
// the same register can be overwritten by different instructions in
different
@@ -220,9 +220,8 @@ struct GadgetReport : public Report {
SmallVector OverwritingInstrs;
GadgetReport(const GadgetKind &Kind, MCInstReference Location,
- const BitVector &AffectedRegisters)
- : Report(Location), Kind(Kind),
-AffectedRegisters(AffectedRegisters.set_bits()) {}
+ MCPhysReg AffectedRegister)
+ : Report(Location), Kind(Kind), AffectedRegisters({AffectedRegister}) {}
void generateReport(raw_ostream &OS, const BinaryContext &BC) const override;
diff --git a/bolt/lib/Passes/PAuthGadgetScanner.cpp
b/bolt/lib/Passes/PAuthGadgetScanner.cpp
index 84c209ac838f8..5269710e1c995 100644
--- a/bolt/lib/Passes/PAuthGadgetScanner.cpp
+++ b/bolt/lib/Passes/PAuthGadgetScanner.cpp
@@ -126,18 +126,16 @@ class TrackedRegisters {
// The security property that is checked is:
// When a register is used as the address to jump to in a return instruction,
-// that register must either:
-// (a) never be changed within this function, i.e. have the same value as when
-// the function started, or
+// that register must be safe-to-dereference. It must either
+// (a) be safe-to-dereference at function entry and never be changed within
this
+// function, i.e. have the same value as when the function started, or
// (b) the last write to the register must be by an authentication instruction.
// This property is checked by using dataflow analysis to keep track of which
-// registers have been written (def-ed), since last authenticated. Those are
-// exactly the registers containing values that should not be trusted (as they
-// could have changed since the last time they were authenticated). For
pac-ret,
-// any return instruction using such a register is a gadget to be reported. For
-// PAuthABI, probably at least any indirect control flow using such a register
-// should be reported.
+// registers have been written (def-ed), since last authenticated. For pac-ret,
+// any return instruction using a register which is not safe-to-dereference is
+// a gadget to be reported. For PAuthABI, probably at least any indirect
control
+// flow using such a register should be reported.
// Fu
[llvm-branch-commits] [llvm] release/20.x: Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol" (#133291) (PR #133348)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/133348
Backport cd6e959102888279dc7e75a41ebd75a08ac3f7a5
Requested by: @efriedma-quic
>From 2406e0d4467a265678f4e414f23a88faf5012944 Mon Sep 17 00:00:00 2001
From: Eli Friedman
Date: Thu, 27 Mar 2025 17:46:42 -0700
Subject: [PATCH] Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol"
(#133291)
Reverts llvm/llvm-project#108880 .
The patch has no regression test, no description of why the fix is
necessary, and the code is modifying MC datastructures in a way that's
forbidden in the AsmPrinter.
Fixes #132055.
(cherry picked from commit cd6e959102888279dc7e75a41ebd75a08ac3f7a5)
---
llvm/lib/Target/X86/X86MCInstLower.cpp | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 645a9baeba65c..680bf4286da0c 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -348,12 +348,8 @@ MCOperand X86MCInstLower::LowerMachineOperand(const
MachineInstr *MI,
return MCOperand::createImm(MO.getImm());
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_ExternalSymbol:
return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
- case MachineOperand::MO_ExternalSymbol: {
-MCSymbol *Sym = GetSymbolFromOperand(MO);
-Sym->setExternal(true);
-return LowerSymbolOperand(MO, Sym);
- }
case MachineOperand::MO_MCSymbol:
return LowerSymbolOperand(MO, MO.getMCSymbol());
case MachineOperand::MO_JumpTableIndex:
___
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[llvm-branch-commits] [llvm] release/20.x: Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol" (#133291) (PR #133348)
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: None (llvmbot)
Changes
Backport cd6e959102888279dc7e75a41ebd75a08ac3f7a5
Requested by: @efriedma-quic
---
Full diff: https://github.com/llvm/llvm-project/pull/133348.diff
1 Files Affected:
- (modified) llvm/lib/Target/X86/X86MCInstLower.cpp (+1-5)
``diff
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 645a9baeba65c..680bf4286da0c 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -348,12 +348,8 @@ MCOperand X86MCInstLower::LowerMachineOperand(const
MachineInstr *MI,
return MCOperand::createImm(MO.getImm());
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_ExternalSymbol:
return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
- case MachineOperand::MO_ExternalSymbol: {
-MCSymbol *Sym = GetSymbolFromOperand(MO);
-Sym->setExternal(true);
-return LowerSymbolOperand(MO, Sym);
- }
case MachineOperand::MO_MCSymbol:
return LowerSymbolOperand(MO, MO.getMCSymbol());
case MachineOperand::MO_JumpTableIndex:
``
https://github.com/llvm/llvm-project/pull/133348
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[llvm-branch-commits] [llvm] release/20.x: Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol" (#133291) (PR #133348)
llvmbot wrote: @MaskRay What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/133348 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: workflows: Add missing apt-get update to abi tests (#133264) (PR #133336)
llvmbot wrote:
@llvm/pr-subscribers-github-workflow
Author: None (llvmbot)
Changes
Backport a10a9134023539ee6ab3d166518487f40e368334
Requested by: @tstellar
---
Full diff: https://github.com/llvm/llvm-project/pull/16.diff
2 Files Affected:
- (modified) .github/workflows/libclang-abi-tests.yml (+4-1)
- (modified) .github/workflows/llvm-tests.yml (+4-1)
``diff
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index 41b3075288d2d..ff8f38b43098e 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -103,6 +103,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -154,7 +155,9 @@ jobs:
path: build-latest
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 9b3d49d4e99b9..92debf2a8a269 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -91,6 +91,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -163,7 +164,9 @@ jobs:
path: symbol-list
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
if [ -s symbol-list/llvm.symbols ]; then
``
https://github.com/llvm/llvm-project/pull/16
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[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
@@ -2233,8 +2235,17 @@ ParseStatus
RISCVAsmParser::parseOperandWithSpecifier(OperandVector &Operands) {
SMLoc S = getLoc();
SMLoc E;
- if (!parseOptionalToken(AsmToken::Percent) ||
- getLexer().getKind() != AsmToken::Identifier)
+ if (!parseOptionalToken(AsmToken::Percent))
+return Error(getLoc(), "expected '%' relocation specifier");
+ const MCExpr *Expr = nullptr;
+ bool Failed = parseExprWithSpecifier(Expr, E);
+ if (!Failed)
+Operands.push_back(RISCVOperand::createImm(Expr, S, E, isRV64()));
+ return Failed;
+}
+
+bool RISCVAsmParser::parseExprWithSpecifier(const MCExpr *&Res, SMLoc &E) {
MaskRay wrote:
As I understand it, `ParseStatus` is preferred for `parse*` functions generated
by TableGen.
However, `ParseStatus` is used very lightly in AsmParser.cpp, where
`parseDataExpr` is needed. So the bool return value here should be ok.
https://github.com/llvm/llvm-project/pull/132569
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[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
@@ -2233,8 +2235,17 @@ ParseStatus
RISCVAsmParser::parseOperandWithSpecifier(OperandVector &Operands) {
SMLoc S = getLoc();
SMLoc E;
- if (!parseOptionalToken(AsmToken::Percent) ||
- getLexer().getKind() != AsmToken::Identifier)
+ if (!parseOptionalToken(AsmToken::Percent))
+return Error(getLoc(), "expected '%' relocation specifier");
+ const MCExpr *Expr = nullptr;
+ bool Failed = parseExprWithSpecifier(Expr, E);
+ if (!Failed)
+Operands.push_back(RISCVOperand::createImm(Expr, S, E, isRV64()));
+ return Failed;
+}
+
+bool RISCVAsmParser::parseExprWithSpecifier(const MCExpr *&Res, SMLoc &E) {
lenary wrote:
Would be great to move these all to ParseStatus, but this PR isn't the right
moment.
https://github.com/llvm/llvm-project/pull/132569
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[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
@@ -2233,8 +2235,17 @@ ParseStatus
RISCVAsmParser::parseOperandWithSpecifier(OperandVector &Operands) {
SMLoc S = getLoc();
SMLoc E;
- if (!parseOptionalToken(AsmToken::Percent) ||
- getLexer().getKind() != AsmToken::Identifier)
+ if (!parseOptionalToken(AsmToken::Percent))
+return Error(getLoc(), "expected '%' relocation specifier");
lenary wrote:
Nit: this means the % is not optional, is there maybe a better way to write
this?
```suggestion
if (parseToken(AsmToken::Percent, "expected '%' relocation specifier"))
return ParseStatus::Failure;
```
maybe?
https://github.com/llvm/llvm-project/pull/132569
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[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/132569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol" (#133291) (PR #133348)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/133348 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel (PR #132569)
https://github.com/lenary approved this pull request. I am happy with this, but I don't know if Jessica has more feedback. Comments below are nits or for follow-ups https://github.com/llvm/llvm-project/pull/132569 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol" (#133291) (PR #133348)
https://github.com/MaskRay approved this pull request. https://github.com/llvm/llvm-project/pull/133348 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)
https://github.com/tstellar milestoned https://github.com/llvm/llvm-project/pull/133219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [CI] Add rich build information for github workflows (PR #133197)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/133197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [hexagon] Enable --eh-frame-hdr (#130225) (PR #130678)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/130678
>From 1a76c29a9ba877c85acf455f05af47039607958b Mon Sep 17 00:00:00 2001
From: Brian Cain
Date: Mon, 10 Mar 2025 16:35:22 -0600
Subject: [PATCH] [hexagon] Enable --eh-frame-hdr (#130225)
The missing `PT_GNU_EH_FRAME` was causing C++ exception handling test
failures in llvm-test-suite. We should unconditionally add this argument
like the other drivers do.
Discovered-by: Alexey Karyakin
Fixes: #129745
(cherry picked from commit 6657769199ad625ea0cb7f7c054d4f6a27806080)
---
clang/lib/Driver/ToolChains/Hexagon.cpp | 1 +
clang/test/Driver/hexagon-toolchain-elf.c | 1 +
clang/test/Driver/hexagon-toolchain-linux.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 76cedf312d68a..772a9827cb211 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -313,6 +313,7 @@ constructHexagonLinkArgs(Compilation &C, const JobAction
&JA,
// handled somewhere else.
Args.ClaimAllArgs(options::OPT_static_libgcc);
+ CmdArgs.push_back("--eh-frame-hdr");
//
//
//
diff --git a/clang/test/Driver/hexagon-toolchain-elf.c
b/clang/test/Driver/hexagon-toolchain-elf.c
index be812dda40d57..de2ebfeeda26c 100644
--- a/clang/test/Driver/hexagon-toolchain-elf.c
+++ b/clang/test/Driver/hexagon-toolchain-elf.c
@@ -555,6 +555,7 @@
// RUN: -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \
// RUN: -mcpu=hexagonv60 \
// RUN: -fuse-ld=lld %s 2>&1 | FileCheck -check-prefix=CHECK382 %s
+// CHECK382: "--eh-frame-hdr
// CHECK382-NOT: "-march=
// CHECK382-NOT: "-mcpu=
//
-
diff --git a/clang/test/Driver/hexagon-toolchain-linux.c
b/clang/test/Driver/hexagon-toolchain-linux.c
index 6f7f3b20f9141..e791353cca07f 100644
--- a/clang/test/Driver/hexagon-toolchain-linux.c
+++ b/clang/test/Driver/hexagon-toolchain-linux.c
@@ -127,6 +127,7 @@
// RUN:--target=hexagon-unknown-linux-musl %s -### 2>&1 \
// RUN:| FileCheck -check-prefix=CHECK011 %s
// CHECK011: InstalledDir: [[INSTALLED_DIR:.+]]
+// CHECK011: "--eh-frame-hdr"
// CHECK011: crt1.o
// CHECK011-NOT: "-lunwind"
// CHECK011-NOT: "-lgcc_eh"
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[llvm-branch-commits] [compiler-rt] 6f5c633 - Revert "[sanitizer] intercept getservent_r, getservbyname_r, getservbyport_r …"
Author: Florian Mayer
Date: 2025-03-27T22:50:45-04:00
New Revision: 6f5c63325cea5e6df071fac83161883406ad5844
URL:
https://github.com/llvm/llvm-project/commit/6f5c63325cea5e6df071fac83161883406ad5844
DIFF:
https://github.com/llvm/llvm-project/commit/6f5c63325cea5e6df071fac83161883406ad5844.diff
LOG: Revert "[sanitizer] intercept getservent_r, getservbyname_r,
getservbyport_r …"
This reverts commit aa3149d204ed019c53eedd1bb00a315c0db41270.
Added:
Modified:
compiler-rt/lib/msan/tests/msan_test.cpp
compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
Removed:
diff --git a/compiler-rt/lib/msan/tests/msan_test.cpp
b/compiler-rt/lib/msan/tests/msan_test.cpp
index 8b7df85e0ff04..a126dd4fdd55e 100644
--- a/compiler-rt/lib/msan/tests/msan_test.cpp
+++ b/compiler-rt/lib/msan/tests/msan_test.cpp
@@ -4908,74 +4908,5 @@ TEST(MemorySanitizer, timer_create) {
EXPECT_POISONED(timer2);
timer_delete(timer);
}
-
-TEST(MemorySanitizer, getservent_r) {
- struct servent result_buf;
- struct servent *result;
- char buf[1024];
- EXPECT_POISONED(result_buf);
- EXPECT_POISONED(result);
- EXPECT_POISONED(buf);
- ASSERT_EQ(getservent_r(&result_buf, buf, sizeof(buf), &result), 0);
- EXPECT_NOT_POISONED(result);
- ASSERT_NE(result, nullptr);
- EXPECT_NOT_POISONED(result_buf);
- EXPECT_NOT_POISONED(buf);
-}
-
-TEST(MemorySanitizer, getservbyname_r) {
- struct servent result_buf;
- struct servent *result;
- char buf[1024];
- EXPECT_POISONED(result_buf);
- EXPECT_POISONED(result);
- EXPECT_POISONED(buf);
- ASSERT_EQ(
- getservbyname_r("ssh", nullptr, &result_buf, buf, sizeof(buf), &result),
- 0);
- EXPECT_NOT_POISONED(result);
- // If this fails, check /etc/services if "ssh" exists. I picked this because
- // it should exist everywhere, if it doesn't, I am sorry. Disable the test
- // then please.
- ASSERT_NE(result, nullptr);
- EXPECT_NOT_POISONED(result_buf);
- EXPECT_NOT_POISONED(buf);
-}
-
-TEST(MemorySanitizer, getservbyname_r_unknown) {
- struct servent result_buf;
- struct servent *result;
- char buf[1024];
- EXPECT_POISONED(result_buf);
- EXPECT_POISONED(result);
- EXPECT_POISONED(buf);
- ASSERT_EQ(getservbyname_r("invalidhadfuiasdhi", nullptr, &result_buf, buf,
-sizeof(buf), &result),
-0);
- EXPECT_NOT_POISONED(result);
- ASSERT_EQ(result, nullptr);
- EXPECT_POISONED(result_buf);
- EXPECT_POISONED(buf);
-}
-
-TEST(MemorySanitizer, getservbyport_r) {
- struct servent result_buf;
- struct servent *result;
- char buf[1024];
- EXPECT_POISONED(result_buf);
- EXPECT_POISONED(result);
- EXPECT_POISONED(buf);
- ASSERT_EQ(getservbyport_r(htons(22), nullptr, &result_buf, buf, sizeof(buf),
-&result),
-0);
- EXPECT_NOT_POISONED(result);
- // If this fails, check /etc/services if "ssh" exists. I picked this because
- // it should exist everywhere, if it doesn't, I am sorry. Disable the test
- // then please.
- ASSERT_NE(result, nullptr);
- EXPECT_NOT_POISONED(result_buf);
- EXPECT_NOT_POISONED(buf);
-}
-
#endif
} // namespace
diff --git
a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
index 1be8a901ab06e..761dbd3f5a679 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
@@ -10279,66 +10279,6 @@ INTERCEPTOR(SSIZE_T, freadlink, int fd, char *buf,
SIZE_T bufsiz) {
# define INIT_FREADLINK
#endif
-UNUSED static void HandleGetServentReentrantResult(
-void *ctx, int res, struct __sanitizer_servent *result_buf, char *buf,
-SIZE_T buflen, struct __sanitizer_servent **result) {
- if (res)
-return;
- COMMON_INTERCEPTOR_WRITE_RANGE(ctx, (char *)result, sizeof(void *));
- if (*result) {
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, (char *)*result,
- sizeof(__sanitizer_servent));
-COMMON_INTERCEPTOR_WRITE_RANGE(ctx, buf, buflen);
- }
-}
-
-#if SANITIZER_INTERCEPT_GETSERVENT_R
-INTERCEPTOR(int, getservent_r, struct __sanitizer_servent *result_buf,
-char *buf, SIZE_T buflen, struct __sanitizer_servent **result) {
- void *ctx;
- COMMON_INTERCEPTOR_ENTER(ctx, getservent_r, result_buf, buf, buflen, result);
- int res = REAL(getservent_r)(result_buf, buf, buflen, result);
- HandleGetServentReentrantResult(ctx, res, result_buf, buf, buflen, result);
- return res;
-}
-# define INIT_GETSERVENT_R COMMON_INTERCEPT_FUNCTION(getservent_r)
-#else
-# define INIT_GETSERVENT_R
-#endif
-
-#if SANITIZER_INTERCEPT_GETSERVBYNAME_R
-INTERCEPTOR(int, getservbyname_r, const char *name, const char *proto,
[llvm-branch-commits] [llvm] [LoongArch][MC] Add relocation support for fld fst [x]vld [x]vst (PR #133225)
https://github.com/tangaac approved this pull request. https://github.com/llvm/llvm-project/pull/133225 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [clang-format] Allow `Language: Cpp` for C files (#133033) (PR #133216)
llvmbot wrote:
@llvm/pr-subscribers-clang-format
Author: None (llvmbot)
Changes
Backport 05fb8408de23c3ccb6125b6886742177755bd757
Requested by: @owenca
---
Full diff: https://github.com/llvm/llvm-project/pull/133216.diff
2 Files Affected:
- (modified) clang/lib/Format/Format.cpp (+14-4)
- (modified) clang/unittests/Format/ConfigParseTest.cpp (+20)
``diff
diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index 0bb8545884442..768e655f65ce7 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -2114,10 +2114,14 @@ std::error_code
parseConfiguration(llvm::MemoryBufferRef Config,
FormatStyle::FormatStyleSet StyleSet;
bool LanguageFound = false;
for (const FormatStyle &Style : llvm::reverse(Styles)) {
-if (Style.Language != FormatStyle::LK_None)
+const auto Lang = Style.Language;
+if (Lang != FormatStyle::LK_None)
StyleSet.Add(Style);
-if (Style.Language == Language)
+if (Lang == Language ||
+// For backward compatibility.
+(Lang == FormatStyle::LK_Cpp && Language == FormatStyle::LK_C)) {
LanguageFound = true;
+}
}
if (!LanguageFound) {
if (Styles.empty() || Styles[0].Language != FormatStyle::LK_None)
@@ -2157,8 +2161,14 @@
FormatStyle::FormatStyleSet::Get(FormatStyle::LanguageKind Language) const {
if (!Styles)
return std::nullopt;
auto It = Styles->find(Language);
- if (It == Styles->end())
-return std::nullopt;
+ if (It == Styles->end()) {
+if (Language != FormatStyle::LK_C)
+ return std::nullopt;
+// For backward compatibility.
+It = Styles->find(FormatStyle::LK_Cpp);
+if (It == Styles->end())
+ return std::nullopt;
+ }
FormatStyle Style = It->second;
Style.StyleSet = *this;
return Style;
diff --git a/clang/unittests/Format/ConfigParseTest.cpp
b/clang/unittests/Format/ConfigParseTest.cpp
index 10788449a1a1d..fcf07e660ddb6 100644
--- a/clang/unittests/Format/ConfigParseTest.cpp
+++ b/clang/unittests/Format/ConfigParseTest.cpp
@@ -1214,6 +1214,26 @@ TEST(ConfigParseTest, ParsesConfigurationWithLanguages) {
IndentWidth, 56u);
}
+TEST(ConfigParseTest, AllowCppForC) {
+ FormatStyle Style = {};
+ Style.Language = FormatStyle::LK_C;
+ EXPECT_EQ(parseConfiguration("Language: Cpp", &Style), ParseError::Success);
+
+ CHECK_PARSE("---\n"
+ "IndentWidth: 4\n"
+ "---\n"
+ "Language: Cpp\n"
+ "IndentWidth: 8\n",
+ IndentWidth, 8u);
+
+ EXPECT_EQ(parseConfiguration("---\n"
+ "Language: ObjC\n"
+ "---\n"
+ "Language: Cpp\n",
+ &Style),
+ParseError::Success);
+}
+
TEST(ConfigParseTest, UsesLanguageForBasedOnStyle) {
FormatStyle Style = {};
Style.Language = FormatStyle::LK_JavaScript;
``
https://github.com/llvm/llvm-project/pull/133216
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[llvm-branch-commits] [clang] release/20.x: [clang-format] Allow `Language: Cpp` for C files (#133033) (PR #133216)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/133216 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] release/20.x: [flang] Fix missed case of symbol renaming in module file generation (#132475) (PR #133223)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/133223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [flang] release/20.x: [flang] Fix missed case of symbol renaming in module file generation (#132475) (PR #133223)
llvmbot wrote: @eugeneepshteyn What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/133223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [clang-format] Allow `Language: Cpp` for C files (#133033) (PR #133216)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/133216
Backport 05fb8408de23c3ccb6125b6886742177755bd757
Requested by: @owenca
>From f5f3f87c9ca7fdcc29a9e6cc54424e66021af0e5 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Thu, 27 Mar 2025 01:00:02 -0700
Subject: [PATCH] [clang-format] Allow `Language: Cpp` for C files (#133033)
Fix #132832
(cherry picked from commit 05fb8408de23c3ccb6125b6886742177755bd757)
---
clang/lib/Format/Format.cpp| 18 ++
clang/unittests/Format/ConfigParseTest.cpp | 20
2 files changed, 34 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index 0bb8545884442..768e655f65ce7 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -2114,10 +2114,14 @@ std::error_code
parseConfiguration(llvm::MemoryBufferRef Config,
FormatStyle::FormatStyleSet StyleSet;
bool LanguageFound = false;
for (const FormatStyle &Style : llvm::reverse(Styles)) {
-if (Style.Language != FormatStyle::LK_None)
+const auto Lang = Style.Language;
+if (Lang != FormatStyle::LK_None)
StyleSet.Add(Style);
-if (Style.Language == Language)
+if (Lang == Language ||
+// For backward compatibility.
+(Lang == FormatStyle::LK_Cpp && Language == FormatStyle::LK_C)) {
LanguageFound = true;
+}
}
if (!LanguageFound) {
if (Styles.empty() || Styles[0].Language != FormatStyle::LK_None)
@@ -2157,8 +2161,14 @@
FormatStyle::FormatStyleSet::Get(FormatStyle::LanguageKind Language) const {
if (!Styles)
return std::nullopt;
auto It = Styles->find(Language);
- if (It == Styles->end())
-return std::nullopt;
+ if (It == Styles->end()) {
+if (Language != FormatStyle::LK_C)
+ return std::nullopt;
+// For backward compatibility.
+It = Styles->find(FormatStyle::LK_Cpp);
+if (It == Styles->end())
+ return std::nullopt;
+ }
FormatStyle Style = It->second;
Style.StyleSet = *this;
return Style;
diff --git a/clang/unittests/Format/ConfigParseTest.cpp
b/clang/unittests/Format/ConfigParseTest.cpp
index 10788449a1a1d..fcf07e660ddb6 100644
--- a/clang/unittests/Format/ConfigParseTest.cpp
+++ b/clang/unittests/Format/ConfigParseTest.cpp
@@ -1214,6 +1214,26 @@ TEST(ConfigParseTest, ParsesConfigurationWithLanguages) {
IndentWidth, 56u);
}
+TEST(ConfigParseTest, AllowCppForC) {
+ FormatStyle Style = {};
+ Style.Language = FormatStyle::LK_C;
+ EXPECT_EQ(parseConfiguration("Language: Cpp", &Style), ParseError::Success);
+
+ CHECK_PARSE("---\n"
+ "IndentWidth: 4\n"
+ "---\n"
+ "Language: Cpp\n"
+ "IndentWidth: 8\n",
+ IndentWidth, 8u);
+
+ EXPECT_EQ(parseConfiguration("---\n"
+ "Language: ObjC\n"
+ "---\n"
+ "Language: Cpp\n",
+ &Style),
+ParseError::Success);
+}
+
TEST(ConfigParseTest, UsesLanguageForBasedOnStyle) {
FormatStyle Style = {};
Style.Language = FormatStyle::LK_JavaScript;
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[llvm-branch-commits] [flang] release/20.x: [flang] Fix missed case of symbol renaming in module file generation (#132475) (PR #133223)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/133223
Backport 6df27dd42d827a2468dcf4b4b1ee1a8e8af1a408
Requested by: @pawosm-arm
>From 78b0eb25e001071d7793bd8f253c3d2efc5cbf0a Mon Sep 17 00:00:00 2001
From: Peter Klausler
Date: Wed, 26 Mar 2025 12:09:38 -0700
Subject: [PATCH] [flang] Fix missed case of symbol renaming in module file
generation (#132475)
The map of symbols requiring new local aliases for USE association needs
to use the symbols' ultimate resolutions to avoid missing cases that can
arise in convoluted codes with lots of confusing renamings.
Fixes https://github.com/llvm/llvm-project/issues/132435.
(cherry picked from commit 6df27dd42d827a2468dcf4b4b1ee1a8e8af1a408)
---
flang/lib/Evaluate/formatting.cpp | 3 +-
flang/lib/Semantics/mod-file.cpp | 2 +-
flang/test/Semantics/bug132435.f90 | 85 ++
3 files changed, 88 insertions(+), 2 deletions(-)
create mode 100644 flang/test/Semantics/bug132435.f90
diff --git a/flang/lib/Evaluate/formatting.cpp
b/flang/lib/Evaluate/formatting.cpp
index f3a53c1f983df..cf0b43bc94c36 100644
--- a/flang/lib/Evaluate/formatting.cpp
+++ b/flang/lib/Evaluate/formatting.cpp
@@ -129,7 +129,8 @@ llvm::raw_ostream &Constant>::AsFortran(
llvm::raw_ostream &EmitVar(llvm::raw_ostream &o, const Symbol &symbol,
std::optional name = std::nullopt) {
const auto &renamings{symbol.owner().context().moduleFileOutputRenamings()};
- if (auto iter{renamings.find(&symbol)}; iter != renamings.end()) {
+ if (auto iter{renamings.find(&symbol.GetUltimate())};
+ iter != renamings.end()) {
return o << iter->second.ToString();
} else if (name) {
return o << name->ToString();
diff --git a/flang/lib/Semantics/mod-file.cpp b/flang/lib/Semantics/mod-file.cpp
index b45f1c060da2f..ea3eae8468b50 100644
--- a/flang/lib/Semantics/mod-file.cpp
+++ b/flang/lib/Semantics/mod-file.cpp
@@ -346,7 +346,7 @@ void ModFileWriter::PrepareRenamings(const Scope &scope) {
uses_ << DEREF(sMod->symbol()).name() << ",only:";
if (rename != s->name()) {
uses_ << rename << "=>";
- renamings.emplace(&*s, rename);
+ renamings.emplace(&s->GetUltimate(), rename);
}
uses_ << s->name() << '\n';
useExtraAttrs_ << "private::" << rename << '\n';
diff --git a/flang/test/Semantics/bug132435.f90
b/flang/test/Semantics/bug132435.f90
new file mode 100644
index 0..be8b661fcf6cc
--- /dev/null
+++ b/flang/test/Semantics/bug132435.f90
@@ -0,0 +1,85 @@
+! RUN: %python %S/test_modfile.py %s %flang_fc1
+module m1
+ type foo
+integer :: c1 = 123
+ end type
+end
+
+module m2
+ use m1, only: foo
+ type baz
+type(foo) :: d = foo()
+ end type
+ type bar
+type(baz) :: e = baz()
+ end type
+end
+
+module m3
+ use m1, only: m1foo => foo
+ type foo
+type(m1foo), private :: c2 = m1foo()
+ end type
+end
+
+module m4
+ use m2, only: m3foo => foo
+ type foo
+type(m3foo), private :: c3 = m3foo()
+ end type
+end
+
+module m5
+ use m2, only: m2bar => bar
+ use m4, only: foo
+ type blah
+type(m2bar) :: f = m2bar()
+ end type
+end
+
+!Expect: m1.mod
+!module m1
+!type::foo
+!integer(4)::c1=123_4
+!end type
+!end
+
+!Expect: m2.mod
+!module m2
+!use m1,only:foo
+!type::baz
+!type(foo)::d=foo(c1=123_4)
+!end type
+!type::bar
+!type(baz)::e=baz(d=foo(c1=123_4))
+!end type
+!end
+
+!Expect: m3.mod
+!module m3
+!use m1,only:m1foo=>foo
+!type::foo
+!type(m1foo),private::c2=m1foo(c1=123_4)
+!end type
+!end
+
+!Expect: m4.mod
+!module m4
+!use m2,only:m3foo=>foo
+!type::foo
+!type(m3foo),private::c3=m3foo(c1=123_4)
+!end type
+!end
+
+!Expect: m5.mod
+!module m5
+!use m2,only:m2$foo=>foo
+!use m2,only:baz
+!use m2,only:m2bar=>bar
+!use m4,only:foo
+!private::m2$foo
+!private::baz
+!type::blah
+!type(m2bar)::f=m2bar(e=baz(d=m2$foo(c1=123_4)))
+!end type
+!end
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[llvm-branch-commits] [flang] release/20.x: [flang] Fix missed case of symbol renaming in module file generation (#132475) (PR #133223)
llvmbot wrote:
@llvm/pr-subscribers-flang-semantics
Author: None (llvmbot)
Changes
Backport 6df27dd42d827a2468dcf4b4b1ee1a8e8af1a408
Requested by: @pawosm-arm
---
Full diff: https://github.com/llvm/llvm-project/pull/133223.diff
3 Files Affected:
- (modified) flang/lib/Evaluate/formatting.cpp (+2-1)
- (modified) flang/lib/Semantics/mod-file.cpp (+1-1)
- (added) flang/test/Semantics/bug132435.f90 (+85)
``diff
diff --git a/flang/lib/Evaluate/formatting.cpp
b/flang/lib/Evaluate/formatting.cpp
index f3a53c1f983df..cf0b43bc94c36 100644
--- a/flang/lib/Evaluate/formatting.cpp
+++ b/flang/lib/Evaluate/formatting.cpp
@@ -129,7 +129,8 @@ llvm::raw_ostream &Constant>::AsFortran(
llvm::raw_ostream &EmitVar(llvm::raw_ostream &o, const Symbol &symbol,
std::optional name = std::nullopt) {
const auto &renamings{symbol.owner().context().moduleFileOutputRenamings()};
- if (auto iter{renamings.find(&symbol)}; iter != renamings.end()) {
+ if (auto iter{renamings.find(&symbol.GetUltimate())};
+ iter != renamings.end()) {
return o << iter->second.ToString();
} else if (name) {
return o << name->ToString();
diff --git a/flang/lib/Semantics/mod-file.cpp b/flang/lib/Semantics/mod-file.cpp
index b45f1c060da2f..ea3eae8468b50 100644
--- a/flang/lib/Semantics/mod-file.cpp
+++ b/flang/lib/Semantics/mod-file.cpp
@@ -346,7 +346,7 @@ void ModFileWriter::PrepareRenamings(const Scope &scope) {
uses_ << DEREF(sMod->symbol()).name() << ",only:";
if (rename != s->name()) {
uses_ << rename << "=>";
- renamings.emplace(&*s, rename);
+ renamings.emplace(&s->GetUltimate(), rename);
}
uses_ << s->name() << '\n';
useExtraAttrs_ << "private::" << rename << '\n';
diff --git a/flang/test/Semantics/bug132435.f90
b/flang/test/Semantics/bug132435.f90
new file mode 100644
index 0..be8b661fcf6cc
--- /dev/null
+++ b/flang/test/Semantics/bug132435.f90
@@ -0,0 +1,85 @@
+! RUN: %python %S/test_modfile.py %s %flang_fc1
+module m1
+ type foo
+integer :: c1 = 123
+ end type
+end
+
+module m2
+ use m1, only: foo
+ type baz
+type(foo) :: d = foo()
+ end type
+ type bar
+type(baz) :: e = baz()
+ end type
+end
+
+module m3
+ use m1, only: m1foo => foo
+ type foo
+type(m1foo), private :: c2 = m1foo()
+ end type
+end
+
+module m4
+ use m2, only: m3foo => foo
+ type foo
+type(m3foo), private :: c3 = m3foo()
+ end type
+end
+
+module m5
+ use m2, only: m2bar => bar
+ use m4, only: foo
+ type blah
+type(m2bar) :: f = m2bar()
+ end type
+end
+
+!Expect: m1.mod
+!module m1
+!type::foo
+!integer(4)::c1=123_4
+!end type
+!end
+
+!Expect: m2.mod
+!module m2
+!use m1,only:foo
+!type::baz
+!type(foo)::d=foo(c1=123_4)
+!end type
+!type::bar
+!type(baz)::e=baz(d=foo(c1=123_4))
+!end type
+!end
+
+!Expect: m3.mod
+!module m3
+!use m1,only:m1foo=>foo
+!type::foo
+!type(m1foo),private::c2=m1foo(c1=123_4)
+!end type
+!end
+
+!Expect: m4.mod
+!module m4
+!use m2,only:m3foo=>foo
+!type::foo
+!type(m3foo),private::c3=m3foo(c1=123_4)
+!end type
+!end
+
+!Expect: m5.mod
+!module m5
+!use m2,only:m2$foo=>foo
+!use m2,only:baz
+!use m2,only:m2bar=>bar
+!use m4,only:foo
+!private::m2$foo
+!private::baz
+!type::blah
+!type(m2bar)::f=m2bar(e=baz(d=m2$foo(c1=123_4)))
+!end type
+!end
``
https://github.com/llvm/llvm-project/pull/133223
___
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[llvm-branch-commits] [LoongArch][MC] Add relocation support for fld fst [x]vld [x]vst (PR #133225)
https://github.com/wangleiat created
https://github.com/llvm/llvm-project/pull/133225
This also fixes errors when using Clang with step-by-step compilation.
Because the optimization will pass relocation information to memory
access instructions. For example:
t.c:
```
float f = 0.1;
float foo() { return f;}
```
```
clang --target=loongarch64 -O2 -c t.c --save-temps
```
___
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llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch][MC] Add relocation support for fld fst [x]vld [x]vst (PR #133225)
llvmbot wrote:
@llvm/pr-subscribers-backend-loongarch
Author: wanglei (wangleiat)
Changes
This also fixes errors when using Clang with step-by-step compilation.
Because the optimization will pass relocation information to memory
access instructions. For example:
t.c:
```
float f = 0.1;
float foo() { return f;}
```
```
clang --target=loongarch64 -O2 -c t.c --save-temps
```
---
Full diff: https://github.com/llvm/llvm-project/pull/133225.diff
4 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td (+2-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (+2-2)
- (modified) llvm/test/MC/LoongArch/Relocations/relocations.s (+18-13)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
index f66f620ca8b26..ce42236895c76 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
@@ -206,7 +206,7 @@ class FP_LOAD_3R op, RegisterClass rc = FPR32>
: FPFmtMEM;
class FP_LOAD_2RI12 op, RegisterClass rc = FPR32>
-: FPFmt2RI12;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
@@ -215,7 +215,7 @@ class FP_STORE_3R op, RegisterClass rc = FPR32>
: FPFmtMEM;
class FP_STORE_2RI12 op, RegisterClass rc = FPR32>
-: FPFmt2RI12;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index 24b5ed5a9344f..7022fddf34100 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -186,10 +186,10 @@ class LASX2RI10_Load op, Operand ImmOpnd =
simm10_lsl2>
class LASX2RI11_Load op, Operand ImmOpnd = simm11_lsl1>
: Fmt2RI11_XRI;
-class LASX2RI12_Load op, Operand ImmOpnd = simm12>
+class LASX2RI12_Load op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_XRI;
-class LASX2RI12_Store op, Operand ImmOpnd = simm12>
+class LASX2RI12_Store op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_XRI;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index d2063a8aaae9b..e37de4f545a2a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -374,10 +374,10 @@ class LSX2RI10_Load op, Operand ImmOpnd =
simm10_lsl2>
class LSX2RI11_Load op, Operand ImmOpnd = simm11_lsl1>
: Fmt2RI11_VRI;
-class LSX2RI12_Load op, Operand ImmOpnd = simm12>
+class LSX2RI12_Load op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_VRI;
-class LSX2RI12_Store op, Operand ImmOpnd = simm12>
+class LSX2RI12_Store op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_VRI;
diff --git a/llvm/test/MC/LoongArch/Relocations/relocations.s
b/llvm/test/MC/LoongArch/Relocations/relocations.s
index 180eeaa3100fa..f91a941295d9e 100644
--- a/llvm/test/MC/LoongArch/Relocations/relocations.s
+++ b/llvm/test/MC/LoongArch/Relocations/relocations.s
@@ -3,9 +3,6 @@
# RUN: llvm-mc --filetype=obj --triple=loongarch64 < %s \
# RUN: | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
-# RUN: not llvm-mc --triple=loongarch64 --defsym=FIXME=1 < %s 2>&1 \
-# RUN: | FileCheck --check-prefix=ERROR %s
-
## Check prefixes:
## RELOC - Check the relocation in the object.
## FIXUP - Check the fixup on the instruction.
@@ -312,24 +309,32 @@ pcaddi $t1, %desc_pcrel_20(foo)
# INSTR: pcaddi $t1, %desc_pcrel_20(foo)
# FIXUP: fixup A - offset: 0, value: %desc_pcrel_20(foo), kind: FK_NONE
-.ifdef FIXME
-
fld.s $ft1, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:17: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: fld.s $ft1, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
fst.d $ft1, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:17: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: fst.d $ft1, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
vld $vr9, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:16: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: vld $vr9, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
vst $vr9, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:16: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: vst $vr9, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
xvld $xr9, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:17: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: xvld $xr9, $a0, %pc_
[llvm-branch-commits] [LoongArch][MC] Add relocation support for fld fst [x]vld [x]vst (PR #133225)
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: wanglei (wangleiat)
Changes
This also fixes errors when using Clang with step-by-step compilation.
Because the optimization will pass relocation information to memory
access instructions. For example:
t.c:
```
float f = 0.1;
float foo() { return f;}
```
```
clang --target=loongarch64 -O2 -c t.c --save-temps
```
---
Full diff: https://github.com/llvm/llvm-project/pull/133225.diff
4 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td (+2-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (+2-2)
- (modified) llvm/test/MC/LoongArch/Relocations/relocations.s (+18-13)
``diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
index f66f620ca8b26..ce42236895c76 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
@@ -206,7 +206,7 @@ class FP_LOAD_3R op, RegisterClass rc = FPR32>
: FPFmtMEM;
class FP_LOAD_2RI12 op, RegisterClass rc = FPR32>
-: FPFmt2RI12;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
@@ -215,7 +215,7 @@ class FP_STORE_3R op, RegisterClass rc = FPR32>
: FPFmtMEM;
class FP_STORE_2RI12 op, RegisterClass rc = FPR32>
-: FPFmt2RI12;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index 24b5ed5a9344f..7022fddf34100 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -186,10 +186,10 @@ class LASX2RI10_Load op, Operand ImmOpnd =
simm10_lsl2>
class LASX2RI11_Load op, Operand ImmOpnd = simm11_lsl1>
: Fmt2RI11_XRI;
-class LASX2RI12_Load op, Operand ImmOpnd = simm12>
+class LASX2RI12_Load op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_XRI;
-class LASX2RI12_Store op, Operand ImmOpnd = simm12>
+class LASX2RI12_Store op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_XRI;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index d2063a8aaae9b..e37de4f545a2a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -374,10 +374,10 @@ class LSX2RI10_Load op, Operand ImmOpnd =
simm10_lsl2>
class LSX2RI11_Load op, Operand ImmOpnd = simm11_lsl1>
: Fmt2RI11_VRI;
-class LSX2RI12_Load op, Operand ImmOpnd = simm12>
+class LSX2RI12_Load op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_VRI;
-class LSX2RI12_Store op, Operand ImmOpnd = simm12>
+class LSX2RI12_Store op, Operand ImmOpnd = simm12_addlike>
: Fmt2RI12_VRI;
diff --git a/llvm/test/MC/LoongArch/Relocations/relocations.s
b/llvm/test/MC/LoongArch/Relocations/relocations.s
index 180eeaa3100fa..f91a941295d9e 100644
--- a/llvm/test/MC/LoongArch/Relocations/relocations.s
+++ b/llvm/test/MC/LoongArch/Relocations/relocations.s
@@ -3,9 +3,6 @@
# RUN: llvm-mc --filetype=obj --triple=loongarch64 < %s \
# RUN: | llvm-readobj -r - | FileCheck --check-prefix=RELOC %s
-# RUN: not llvm-mc --triple=loongarch64 --defsym=FIXME=1 < %s 2>&1 \
-# RUN: | FileCheck --check-prefix=ERROR %s
-
## Check prefixes:
## RELOC - Check the relocation in the object.
## FIXUP - Check the fixup on the instruction.
@@ -312,24 +309,32 @@ pcaddi $t1, %desc_pcrel_20(foo)
# INSTR: pcaddi $t1, %desc_pcrel_20(foo)
# FIXUP: fixup A - offset: 0, value: %desc_pcrel_20(foo), kind: FK_NONE
-.ifdef FIXME
-
fld.s $ft1, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:17: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: fld.s $ft1, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
fst.d $ft1, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:17: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: fst.d $ft1, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
vld $vr9, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:16: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: vld $vr9, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
vst $vr9, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:16: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: vst $vr9, $a0, %pc_lo12(foo)
+# FIXUP: fixup A - offset: 0, value: %pc_lo12(foo), kind: FK_NONE
xvld $xr9, $a0, %pc_lo12(foo)
-# ERROR: :[[#@LINE-1]]:17: error: immediate must be an integer in the range
[-2048, 2047]
+# RELOC: R_LARCH_PCALA_LO12 foo 0x0
+# INSTR: xvld $xr9, $a0, %pc_lo12(foo)
+# FI
[llvm-branch-commits] [llvm] [SDAG] Introduce inbounds flag for pointer arithmetic (PR #131862)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/131862
>From 42481628ec10fe863bc9bca94efa84cd414d385b Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Mon, 17 Mar 2025 06:51:16 -0400
Subject: [PATCH] [SDAG] Introduce inbounds flag for pointer arithmetic
This patch introduces an inbounds SDNodeFlag, to show that a pointer
addition SDNode implements an inbounds getelementptr operation (i.e.,
the pointer operand is in bounds wrt. the allocated object it is based
on, and the arithmetic does not change that). The flag is set in the DAG
construction when lowering inbounds GEPs.
Inbounds information is useful in the ISel when selecting memory
instructions that perform address computations whose intermediate steps
must be in the same memory region as the final result. A follow-up patch
will start using it for AMDGPU's flat memory instructions, where the
immediate offset must not affect the memory aperture of the address.
A similar patch for gMIR and GlobalISel will follow.
For SWDEV-516125.
---
llvm/include/llvm/CodeGen/SelectionDAGNodes.h| 9 +++--
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp| 3 +++
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 3 +++
.../CodeGen/X86/merge-store-partially-alias-loads.ll | 2 +-
4 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
index 2283f99202e2f..13ac65f5d731c 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -415,12 +415,15 @@ struct SDNodeFlags {
Unpredictable = 1 << 13,
// Compare instructions which may carry the samesign flag.
SameSign = 1 << 14,
+// Pointer arithmetic instructions that remain in bounds, e.g.,
implementing
+// an inbounds GEP.
+InBounds = 1 << 15,
// NOTE: Please update LargestValue in LLVM_DECLARE_ENUM_AS_BITMASK below
// the class definition when adding new flags.
PoisonGeneratingFlags = NoUnsignedWrap | NoSignedWrap | Exact | Disjoint |
-NonNeg | NoNaNs | NoInfs | SameSign,
+NonNeg | NoNaNs | NoInfs | SameSign | InBounds,
FastMathFlags = NoNaNs | NoInfs | NoSignedZeros | AllowReciprocal |
AllowContract | ApproximateFuncs | AllowReassociation,
};
@@ -455,6 +458,7 @@ struct SDNodeFlags {
void setAllowReassociation(bool b) { setFlag(b); }
void setNoFPExcept(bool b) { setFlag(b); }
void setUnpredictable(bool b) { setFlag(b); }
+ void setInBounds(bool b) { setFlag(b); }
// These are accessors for each flag.
bool hasNoUnsignedWrap() const { return Flags & NoUnsignedWrap; }
@@ -472,6 +476,7 @@ struct SDNodeFlags {
bool hasAllowReassociation() const { return Flags & AllowReassociation; }
bool hasNoFPExcept() const { return Flags & NoFPExcept; }
bool hasUnpredictable() const { return Flags & Unpredictable; }
+ bool hasInBounds() const { return Flags & InBounds; }
bool operator==(const SDNodeFlags &Other) const {
return Flags == Other.Flags;
@@ -481,7 +486,7 @@ struct SDNodeFlags {
};
LLVM_DECLARE_ENUM_AS_BITMASK(decltype(SDNodeFlags::None),
- SDNodeFlags::SameSign);
+ SDNodeFlags::InBounds);
inline SDNodeFlags operator|(SDNodeFlags LHS, SDNodeFlags RHS) {
LHS |= RHS;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index e3c34382d6354..e8336399d289f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4284,6 +4284,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
if (NW.hasNoUnsignedWrap() ||
(int64_t(Offset) >= 0 && NW.hasNoUnsignedSignedWrap()))
Flags |= SDNodeFlags::NoUnsignedWrap;
+Flags.setInBounds(NW.isInBounds());
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
DAG.getConstant(Offset, dl, N.getValueType()), Flags);
@@ -4327,6 +4328,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
if (NW.hasNoUnsignedWrap() ||
(Offs.isNonNegative() && NW.hasNoUnsignedSignedWrap()))
Flags.setNoUnsignedWrap(true);
+Flags.setInBounds(NW.isInBounds());
OffsVal = DAG.getSExtOrTrunc(OffsVal, dl, N.getValueType());
@@ -4389,6 +4391,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User
&I) {
// pointer index type (add nuw).
SDNodeFlags AddFlags;
AddFlags.setNoUnsignedWrap(NW.hasNoUnsignedWrap());
+ AddFlags.setInBounds(NW.isInBounds());
N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, IdxN, AddFlags);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
ind
[llvm-branch-commits] [flang] release/20.x: [flang] Fix missed case of symbol renaming in module file generation (#132475) (PR #133223)
pawosm-arm wrote: Considering importance of CP2K in the Fortran world, I'd suggest cherry-picking it to the LLVM20 release branch. https://github.com/llvm/llvm-project/pull/133223 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)
RKSimon wrote: Although these instructions aren't supported by current hardware this probably needs a release notes entry - wdyt? https://github.com/llvm/llvm-project/pull/133219 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [compiler-rt] [ctxprof][nfc] Move 2 implementation functions up in `CtxInstrProfiling.cpp` (PR #133146)
mtrofin wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/133146?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#133147** https://app.graphite.dev/github/pr/llvm/llvm-project/133147?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#133146** https://app.graphite.dev/github/pr/llvm/llvm-project/133146?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/133146?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#133106** https://app.graphite.dev/github/pr/llvm/llvm-project/133106?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/133146 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 9c22bc4 - Revert "[MIPS] Define SubTargetFeature for i6500 cpu (#132907)"
Author: Djordje Todorovic
Date: 2025-03-27T09:04:45+01:00
New Revision: 9c22bc410d3e157686ae5fd76f8c000e65949a9e
URL:
https://github.com/llvm/llvm-project/commit/9c22bc410d3e157686ae5fd76f8c000e65949a9e
DIFF:
https://github.com/llvm/llvm-project/commit/9c22bc410d3e157686ae5fd76f8c000e65949a9e.diff
LOG: Revert "[MIPS] Define SubTargetFeature for i6500 cpu (#132907)"
This reverts commit 6294325a535d8042a667ccfb4400a9f63e1bee63.
Added:
Modified:
llvm/lib/Target/Mips/Mips.td
llvm/lib/Target/Mips/MipsSubtarget.h
Removed:
clang/test/CodeGen/Mips/subtarget-feature-test.c
diff --git a/clang/test/CodeGen/Mips/subtarget-feature-test.c
b/clang/test/CodeGen/Mips/subtarget-feature-test.c
deleted file mode 100644
index 7f0b8e7e77135..0
--- a/clang/test/CodeGen/Mips/subtarget-feature-test.c
+++ /dev/null
@@ -1,5 +0,0 @@
-// RUN: %clang --target=mips64-linux-gnu -mcpu=i6400 -o %t -c %s 2>&1 |
FileCheck --allow-empty %s
-// CHECK-NOT: {{.*}} is not a recognized feature for this target
-
-// RUN: %clang --target=mips64-linux-gnu -mcpu=i6500 -o %t -c %s 2>&1 |
FileCheck --allow-empty %s
-// CHECK-NOT: {{.*}} is not a recognized feature for this target
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..9159d11fd486f 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,7 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
- "MIPS I6400 Processor", [FeatureMips64r6]>;
-
-def ImplI6500
-: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
- "MIPS I6500 Processor", [FeatureMips64r6]>;
+ "MIPS I6400/I6500 Processors", [FeatureMips64r6]>;
class Proc Features>
: ProcessorModel;
@@ -272,7 +268,7 @@ def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
-def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
+def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;
def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h
b/llvm/lib/Target/Mips/MipsSubtarget.h
index 15127b11d5cdd..0c75597d3decf 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};
- enum class CPU { P5600, I6400, I6500 };
+ enum class CPU { P5600, I6400 };
// Used to avoid printing dsp warnings multiple times.
static bool DspWarningPrinted;
___
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[llvm-branch-commits] [clang] release/20.x: [clang-format] Allow `Language: Cpp` for C files (#133033) (PR #133216)
llvmbot wrote: @HazardyKnusperkeks What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/133216 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Only fold flat offsets if they are inbounds (PR #132353)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/132353
>From dd12dc2dc49b65b426b6ced3268e85939e55f9f6 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 21 Mar 2025 03:33:02 -0400
Subject: [PATCH] [AMDGPU][SDAG] Only fold flat offsets if they are inbounds
For flat memory instructions where the address is supplied as a base address
register with an immediate offset, the memory aperture test ignores the
immediate offset. Currently, ISel does not respect that, which leads to
miscompilations where valid input programs crash when the address computation
relies on the immediate offset to get the base address in the proper memory
aperture. Global or scratch instructions are not affected.
This patch only selects flat instructions with immediate offsets from address
computations with the inbounds flag: If the address computation does not leave
the bounds of the allocated object, it cannot leave the bounds of the memory
aperture and is therefore safe to handle with an immediate offset.
It also adds the inbounds flag to DAG nodes resulting from transformations:
- Address computations resulting from getObjectPtrOffset. As far as I can tell,
this function is only used to compute addresses within accessed memory ranges,
e.g., for loads and stores that are split during legalization.
- Reassociated inbounds adds. If both involved operations are inbounds, then so
are operations after the transformation.
- Address computations in the SelectionDAG lowering of the memcpy/move/set
intrinsics. Base and result of the address arithmetic there are accessed, so
the operation must be inbounds.
It might make sense to separate these changes into their own PR, but I don't
see a way to test them without adding a use of the inbounds SDAG flag.
Affected tests:
- CodeGen/AMDGPU/fold-gep-offset.ll: Offsets are no longer wrongly folded,
added new positive tests where we still do fold them.
- Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll: Offset folding doesn't
seem integral to this test, so the test is not changed to make offset folding
still happen.
- CodeGen/AMDGPU/loop-prefetch-data.ll: loop-reduce prefers to base addresses
on the potentially OOB addresses used for prefetching for memory accesses,
that might be a separate issue to look into.
- Added memset tests to CodeGen/AMDGPU/memintrinsic-unroll.ll to make sure that
offsets in the memset DAG lowering are still folded properly.
A similar patch for GlobalISel will follow.
Fixes SWDEV-516125.
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 12 +-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +-
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +-
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 140 ---
llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll | 377 +-
.../test/CodeGen/AMDGPU/loop-prefetch-data.ll | 17 +-
.../CodeGen/AMDGPU/memintrinsic-unroll.ll | 241 +++
.../InferAddressSpaces/AMDGPU/flat_atomic.ll | 6 +-
8 files changed, 720 insertions(+), 94 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h
b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 15a2370e5d8b8..aa3668d3e9aae 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1069,7 +1069,8 @@ class SelectionDAG {
SDValue EVL);
/// Returns sum of the base pointer and offset.
- /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
+ /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap and InBounds
by
+ /// default.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL,
const SDNodeFlags Flags = SDNodeFlags());
SDValue getMemBasePlusOffset(SDValue Base, SDValue Offset, const SDLoc &DL,
@@ -1077,15 +1078,18 @@ class SelectionDAG {
/// Create an add instruction with appropriate flags when used for
/// addressing some offset of an object. i.e. if a load is split into
multiple
- /// components, create an add nuw from the base pointer to the offset.
+ /// components, create an add nuw inbounds from the base pointer to the
+ /// offset.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) {
-return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
+return getMemBasePlusOffset(
+Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap | SDNodeFlags::InBounds);
}
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) {
// The object itself can't wrap around the address space, so it shouldn't
be
// possible for the adds of the offsets to the split parts to overflow.
-return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
+return getMemBasePlusOffset(
+Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap | SDNodeFlags::InBounds);
}
/// Return a new CALLSEQ_START node, that starts new call fram
[llvm-branch-commits] [clang] [llvm] [X86] Backport new intrinsic and instruction changes in AVX10.2 (PR #133219)
llvmbot wrote: @llvm/pr-subscribers-clang Author: Phoebe Wang (phoebewang) Changes Close: #133206 --- Patch is 1.24 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/133219.diff 63 Files Affected: - (modified) clang/include/clang/Basic/BuiltinsX86.td (+20-146) - (modified) clang/lib/CodeGen/CGBuiltin.cpp (-120) - (modified) clang/lib/Headers/avx10_2_512convertintrin.h (+24-22) - (modified) clang/lib/Headers/avx10_2_512satcvtdsintrin.h (+28-24) - (modified) clang/lib/Headers/avx10_2_512satcvtintrin.h (+84-84) - (modified) clang/lib/Headers/avx10_2convertintrin.h (+53-68) - (modified) clang/lib/Headers/avx10_2minmaxintrin.h (+18-63) - (modified) clang/lib/Headers/avx10_2niintrin.h (-1666) - (modified) clang/lib/Headers/avx10_2satcvtdsintrin.h (+100-220) - (modified) clang/lib/Headers/avx10_2satcvtintrin.h (+112-244) - (modified) clang/lib/Sema/SemaX86.cpp (+3-162) - (modified) clang/test/CodeGen/X86/avx10_2_512convert-builtins.c (+54-54) - (modified) clang/test/CodeGen/X86/avx10_2_512minmax-error.c (-11) - (removed) clang/test/CodeGen/X86/avx10_2_512satcvt-builtins-error.c (-198) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c (+180-180) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c (+48-48) - (modified) clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c (+37-37) - (modified) clang/test/CodeGen/X86/avx10_2convert-builtins.c (+108-126) - (modified) clang/test/CodeGen/X86/avx10_2minmax-builtins.c (+9-63) - (modified) clang/test/CodeGen/X86/avx10_2ni-builtins.c (-2405) - (modified) clang/test/CodeGen/X86/avx10_2satcvt-builtins.c (+216-358) - (removed) clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c (-57) - (modified) clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c (+96-168) - (modified) clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c (+86-161) - (modified) llvm/include/llvm/IR/IntrinsicsX86.td (+50-486) - (modified) llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp (+1-1) - (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+1-328) - (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+4-4) - (modified) llvm/lib/Target/X86/X86InstrFMA3Info.cpp (+3-6) - (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (+35-218) - (modified) llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll (+4-45) - (modified) llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll (+21-113) - (modified) llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll (-4393) - (modified) llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll (+32-416) - (modified) llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll (+38-38) - (modified) llvm/test/MC/Disassembler/X86/avx10.2-satcvt-32.txt (-64) - (modified) llvm/test/MC/Disassembler/X86/avx10.2-satcvt-64.txt (-64) - (modified) llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt (-48) - (modified) llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt (-48) - (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-32.txt (-8) - (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-64.txt (-8) - (modified) llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt (-24) - (modified) llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt (-24) - (modified) llvm/test/MC/Disassembler/X86/avx10_2ni-32.txt (-1778) - (modified) llvm/test/MC/Disassembler/X86/avx10_2ni-64.txt (-1778) - (modified) llvm/test/MC/X86/avx10.2convert-32-att.s (-8) - (modified) llvm/test/MC/X86/avx10.2convert-32-intel.s (-8) - (modified) llvm/test/MC/X86/avx10.2convert-64-att.s (-8) - (modified) llvm/test/MC/X86/avx10.2convert-64-intel.s (-8) - (modified) llvm/test/MC/X86/avx10.2minmax-32-att.s (-24) - (modified) llvm/test/MC/X86/avx10.2minmax-32-intel.s (-24) - (modified) llvm/test/MC/X86/avx10.2minmax-64-att.s (-24) - (modified) llvm/test/MC/X86/avx10.2minmax-64-intel.s (-24) - (modified) llvm/test/MC/X86/avx10.2satcvt-32-att.s (-64) - (modified) llvm/test/MC/X86/avx10.2satcvt-32-intel.s (-64) - (modified) llvm/test/MC/X86/avx10.2satcvt-64-att.s (-64) - (modified) llvm/test/MC/X86/avx10.2satcvt-64-intel.s (-64) - (modified) llvm/test/MC/X86/avx10_2ni-32-intel.s (-1778) - (modified) llvm/test/MC/X86/avx10_2ni-64-att.s (-1778) - (modified) llvm/test/MC/X86/avx10_2satcvtds-32-att.s (-48) - (modified) llvm/test/MC/X86/avx10_2satcvtds-32-intel.s (-64) - (modified) llvm/test/MC/X86/avx10_2satcvtds-64-att.s (-48) - (modified) llvm/test/MC/X86/avx10_2satcvtds-64-intel.s (-64) ``diff diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index 572ac7235be02..491ce14e7097f 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -4558,132 +4558,6 @@ let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth< def mpsadbw512 : X86Builtin<"_Vector<32, short>(_Vector<64, char>, _Vector<64, char>, _Constant char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Re
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Only fold flat offsets if they are inbounds (PR #132353)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/132353
>From 9294d4f1094afd1b955447a0e76480d83fadb3d4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 21 Mar 2025 03:33:02 -0400
Subject: [PATCH] [AMDGPU][SDAG] Only fold flat offsets if they are inbounds
For flat memory instructions where the address is supplied as a base address
register with an immediate offset, the memory aperture test ignores the
immediate offset. Currently, ISel does not respect that, which leads to
miscompilations where valid input programs crash when the address computation
relies on the immediate offset to get the base address in the proper memory
aperture. Global or scratch instructions are not affected.
This patch only selects flat instructions with immediate offsets from address
computations with the inbounds flag: If the address computation does not leave
the bounds of the allocated object, it cannot leave the bounds of the memory
aperture and is therefore safe to handle with an immediate offset.
It also adds the inbounds flag to DAG nodes resulting from transformations:
- Address computations resulting from getObjectPtrOffset. As far as I can tell,
this function is only used to compute addresses within accessed memory ranges,
e.g., for loads and stores that are split during legalization.
- Reassociated inbounds adds. If both involved operations are inbounds, then so
are operations after the transformation.
- Address computations in the SelectionDAG lowering of the memcpy/move/set
intrinsics. Base and result of the address arithmetic there are accessed, so
the operation must be inbounds.
It might make sense to separate these changes into their own PR, but I don't
see a way to test them without adding a use of the inbounds SDAG flag.
Affected tests:
- CodeGen/AMDGPU/fold-gep-offset.ll: Offsets are no longer wrongly folded,
added new positive tests where we still do fold them.
- Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll: Offset folding doesn't
seem integral to this test, so the test is not changed to make offset folding
still happen.
- CodeGen/AMDGPU/loop-prefetch-data.ll: loop-reduce prefers to base addresses
on the potentially OOB addresses used for prefetching for memory accesses,
that might be a separate issue to look into.
- Added memset tests to CodeGen/AMDGPU/memintrinsic-unroll.ll to make sure that
offsets in the memset DAG lowering are still folded properly.
A similar patch for GlobalISel will follow.
Fixes SWDEV-516125.
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 12 +-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +-
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +-
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 140 ---
llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll | 377 +-
.../test/CodeGen/AMDGPU/loop-prefetch-data.ll | 17 +-
.../CodeGen/AMDGPU/memintrinsic-unroll.ll | 241 +++
.../InferAddressSpaces/AMDGPU/flat_atomic.ll | 6 +-
8 files changed, 720 insertions(+), 94 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h
b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 15a2370e5d8b8..aa3668d3e9aae 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1069,7 +1069,8 @@ class SelectionDAG {
SDValue EVL);
/// Returns sum of the base pointer and offset.
- /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
+ /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap and InBounds
by
+ /// default.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL,
const SDNodeFlags Flags = SDNodeFlags());
SDValue getMemBasePlusOffset(SDValue Base, SDValue Offset, const SDLoc &DL,
@@ -1077,15 +1078,18 @@ class SelectionDAG {
/// Create an add instruction with appropriate flags when used for
/// addressing some offset of an object. i.e. if a load is split into
multiple
- /// components, create an add nuw from the base pointer to the offset.
+ /// components, create an add nuw inbounds from the base pointer to the
+ /// offset.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) {
-return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
+return getMemBasePlusOffset(
+Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap | SDNodeFlags::InBounds);
}
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) {
// The object itself can't wrap around the address space, so it shouldn't
be
// possible for the adds of the offsets to the split parts to overflow.
-return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
+return getMemBasePlusOffset(
+Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap | SDNodeFlags::InBounds);
}
/// Return a new CALLSEQ_START node, that starts new call fram
[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Only fold flat offsets if they are inbounds (PR #132353)
https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/132353
>From 9294d4f1094afd1b955447a0e76480d83fadb3d4 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Fri, 21 Mar 2025 03:33:02 -0400
Subject: [PATCH] [AMDGPU][SDAG] Only fold flat offsets if they are inbounds
For flat memory instructions where the address is supplied as a base address
register with an immediate offset, the memory aperture test ignores the
immediate offset. Currently, ISel does not respect that, which leads to
miscompilations where valid input programs crash when the address computation
relies on the immediate offset to get the base address in the proper memory
aperture. Global or scratch instructions are not affected.
This patch only selects flat instructions with immediate offsets from address
computations with the inbounds flag: If the address computation does not leave
the bounds of the allocated object, it cannot leave the bounds of the memory
aperture and is therefore safe to handle with an immediate offset.
It also adds the inbounds flag to DAG nodes resulting from transformations:
- Address computations resulting from getObjectPtrOffset. As far as I can tell,
this function is only used to compute addresses within accessed memory ranges,
e.g., for loads and stores that are split during legalization.
- Reassociated inbounds adds. If both involved operations are inbounds, then so
are operations after the transformation.
- Address computations in the SelectionDAG lowering of the memcpy/move/set
intrinsics. Base and result of the address arithmetic there are accessed, so
the operation must be inbounds.
It might make sense to separate these changes into their own PR, but I don't
see a way to test them without adding a use of the inbounds SDAG flag.
Affected tests:
- CodeGen/AMDGPU/fold-gep-offset.ll: Offsets are no longer wrongly folded,
added new positive tests where we still do fold them.
- Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll: Offset folding doesn't
seem integral to this test, so the test is not changed to make offset folding
still happen.
- CodeGen/AMDGPU/loop-prefetch-data.ll: loop-reduce prefers to base addresses
on the potentially OOB addresses used for prefetching for memory accesses,
that might be a separate issue to look into.
- Added memset tests to CodeGen/AMDGPU/memintrinsic-unroll.ll to make sure that
offsets in the memset DAG lowering are still folded properly.
A similar patch for GlobalISel will follow.
Fixes SWDEV-516125.
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 12 +-
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +-
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 +-
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 140 ---
llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll | 377 +-
.../test/CodeGen/AMDGPU/loop-prefetch-data.ll | 17 +-
.../CodeGen/AMDGPU/memintrinsic-unroll.ll | 241 +++
.../InferAddressSpaces/AMDGPU/flat_atomic.ll | 6 +-
8 files changed, 720 insertions(+), 94 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h
b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 15a2370e5d8b8..aa3668d3e9aae 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1069,7 +1069,8 @@ class SelectionDAG {
SDValue EVL);
/// Returns sum of the base pointer and offset.
- /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
+ /// Unlike getObjectPtrOffset this does not set NoUnsignedWrap and InBounds
by
+ /// default.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL,
const SDNodeFlags Flags = SDNodeFlags());
SDValue getMemBasePlusOffset(SDValue Base, SDValue Offset, const SDLoc &DL,
@@ -1077,15 +1078,18 @@ class SelectionDAG {
/// Create an add instruction with appropriate flags when used for
/// addressing some offset of an object. i.e. if a load is split into
multiple
- /// components, create an add nuw from the base pointer to the offset.
+ /// components, create an add nuw inbounds from the base pointer to the
+ /// offset.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) {
-return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
+return getMemBasePlusOffset(
+Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap | SDNodeFlags::InBounds);
}
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) {
// The object itself can't wrap around the address space, so it shouldn't
be
// possible for the adds of the offsets to the split parts to overflow.
-return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap);
+return getMemBasePlusOffset(
+Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap | SDNodeFlags::InBounds);
}
/// Return a new CALLSEQ_START node, that starts new call fram
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 55cb190188c7202057c9275447f46eecaea10153 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:44:20 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and
trunc
Uniform S1:
Truncs to uniform S1 and AnyExts from S1 are left as is as they are meant
to be combined away. Uniform S1 ZExt and SExt are lowered using select.
Divergent S1:
Trunc of VGPR to VCC is lowered as compare.
Extends of VCC are lowered using select.
For remaining types:
S32 to S64 ZExt and SExt are lowered using merge values, AnyExt and Trunc
are again left as is to be combined away.
Notably uniform S16 for SExt and Zext is not lowered to S32 and left as is
for instruction select to deal with them. This is because there are patterns
that check for S16 type.
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 7 ++
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 108 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 47 +++-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 3 +
.../GlobalISel/regbankselect-and-s1.mir | 105 +
.../GlobalISel/regbankselect-anyext.mir | 59 +-
.../AMDGPU/GlobalISel/regbankselect-sext.mir | 100 ++--
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 22 +++-
.../AMDGPU/GlobalISel/regbankselect-zext.mir | 89 +--
10 files changed, 358 insertions(+), 183 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index d5a83903e2b13..15df0a29b0fe6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -216,6 +216,13 @@ class AMDGPURegBankLegalizeCombiner {
return;
}
+if (DstTy == S64 && TruncSrcTy == S32) {
+ B.buildMergeLikeInstr(MI.getOperand(0).getReg(),
+{TruncSrc, B.buildUndef({SgprRB, S32})});
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
if (DstTy == S32 && TruncSrcTy == S16) {
B.buildAnyExt(Dst, TruncSrc);
cleanUpAfterCombine(MI, Trunc);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 57ad43cfb8fa9..89f2d7718794e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -131,6 +131,41 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI.getOperand(1).getReg();
+ unsigned Opc = MI.getOpcode();
+ if (Ty == S32 || Ty == S16) {
+auto True = B.buildConstant({VgprRB, Ty}, Opc == G_SEXT ? -1 : 1);
+auto False = B.buildConstant({VgprRB, Ty}, 0);
+B.buildSelect(Dst, Src, True, False);
+ }
+ if (Ty == S64) {
+auto True = B.buildConstant({VgprRB, S32}, Opc == G_SEXT ? -1 : 1);
+auto False = B.buildConstant({VgprRB, S32}, 0);
+auto Lo = B.buildSelect({VgprRB, S32}, Src, True, False);
+MachineInstrBuilder Hi;
+switch (Opc) {
+case G_SEXT:
+ Hi = Lo;
+ break;
+case G_ZEXT:
+ Hi = False;
+ break;
+case G_ANYEXT:
+ Hi = B.buildUndef({VgprRB_S32});
+ break;
+default:
+ llvm_unreachable("Opcode not supported");
+}
+
+B.buildMergeValues(Dst, {Lo.getReg(0), Hi.getReg(0)});
+ }
+ MI.eraseFromParent();
+ return;
+}
+
bool isSignedBFE(MachineInstr &MI) {
unsigned Opc =
isa(MI) ? MI.getOperand(1).getIntrinsicID() : MI.getOpcode();
@@ -265,26 +300,8 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
switch (Mapping.LoweringMethod) {
case DoNotLower:
return;
- case VccExtToSel: {
-LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-Register Src = MI.getOperand(1).getReg();
-unsigned Opc = MI.getOpcode();
-if (Ty == S32 || Ty == S16) {
- auto True = B.buildConstant({VgprRB, Ty}, Opc == G_SEXT ? -1 : 1);
- auto False = B.buildConstant({VgprRB, Ty}, 0);
- B.buildSelect(MI.getOperand(0).getReg(), Src, True, False);
-}
-if (Ty == S64) {
- auto True = B.buildConstant({VgprRB, S32}, Opc == G_SEXT ? -1 : 1);
- auto False = B.buildConstant({VgprRB, S32}, 0);
- auto Sel = B.buildSelect({VgprRB, S32}, Src, True, False);
- B.buildMergeValues(
- MI.getOperand(0).getReg(),
- {Sel.getReg(0), Opc == G_SEXT ? Sel.getReg(0) : False.getReg(0)});
-}
-MI.eraseFromParent();
-return;
- }
+ case VccExtToSel:
+return lowerVccExtToSel(MI);
case UniExtToSel: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
auto True = B.buildConstant({SgprRB, Ty},
@@ -301,13 +3
[llvm-branch-commits] [llvm] 4Abi debug 20 (PR #133266)
https://github.com/tstellar created
https://github.com/llvm/llvm-project/pull/133266
None
>From b2b05ff2f84cb7963093752b9e0d3fe93a6cd021 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:11:08 -0700
Subject: [PATCH 1/3] workflows: Add missing apt-get update to abi tests
---
.github/workflows/libclang-abi-tests.yml | 5 -
.github/workflows/llvm-tests.yml | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index 41b3075288d2d..ff8f38b43098e 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -103,6 +103,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -154,7 +155,9 @@ jobs:
path: build-latest
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 9b3d49d4e99b9..92debf2a8a269 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -91,6 +91,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -163,7 +164,9 @@ jobs:
path: symbol-list
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
if [ -s symbol-list/llvm.symbols ]; then
>From f6c1c53267b35855cfdc450cc88761b2116ae050 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:20:25 -0700
Subject: [PATCH 2/3] [workflows] Use -g instead of -g1 for the abi tests
This should improve the debuginfo and hopefully make the abi tests
more accurate.
---
.github/workflows/libclang-abi-tests.yml | 2 +-
.github/workflows/llvm-tests.yml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ff8f38b43098e..b740e5696350b 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -120,7 +120,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
- name: Build
run: ninja -C build/ ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}
install-clang-headers
- name: Dump ABI
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 92debf2a8a269..43cdccedfc894 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -108,7 +108,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DCMAKE_C_FLAGS_DEBUG="-g1 -Og" -DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g
-Og" -DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install
llvm
- name: Build
# Need to run install-LLVM twice to ensure the symlink is installed
(this is a bug).
run: |
>From 12036ba96b6efc54973d895cd1db5ee6143e2804 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:25:56 -0700
Subject: [PATCH 3/3] [workfows] Run abi checks in the ci container
This has a faster compiler and should help reduce build times.
---
.github/workflows/libclang-abi-tests.yml | 2 ++
.github/workflows/llvm-tests.yml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/.github/workflows/libclang
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0572a36a99cc3ab39de8e4f06a1ff37c29c2a53f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 15:22:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts
and sext-inreg
Uniform S16 shifts have to be extended to S32 using appropriate Extend
before lowering to S32 instruction.
Uniform packed V2S16 are lowered to SGPR S32 instructions,
other option is to use VALU packed V2S16 and ReadAnyLane.
For uniform S32 and S64 and divergent S16, S32, S64 and V2S16 there are
instructions available.
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 2 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 109 ++
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 5 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 43 +++-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 11 ++
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 10 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 187 +-
.../AMDGPU/GlobalISel/regbankselect-ashr.mir | 6 +-
.../AMDGPU/GlobalISel/regbankselect-lshr.mir | 17 +-
.../GlobalISel/regbankselect-sext-inreg.mir | 24 +--
.../AMDGPU/GlobalISel/regbankselect-shl.mir | 6 +-
.../CodeGen/AMDGPU/GlobalISel/sext_inreg.ll | 34 ++--
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll| 10 +-
13 files changed, 313 insertions(+), 151 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index 15df0a29b0fe6..2d2faea7f0088 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -312,7 +312,7 @@ bool
AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
// Opcodes that support pretty much all combinations of reg banks and LLTs
// (except S1). There is no point in writing rules for them.
if (Opc == AMDGPU::G_BUILD_VECTOR || Opc == AMDGPU::G_UNMERGE_VALUES ||
-Opc == AMDGPU::G_MERGE_VALUES) {
+Opc == AMDGPU::G_MERGE_VALUES || Opc == G_BITCAST) {
RBLHelper.applyMappingTrivial(*MI);
continue;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 65d1088d20ed0..d0bd4a8c0ba56 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -14,11 +14,13 @@
#include "AMDGPURegBankLegalizeHelper.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
+#include "AMDGPURegBankLegalizeRules.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/ErrorHandling.h"
@@ -166,6 +168,60 @@ void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr
&MI) {
return;
}
+std::pair RegBankLegalizeHelper::unpackZExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Mask = B.buildConstant(SgprRB_S32, 0x);
+ auto Lo = B.buildAnd(SgprRB_S32, PackedS32, Mask);
+ auto Hi = B.buildLShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32,
16));
+ return {Lo.getReg(0), Hi.getReg(0)};
+}
+
+std::pair RegBankLegalizeHelper::unpackSExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Lo = B.buildSExtInReg(SgprRB_S32, PackedS32, 16);
+ auto Hi = B.buildAShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32,
16));
+ return {Lo.getReg(0), Hi.getReg(0)};
+}
+
+std::pair RegBankLegalizeHelper::unpackAExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Lo = PackedS32;
+ auto Hi = B.buildLShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32,
16));
+ return {Lo.getReg(0), Hi.getReg(0)};
+}
+
+void RegBankLegalizeHelper::lowerUnpack(MachineInstr &MI) {
+ Register Lo, Hi;
+ switch (MI.getOpcode()) {
+ case AMDGPU::G_SHL: {
+auto [Val0, Val1] = unpackAExt(MI.getOperand(1).getReg());
+auto [Amt0, Amt1] = unpackAExt(MI.getOperand(2).getReg());
+Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0);
+Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0);
+break;
+ }
+ case AMDGPU::G_LSHR: {
+auto [Val0, Val1] = unpackZExt(MI.getOperand(1).getReg());
+auto [Amt0, Amt1] = unpackZExt(MI.getOperand(2).getReg());
+Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0);
+Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0);
+break;
+ }
+ case AMDGPU::G_ASHR: {
+auto [Val0, Val1] = unpackSExt(MI.getOperand(1).getReg());
+auto [Amt0, Amt1] = unpackSExt(MI.getOperand(2).getRe
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and XOR (PR #132382)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132382
>From 54ff03532148bfc48ace062e453eaad8ec74fdda Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:42:48 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for AND OR and
XOR
Uniform S1 is lowered to S32.
Divergent S1 is selected as VCC(S1) instruction select will select
SALU instruction based on wavesize (S32 or S64).
S16 are selected as is. There are register classes for vgpr S16.
Since some isel patterns check for sgpr S16 we don't lower to S32.
For 32 and 64 bit types we use B32/B64 rules that cover scalar vector
and pointers types.
SALU B32 and B64 and VALU B32 instructions are available.
Divergent B64 is lowered to B32.
---
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 32 ---
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 10 ++-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 2 +
.../AMDGPU/GlobalISel/regbankselect-and.mir | 33 ---
.../AMDGPU/GlobalISel/regbankselect-or.mir| 85 +--
.../AMDGPU/GlobalISel/regbankselect-xor.mir | 84 +-
7 files changed, 134 insertions(+), 113 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index e2f664396c16d..57ad43cfb8fa9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -242,6 +242,22 @@ void RegBankLegalizeHelper::lowerUni_BFE(MachineInstr &MI)
{
return;
}
+void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst) == V4S16 ? V2S16 : S32;
+ auto Op1 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(1).getReg());
+ auto Op2 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(2).getReg());
+ unsigned Opc = MI.getOpcode();
+ auto Flags = MI.getFlags();
+ auto Lo =
+ B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(0), Op2.getReg(0)}, Flags);
+ auto Hi =
+ B.buildInstr(Opc, {{VgprRB, Ty}}, {Op1.getReg(1), Op2.getReg(1)}, Flags);
+ B.buildMergeLikeInstr(MI.getOperand(0).getReg(), {Lo, Hi});
+ MI.eraseFromParent();
+ return;
+}
+
void RegBankLegalizeHelper::lower(MachineInstr &MI,
const RegBankLLTMapping &Mapping,
SmallSet &WaterfallSgprs) {
@@ -330,20 +346,12 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
MI.eraseFromParent();
return;
}
- case SplitTo32: {
-auto Op1 = B.buildUnmerge(VgprRB_S32, MI.getOperand(1).getReg());
-auto Op2 = B.buildUnmerge(VgprRB_S32, MI.getOperand(2).getReg());
-unsigned Opc = MI.getOpcode();
-auto Lo = B.buildInstr(Opc, {VgprRB_S32}, {Op1.getReg(0), Op2.getReg(0)});
-auto Hi = B.buildInstr(Opc, {VgprRB_S32}, {Op1.getReg(1), Op2.getReg(1)});
-B.buildMergeLikeInstr(MI.getOperand(0).getReg(), {Lo, Hi});
-MI.eraseFromParent();
-break;
- }
case Div_BFE:
return lowerDiv_BFE(MI);
case Uni_BFE:
return lowerUni_BFE(MI);
+ case SplitTo32:
+return lowerSplitTo32(MI);
case SplitLoad: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = DstTy.getSizeInBits();
@@ -403,6 +411,7 @@ LLT
RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case UniInVcc:
return LLT::scalar(1);
case Sgpr16:
+ case Vgpr16:
return LLT::scalar(16);
case Sgpr32:
case Sgpr32Trunc:
@@ -522,6 +531,7 @@
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Sgpr32AExtBoolInReg:
case Sgpr32SExt:
return SgprRB;
+ case Vgpr16:
case Vgpr32:
case Vgpr64:
case VgprP0:
@@ -565,6 +575,7 @@ void RegBankLegalizeHelper::applyMappingDst(
case SgprP4:
case SgprP5:
case SgprV4S32:
+case Vgpr16:
case Vgpr32:
case Vgpr64:
case VgprP0:
@@ -696,6 +707,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
break;
}
// vgpr scalars, pointers and vectors
+case Vgpr16:
case Vgpr32:
case Vgpr64:
case VgprP0:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
index f91a1e2fa4771..a518c708a07b3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
@@ -111,6 +111,7 @@ class RegBankLegalizeHelper {
void lowerDiv_BFE(MachineInstr &MI);
void lowerUni_BFE(MachineInstr &MI);
+ void lowerSplitTo32(MachineInstr &MI);
};
} // end namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 7959bf30ca27d..96bc969dd1f40 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -106,6 +106,8 @@ bool
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (PR #132385)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132385
>From 0572a36a99cc3ab39de8e4f06a1ff37c29c2a53f Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 15:22:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts
and sext-inreg
Uniform S16 shifts have to be extended to S32 using appropriate Extend
before lowering to S32 instruction.
Uniform packed V2S16 are lowered to SGPR S32 instructions,
other option is to use VALU packed V2S16 and ReadAnyLane.
For uniform S32 and S64 and divergent S16, S32, S64 and V2S16 there are
instructions available.
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 2 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 109 ++
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 5 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 43 +++-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 11 ++
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 10 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 187 +-
.../AMDGPU/GlobalISel/regbankselect-ashr.mir | 6 +-
.../AMDGPU/GlobalISel/regbankselect-lshr.mir | 17 +-
.../GlobalISel/regbankselect-sext-inreg.mir | 24 +--
.../AMDGPU/GlobalISel/regbankselect-shl.mir | 6 +-
.../CodeGen/AMDGPU/GlobalISel/sext_inreg.ll | 34 ++--
llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll| 10 +-
13 files changed, 313 insertions(+), 151 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index 15df0a29b0fe6..2d2faea7f0088 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -312,7 +312,7 @@ bool
AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
// Opcodes that support pretty much all combinations of reg banks and LLTs
// (except S1). There is no point in writing rules for them.
if (Opc == AMDGPU::G_BUILD_VECTOR || Opc == AMDGPU::G_UNMERGE_VALUES ||
-Opc == AMDGPU::G_MERGE_VALUES) {
+Opc == AMDGPU::G_MERGE_VALUES || Opc == G_BITCAST) {
RBLHelper.applyMappingTrivial(*MI);
continue;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 65d1088d20ed0..d0bd4a8c0ba56 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -14,11 +14,13 @@
#include "AMDGPURegBankLegalizeHelper.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
+#include "AMDGPURegBankLegalizeRules.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/ErrorHandling.h"
@@ -166,6 +168,60 @@ void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr
&MI) {
return;
}
+std::pair RegBankLegalizeHelper::unpackZExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Mask = B.buildConstant(SgprRB_S32, 0x);
+ auto Lo = B.buildAnd(SgprRB_S32, PackedS32, Mask);
+ auto Hi = B.buildLShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32,
16));
+ return {Lo.getReg(0), Hi.getReg(0)};
+}
+
+std::pair RegBankLegalizeHelper::unpackSExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Lo = B.buildSExtInReg(SgprRB_S32, PackedS32, 16);
+ auto Hi = B.buildAShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32,
16));
+ return {Lo.getReg(0), Hi.getReg(0)};
+}
+
+std::pair RegBankLegalizeHelper::unpackAExt(Register Reg) {
+ auto PackedS32 = B.buildBitcast(SgprRB_S32, Reg);
+ auto Lo = PackedS32;
+ auto Hi = B.buildLShr(SgprRB_S32, PackedS32, B.buildConstant(SgprRB_S32,
16));
+ return {Lo.getReg(0), Hi.getReg(0)};
+}
+
+void RegBankLegalizeHelper::lowerUnpack(MachineInstr &MI) {
+ Register Lo, Hi;
+ switch (MI.getOpcode()) {
+ case AMDGPU::G_SHL: {
+auto [Val0, Val1] = unpackAExt(MI.getOperand(1).getReg());
+auto [Amt0, Amt1] = unpackAExt(MI.getOperand(2).getReg());
+Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0);
+Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0);
+break;
+ }
+ case AMDGPU::G_LSHR: {
+auto [Val0, Val1] = unpackZExt(MI.getOperand(1).getReg());
+auto [Amt0, Amt1] = unpackZExt(MI.getOperand(2).getReg());
+Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val0, Amt0}).getReg(0);
+Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {Val1, Amt1}).getReg(0);
+break;
+ }
+ case AMDGPU::G_ASHR: {
+auto [Val0, Val1] = unpackSExt(MI.getOperand(1).getReg());
+auto [Amt0, Amt1] = unpackSExt(MI.getOperand(2).getRe
[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)
https://github.com/alexrp approved this pull request. https://github.com/llvm/llvm-project/pull/133279 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][LLVM] Delete `LLVMFixedVectorType` (PR #133286)
https://github.com/matthias-springer updated
https://github.com/llvm/llvm-project/pull/133286
>From 44cfa133cbaae27620c911d15d985a5b51f1f1aa Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Thu, 27 Mar 2025 18:42:56 +0100
Subject: [PATCH 1/2] [mlir][LLVM] Delete `LLVMFixedVectorType`
---
mlir/docs/Dialects/LLVM.md| 8 +-
mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 1 -
mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td | 46 +++--
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp| 54 +--
mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp | 2 +-
mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp | 18 ++--
mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 95 ++-
mlir/lib/Target/LLVMIR/TypeToLLVM.cpp | 10 +-
mlir/test/Dialect/LLVMIR/types-invalid.mlir | 19
mlir/test/Dialect/LLVMIR/types.mlir | 2 +
10 files changed, 79 insertions(+), 176 deletions(-)
diff --git a/mlir/docs/Dialects/LLVM.md b/mlir/docs/Dialects/LLVM.md
index fadc81b567b4e..81c358244d96e 100644
--- a/mlir/docs/Dialects/LLVM.md
+++ b/mlir/docs/Dialects/LLVM.md
@@ -327,11 +327,9 @@ multiple of some fixed size in case of _scalable_ vectors,
and the element type.
Vectors cannot be nested and only 1D vectors are supported. Scalable vectors
are
still considered 1D.
-LLVM dialect uses built-in vector types for _fixed_-size vectors of built-in
-types, and provides additional types for fixed-sized vectors of LLVM dialect
-types (`LLVMFixedVectorType`) and scalable vectors of any types
-(`LLVMScalableVectorType`). These two additional types share the following
-syntax:
+The LLVM dialect uses built-in vector types for _fixed_-size vectors of
built-in
+types, and provides additional types for scalable vectors of any types
+(`LLVMScalableVectorType`):
```
llvm-vec-type ::= `!llvm.vec<` (`?` `x`)? integer-literal `x` type `>`
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
index bca0feb45aab2..9d238fc746b8f 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
@@ -67,7 +67,6 @@ namespace LLVM {
}
DEFINE_TRIVIAL_LLVM_TYPE(LLVMVoidType, "llvm.void");
-DEFINE_TRIVIAL_LLVM_TYPE(LLVMPPCFP128Type, "llvm.ppc_fp128");
DEFINE_TRIVIAL_LLVM_TYPE(LLVMTokenType, "llvm.token");
DEFINE_TRIVIAL_LLVM_TYPE(LLVMLabelType, "llvm.label");
DEFINE_TRIVIAL_LLVM_TYPE(LLVMMetadataType, "llvm.metadata");
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
index 3386003cb61fb..fe12ab99b9141 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
@@ -11,6 +11,7 @@
include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
include "mlir/IR/AttrTypeBase.td"
+include "mlir/IR/BuiltinTypeInterfaces.td"
include "mlir/IR/BuiltinTypes.td"
include "mlir/Interfaces/DataLayoutInterfaces.td"
include "mlir/Interfaces/MemorySlotInterfaces.td"
@@ -288,38 +289,6 @@ def LLVMPointerType : LLVMType<"LLVMPointer", "ptr", [
];
}
-//===--===//
-// LLVMFixedVectorType
-//===--===//
-
-def LLVMFixedVectorType : LLVMType<"LLVMFixedVector", "vec"> {
- let summary = "LLVM fixed vector type";
- let description = [{
-LLVM dialect vector type that supports all element types that are supported
-in LLVM vectors but that are not supported by the builtin MLIR vector type.
-E.g., LLVMFixedVectorType supports LLVM pointers as element type.
- }];
-
- let typeName = "llvm.fixed_vec";
-
- let parameters = (ins "Type":$elementType, "unsigned":$numElements);
- let assemblyFormat = [{
-`<` $numElements `x` custom($elementType) `>`
- }];
-
- let genVerifyDecl = 1;
-
- let builders = [
-TypeBuilderWithInferredContext<(ins "Type":$elementType,
-"unsigned":$numElements)>
- ];
-
- let extraClassDeclaration = [{
-/// Checks if the given type can be used in a vector type.
-static bool isValidElementType(Type type);
- }];
-}
-
//===--===//
// LLVMScalableVectorType
//===--===//
@@ -400,4 +369,17 @@ def LLVMX86AMXType : LLVMType<"LLVMX86AMX", "x86_amx"> {
}];
}
+//===--===//
+// LLVMPPCFP128Type
+//===--===//
+
+def LLVMPPCFP128Type : LLVMType<"LLVMPPCFP128", "ppc_fp128",
+[DeclareTypeInterfaceMethods]> {
+ let summary = "128 bit FP type with IBM double-double semantics";
+ let description = [{
+A 128 bit floating-point type with IBM double-double semantics.
+See S_PPCDoubleDouble in APFloat.h for details.
+ }];
+
[llvm-branch-commits] [mlir] [mlir][LLVM] Delete `LLVMFixedVectorType` and `LLVMScalableVectorType` (PR #133286)
https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/133286 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/132383
>From 55cb190188c7202057c9275447f46eecaea10153 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Thu, 27 Mar 2025 14:44:20 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and
trunc
Uniform S1:
Truncs to uniform S1 and AnyExts from S1 are left as is as they are meant
to be combined away. Uniform S1 ZExt and SExt are lowered using select.
Divergent S1:
Trunc of VGPR to VCC is lowered as compare.
Extends of VCC are lowered using select.
For remaining types:
S32 to S64 ZExt and SExt are lowered using merge values, AnyExt and Trunc
are again left as is to be combined away.
Notably uniform S16 for SExt and Zext is not lowered to S32 and left as is
for instruction select to deal with them. This is because there are patterns
that check for S16 type.
---
.../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 7 ++
.../AMDGPU/AMDGPURegBankLegalizeHelper.cpp| 108 +-
.../AMDGPU/AMDGPURegBankLegalizeHelper.h | 1 +
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 47 +++-
.../AMDGPU/AMDGPURegBankLegalizeRules.h | 3 +
.../GlobalISel/regbankselect-and-s1.mir | 105 +
.../GlobalISel/regbankselect-anyext.mir | 59 +-
.../AMDGPU/GlobalISel/regbankselect-sext.mir | 100 ++--
.../AMDGPU/GlobalISel/regbankselect-trunc.mir | 22 +++-
.../AMDGPU/GlobalISel/regbankselect-zext.mir | 89 +--
10 files changed, 358 insertions(+), 183 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index d5a83903e2b13..15df0a29b0fe6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -216,6 +216,13 @@ class AMDGPURegBankLegalizeCombiner {
return;
}
+if (DstTy == S64 && TruncSrcTy == S32) {
+ B.buildMergeLikeInstr(MI.getOperand(0).getReg(),
+{TruncSrc, B.buildUndef({SgprRB, S32})});
+ cleanUpAfterCombine(MI, Trunc);
+ return;
+}
+
if (DstTy == S32 && TruncSrcTy == S16) {
B.buildAnyExt(Dst, TruncSrc);
cleanUpAfterCombine(MI, Trunc);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 57ad43cfb8fa9..89f2d7718794e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -131,6 +131,41 @@ void RegBankLegalizeHelper::widenLoad(MachineInstr &MI,
LLT WideTy,
MI.eraseFromParent();
}
+void RegBankLegalizeHelper::lowerVccExtToSel(MachineInstr &MI) {
+ Register Dst = MI.getOperand(0).getReg();
+ LLT Ty = MRI.getType(Dst);
+ Register Src = MI.getOperand(1).getReg();
+ unsigned Opc = MI.getOpcode();
+ if (Ty == S32 || Ty == S16) {
+auto True = B.buildConstant({VgprRB, Ty}, Opc == G_SEXT ? -1 : 1);
+auto False = B.buildConstant({VgprRB, Ty}, 0);
+B.buildSelect(Dst, Src, True, False);
+ }
+ if (Ty == S64) {
+auto True = B.buildConstant({VgprRB, S32}, Opc == G_SEXT ? -1 : 1);
+auto False = B.buildConstant({VgprRB, S32}, 0);
+auto Lo = B.buildSelect({VgprRB, S32}, Src, True, False);
+MachineInstrBuilder Hi;
+switch (Opc) {
+case G_SEXT:
+ Hi = Lo;
+ break;
+case G_ZEXT:
+ Hi = False;
+ break;
+case G_ANYEXT:
+ Hi = B.buildUndef({VgprRB_S32});
+ break;
+default:
+ llvm_unreachable("Opcode not supported");
+}
+
+B.buildMergeValues(Dst, {Lo.getReg(0), Hi.getReg(0)});
+ }
+ MI.eraseFromParent();
+ return;
+}
+
bool isSignedBFE(MachineInstr &MI) {
unsigned Opc =
isa(MI) ? MI.getOperand(1).getIntrinsicID() : MI.getOpcode();
@@ -265,26 +300,8 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
switch (Mapping.LoweringMethod) {
case DoNotLower:
return;
- case VccExtToSel: {
-LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-Register Src = MI.getOperand(1).getReg();
-unsigned Opc = MI.getOpcode();
-if (Ty == S32 || Ty == S16) {
- auto True = B.buildConstant({VgprRB, Ty}, Opc == G_SEXT ? -1 : 1);
- auto False = B.buildConstant({VgprRB, Ty}, 0);
- B.buildSelect(MI.getOperand(0).getReg(), Src, True, False);
-}
-if (Ty == S64) {
- auto True = B.buildConstant({VgprRB, S32}, Opc == G_SEXT ? -1 : 1);
- auto False = B.buildConstant({VgprRB, S32}, 0);
- auto Sel = B.buildSelect({VgprRB, S32}, Src, True, False);
- B.buildMergeValues(
- MI.getOperand(0).getReg(),
- {Sel.getReg(0), Opc == G_SEXT ? Sel.getReg(0) : False.getReg(0)});
-}
-MI.eraseFromParent();
-return;
- }
+ case VccExtToSel:
+return lowerVccExtToSel(MI);
case UniExtToSel: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
auto True = B.buildConstant({SgprRB, Ty},
@@ -301,13 +3
[llvm-branch-commits] [mlir] [mlir][LLVM] Delete `LLVMFixedVectorType` and `LLVMScalableVectorType` (PR #133286)
@@ -150,8 +150,7 @@ generatedTypePrinter(Type def, AsmPrinter &printer);
bool LLVMArrayType::isValidElementType(Type type) {
return !llvm::isa(
- type);
+LLVMFunctionType, LLVMTokenType>(type);
matthias-springer wrote:
Note: `LLVMScalableVectorType` was in here, but I think it should not have been
because LLVM does not support it.
```c++
bool ArrayType::isValidElementType(Type *ElemTy) {
return !ElemTy->isVoidTy() && !ElemTy->isLabelTy() &&
!ElemTy->isMetadataTy() && !ElemTy->isFunctionTy() &&
!ElemTy->isTokenTy() && !ElemTy->isX86_AMXTy();
}
```
https://github.com/llvm/llvm-project/pull/133286
___
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[llvm-branch-commits] [llvm] 3593789 - Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol (#108880)"
Author: Eli Friedman
Date: 2025-03-27T11:12:51-07:00
New Revision: 35937892be532c8bd5fda5b738141cab1b347f81
URL:
https://github.com/llvm/llvm-project/commit/35937892be532c8bd5fda5b738141cab1b347f81
DIFF:
https://github.com/llvm/llvm-project/commit/35937892be532c8bd5fda5b738141cab1b347f81.diff
LOG: Revert "[MC] Explicitly mark MCSymbol for MO_ExternalSymbol (#108880)"
This reverts commit 3d0846bedcd18d546fd3733c93c2e144f2faab09.
Added:
Modified:
llvm/lib/Target/X86/X86MCInstLower.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 3bd012c13cf0d..3f6cd55618666 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -349,12 +349,8 @@ MCOperand X86MCInstLower::LowerMachineOperand(const
MachineInstr *MI,
return MCOperand::createImm(MO.getImm());
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_ExternalSymbol:
return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
- case MachineOperand::MO_ExternalSymbol: {
-MCSymbol *Sym = GetSymbolFromOperand(MO);
-Sym->setExternal(true);
-return LowerSymbolOperand(MO, Sym);
- }
case MachineOperand::MO_MCSymbol:
return LowerSymbolOperand(MO, MO.getMCSymbol());
case MachineOperand::MO_JumpTableIndex:
___
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[llvm-branch-commits] [llvm] 4Abi debug 20 (PR #133266)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/133266
>From b2b05ff2f84cb7963093752b9e0d3fe93a6cd021 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:11:08 -0700
Subject: [PATCH 1/6] workflows: Add missing apt-get update to abi tests
---
.github/workflows/libclang-abi-tests.yml | 5 -
.github/workflows/llvm-tests.yml | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index 41b3075288d2d..ff8f38b43098e 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -103,6 +103,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -154,7 +155,9 @@ jobs:
path: build-latest
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 9b3d49d4e99b9..92debf2a8a269 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -91,6 +91,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -163,7 +164,9 @@ jobs:
path: symbol-list
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
if [ -s symbol-list/llvm.symbols ]; then
>From f6c1c53267b35855cfdc450cc88761b2116ae050 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:20:25 -0700
Subject: [PATCH 2/6] [workflows] Use -g instead of -g1 for the abi tests
This should improve the debuginfo and hopefully make the abi tests
more accurate.
---
.github/workflows/libclang-abi-tests.yml | 2 +-
.github/workflows/llvm-tests.yml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ff8f38b43098e..b740e5696350b 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -120,7 +120,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
- name: Build
run: ninja -C build/ ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}
install-clang-headers
- name: Dump ABI
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 92debf2a8a269..43cdccedfc894 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -108,7 +108,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DCMAKE_C_FLAGS_DEBUG="-g1 -Og" -DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g
-Og" -DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install
llvm
- name: Build
# Need to run install-LLVM twice to ensure the symlink is installed
(this is a bug).
run: |
>From 12036ba96b6efc54973d895cd1db5ee6143e2804 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:25:56 -0700
Subject: [PATCH 3/6] [workfows] Run abi checks in the ci container
This has a faster compiler and should help reduce build times.
---
.github/workflows/libclang-abi-tests.yml | 2 ++
.github/workflows/llvm-tests.yml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/.github/workflows/libclang-abi-t
[llvm-branch-commits] [CI] Add rich build information for github workflows (PR #133197)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/133197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [CI] Add rich build information for github workflows (PR #133197)
https://github.com/boomanaiden154 updated https://github.com/llvm/llvm-project/pull/133197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][LLVM] Delete `LLVMFixedVectorType` and `LLVMScalableVectorType` (PR #133286)
https://github.com/matthias-springer edited https://github.com/llvm/llvm-project/pull/133286 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for select (PR #132384)
@@ -492,7 +511,8 @@ LLT
RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
case UniInVgprB64:
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
-Ty == LLT::pointer(1, 64) || Ty == LLT::pointer(4, 64))
+Ty == LLT::pointer(1, 64) || Ty == LLT::pointer(4, 64) ||
+Ty == LLT::pointer(999, 64))
ritter-x2a wrote:
I don't think we should have special case handling for address space 999. The
tests using that AS surely just use it to represent "any other address space"?
https://github.com/llvm/llvm-project/pull/132384
___
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[llvm-branch-commits] [llvm] [PowerPC] Add dense math half-precision floating-point outer-product accumulate to DMR instructions (PR #133272)
https://github.com/maryammo created
https://github.com/llvm/llvm-project/pull/133272
This patch adds the following Dense Math Facility 16-bit half-precision
floating-point calculation instructions: dmxvf16gerx2, dmxvf16gerx2pp,
dmxvf16gerx2pn, dmxvf16gerx2np, dmxvf16gerx2nn, pmdmxvf16gerx2,
pmdmxvf16gerx2pp, pmdmxvf16gerx2pn, pmdmxvf16gerx2np, pmdmxvf16gerx2nn, along
with their corresponding intrinsics and tests.
>From 109f52126c42231776d7cd2402827cedb036a240 Mon Sep 17 00:00:00 2001
From: Maryam Moghadas
Date: Thu, 27 Mar 2025 16:30:41 +
Subject: [PATCH] [PowerPC] Add dense math half-precision floating-point
outer-product accumulate to DMR instructions
This patch adds the following Dense Math Facility 16-bit half-precision
floating-point calculation instructions: dmxvf16gerx2, dmxvf16gerx2pp,
dmxvf16gerx2pn, dmxvf16gerx2np, dmxvf16gerx2nn, pmdmxvf16gerx2,
pmdmxvf16gerx2pp, pmdmxvf16gerx2pn, pmdmxvf16gerx2np, pmdmxvf16gerx2nn,
along with their corresponding intrinsics and tests.
---
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 7 +
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td | 116 -
.../test/CodeGen/PowerPC/dmf-outer-product.ll | 483 ++
.../PowerPC/ppc-encoding-ISAFuture.txt| 30 ++
.../PowerPC/ppc64le-encoding-ISAFuture.txt| 30 ++
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 50 ++
6 files changed, 714 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b57102ef68f09..bcc3fc6f0fc13 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1755,6 +1755,13 @@ let TargetPrefix = "ppc" in {
defm int_ppc_mma_pmdmxvbf16gerx2 :
PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty]>;
+
+ // MMA+ Half-precision Outer Product Intrinsic Definitions.
+ defm int_ppc_mma_dmxvf16gerx2 :
+ PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty]>;
+ defm int_ppc_mma_pmdmxvf16gerx2 :
+ PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
+ llvm_i32_ty, llvm_i32_ty]>;
}
// XL Compat intrinsics.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 8ea0924f09b43..331649bddafb7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -207,7 +207,7 @@ multiclass DMR_BF16_UM_XOEO opcode, bits<8> xo, dag
IOL, string asmbase,
}
}
-multiclass DMR_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string
asmbase,
+multiclass DMR_BF16_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string
asmbase,
string asmstr> {
defm NAME : DMR_BF16_UM_XOEO;
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
@@ -228,9 +228,30 @@ multiclass DMR_UM_M284_XOEO opcode, bits<8> xo,
dag IOL, string asmbase,
}
}
+multiclass DMR_F16_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string
asmbase,
+string asmstr> {
+ defm NAME : DMR_UM_XOEO;
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
+ def PM#NAME :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !or(xo, 0x01), (outs dmr:$AT),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK,
u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
multiclass DMR_NEG_UM_M284_XOXORf939a0 opcode, bits<8> xo, dag IOL,
string asmbase, string asmstr> {
- defm NAME : DMR_UM_M284_XOEO;
+ defm NAME : DMR_BF16_UM_M284_XOEO;
let Predicates = [MMA, IsISAFuture] in {
def PN : XX3Form_AT3_XAp5B6<
opcode, !xor(xo, 0xF9), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
@@ -270,6 +291,48 @@ multiclass DMR_NEG_UM_M284_XOXORf939a0 opcode,
bits<8> xo, dag IOL,
}
}
+multiclass DMR_NEG_UM_M284_XOXORd11188 opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
+ defm NAME : DMR_F16_UM_M284_XOEO;
+ let Predicates = [MMA, IsISAFuture] in {
+ def PN : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0xD1), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NP : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0x11), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">,
[llvm-branch-commits] [llvm] [PowerPC] Add dense math half-precision floating-point outer-product accumulate to DMR instructions (PR #133272)
llvmbot wrote:
@llvm/pr-subscribers-backend-powerpc
Author: Maryam Moghadas (maryammo)
Changes
This patch adds the following Dense Math Facility 16-bit half-precision
floating-point calculation instructions: dmxvf16gerx2, dmxvf16gerx2pp,
dmxvf16gerx2pn, dmxvf16gerx2np, dmxvf16gerx2nn, pmdmxvf16gerx2,
pmdmxvf16gerx2pp, pmdmxvf16gerx2pn, pmdmxvf16gerx2np, pmdmxvf16gerx2nn, along
with their corresponding intrinsics and tests.
---
Patch is 34.41 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/133272.diff
6 Files Affected:
- (modified) llvm/include/llvm/IR/IntrinsicsPowerPC.td (+7)
- (modified) llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td (+114-2)
- (modified) llvm/test/CodeGen/PowerPC/dmf-outer-product.ll (+483)
- (modified) llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt (+30)
- (modified) llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
(+30)
- (modified) llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s (+50)
``diff
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index b57102ef68f09..bcc3fc6f0fc13 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1755,6 +1755,13 @@ let TargetPrefix = "ppc" in {
defm int_ppc_mma_pmdmxvbf16gerx2 :
PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty]>;
+
+ // MMA+ Half-precision Outer Product Intrinsic Definitions.
+ defm int_ppc_mma_dmxvf16gerx2 :
+ PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty]>;
+ defm int_ppc_mma_pmdmxvf16gerx2 :
+ PowerPC_MMA_DMR_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
+ llvm_i32_ty, llvm_i32_ty]>;
}
// XL Compat intrinsics.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 8ea0924f09b43..331649bddafb7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -207,7 +207,7 @@ multiclass DMR_BF16_UM_XOEO opcode, bits<8> xo, dag
IOL, string asmbase,
}
}
-multiclass DMR_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string
asmbase,
+multiclass DMR_BF16_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string
asmbase,
string asmstr> {
defm NAME : DMR_BF16_UM_XOEO;
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
@@ -228,9 +228,30 @@ multiclass DMR_UM_M284_XOEO opcode, bits<8> xo,
dag IOL, string asmbase,
}
}
+multiclass DMR_F16_UM_M284_XOEO opcode, bits<8> xo, dag IOL, string
asmbase,
+string asmstr> {
+ defm NAME : DMR_UM_XOEO;
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
+ def PM#NAME :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !or(xo, 0x01), (outs dmr:$AT),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK,
u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+}
+
multiclass DMR_NEG_UM_M284_XOXORf939a0 opcode, bits<8> xo, dag IOL,
string asmbase, string asmstr> {
- defm NAME : DMR_UM_M284_XOEO;
+ defm NAME : DMR_BF16_UM_M284_XOEO;
let Predicates = [MMA, IsISAFuture] in {
def PN : XX3Form_AT3_XAp5B6<
opcode, !xor(xo, 0xF9), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
@@ -270,6 +291,48 @@ multiclass DMR_NEG_UM_M284_XOXORf939a0 opcode,
bits<8> xo, dag IOL,
}
}
+multiclass DMR_NEG_UM_M284_XOXORd11188 opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
+ defm NAME : DMR_F16_UM_M284_XOEO;
+ let Predicates = [MMA, IsISAFuture] in {
+ def PN : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0xD1), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NP : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0x11), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NN : XX3Form_AT3_XAp5B6<
+ opcode, !xor(xo, 0x88), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ }
+ let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
+ def PM#NAME#PN :
+MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for extends and trunc (PR #132383)
@@ -489,22 +489,61 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
addRulesForGOpcs({G_ANYEXT})
+ .Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away
.Any({{UniS32, S1}, {{None}, {None}}}) // should be combined away
- .Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}});
+ .Any({{UniS64, S1}, {{None}, {None}}}) // should be combined away
+ .Any({{{DivS16, S1}}, {{Vgpr16}, {Vcc}, VccExtToSel}})
+ .Any({{{DivS32, S1}}, {{Vgpr32}, {Vcc}, VccExtToSel}})
+ .Any({{{DivS64, S1}}, {{Vgpr64}, {Vcc}, VccExtToSel}})
+ .Any({{UniS64, S32}, {{Sgpr64}, {Sgpr32}, Ext32To64}})
petar-avramovic wrote:
Quick explanation for now:
.Any({**{DivS32, S1}**, {{Vgpr32}, {Vcc}, VccExtToSel}}) is list for predicate
checks uniform/divergent and types of operands. Usually one is enough (just
dst) but here we check for divergent S32 dst and S1 source
there is a place for c++ check here (see loads)
.Any({{DivS32, S1}, {**{Vgpr32}**, {Vcc}, VccExtToSel}}) list of which register
bank to apply on dst registers (check RegBankLegalizeHelper for details)
.Any({{DivS32, S1}, {{Vgpr32}, **{Vcc}**, VccExtToSel}}) list of which register
bank to apply on source registers
.Any({{DivS32, S1}, {{Vgpr32}, {Vcc}, **VccExtToSel**}}) ID of more complicated
lowering method, for example this one is transforming G_ANYEXT to G_SELECT
https://github.com/llvm/llvm-project/pull/132383
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[llvm-branch-commits] [CI] Add rich build information for github workflows (PR #133197)
https://github.com/DavidSpickett approved this pull request. LGTM. https://github.com/llvm/llvm-project/pull/133197 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 4Abi debug 20 (PR #133266)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/133266
>From b2b05ff2f84cb7963093752b9e0d3fe93a6cd021 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:11:08 -0700
Subject: [PATCH 1/5] workflows: Add missing apt-get update to abi tests
---
.github/workflows/libclang-abi-tests.yml | 5 -
.github/workflows/llvm-tests.yml | 5 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index 41b3075288d2d..ff8f38b43098e 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -103,6 +103,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -154,7 +155,9 @@ jobs:
path: build-latest
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
for lib in ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}; do
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 9b3d49d4e99b9..92debf2a8a269 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -91,6 +91,7 @@ jobs:
uses: llvm/actions/install-ninja@main
- name: Install abi-compliance-checker
run: |
+ sudo apt-get update
sudo apt-get install abi-dumper autoconf pkg-config
- name: Install universal-ctags
run: |
@@ -163,7 +164,9 @@ jobs:
path: symbol-list
- name: Install abi-compliance-checker
-run: sudo apt-get install abi-compliance-checker
+run: |
+ sudo apt-get update
+ sudo apt-get install abi-compliance-checker
- name: Compare ABI
run: |
if [ -s symbol-list/llvm.symbols ]; then
>From f6c1c53267b35855cfdc450cc88761b2116ae050 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:20:25 -0700
Subject: [PATCH 2/5] [workflows] Use -g instead of -g1 for the abi tests
This should improve the debuginfo and hopefully make the abi tests
more accurate.
---
.github/workflows/libclang-abi-tests.yml | 2 +-
.github/workflows/llvm-tests.yml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ff8f38b43098e..b740e5696350b 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -120,7 +120,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -S llvm -G Ninja -DLLVM_ENABLE_PROJECTS=clang
-DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DLLVM_LINK_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g -Og"
-DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
- name: Build
run: ninja -C build/ ${{ needs.abi-dump-setup.outputs.ABI_LIBS }}
install-clang-headers
- name: Dump ABI
diff --git a/.github/workflows/llvm-tests.yml b/.github/workflows/llvm-tests.yml
index 92debf2a8a269..43cdccedfc894 100644
--- a/.github/workflows/llvm-tests.yml
+++ b/.github/workflows/llvm-tests.yml
@@ -108,7 +108,7 @@ jobs:
- name: Configure
run: |
mkdir install
- cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON
-DCMAKE_C_FLAGS_DEBUG="-g1 -Og" -DCMAKE_CXX_FLAGS_DEBUG="-g1 -Og"
-DCMAKE_INSTALL_PREFIX="$(pwd)"/install llvm
+ cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Debug
-DLLVM_TARGETS_TO_BUILD="" -DLLVM_BUILD_LLVM_DYLIB=ON -DCMAKE_C_FLAGS_DEBUG="-g
-Og" -DCMAKE_CXX_FLAGS_DEBUG="-g -Og" -DCMAKE_INSTALL_PREFIX="$(pwd)"/install
llvm
- name: Build
# Need to run install-LLVM twice to ensure the symlink is installed
(this is a bug).
run: |
>From 12036ba96b6efc54973d895cd1db5ee6143e2804 Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Thu, 27 Mar 2025 08:25:56 -0700
Subject: [PATCH 3/5] [workfows] Run abi checks in the ci container
This has a faster compiler and should help reduce build times.
---
.github/workflows/libclang-abi-tests.yml | 2 ++
.github/workflows/llvm-tests.yml | 2 ++
2 files changed, 4 insertions(+)
diff --git a/.github/workflows/libclang-abi-t
[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for select (PR #132384)
petar-avramovic wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/132384?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#132385** https://app.graphite.dev/github/pr/llvm/llvm-project/132385?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#132384** https://app.graphite.dev/github/pr/llvm/llvm-project/132384?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/132384?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#132383** https://app.graphite.dev/github/pr/llvm/llvm-project/132383?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#132382** https://app.graphite.dev/github/pr/llvm/llvm-project/132382?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#132381** https://app.graphite.dev/github/pr/llvm/llvm-project/132381?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/132384 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/133279
Backport
https://github.com/llvm/llvm-project/commit/ade22fc1d9616c95bd1aa4ea658a21ddb073b73c
Requested by: @lei137
>From f04efc3eafa9e1397613cbbc33f1370f896202c8 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Wed, 19 Mar 2025 10:19:57 -0400
Subject: [PATCH 1/2] [PowerPC] Support conversion between f16 and f128
(#130158)
Enables conversion between f16 and f128.
Expanding on pre-Power9 targets and using HW instructions on Power9.
Fixes https://github.com/llvm/llvm-project/issues/92866
Commandeer of: https://github.com/llvm/llvm-project/pull/97677
-
Co-authored-by: esmeyi
(cherry picked from commit ade22fc1d9616c95bd1aa4ea658a21ddb073b73c)
---
llvm/lib/IR/RuntimeLibcalls.cpp | 1 +
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +
llvm/lib/Target/PowerPC/PPCInstrVSX.td | 4 +
llvm/test/CodeGen/PowerPC/f128-conv.ll | 487
llvm/test/CodeGen/PowerPC/fp128-libcalls.ll | 17 +
5 files changed, 215 insertions(+), 300 deletions(-)
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index e38fce764b640..085a3bc0586b6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -82,6 +82,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
setLibcallName(RTLIB::POWI_F128, "__powikf2");
setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
+setLibcallName(RTLIB::FPROUND_F128_F16, "__trunckfhf2");
setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 21ff6f050817a..16491a145a5b9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -223,13 +223,19 @@ PPCTargetLowering::PPCTargetLowering(const
PPCTargetMachine &TM,
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}
+ setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+ setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
if (Subtarget.isISA3_0()) {
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
setTruncStoreAction(MVT::f64, MVT::f16, Legal);
setTruncStoreAction(MVT::f32, MVT::f16, Legal);
} else {
// No extending loads from f16 or HW conversions back and forth.
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
+setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 8e400bc63b785..a8724ea125140 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3997,6 +3997,8 @@ defm : ScalToVecWPermute<
(SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
// Load/convert and convert/store patterns for f16.
+def : Pat<(f128 (extloadf16 ForceXForm:$src)),
+ (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src>;
def : Pat<(f64 (extloadf16 ForceXForm:$src)),
(f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4005,6 +4007,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)),
VSSRC))>;
def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
(STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)),
ForceXForm:$dst)>;
+def : Pat<(f128 (f16_to_fp i32:$A)),
+ (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A>;
def : Pat<(f64 (f16_to_fp i32:$A)),
(f64 (XSCVHPDP (MTVSRWZ $A)))>;
def : Pat<(f32 (f16_to_fp i32:$A)),
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index d8eed1fb4092c..f8b2861156db4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -10,11 +10,11 @@
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
-@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16
0], align 2
-@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
+@uhwMem = global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
+@ubMem = global [5 x i8] c"\05\02\03\04\00", align 1
; Function Attrs: norecurse nounwin
[llvm-branch-commits] [llvm] release/20.x: [PowerPC] Support conversion between f16 and f128 (#130158) (PR #132049)
lei137 wrote: New PR to backport to V20.x: https://github.com/llvm/llvm-project/pull/133279 https://github.com/llvm/llvm-project/pull/132049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)
llvmbot wrote:
@llvm/pr-subscribers-backend-powerpc
Author: Lei Huang (lei137)
Changes
Backport
https://github.com/llvm/llvm-project/commit/ade22fc1d9616c95bd1aa4ea658a21ddb073b73c
Requested by: @lei137
---
Patch is 59.34 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/133279.diff
5 Files Affected:
- (modified) llvm/lib/IR/RuntimeLibcalls.cpp (+1)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+6)
- (modified) llvm/lib/Target/PowerPC/PPCInstrVSX.td (+4)
- (modified) llvm/test/CodeGen/PowerPC/f128-conv.ll (+187-300)
- (modified) llvm/test/CodeGen/PowerPC/fp128-libcalls.ll (+17)
``diff
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index e38fce764b640..085a3bc0586b6 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -82,6 +82,7 @@ void RuntimeLibcallsInfo::initLibcalls(const Triple &TT) {
setLibcallName(RTLIB::POWI_F128, "__powikf2");
setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
+setLibcallName(RTLIB::FPROUND_F128_F16, "__trunckfhf2");
setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 21ff6f050817a..16491a145a5b9 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -223,13 +223,19 @@ PPCTargetLowering::PPCTargetLowering(const
PPCTargetMachine &TM,
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}
+ setTruncStoreAction(MVT::f128, MVT::f16, Expand);
+ setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
+
if (Subtarget.isISA3_0()) {
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
setTruncStoreAction(MVT::f64, MVT::f16, Legal);
setTruncStoreAction(MVT::f32, MVT::f16, Legal);
} else {
// No extending loads from f16 or HW conversions back and forth.
+setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand);
+setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 8e400bc63b785..a8724ea125140 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -3997,6 +3997,8 @@ defm : ScalToVecWPermute<
(SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>;
// Load/convert and convert/store patterns for f16.
+def : Pat<(f128 (extloadf16 ForceXForm:$src)),
+ (f128 (XSCVDPQP (XSCVHPDP (LXSIHZX ForceXForm:$src>;
def : Pat<(f64 (extloadf16 ForceXForm:$src)),
(f64 (XSCVHPDP (LXSIHZX ForceXForm:$src)))>;
def : Pat<(truncstoref16 f64:$src, ForceXForm:$dst),
@@ -4005,6 +4007,8 @@ def : Pat<(f32 (extloadf16 ForceXForm:$src)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX ForceXForm:$src)),
VSSRC))>;
def : Pat<(truncstoref16 f32:$src, ForceXForm:$dst),
(STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)),
ForceXForm:$dst)>;
+def : Pat<(f128 (f16_to_fp i32:$A)),
+ (f128 (XSCVDPQP (XSCVHPDP (MTVSRWZ $A>;
def : Pat<(f64 (f16_to_fp i32:$A)),
(f64 (XSCVHPDP (MTVSRWZ $A)))>;
def : Pat<(f32 (f16_to_fp i32:$A)),
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll
b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index d8eed1fb4092c..1a51ca64177a0 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -10,11 +10,11 @@
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
@swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
@uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
-@uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16
0], align 2
-@ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
+@uhwMem = global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
+@ubMem = global [5 x i8] c"\05\02\03\04\00", align 1
; Function Attrs: norecurse nounwind
-define void @sdwConv2qp(ptr nocapture %a, i64 %b) {
+define void @sdwConv2qp(ptr nocapture %a, i64 %b) nounwind {
; CHECK-LABEL: sdwConv2qp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT:mtvsrd v2, r4
@@ -25,9 +25,6 @@ define void @sdwConv2qp(ptr nocapture %a, i64 %b) {
; CHECK-P8-LABEL: sdwConv2qp:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT:mflr r0
-; CHECK-P8-NEXT:.cfi_def_cfa_offse
[llvm-branch-commits] [llvm] [PowerPC] Support conversion between f16 and f128 (#130158) (PR #133279)
https://github.com/lei137 milestoned https://github.com/llvm/llvm-project/pull/133279 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [LoongArch][MC] Add relocation support for fld fst [x]vld [x]vst (PR #133225)
https://github.com/wangleiat updated https://github.com/llvm/llvm-project/pull/133225 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/20.x: [libcxx] [test] Fix restoring LLVM_DIR and Clang_DIR (#132838) (PR #133153)
https://github.com/mordante approved this pull request. LGTM! https://github.com/llvm/llvm-project/pull/133153 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [mlir] [mlir][LLVM] Delete `LLVMFixedVectorType` (PR #133286)
https://github.com/matthias-springer created
https://github.com/llvm/llvm-project/pull/133286
Since #125690, the MLIR vector type supports `!llvm.ptr` as an element type.
The only remaining element type for `LLVMFixedVectorType` is now
`LLVMPPCFP128Type`.
This commit turns `LLVMPPCFP128Type` into a proper FP type (by implementing
`FloatTypeInterface`), so that the MLIR vector type accepts it as an element
type. This makes `LLVMFixedVectorType` obsolete. This commit deletes
`LLVMFixedVectorType`.
Note: `LLVMScalableVectorType` remains for now.
Depends on #125690.
>From 44cfa133cbaae27620c911d15d985a5b51f1f1aa Mon Sep 17 00:00:00 2001
From: Matthias Springer
Date: Thu, 27 Mar 2025 18:42:56 +0100
Subject: [PATCH] [mlir][LLVM] Delete `LLVMFixedVectorType`
---
mlir/docs/Dialects/LLVM.md| 8 +-
mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 1 -
mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td | 46 +++--
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp| 54 +--
mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp | 2 +-
mlir/lib/Dialect/LLVMIR/IR/LLVMTypeSyntax.cpp | 18 ++--
mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 95 ++-
mlir/lib/Target/LLVMIR/TypeToLLVM.cpp | 10 +-
mlir/test/Dialect/LLVMIR/types-invalid.mlir | 19
mlir/test/Dialect/LLVMIR/types.mlir | 2 +
10 files changed, 79 insertions(+), 176 deletions(-)
diff --git a/mlir/docs/Dialects/LLVM.md b/mlir/docs/Dialects/LLVM.md
index fadc81b567b4e..81c358244d96e 100644
--- a/mlir/docs/Dialects/LLVM.md
+++ b/mlir/docs/Dialects/LLVM.md
@@ -327,11 +327,9 @@ multiple of some fixed size in case of _scalable_ vectors,
and the element type.
Vectors cannot be nested and only 1D vectors are supported. Scalable vectors
are
still considered 1D.
-LLVM dialect uses built-in vector types for _fixed_-size vectors of built-in
-types, and provides additional types for fixed-sized vectors of LLVM dialect
-types (`LLVMFixedVectorType`) and scalable vectors of any types
-(`LLVMScalableVectorType`). These two additional types share the following
-syntax:
+The LLVM dialect uses built-in vector types for _fixed_-size vectors of
built-in
+types, and provides additional types for scalable vectors of any types
+(`LLVMScalableVectorType`):
```
llvm-vec-type ::= `!llvm.vec<` (`?` `x`)? integer-literal `x` type `>`
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
index bca0feb45aab2..9d238fc746b8f 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
@@ -67,7 +67,6 @@ namespace LLVM {
}
DEFINE_TRIVIAL_LLVM_TYPE(LLVMVoidType, "llvm.void");
-DEFINE_TRIVIAL_LLVM_TYPE(LLVMPPCFP128Type, "llvm.ppc_fp128");
DEFINE_TRIVIAL_LLVM_TYPE(LLVMTokenType, "llvm.token");
DEFINE_TRIVIAL_LLVM_TYPE(LLVMLabelType, "llvm.label");
DEFINE_TRIVIAL_LLVM_TYPE(LLVMMetadataType, "llvm.metadata");
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
index 3386003cb61fb..fe12ab99b9141 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.td
@@ -11,6 +11,7 @@
include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
include "mlir/IR/AttrTypeBase.td"
+include "mlir/IR/BuiltinTypeInterfaces.td"
include "mlir/IR/BuiltinTypes.td"
include "mlir/Interfaces/DataLayoutInterfaces.td"
include "mlir/Interfaces/MemorySlotInterfaces.td"
@@ -288,38 +289,6 @@ def LLVMPointerType : LLVMType<"LLVMPointer", "ptr", [
];
}
-//===--===//
-// LLVMFixedVectorType
-//===--===//
-
-def LLVMFixedVectorType : LLVMType<"LLVMFixedVector", "vec"> {
- let summary = "LLVM fixed vector type";
- let description = [{
-LLVM dialect vector type that supports all element types that are supported
-in LLVM vectors but that are not supported by the builtin MLIR vector type.
-E.g., LLVMFixedVectorType supports LLVM pointers as element type.
- }];
-
- let typeName = "llvm.fixed_vec";
-
- let parameters = (ins "Type":$elementType, "unsigned":$numElements);
- let assemblyFormat = [{
-`<` $numElements `x` custom($elementType) `>`
- }];
-
- let genVerifyDecl = 1;
-
- let builders = [
-TypeBuilderWithInferredContext<(ins "Type":$elementType,
-"unsigned":$numElements)>
- ];
-
- let extraClassDeclaration = [{
-/// Checks if the given type can be used in a vector type.
-static bool isValidElementType(Type type);
- }];
-}
-
//===--===//
// LLVMScalableVectorType
//===--===//
@@ -400,4 +369,17 @@ def LLVMX86AMXType : LLVMType<"LLVMX86AMX", "x86_amx"> {
}];
}
+//===---
