llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-hexagon Author: None (llvmbot) <details> <summary>Changes</summary> Backport 759ef5811e22 c0b2c10e9f3a Requested by: @<!-- -->androm3da --- Patch is 32.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132499.diff 23 Files Affected: - (modified) clang/lib/Driver/ToolChains/Hexagon.cpp (+1-3) - (added) clang/test/Driver/hexagon-cpu-default.c (+4) - (modified) lld/ELF/Arch/Hexagon.cpp (+1-1) - (modified) lld/docs/ReleaseNotes.rst (+5) - (modified) lld/test/ELF/emulation-hexagon.s (+2-2) - (modified) lld/test/ELF/hexagon-eflag.s (+3-2) - (modified) llvm/docs/ReleaseNotes.md (+4) - (modified) llvm/include/llvm/BinaryFormat/ELF.h (+10) - (modified) llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (+1-1) - (modified) llvm/test/CodeGen/Hexagon/arg-copy-elison.ll (+11-12) - (modified) llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll (+1-3) - (modified) llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll (+6-6) - (modified) llvm/test/CodeGen/Hexagon/bank-conflict.mir (+1-1) - (modified) llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll (+3-2) - (modified) llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll (+28-22) - (modified) llvm/test/CodeGen/Hexagon/isel/logical.ll (+26-26) - (modified) llvm/test/CodeGen/Hexagon/isel/select-i1.ll (+3-9) - (modified) llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir (+2-2) - (modified) llvm/test/CodeGen/Hexagon/setmemrefs.ll (+1-1) - (modified) llvm/test/MC/Hexagon/arch-support.s (+4) - (modified) llvm/test/MC/Hexagon/hexagon_attributes.s (+8-4) - (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected (+12-13) - (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected (+12-13) ``````````diff diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp b/clang/lib/Driver/ToolChains/Hexagon.cpp index 76cedf312d68a..7ca5ab9af8810 100644 --- a/clang/lib/Driver/ToolChains/Hexagon.cpp +++ b/clang/lib/Driver/ToolChains/Hexagon.cpp @@ -802,9 +802,7 @@ bool HexagonToolChain::isAutoHVXEnabled(const llvm::opt::ArgList &Args) { // Returns the default CPU for Hexagon. This is the default compilation target // if no Hexagon processor is selected at the command-line. // -StringRef HexagonToolChain::GetDefaultCPU() { - return "hexagonv60"; -} +StringRef HexagonToolChain::GetDefaultCPU() { return "hexagonv68"; } StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) { Arg *CpuArg = nullptr; diff --git a/clang/test/Driver/hexagon-cpu-default.c b/clang/test/Driver/hexagon-cpu-default.c new file mode 100644 index 0000000000000..31fb839f21656 --- /dev/null +++ b/clang/test/Driver/hexagon-cpu-default.c @@ -0,0 +1,4 @@ +// CHECK: "-target-cpu" "hexagonv68" + +// RUN: %clang -c %s -### --target=hexagon-unknown-elf \ +// RUN: 2>&1 | FileCheck %s diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp index 23b60672f6317..4ba61db2733c2 100644 --- a/lld/ELF/Arch/Hexagon.cpp +++ b/lld/ELF/Arch/Hexagon.cpp @@ -68,7 +68,7 @@ uint32_t Hexagon::calcEFlags() const { if (!ret || eflags > *ret) ret = eflags; } - return ret.value_or(/* Default Arch Rev: */ 0x60); + return ret.value_or(/* Default Arch Rev: */ EF_HEXAGON_MACH_V68); } static uint32_t applyMask(uint32_t mask, uint32_t data) { diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index e13b0cf0678ce..b8604611e286e 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -76,6 +76,11 @@ ELF Improvements * Supported relocation types for LoongArch target: ``R_LARCH_TLS_{LD,GD,DESC}_PCREL20_S2``. (`#100105 <https://github.com/llvm/llvm-project/pull/100105>`_) +* The default Hexagon architecture version in ELF object files produced by + lld is changed to v68. This change is only effective when the version is + not provided in the command line by the user and cannot be inferred from + inputs. + Breaking changes ---------------- diff --git a/lld/test/ELF/emulation-hexagon.s b/lld/test/ELF/emulation-hexagon.s index a8a02d4c428b5..5bdd88941c269 100644 --- a/lld/test/ELF/emulation-hexagon.s +++ b/lld/test/ELF/emulation-hexagon.s @@ -1,5 +1,5 @@ # REQUIRES: hexagon -# RUN: llvm-mc -filetype=obj -triple=hexagon %s -o %t.o +# RUN: llvm-mc -filetype=obj -triple=hexagon --mcpu=hexagonv73 %s -o %t.o # RUN: ld.lld %t.o -o %t # RUN: llvm-readelf --file-headers %t | FileCheck --check-prefix=CHECK %s # RUN: ld.lld -m hexagonelf %t.o -o %t @@ -26,7 +26,7 @@ # CHECK-NEXT: Entry point address: 0x200B4 # CHECK-NEXT: Start of program headers: 52 (bytes into file) # CHECK-NEXT: Start of section headers: -# CHECK-NEXT: Flags: 0x60 +# CHECK-NEXT: Flags: 0x73 # CHECK-NEXT: Size of this header: 52 (bytes) # CHECK-NEXT: Size of program headers: 32 (bytes) diff --git a/lld/test/ELF/hexagon-eflag.s b/lld/test/ELF/hexagon-eflag.s index dbe8604f69fda..ac9123832ac8a 100644 --- a/lld/test/ELF/hexagon-eflag.s +++ b/lld/test/ELF/hexagon-eflag.s @@ -3,10 +3,11 @@ # RUN: llvm-mc -filetype=obj -mv60 -triple=hexagon-unknown-elf %S/Inputs/hexagon.s -o %t2 # RUN: ld.lld %t2 %t -o %t3 # RUN: llvm-readelf -h %t3 | FileCheck %s -# Verify that the largest arch in the input list is selected. +## Verify that the largest arch in the input list is selected. # CHECK: Flags: 0x62 +## Verify the arch version when it cannot be inferred from inputs. # RUN: llvm-ar rcsD %t4 # RUN: ld.lld -m hexagonelf %t4 -o %t5 # RUN: llvm-readelf -h %t5 | FileCheck --check-prefix=CHECK-EMPTYARCHIVE %s -# CHECK-EMPTYARCHIVE: Flags: 0x60 +# CHECK-EMPTYARCHIVE: Flags: 0x68 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 958b7adbc4c36..f34003eaf0fe2 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -202,6 +202,10 @@ Changes to the DirectX Backend Changes to the Hexagon Backend ------------------------------ +* The default Hexagon architecture version in ELF object files produced by + the tools such as llvm-mc is changed to v68. This version will be set if + the user does not provide the CPU version in the command line. + Changes to the LoongArch Backend -------------------------------- diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index 48ae0db80f43e..8853c4a88b0b5 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -619,6 +619,7 @@ enum { EF_HEXAGON_MACH_V5 = 0x00000004, // Hexagon V5 EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55 EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60 + EF_HEXAGON_MACH_V61 = 0x00000061, // Hexagon V61 EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62 EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65 EF_HEXAGON_MACH_V66 = 0x00000066, // Hexagon V66 @@ -630,7 +631,11 @@ enum { EF_HEXAGON_MACH_V71T = 0x00008071, // Hexagon V71T EF_HEXAGON_MACH_V73 = 0x00000073, // Hexagon V73 EF_HEXAGON_MACH_V75 = 0x00000075, // Hexagon V75 + EF_HEXAGON_MACH_V77 = 0x00000077, // Hexagon V77 EF_HEXAGON_MACH_V79 = 0x00000079, // Hexagon V79 + EF_HEXAGON_MACH_V81 = 0x00000081, // Hexagon V81 + EF_HEXAGON_MACH_V83 = 0x00000083, // Hexagon V83 + EF_HEXAGON_MACH_V85 = 0x00000085, // Hexagon V85 EF_HEXAGON_MACH = 0x000003ff, // Hexagon V.. // Highest ISA version flags @@ -642,6 +647,7 @@ enum { EF_HEXAGON_ISA_V5 = 0x00000040, // Hexagon V5 ISA EF_HEXAGON_ISA_V55 = 0x00000050, // Hexagon V55 ISA EF_HEXAGON_ISA_V60 = 0x00000060, // Hexagon V60 ISA + EF_HEXAGON_ISA_V61 = 0x00000061, // Hexagon V61 ISA EF_HEXAGON_ISA_V62 = 0x00000062, // Hexagon V62 ISA EF_HEXAGON_ISA_V65 = 0x00000065, // Hexagon V65 ISA EF_HEXAGON_ISA_V66 = 0x00000066, // Hexagon V66 ISA @@ -651,7 +657,11 @@ enum { EF_HEXAGON_ISA_V71 = 0x00000071, // Hexagon V71 ISA EF_HEXAGON_ISA_V73 = 0x00000073, // Hexagon V73 ISA EF_HEXAGON_ISA_V75 = 0x00000075, // Hexagon V75 ISA + EF_HEXAGON_ISA_V77 = 0x00000077, // Hexagon V77 ISA EF_HEXAGON_ISA_V79 = 0x00000079, // Hexagon V79 ISA + EF_HEXAGON_ISA_V81 = 0x00000081, // Hexagon V81 ISA + EF_HEXAGON_ISA_V83 = 0x00000083, // Hexagon V83 ISA + EF_HEXAGON_ISA_V85 = 0x00000085, // Hexagon V85 ISA EF_HEXAGON_ISA = 0x000003ff, // Hexagon V.. ISA }; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index a98f6048b051c..8d18aade1a2be 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -125,7 +125,7 @@ static cl::opt<bool> static cl::opt<bool> EnableHexagonCabac ("mcabac", cl::desc("tbd"), cl::init(false)); -static StringRef DefaultArch = "hexagonv60"; +static constexpr StringRef DefaultArch = "hexagonv68"; static StringRef HexagonGetArchVariant() { if (MV5) diff --git a/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll b/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll index f0c30c301f446..52f29eefa5ce6 100644 --- a/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll +++ b/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll @@ -1,8 +1,7 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs --version 4 ; RUN: llc -mtriple hexagon-- -o - %s | FileCheck %s ; Reproducer for https://github.com/llvm/llvm-project/issues/89060 -; ; Problem was a bug in argument copy elison. Given that the %alloca is ; eliminated, the same frame index will be used for accessing %alloca and %a ; on the fixed stack. Care must be taken when setting up @@ -11,8 +10,15 @@ ; ir.alloca name), or make sure that we still detect that they alias each ; other if using different kinds of MemOperands to identify the same fixed ; stack entry. -; define i32 @f(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %q1, i32 %a, i32 %q2) { + %alloca = alloca i32 + store i32 %a, ptr %alloca ; Should be elided. + store i32 666, ptr %alloca + %x = sub i32 %q1, %q2 + %y = xor i32 %x, %a ; Results in a load of %a from fixed stack. + ; Using same frame index as elided %alloca. + ret i32 %y +} ; CHECK-LABEL: f: ; CHECK: .cfi_startproc ; CHECK-NEXT: // %bb.0: @@ -24,16 +30,9 @@ define i32 @f(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i ; CHECK-NEXT: r0 = sub(r1,r0) ; CHECK-NEXT: r2 = memw(r29+#32) ; CHECK-NEXT: memw(r29+#32) = ##666 -; CHECK-NEXT: } +; CHECK-EMPTY: +; CHECK-NEXT: } :mem_noshuf ; CHECK-NEXT: { ; CHECK-NEXT: r0 = xor(r0,r2) ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: } - %alloca = alloca i32 - store i32 %a, ptr %alloca ; Should be elided. - store i32 666, ptr %alloca - %x = sub i32 %q1, %q2 - %y = xor i32 %x, %a ; Results in a load of %a from fixed stack. - ; Using same frame index as elided %alloca. - ret i32 %y -} diff --git a/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll index ba09c3e2852df..0e0b64aac4f6d 100644 --- a/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll @@ -152,10 +152,8 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; CHECK-NEXT: r5:4 = memd_locked(r0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7:6 = sub(r5:4,r3:2) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4) +; CHECK-NEXT: r7:6 = sub(r5:4,r3:2) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r8 = mux(p0,r4,r6) diff --git a/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll index 6b6946d0dbb0e..8e673c1bb06ba 100644 --- a/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll @@ -156,12 +156,12 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; CHECK-NEXT: r5:4 = memd_locked(r0) ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4) ; CHECK-NEXT: r9:8 = add(r5:4,r7:6) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4) -; CHECK-NEXT: if (!p0.new) r8 = add(r1,#0) -; CHECK-NEXT: if (!p0.new) r9 = add(r1,#0) +; CHECK-NEXT: if (!p0) r8 = add(r1,#0) +; CHECK-NEXT: if (!p0) r9 = add(r1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: memd_locked(r0,p0) = r9:8 @@ -345,13 +345,13 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; CHECK-NEXT: r5:4 = memd_locked(r0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r13:12 = add(r5:4,r7:6) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p1 = cmp.gtu(r5:4,r3:2) ; CHECK-NEXT: p0 = cmp.eq(r5:4,r9:8) ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: r13:12 = add(r5:4,r7:6) +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: r1 = mux(p1,r2,r12) ; CHECK-NEXT: r14 = mux(p1,r3,r13) ; CHECK-NEXT: } diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict.mir b/llvm/test/CodeGen/Hexagon/bank-conflict.mir index 12d7838b8372d..f32c3868dcf09 100644 --- a/llvm/test/CodeGen/Hexagon/bank-conflict.mir +++ b/llvm/test/CodeGen/Hexagon/bank-conflict.mir @@ -8,9 +8,9 @@ # CHECK: = A2_tfr # CHECK: = L2_loadrigp -# CHECK: = L4_loadri_rr # CHECK: = S2_tstbit_i # CHECK: = L4_loadri_rr +# CHECK: = L4_loadri_rr --- | %s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] } diff --git a/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll b/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll index f99b448cc1a78..aa8766661a24a 100644 --- a/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll +++ b/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll @@ -12,10 +12,11 @@ ; The problem is that the load will execute before the store, clobbering the ; pair r17:16. ; -; Check that the store and the load are not in the same packet. + +; Validate that store executes before load. ; CHECK: memd{{.*}} = r17:16 -; CHECK: } ; CHECK: r17:16 = memd +; CHECK: } :mem_noshuf ; CHECK-LABEL: LBB0_1: target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll b/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll index e1b848c0d247b..23c919df05556 100644 --- a/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll @@ -8,12 +8,15 @@ define i64 @f0(ptr %a0, <8 x i8> %a1) #0 { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5:4 = combine(#0,#0) +; CHECK-NEXT: r1 = #0 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = r0 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: r5:4 = vsplatb(r1) +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: r1:0 = vmux(p0,r3:2,r5:4) ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -114,7 +117,10 @@ define void @f4(ptr %a0, i64 %a1) #0 { ; CHECK-LABEL: f4: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r5:4 = combine(#0,#0) +; CHECK-NEXT: r1 = #0 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r5:4 = vsplatb(r1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r3:2,r5:4) @@ -123,10 +129,10 @@ define void @f4(ptr %a0, i64 %a1) #0 { ; CHECK-NEXT: p0 = not(p0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r1 = p0 +; CHECK-NEXT: r2 = p0 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: memb(r0+#0) = r1 +; CHECK-NEXT: memb(r0+#0) = r2 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 @@ -173,64 +179,64 @@ define void @f6(ptr %a0, i16 %a1) #0 { ; CHECK-LABEL: f6: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r2 = extractu(r1,#8,#8) +; CHECK-NEXT: r2 = #255 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r3 = #255 +; CHECK-NEXT: r3 = extractu(r1,#8,#8) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: p1 = !bitsclr(r1,r3) +; CHECK-NEXT: p1 = !bitsclr(r1,r2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: p0 = cmp.eq(r2,#0) +; CHECK-NEXT: p0 = cmp.eq(r3,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (p0) r2 = #0 +; CHECK-NEXT: if (p0) r3 = #0 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r1 = mux(p1,#8,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r3 = mux(p1,#2,#0) +; CHECK-NEXT: r2 = mux(p1,#2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = setbit(r1,#2) +; CHECK-NEXT: if (!p0) r3 = #128 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r6 = setbit(r3,#0) +; CHECK-NEXT: r4 = mux(p0,#0,#32) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p0) r2 = #128 +; CHECK-NEXT: r5 = setbit(r1,#2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r4 = mux(p0,#0,#32) +; CHECK-NEXT: r6 = setbit(r2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: if (!p1) r5 = add(r1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p1) r6 = add(r3,#0) +; CHECK-NEXT: r1 = setbit(r3,#6) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r1 = setbit(r2,#6) +; CHECK-NEXT: if (!p1) r6 = add(r2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r3 = setbit(r4,#4) +; CHECK-NEXT: r2 = setbit(r4,#4) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = or(r6,r5) +; CHECK-NEXT: if (!p0) r4 = add(r2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p0) r2 = add(r1,#0) +; CHECK-NEXT: if (!p0) r3 = add(r1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p0) r4 = add(r3,#0) +; CHECK-NEXT: r2 = or(r6,r5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 |= or(r4,r2) +; CHECK-NEXT: r2 |= or(r4,r3) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: memb(r0+#0) = r5 +; CHECK-NEXT: memb(r0+#0) = r2 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/isel/logical.ll b/llvm/test/CodeGen/Hexagon/isel/logical.ll index 7f9c178c42416..669d01dcd6add 100644 --- a/llvm/test/CodeGen/Hexagon/isel/logical.ll +++ b/llvm/test/CodeGen/Hexagon/isel/logical.ll @@ -1399,10 +1399,10 @@ define <8 x i8> @f39(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f39: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1431,10 +1431,10 @@ define <8 x i8> @f40(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f40: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1463,10 +1463,10 @@ define <8 x i8> @f41(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f41: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1495,10 +1495,10 @@ define <8 x i8> @f42(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f42: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1528,10 +1528,10 @@ define <8 x i8> @f43(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f43: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1561,10 +1561,10 @@ define <8 x i8> @f44(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f44: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1598,10 +1598,10 @@ define <8 x i8> @f45(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f45: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1635,10 +1635,10 @@ define <8 x i8> @f46(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f46: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1672,10 +1672,10 @@ define <8 x i8> @f47(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f47: ; CHECK: // %bb.0: // %b0 ; CH... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/132499 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
