[llvm-branch-commits] [clang] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2 to alias of 512 bit options (#124511) (PR #125057)
https://github.com/phoebewang updated
https://github.com/llvm/llvm-project/pull/125057
>From f816bd39f6986825e338198fce8747939ab1c882 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Thu, 30 Jan 2025 21:13:49 +0800
Subject: [PATCH] [X86][AVX10] Disable m[no-]avx10.1 and switch m[no-]avx10.2
to alias of 512 bit options (#124511)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Per the feedback we got, we’d like to switch m[no-]avx10.2 to alias of
512 bit options and disable m[no-]avx10.1 due to they were alias of 256
bit options.
We also change -mno-avx10.[1,2]-512 to alias of 256 bit options to
disable both 256 and 512 instructions.
---
clang/docs/ReleaseNotes.rst | 4
clang/include/clang/Driver/Options.td | 12 +---
clang/lib/Driver/ToolChains/Arch/X86.cpp | 13 -
clang/test/Driver/x86-target-features.c | 16 ++--
clang/test/Preprocessor/x86_target_features.c | 3 +--
5 files changed, 28 insertions(+), 20 deletions(-)
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index d8a94703bd9c57..c36a84c2b8362b 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1159,6 +1159,10 @@ X86 Support
- Support ISA of ``MOVRS``.
- Supported ``-march/tune=diamondrapids``
+- Disable ``-m[no-]avx10.1`` and switch ``-m[no-]avx10.2`` to alias of 512 bit
+ options.
+- Change ``-mno-avx10.1-512`` to alias of ``-mno-avx10.1-256`` to disable both
+ 256 and 512 bit instructions.
Arm and AArch64 Support
^^^
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 1af633e59d0bba..a2b47b943ef90d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6441,15 +6441,13 @@ def mno_avx : Flag<["-"], "mno-avx">,
Group;
def mavx10_1_256 : Flag<["-"], "mavx10.1-256">,
Group;
def mno_avx10_1_256 : Flag<["-"], "mno-avx10.1-256">,
Group;
def mavx10_1_512 : Flag<["-"], "mavx10.1-512">,
Group;
-def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">,
Group;
-def mavx10_1 : Flag<["-"], "mavx10.1">, Alias;
-def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Alias;
+def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">, Alias;
+def mavx10_1 : Flag<["-"], "mavx10.1">, Flags<[Unsupported]>;
+def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Flags<[Unsupported]>;
def mavx10_2_256 : Flag<["-"], "mavx10.2-256">,
Group;
-def mno_avx10_2_256 : Flag<["-"], "mno-avx10.2-256">,
Group;
def mavx10_2_512 : Flag<["-"], "mavx10.2-512">,
Group;
-def mno_avx10_2_512 : Flag<["-"], "mno-avx10.2-512">,
Group;
-def mavx10_2 : Flag<["-"], "mavx10.2">, Alias;
-def mno_avx10_2 : Flag<["-"], "mno-avx10.2">, Alias;
+def mavx10_2 : Flag<["-"], "mavx10.2">, Alias;
+def mno_avx10_2 : Flag<["-"], "mno-avx10.2">,
Group;
def mavx2 : Flag<["-"], "mavx2">, Group;
def mno_avx2 : Flag<["-"], "mno-avx2">, Group;
def mavx512f : Flag<["-"], "mavx512f">, Group;
diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp
b/clang/lib/Driver/ToolChains/Arch/X86.cpp
index b2109e11038fe8..47c2c3e23f9fd9 100644
--- a/clang/lib/Driver/ToolChains/Arch/X86.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp
@@ -237,15 +237,18 @@ void x86::getX86TargetFeatures(const Driver &D, const
llvm::Triple &Triple,
bool IsNegative = Name.consume_front("no-");
-#ifndef NDEBUG
-assert(Name.starts_with("avx10.") && "Invalid AVX10 feature name.");
StringRef Version, Width;
std::tie(Version, Width) = Name.substr(6).split('-');
+assert(Name.starts_with("avx10.") && "Invalid AVX10 feature name.");
assert((Version == "1" || Version == "2") && "Invalid AVX10 feature
name.");
-assert((Width == "256" || Width == "512") && "Invalid AVX10 feature
name.");
-#endif
-Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
+if (Width == "") {
+ assert(IsNegative && "Only negative options can omit width.");
+ Features.push_back(Args.MakeArgString("-" + Name + "-256"));
+} else {
+ assert((Width == "256" || Width == "512") && "Invalid vector length.");
+ Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name));
+}
}
// Now add any that the user explicitly requested on the command line,
diff --git a/clang/test/Driver/x86-target-features.c
b/clang/test/Driver/x86-target-features.c
index 339f593dc760a8..18361251dcebc5 100644
--- a/clang/test/Driver/x86-target-features.c
+++ b/clang/test/Driver/x86-target-features.c
@@ -395,7 +395,8 @@
// EVEX512: "-target-feature" "+evex512"
// NO-EVEX512: "-target-feature" "-evex512"
-// RUN: %clang --target=i386 -mavx10.1 %s -### -o %t.o 2>&1 | FileCheck
-check-prefix=AVX10_1_256 %s
+// RUN: not %clang --target=i386 -march=i386 -mavx10.1 %s -### -o %t.o 2>&1 |
FileCheck -check-prefix=UNSUPPORT-AVX10 %s
+// RUN: not %clang --target=i386 -march=i386 -mno-avx10.1 %s -### -o %t.o 2>&1
| FileChec
[llvm-branch-commits] [clang] release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (PR #125368)
tstellar wrote: Sorry, I didn't realize a review was requested on this. I usually merge release notes patches right away. I'll keep this in -rc1 and any follow up changes can be made for -rc2. https://github.com/llvm/llvm-project/pull/125368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/125150 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
https://github.com/koachan updated https://github.com/llvm/llvm-project/pull/125150 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
return false;
}
+bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
+ SmallVectorImpl &Instructions) {
+ MCOperand MCRegOp = Inst.getOperand(0);
+ MCOperand MCValOp = Inst.getOperand(1);
+ assert(MCRegOp.isReg());
+ assert(MCValOp.isImm() || MCValOp.isExpr());
+
+ // the imm operand can be either an expression or an immediate.
+ bool IsImm = Inst.getOperand(1).isImm();
+ int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
+ const MCExpr *ValExpr = IsImm ? MCConstantExpr::create(ImmValue,
getContext())
+: MCValOp.getExpr();
+
+ bool IsSmallImm = IsImm && isInt<13>(ImmValue);
koachan wrote:
[-4096, 4095] / [-(212), 212-1] is signed int13.
But otherwise, I've changed the tests to use the boundary values for coverage.
https://github.com/llvm/llvm-project/pull/125150
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [llvm] Introduce type id operand bundle (PR #87573)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87573
>From a8a5848885e12c771f12cfa33b4dbc6a0272e925 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:04 -0700
Subject: [PATCH 1/5] Update clang/lib/CodeGen/CodeGenModule.cpp
Cleaner if checks.
Co-authored-by: Matt Arsenault
---
clang/lib/CodeGen/CodeGenModule.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index e19bbee996f582..ff1586d2fa8abe 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2711,7 +2711,7 @@ void
CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
void CodeGenModule::CreateFunctionTypeMetadataForIcall(const QualType &QT,
llvm::CallBase *CB) {
// Only if needed for call graph section and only for indirect calls.
- if (!(CodeGenOpts.CallGraphSection && CB && CB->isIndirectCall()))
+ if (!CodeGenOpts.CallGraphSection || !CB || !CB->isIndirectCall())
return;
auto *MD = CreateMetadataIdentifierGeneralized(QT);
>From 019b2ca5e1c263183ed114e0b967b4e77b4a17a8 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:31 -0700
Subject: [PATCH 2/5] Update clang/lib/CodeGen/CodeGenModule.cpp
Update the comments as suggested.
Co-authored-by: Matt Arsenault
---
clang/lib/CodeGen/CodeGenModule.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index ff1586d2fa8abe..5635a87d2358a7 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2680,9 +2680,9 @@ void
CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
bool EmittedMDIdGeneralized = false;
if (CodeGenOpts.CallGraphSection &&
(!F->hasLocalLinkage() ||
- F->getFunction().hasAddressTaken(nullptr, /* IgnoreCallbackUses */ true,
-/* IgnoreAssumeLikeCalls */ true,
-/* IgnoreLLVMUsed */ false))) {
+ F->getFunction().hasAddressTaken(nullptr, /*IgnoreCallbackUses=*/ true,
+/*IgnoreAssumeLikeCalls=*/ true,
+/*IgnoreLLVMUsed=*/ false))) {
F->addTypeMetadata(0, CreateMetadataIdentifierGeneralized(FD->getType()));
EmittedMDIdGeneralized = true;
}
>From 99242900c51778abd4b7e7f4361b09202b7abcda Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 29 Apr 2024 11:53:40 -0700
Subject: [PATCH 3/5] dyn_cast to isa
Created using spr 1.3.6-beta.1
---
clang/lib/CodeGen/CGCall.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 526a63b24ff834..45033ced1d8344 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -5713,8 +5713,8 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
if (callOrInvoke && *callOrInvoke && (*callOrInvoke)->isIndirectCall()) {
if (const FunctionDecl *FD = dyn_cast_or_null(TargetDecl))
{
// Type id metadata is set only for C/C++ contexts.
-if (dyn_cast(FD) || dyn_cast(FD) ||
-dyn_cast(FD)) {
+if (isa(FD) || isa(FD) ||
+isa(FD)) {
CGM.CreateFunctionTypeMetadataForIcall(FD->getType(), *callOrInvoke);
}
}
>From 24882b15939b781bcf28d87fdf4f6e8834b6cfde Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Tue, 10 Dec 2024 14:54:27 -0800
Subject: [PATCH 4/5] Address review comments. Break llvm and clang patches.
Created using spr 1.3.6-beta.1
---
llvm/lib/IR/Verifier.cpp | 7 +++
llvm/test/Verifier/operand-bundles.ll | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 0ad7ba555bfade..b72672e7b8e561 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3707,10 +3707,9 @@ void Verifier::visitCallBase(CallBase &Call) {
if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID())
visitIntrinsicCall(ID, Call);
- // Verify that a callsite has at most one "deopt", at most one "funclet", at
- // most one "gc-transition", at most one "cfguardtarget", at most one "type",
- // at most one "preallocated" operand bundle, and at most one "ptrauth"
- // operand bundle.
+ // Verify that a callsite has at most one operand bundle for each of the
+ // following: "deopt", "funclet", "gc-transition", "cfguardtarget", "type",
+ // "preallocated", and "ptrauth".
bool FoundDeoptBundle = false, FoundFuncletBundle = false,
FoundGCTransitionBundle = false, FoundCFGuardTargetBundle = false,
FoundPreallocatedBundle = false, FoundGCLiveBundle = false,
diff --git a/llvm/test/Verifier/operand-bundles.ll
b/llvm/t
[llvm-branch-commits] [clang] [llvm] [llvm] Introduce type id operand bundle (PR #87573)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87573
>From a8a5848885e12c771f12cfa33b4dbc6a0272e925 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:04 -0700
Subject: [PATCH 1/5] Update clang/lib/CodeGen/CodeGenModule.cpp
Cleaner if checks.
Co-authored-by: Matt Arsenault
---
clang/lib/CodeGen/CodeGenModule.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index e19bbee996f582..ff1586d2fa8abe 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2711,7 +2711,7 @@ void
CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
void CodeGenModule::CreateFunctionTypeMetadataForIcall(const QualType &QT,
llvm::CallBase *CB) {
// Only if needed for call graph section and only for indirect calls.
- if (!(CodeGenOpts.CallGraphSection && CB && CB->isIndirectCall()))
+ if (!CodeGenOpts.CallGraphSection || !CB || !CB->isIndirectCall())
return;
auto *MD = CreateMetadataIdentifierGeneralized(QT);
>From 019b2ca5e1c263183ed114e0b967b4e77b4a17a8 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:31 -0700
Subject: [PATCH 2/5] Update clang/lib/CodeGen/CodeGenModule.cpp
Update the comments as suggested.
Co-authored-by: Matt Arsenault
---
clang/lib/CodeGen/CodeGenModule.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index ff1586d2fa8abe..5635a87d2358a7 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2680,9 +2680,9 @@ void
CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
bool EmittedMDIdGeneralized = false;
if (CodeGenOpts.CallGraphSection &&
(!F->hasLocalLinkage() ||
- F->getFunction().hasAddressTaken(nullptr, /* IgnoreCallbackUses */ true,
-/* IgnoreAssumeLikeCalls */ true,
-/* IgnoreLLVMUsed */ false))) {
+ F->getFunction().hasAddressTaken(nullptr, /*IgnoreCallbackUses=*/ true,
+/*IgnoreAssumeLikeCalls=*/ true,
+/*IgnoreLLVMUsed=*/ false))) {
F->addTypeMetadata(0, CreateMetadataIdentifierGeneralized(FD->getType()));
EmittedMDIdGeneralized = true;
}
>From 99242900c51778abd4b7e7f4361b09202b7abcda Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 29 Apr 2024 11:53:40 -0700
Subject: [PATCH 3/5] dyn_cast to isa
Created using spr 1.3.6-beta.1
---
clang/lib/CodeGen/CGCall.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 526a63b24ff834..45033ced1d8344 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -5713,8 +5713,8 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
if (callOrInvoke && *callOrInvoke && (*callOrInvoke)->isIndirectCall()) {
if (const FunctionDecl *FD = dyn_cast_or_null(TargetDecl))
{
// Type id metadata is set only for C/C++ contexts.
-if (dyn_cast(FD) || dyn_cast(FD) ||
-dyn_cast(FD)) {
+if (isa(FD) || isa(FD) ||
+isa(FD)) {
CGM.CreateFunctionTypeMetadataForIcall(FD->getType(), *callOrInvoke);
}
}
>From 24882b15939b781bcf28d87fdf4f6e8834b6cfde Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Tue, 10 Dec 2024 14:54:27 -0800
Subject: [PATCH 4/5] Address review comments. Break llvm and clang patches.
Created using spr 1.3.6-beta.1
---
llvm/lib/IR/Verifier.cpp | 7 +++
llvm/test/Verifier/operand-bundles.ll | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 0ad7ba555bfade..b72672e7b8e561 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3707,10 +3707,9 @@ void Verifier::visitCallBase(CallBase &Call) {
if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID())
visitIntrinsicCall(ID, Call);
- // Verify that a callsite has at most one "deopt", at most one "funclet", at
- // most one "gc-transition", at most one "cfguardtarget", at most one "type",
- // at most one "preallocated" operand bundle, and at most one "ptrauth"
- // operand bundle.
+ // Verify that a callsite has at most one operand bundle for each of the
+ // following: "deopt", "funclet", "gc-transition", "cfguardtarget", "type",
+ // "preallocated", and "ptrauth".
bool FoundDeoptBundle = false, FoundFuncletBundle = false,
FoundGCTransitionBundle = false, FoundCFGuardTargetBundle = false,
FoundPreallocatedBundle = false, FoundGCLiveBundle = false,
diff --git a/llvm/test/Verifier/operand-bundles.ll
b/llvm/t
[llvm-branch-commits] [llvm] Add option to emit call graph section (PR #87572)
https://github.com/Prabhuk updated https://github.com/llvm/llvm-project/pull/87572 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Add option to emit call graph section (PR #87572)
https://github.com/Prabhuk updated https://github.com/llvm/llvm-project/pull/87572 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [llvm] Extract and propagate indirect call type id (PR #87575)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH] Fixed the tests and addressed most of the review comments.
Created using spr 1.3.6-beta.1
---
llvm/include/llvm/CodeGen/MachineFunction.h | 15 +++--
.../CodeGen/AArch64/call-site-info-typeid.ll | 28 +++--
.../test/CodeGen/ARM/call-site-info-typeid.ll | 28 +++--
.../CodeGen/MIR/X86/call-site-info-typeid.ll | 58 ---
.../CodeGen/MIR/X86/call-site-info-typeid.mir | 13 ++---
.../CodeGen/Mips/call-site-info-typeid.ll | 28 +++--
.../test/CodeGen/X86/call-site-info-typeid.ll | 28 +++--
7 files changed, 71 insertions(+), 127 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index bb0b87a3a04a37b..44633df38a6516e 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -493,7 +493,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
/// Callee type id.
ConstantInt *TypeId = nullptr;
-CallSiteInfo() {}
+CallSiteInfo() = default;
/// Extracts the numeric type id from the CallBase's type operand bundle,
/// and sets TypeId. This is used as type id for the indirect call in the
@@ -503,12 +503,11 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
if (!CB.isIndirectCall())
return;
- auto Opt = CB.getOperandBundle(LLVMContext::OB_type);
- if (!Opt.has_value()) {
-errs() << "warning: cannot find indirect call type operand bundle for
"
- "call graph section\n";
+ std::optional Opt =
+ CB.getOperandBundle(LLVMContext::OB_type);
+ // Return if the operand bundle for call graph section cannot be found.
+ if (!Opt.has_value())
return;
- }
// Get generalized type id string
auto OB = Opt.value();
@@ -520,9 +519,9 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
"invalid type identifier");
// Compute numeric type id from generalized type id string
- uint64_t TypeIdVal = llvm::MD5Hash(TypeIdStr->getString());
+ uint64_t TypeIdVal = MD5Hash(TypeIdStr->getString());
IntegerType *Int64Ty = Type::getInt64Ty(CB.getContext());
- TypeId = llvm::ConstantInt::get(Int64Ty, TypeIdVal, /*IsSigned=*/false);
+ TypeId = ConstantInt::get(Int64Ty, TypeIdVal, /*IsSigned=*/false);
}
};
diff --git a/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
b/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
index f0a6b44755c5c89..f3b98c2c7a395d8 100644
--- a/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
+++ b/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
@@ -1,14 +1,9 @@
-; Tests that call site type ids can be extracted and set from type operand
-; bundles.
+;; Tests that call site type ids can be extracted and set from type operand
+;; bundles.
-; Verify the exact typeId value to ensure it is not garbage but the value
-; computed as the type id from the type operand bundle.
-; RUN: llc --call-graph-section -mtriple aarch64-linux-gnu %s
-stop-before=finalize-isel -o - | FileCheck %s
-
-; ModuleID = 'test.c'
-source_filename = "test.c"
-target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-unknown-linux-gnu"
+;; Verify the exact typeId value to ensure it is not garbage but the value
+;; computed as the type id from the type operand bundle.
+; RUN: llc --call-graph-section -mtriple aarch64-linux-gnu < %s
-stop-before=finalize-isel -o - | FileCheck %s
define dso_local void @foo(i8 signext %a) !type !3 {
entry:
@@ -19,10 +14,10 @@ entry:
define dso_local i32 @main() !type !4 {
entry:
%retval = alloca i32, align 4
- %fp = alloca void (i8)*, align 8
- store i32 0, i32* %retval, align 4
- store void (i8)* @foo, void (i8)** %fp, align 8
- %0 = load void (i8)*, void (i8)** %fp, align 8
+ %fp = alloca ptr, align 8
+ store i32 0, ptr %retval, align 4
+ store ptr @foo, ptr %fp, align 8
+ %0 = load ptr, ptr %fp, align 8
; CHECK: callSites:
; CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], typeId:
; CHECK-NEXT: 7854600665770582568 }
@@ -30,10 +25,5 @@ entry:
ret i32 0
}
-!llvm.module.flags = !{!0, !1, !2}
-
-!0 = !{i32 1, !"wchar_size", i32 4}
-!1 = !{i32 7, !"uwtable", i32 1}
-!2 = !{i32 7, !"frame-pointer", i32 2}
!3 = !{i64 0, !"_ZTSFvcE.generalized"}
!4 = !{i64 0, !"_ZTSFiE.generalized"}
diff --git a/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
b/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
index ec7f8a425051b8b..9feeef9a564cc4f 100644
--- a/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
+++ b/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
@@ -1,14 +1,9 @@
-; Tests that call site type ids can be extracted and set from type operand
-; bundles.
+;; Tests
[llvm-branch-commits] [llvm] [llvm] Extend CallSiteInfo with TypeId (PR #87574)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
.../CodeGen/MIR/X86/call-site-info-typeid.mir | 21 ++-
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
index 5ab797bfcc18f6..a99ee50a608fbc 100644
--- a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
+++ b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
@@ -8,11 +8,6 @@
# CHECK-NEXT: 123456789 }
--- |
- ; ModuleID = 'test.ll'
- source_filename = "test.ll"
- target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
- target triple = "x86_64-unknown-linux-gnu"
-
define dso_local void @foo(i8 signext %a) {
entry:
ret void
@@ -21,10 +16,10 @@
define dso_local i32 @main() {
entry:
%retval = alloca i32, align 4
-%fp = alloca void (i8)*, align 8
-store i32 0, i32* %retval, align 4
-store void (i8)* @foo, void (i8)** %fp, align 8
-%0 = load void (i8)*, void (i8)** %fp, align 8
+%fp = alloca ptr, align 8
+store i32 0, ptr %retval, align 4
+store ptr @foo, ptr %fp, align 8
+%0 = load ptr, ptr %fp, align 8
call void %0(i8 signext 97)
ret i32 0
}
@@ -42,12 +37,8 @@ body: |
name:main
tracksRegLiveness: true
stack:
- - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
- - { id: 1, name: fp, type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+ - { id: 0, name: retval, size: 4, alignment: 4 }
+ - { id: 1, name: fp, size: 8, alignment: 8 }
callSites:
- { bb: 0, offset: 6, fwdArgRegs: [], typeId:
123456789 }
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[llvm-branch-commits] [llvm] [llvm] Extend CallSiteInfo with TypeId (PR #87574)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
.../CodeGen/MIR/X86/call-site-info-typeid.mir | 21 ++-
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
index 5ab797bfcc18f6..a99ee50a608fbc 100644
--- a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
+++ b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
@@ -8,11 +8,6 @@
# CHECK-NEXT: 123456789 }
--- |
- ; ModuleID = 'test.ll'
- source_filename = "test.ll"
- target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
- target triple = "x86_64-unknown-linux-gnu"
-
define dso_local void @foo(i8 signext %a) {
entry:
ret void
@@ -21,10 +16,10 @@
define dso_local i32 @main() {
entry:
%retval = alloca i32, align 4
-%fp = alloca void (i8)*, align 8
-store i32 0, i32* %retval, align 4
-store void (i8)* @foo, void (i8)** %fp, align 8
-%0 = load void (i8)*, void (i8)** %fp, align 8
+%fp = alloca ptr, align 8
+store i32 0, ptr %retval, align 4
+store ptr @foo, ptr %fp, align 8
+%0 = load ptr, ptr %fp, align 8
call void %0(i8 signext 97)
ret i32 0
}
@@ -42,12 +37,8 @@ body: |
name:main
tracksRegLiveness: true
stack:
- - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
- - { id: 1, name: fp, type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+ - { id: 0, name: retval, size: 4, alignment: 4 }
+ - { id: 1, name: fp, size: 8, alignment: 8 }
callSites:
- { bb: 0, offset: 6, fwdArgRegs: [], typeId:
123456789 }
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[llvm-branch-commits] [llvm][AsmPrinter] Emit call graph section (PR #87576)
https://github.com/Prabhuk updated https://github.com/llvm/llvm-project/pull/87576 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][AsmPrinter] Emit call graph section (PR #87576)
https://github.com/Prabhuk updated https://github.com/llvm/llvm-project/pull/87576 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Add option to emit call graph section (PR #87572)
Prabhuk wrote: > I think this is mostly fine, but the patch currently only adds the LLVM flag > without doing anything. Perhaps this should be higher up in the stack(or I’m > looking at them in the wrong order?)? > > You may want to consider adding a test here to check that the option works. > You could also precommit the tests you’re adding later in the stack, but > since it’s a new feature I don’t think there’s much value in that. Does merging this PR with #87574 (which is the next one to be landed after this one) effectively address your concerns here? https://github.com/llvm/llvm-project/pull/87572 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm][AsmPrinter] Emit call graph section (PR #87576)
@@ -0,0 +1,73 @@ +; Tests that we store the type identifiers in .callgraph section of the binary. + +; RUN: llc --call-graph-section -filetype=obj -o - < %s | \ +; RUN: llvm-readelf -x .callgraph - | FileCheck %s + +target triple = "x86_64-unknown-linux-gnu" MaskRay wrote: Should be placed in X86 so that REQUIRES: is not needed https://github.com/llvm/llvm-project/pull/87576 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
return false;
}
+bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
+ SmallVectorImpl &Instructions) {
+ MCOperand MCRegOp = Inst.getOperand(0);
+ MCOperand MCValOp = Inst.getOperand(1);
+ assert(MCRegOp.isReg());
+ assert(MCValOp.isImm() || MCValOp.isExpr());
+
+ // the imm operand can be either an expression or an immediate.
+ bool IsImm = Inst.getOperand(1).isImm();
+ int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
+ const MCExpr *ValExpr = IsImm ? MCConstantExpr::create(ImmValue,
getContext())
+: MCValOp.getExpr();
+
+ bool IsSmallImm = IsImm && isInt<13>(ImmValue);
+ bool NoLowBitsImm = IsImm && ((ImmValue & 0x3FF) == 0);
+
+ MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
+
+ if (!isInt<32>(ImmValue)) {
+return Error(IDLoc,
+ "set: argument must be between -2147483648 and 2147483647");
+ }
+
+ // Very small immediates can be expressed without emitting a sethi.
+ if (!IsSmallImm) {
+// sethi %hi(val), rd
+Instructions.push_back(
+MCInstBuilder(SP::SETHIi)
+.addReg(MCRegOp.getReg())
+.addExpr(adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr)));
+
+PrevReg = MCRegOp;
+ }
+
+ // If the immediate has the lower bits set or is small, we need to emit an
or.
+ if (!NoLowBitsImm || IsSmallImm) {
+const MCExpr *Expr =
+IsSmallImm ? ValExpr
+ : adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
+
+// orrd, %lo(val), rd
s-barannikov wrote:
(very minor nit) extra spaces here and in the snippet below
https://github.com/llvm/llvm-project/pull/125150
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[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
return false;
}
+bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
+ SmallVectorImpl &Instructions) {
+ MCOperand MCRegOp = Inst.getOperand(0);
+ MCOperand MCValOp = Inst.getOperand(1);
+ assert(MCRegOp.isReg());
+ assert(MCValOp.isImm() || MCValOp.isExpr());
+
+ // the imm operand can be either an expression or an immediate.
s-barannikov wrote:
```suggestion
// The imm operand can be either an expression or an immediate.
```
https://github.com/llvm/llvm-project/pull/125150
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[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
https://github.com/s-barannikov approved this pull request. https://github.com/llvm/llvm-project/pull/125150 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (llvmbot)
Changes
Backport 9f1c825fb62319b94ac9604f733afd59e9eb461b
Requested by: @davemgreen
---
Full diff: https://github.com/llvm/llvm-project/pull/125386.diff
11 Files Affected:
- (modified) clang/include/clang/Basic/TargetInfo.h (+2-1)
- (modified) clang/lib/AST/ASTContext.cpp (+2-1)
- (modified) clang/lib/AST/ItaniumMangle.cpp (+1-1)
- (modified) clang/lib/Basic/Targets/AArch64.cpp (+3-2)
- (modified) clang/lib/Basic/Targets/AArch64.h (+2-1)
- (modified) clang/lib/Basic/Targets/RISCV.cpp (+3-2)
- (modified) clang/lib/Basic/Targets/RISCV.h (+2-1)
- (modified) clang/lib/CodeGen/CodeGenFunction.cpp (+9-8)
- (modified) clang/lib/CodeGen/Targets/RISCV.cpp (+2-2)
- (modified) clang/lib/Sema/SemaType.cpp (+2-1)
- (modified) clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
(+2-2)
``diff
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 43c09cf1f973e3..d762144478b489 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1023,7 +1023,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Returns target-specific min and max values VScale_Range.
virtual std::optional>
- getVScaleRange(const LangOptions &LangOpts) const {
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
return std::nullopt;
}
/// The __builtin_clz* and __builtin_ctz* built-in
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index cd1bcb3b9a063d..e58091ce95f625 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -10363,7 +10363,8 @@ bool ASTContext::areLaxCompatibleSveTypes(QualType
FirstType,
/// getRVVTypeSize - Return RVV vector register size.
static uint64_t getRVVTypeSize(ASTContext &Context, const BuiltinType *Ty) {
assert(Ty->isRVVVLSBuiltinType() && "Invalid RVV Type");
- auto VScale = Context.getTargetInfo().getVScaleRange(Context.getLangOpts());
+ auto VScale =
+ Context.getTargetInfo().getVScaleRange(Context.getLangOpts(), false);
if (!VScale)
return 0;
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 49089c0ea3c8ac..f84ccefd34cacb 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4198,7 +4198,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
// Apend the LMUL suffix.
auto VScale = getASTContext().getTargetInfo().getVScaleRange(
- getASTContext().getLangOpts());
+ getASTContext().getLangOpts(), false);
unsigned VLen = VScale->first * llvm::RISCV::RVVBitsPerBlock;
if (T->getVectorKind() == VectorKind::RVVFixedLengthData) {
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 0b899137bbb5c7..57c9849ef2a728 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -703,12 +703,13 @@ ArrayRef
AArch64TargetInfo::getTargetBuiltins() const {
}
std::optional>
-AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
if (LangOpts.VScaleMin || LangOpts.VScaleMax)
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || (IsArmStreamingFunction && hasFeature("sme")))
return std::pair(1, 16);
return std::nullopt;
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 600940f5e4e23c..b75d2a9dc8ecad 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -184,7 +184,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
ArrayRef getTargetBuiltins() const override;
std::optional>
- getVScaleRange(const LangOptions &LangOpts) const override;
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const override;
bool doesFeatureAffectCodeGen(StringRef Name) const override;
bool validateCpuSupports(StringRef FeatureStr) const override;
bool hasFeature(StringRef Feature) const override;
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 8167d7603b0e14..61b8ae9d098abc 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -222,7 +222,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
// Currently we support the v1.0 RISC-V V intrinsics.
Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(1, 0)));
- auto VScale = getVScaleRange(Opts);
+ auto VScale = getVScaleRange(Opts, false);
if (VScale && VScale->first && VScale->first == VScale->second)
Builder.defineMacro("__riscv_v_fixed_vle
[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: None (llvmbot)
Changes
Backport 9f1c825fb62319b94ac9604f733afd59e9eb461b
Requested by: @davemgreen
---
Full diff: https://github.com/llvm/llvm-project/pull/125386.diff
11 Files Affected:
- (modified) clang/include/clang/Basic/TargetInfo.h (+2-1)
- (modified) clang/lib/AST/ASTContext.cpp (+2-1)
- (modified) clang/lib/AST/ItaniumMangle.cpp (+1-1)
- (modified) clang/lib/Basic/Targets/AArch64.cpp (+3-2)
- (modified) clang/lib/Basic/Targets/AArch64.h (+2-1)
- (modified) clang/lib/Basic/Targets/RISCV.cpp (+3-2)
- (modified) clang/lib/Basic/Targets/RISCV.h (+2-1)
- (modified) clang/lib/CodeGen/CodeGenFunction.cpp (+9-8)
- (modified) clang/lib/CodeGen/Targets/RISCV.cpp (+2-2)
- (modified) clang/lib/Sema/SemaType.cpp (+2-1)
- (modified) clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
(+2-2)
``diff
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 43c09cf1f973e3..d762144478b489 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1023,7 +1023,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Returns target-specific min and max values VScale_Range.
virtual std::optional>
- getVScaleRange(const LangOptions &LangOpts) const {
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
return std::nullopt;
}
/// The __builtin_clz* and __builtin_ctz* built-in
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index cd1bcb3b9a063d..e58091ce95f625 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -10363,7 +10363,8 @@ bool ASTContext::areLaxCompatibleSveTypes(QualType
FirstType,
/// getRVVTypeSize - Return RVV vector register size.
static uint64_t getRVVTypeSize(ASTContext &Context, const BuiltinType *Ty) {
assert(Ty->isRVVVLSBuiltinType() && "Invalid RVV Type");
- auto VScale = Context.getTargetInfo().getVScaleRange(Context.getLangOpts());
+ auto VScale =
+ Context.getTargetInfo().getVScaleRange(Context.getLangOpts(), false);
if (!VScale)
return 0;
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 49089c0ea3c8ac..f84ccefd34cacb 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4198,7 +4198,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
// Apend the LMUL suffix.
auto VScale = getASTContext().getTargetInfo().getVScaleRange(
- getASTContext().getLangOpts());
+ getASTContext().getLangOpts(), false);
unsigned VLen = VScale->first * llvm::RISCV::RVVBitsPerBlock;
if (T->getVectorKind() == VectorKind::RVVFixedLengthData) {
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 0b899137bbb5c7..57c9849ef2a728 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -703,12 +703,13 @@ ArrayRef
AArch64TargetInfo::getTargetBuiltins() const {
}
std::optional>
-AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
if (LangOpts.VScaleMin || LangOpts.VScaleMax)
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || (IsArmStreamingFunction && hasFeature("sme")))
return std::pair(1, 16);
return std::nullopt;
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 600940f5e4e23c..b75d2a9dc8ecad 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -184,7 +184,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
ArrayRef getTargetBuiltins() const override;
std::optional>
- getVScaleRange(const LangOptions &LangOpts) const override;
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const override;
bool doesFeatureAffectCodeGen(StringRef Name) const override;
bool validateCpuSupports(StringRef FeatureStr) const override;
bool hasFeature(StringRef Feature) const override;
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 8167d7603b0e14..61b8ae9d098abc 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -222,7 +222,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
// Currently we support the v1.0 RISC-V V intrinsics.
Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(1, 0)));
- auto VScale = getVScaleRange(Opts);
+ auto VScale = getVScaleRange(Opts, false);
if (VScale && VScale->first && VScale->first == VScale->second)
Builder.defineMacro("__riscv_v_
[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/125386
Backport 9f1c825fb62319b94ac9604f733afd59e9eb461b
Requested by: @davemgreen
>From e615b937bca300c58e3db99c0302e3d7195e70ce Mon Sep 17 00:00:00 2001
From: David Green
Date: Fri, 31 Jan 2025 07:57:43 +
Subject: [PATCH] [AArch64] Enable vscale_range with +sme (#124466)
If we have +sme but not +sve, we would not set vscale_range on
functions. It should be valid to apply it with the same range with just
+sme, which can help mitigate some performance regressions in cases such
as scalable vector bitcasts (https://godbolt.org/z/exhe4jd8d).
(cherry picked from commit 9f1c825fb62319b94ac9604f733afd59e9eb461b)
---
clang/include/clang/Basic/TargetInfo.h | 3 ++-
clang/lib/AST/ASTContext.cpp| 3 ++-
clang/lib/AST/ItaniumMangle.cpp | 2 +-
clang/lib/Basic/Targets/AArch64.cpp | 5 +++--
clang/lib/Basic/Targets/AArch64.h | 3 ++-
clang/lib/Basic/Targets/RISCV.cpp | 5 +++--
clang/lib/Basic/Targets/RISCV.h | 3 ++-
clang/lib/CodeGen/CodeGenFunction.cpp | 17 +
clang/lib/CodeGen/Targets/RISCV.cpp | 4 ++--
clang/lib/Sema/SemaType.cpp | 3 ++-
.../sme-intrinsics/aarch64-sme-attrs.cpp| 4 ++--
11 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 43c09cf1f973e3c..d762144478b489d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1023,7 +1023,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Returns target-specific min and max values VScale_Range.
virtual std::optional>
- getVScaleRange(const LangOptions &LangOpts) const {
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
return std::nullopt;
}
/// The __builtin_clz* and __builtin_ctz* built-in
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index cd1bcb3b9a063d8..e58091ce95f6258 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -10363,7 +10363,8 @@ bool ASTContext::areLaxCompatibleSveTypes(QualType
FirstType,
/// getRVVTypeSize - Return RVV vector register size.
static uint64_t getRVVTypeSize(ASTContext &Context, const BuiltinType *Ty) {
assert(Ty->isRVVVLSBuiltinType() && "Invalid RVV Type");
- auto VScale = Context.getTargetInfo().getVScaleRange(Context.getLangOpts());
+ auto VScale =
+ Context.getTargetInfo().getVScaleRange(Context.getLangOpts(), false);
if (!VScale)
return 0;
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 49089c0ea3c8ac1..f84ccefd34cacbe 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4198,7 +4198,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
// Apend the LMUL suffix.
auto VScale = getASTContext().getTargetInfo().getVScaleRange(
- getASTContext().getLangOpts());
+ getASTContext().getLangOpts(), false);
unsigned VLen = VScale->first * llvm::RISCV::RVVBitsPerBlock;
if (T->getVectorKind() == VectorKind::RVVFixedLengthData) {
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 0b899137bbb5c74..57c9849ef2a7287 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -703,12 +703,13 @@ ArrayRef
AArch64TargetInfo::getTargetBuiltins() const {
}
std::optional>
-AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
if (LangOpts.VScaleMin || LangOpts.VScaleMax)
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || (IsArmStreamingFunction && hasFeature("sme")))
return std::pair(1, 16);
return std::nullopt;
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 600940f5e4e23c1..b75d2a9dc8ecadc 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -184,7 +184,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
ArrayRef getTargetBuiltins() const override;
std::optional>
- getVScaleRange(const LangOptions &LangOpts) const override;
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const override;
bool doesFeatureAffectCodeGen(StringRef Name) const override;
bool validateCpuSupports(StringRef FeatureStr) const override;
bool hasFeature(StringRef Feature) const override;
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 8167d7603b
[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)
llvmbot wrote: @aemerson What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/125386 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/125386 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [AArch64] Enable vscale_range with +sme (#124466) (PR #125386)
llvmbot wrote:
@llvm/pr-subscribers-clang-codegen
Author: None (llvmbot)
Changes
Backport 9f1c825fb62319b94ac9604f733afd59e9eb461b
Requested by: @davemgreen
---
Full diff: https://github.com/llvm/llvm-project/pull/125386.diff
11 Files Affected:
- (modified) clang/include/clang/Basic/TargetInfo.h (+2-1)
- (modified) clang/lib/AST/ASTContext.cpp (+2-1)
- (modified) clang/lib/AST/ItaniumMangle.cpp (+1-1)
- (modified) clang/lib/Basic/Targets/AArch64.cpp (+3-2)
- (modified) clang/lib/Basic/Targets/AArch64.h (+2-1)
- (modified) clang/lib/Basic/Targets/RISCV.cpp (+3-2)
- (modified) clang/lib/Basic/Targets/RISCV.h (+2-1)
- (modified) clang/lib/CodeGen/CodeGenFunction.cpp (+9-8)
- (modified) clang/lib/CodeGen/Targets/RISCV.cpp (+2-2)
- (modified) clang/lib/Sema/SemaType.cpp (+2-1)
- (modified) clang/test/CodeGen/AArch64/sme-intrinsics/aarch64-sme-attrs.cpp
(+2-2)
``diff
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 43c09cf1f973e3..d762144478b489 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1023,7 +1023,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Returns target-specific min and max values VScale_Range.
virtual std::optional>
- getVScaleRange(const LangOptions &LangOpts) const {
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
return std::nullopt;
}
/// The __builtin_clz* and __builtin_ctz* built-in
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index cd1bcb3b9a063d..e58091ce95f625 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -10363,7 +10363,8 @@ bool ASTContext::areLaxCompatibleSveTypes(QualType
FirstType,
/// getRVVTypeSize - Return RVV vector register size.
static uint64_t getRVVTypeSize(ASTContext &Context, const BuiltinType *Ty) {
assert(Ty->isRVVVLSBuiltinType() && "Invalid RVV Type");
- auto VScale = Context.getTargetInfo().getVScaleRange(Context.getLangOpts());
+ auto VScale =
+ Context.getTargetInfo().getVScaleRange(Context.getLangOpts(), false);
if (!VScale)
return 0;
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 49089c0ea3c8ac..f84ccefd34cacb 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4198,7 +4198,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
// Apend the LMUL suffix.
auto VScale = getASTContext().getTargetInfo().getVScaleRange(
- getASTContext().getLangOpts());
+ getASTContext().getLangOpts(), false);
unsigned VLen = VScale->first * llvm::RISCV::RVVBitsPerBlock;
if (T->getVectorKind() == VectorKind::RVVFixedLengthData) {
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 0b899137bbb5c7..57c9849ef2a728 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -703,12 +703,13 @@ ArrayRef
AArch64TargetInfo::getTargetBuiltins() const {
}
std::optional>
-AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
+AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const {
if (LangOpts.VScaleMin || LangOpts.VScaleMax)
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || (IsArmStreamingFunction && hasFeature("sme")))
return std::pair(1, 16);
return std::nullopt;
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index 600940f5e4e23c..b75d2a9dc8ecad 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -184,7 +184,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
ArrayRef getTargetBuiltins() const override;
std::optional>
- getVScaleRange(const LangOptions &LangOpts) const override;
+ getVScaleRange(const LangOptions &LangOpts,
+ bool IsArmStreamingFunction) const override;
bool doesFeatureAffectCodeGen(StringRef Name) const override;
bool validateCpuSupports(StringRef FeatureStr) const override;
bool hasFeature(StringRef Feature) const override;
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 8167d7603b0e14..61b8ae9d098abc 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -222,7 +222,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
// Currently we support the v1.0 RISC-V V intrinsics.
Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(1, 0)));
- auto VScale = getVScaleRange(Opts);
+ auto VScale = getVScaleRange(Opts, false);
if (VScale && VScale->first && VScale->first == VScale->second)
Builder.defineMacro("__riscv_v_f
[llvm-branch-commits] [llvm] release/20.x: [VPlan] Check VPWidenIntrinsicSC in VPRecipeWithIRFlags::classof. (PR #125363)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/125363 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/20.x: [VPlan] Check VPWidenIntrinsicSC in VPRecipeWithIRFlags::classof. (PR #125363)
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: None (llvmbot)
Changes
Backport 75b922dccfc35ec25a520b1941e6682a300802b8
Requested by: @fhahn
---
Full diff: https://github.com/llvm/llvm-project/pull/125363.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/VPlan.h (+1)
- (added)
llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
(+151)
``diff
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h
b/llvm/lib/Transforms/Vectorize/VPlan.h
index a1ff684b2b80175..6c95b08a0201461 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1058,6 +1058,7 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
+ R->getVPDefID() == VPRecipeBase::VPWidenIntrinsicSC ||
R->getVPDefID() == VPRecipeBase::VPReplicateSC ||
R->getVPDefID() == VPRecipeBase::VPReverseVectorPointerSC ||
R->getVPDefID() == VPRecipeBase::VPVectorPointerSC;
diff --git
a/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
b/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
new file mode 100644
index 000..53bd2d119c1ae40
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals none --version 5
+; RUN: opt -p loop-vectorize -mcpu=neoverse-v2 -force-vector-width=4 -S %s |
FileCheck %s
+
+target triple = "aarch64-unknown-linux"
+
+; Test case where we visit a VPWidenIntrinsic (for @llvm.fabs) with nnan flags.
+; For https://github.com/llvm/llvm-project/issues/125301.
+define void @check_widen_intrinsic_with_nnan(ptr noalias %dst.0, ptr noalias
%dst.1, ptr noalias %src.1, ptr %src.2) {
+; CHECK-LABEL: define void @check_widen_intrinsic_with_nnan(
+; CHECK-SAME: ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], ptr
noalias [[SRC_1:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT:br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT:br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [
[[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
+; CHECK-NEXT:[[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:[[TMP1:%.*]] = getelementptr inbounds double, ptr [[SRC_1]],
i64 [[TMP0]]
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds double, ptr [[TMP1]],
i32 0
+; CHECK-NEXT:[[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP2]], align 8
+; CHECK-NEXT:[[TMP3:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x
double> [[WIDE_LOAD]])
+; CHECK-NEXT:[[TMP4:%.*]] = fcmp olt <4 x double> [[TMP3]], splat (double
1.00e+00)
+; CHECK-NEXT:[[TMP5:%.*]] = xor <4 x i1> [[TMP4]], splat (i1 true)
+; CHECK-NEXT:[[TMP6:%.*]] = add i64 [[TMP0]], -1
+; CHECK-NEXT:[[TMP7:%.*]] = getelementptr double, ptr [[DST_0]], i64
[[TMP6]]
+; CHECK-NEXT:[[TMP8:%.*]] = getelementptr double, ptr [[TMP7]], i32 0
+; CHECK-NEXT:call void @llvm.masked.store.v4f64.p0(<4 x double>
zeroinitializer, ptr [[TMP8]], i32 8, <4 x i1> [[TMP5]])
+; CHECK-NEXT:[[TMP9:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
+; CHECK-NEXT:br i1 [[TMP9]], label %[[PRED_LOAD_IF:.*]], label
%[[PRED_LOAD_CONTINUE:.*]]
+; CHECK: [[PRED_LOAD_IF]]:
+; CHECK-NEXT:[[TMP10:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP11:%.*]] = insertelement <4 x double> poison, double
[[TMP10]], i32 0
+; CHECK-NEXT:br label %[[PRED_LOAD_CONTINUE]]
+; CHECK: [[PRED_LOAD_CONTINUE]]:
+; CHECK-NEXT:[[TMP12:%.*]] = phi <4 x double> [ poison, %[[VECTOR_BODY]]
], [ [[TMP11]], %[[PRED_LOAD_IF]] ]
+; CHECK-NEXT:[[TMP13:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1
+; CHECK-NEXT:br i1 [[TMP13]], label %[[PRED_LOAD_IF1:.*]], label
%[[PRED_LOAD_CONTINUE2:.*]]
+; CHECK: [[PRED_LOAD_IF1]]:
+; CHECK-NEXT:[[TMP14:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP15:%.*]] = insertelement <4 x double> [[TMP12]], double
[[TMP14]], i32 1
+; CHECK-NEXT:br label %[[PRED_LOAD_CONTINUE2]]
+; CHECK: [[PRED_LOAD_CONTINUE2]]:
+; CHECK-NEXT:[[TMP16:%.*]] = phi <4 x double> [ [[TMP12]],
%[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]
+; CHECK-NEXT:[[TMP17:%.*]] = extractelement <4 x i1> [[TMP4]], i32 2
+; CHECK-NEXT:br i1 [[TMP17]], label %[[PRED_LOAD_IF3:.*]], label
%[[PRED_LOAD_CONTINUE4:.*]]
+; CHECK: [[PRED_LOAD_IF3]]:
+; CHECK-NEXT:[[TMP18:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP19:%.*]] = insertelement <4 x double> [[TMP16]
[llvm-branch-commits] [llvm] release/20.x: [VPlan] Check VPWidenIntrinsicSC in VPRecipeWithIRFlags::classof. (PR #125363)
llvmbot wrote:
@llvm/pr-subscribers-vectorizers
Author: None (llvmbot)
Changes
Backport 75b922dccfc35ec25a520b1941e6682a300802b8
Requested by: @fhahn
---
Full diff: https://github.com/llvm/llvm-project/pull/125363.diff
2 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/VPlan.h (+1)
- (added)
llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
(+151)
``diff
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h
b/llvm/lib/Transforms/Vectorize/VPlan.h
index a1ff684b2b8017..6c95b08a020146 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1058,6 +1058,7 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
+ R->getVPDefID() == VPRecipeBase::VPWidenIntrinsicSC ||
R->getVPDefID() == VPRecipeBase::VPReplicateSC ||
R->getVPDefID() == VPRecipeBase::VPReverseVectorPointerSC ||
R->getVPDefID() == VPRecipeBase::VPVectorPointerSC;
diff --git
a/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
b/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
new file mode 100644
index 00..53bd2d119c1ae4
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals none --version 5
+; RUN: opt -p loop-vectorize -mcpu=neoverse-v2 -force-vector-width=4 -S %s |
FileCheck %s
+
+target triple = "aarch64-unknown-linux"
+
+; Test case where we visit a VPWidenIntrinsic (for @llvm.fabs) with nnan flags.
+; For https://github.com/llvm/llvm-project/issues/125301.
+define void @check_widen_intrinsic_with_nnan(ptr noalias %dst.0, ptr noalias
%dst.1, ptr noalias %src.1, ptr %src.2) {
+; CHECK-LABEL: define void @check_widen_intrinsic_with_nnan(
+; CHECK-SAME: ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], ptr
noalias [[SRC_1:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT:br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT:br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [
[[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
+; CHECK-NEXT:[[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:[[TMP1:%.*]] = getelementptr inbounds double, ptr [[SRC_1]],
i64 [[TMP0]]
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds double, ptr [[TMP1]],
i32 0
+; CHECK-NEXT:[[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP2]], align 8
+; CHECK-NEXT:[[TMP3:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x
double> [[WIDE_LOAD]])
+; CHECK-NEXT:[[TMP4:%.*]] = fcmp olt <4 x double> [[TMP3]], splat (double
1.00e+00)
+; CHECK-NEXT:[[TMP5:%.*]] = xor <4 x i1> [[TMP4]], splat (i1 true)
+; CHECK-NEXT:[[TMP6:%.*]] = add i64 [[TMP0]], -1
+; CHECK-NEXT:[[TMP7:%.*]] = getelementptr double, ptr [[DST_0]], i64
[[TMP6]]
+; CHECK-NEXT:[[TMP8:%.*]] = getelementptr double, ptr [[TMP7]], i32 0
+; CHECK-NEXT:call void @llvm.masked.store.v4f64.p0(<4 x double>
zeroinitializer, ptr [[TMP8]], i32 8, <4 x i1> [[TMP5]])
+; CHECK-NEXT:[[TMP9:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
+; CHECK-NEXT:br i1 [[TMP9]], label %[[PRED_LOAD_IF:.*]], label
%[[PRED_LOAD_CONTINUE:.*]]
+; CHECK: [[PRED_LOAD_IF]]:
+; CHECK-NEXT:[[TMP10:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP11:%.*]] = insertelement <4 x double> poison, double
[[TMP10]], i32 0
+; CHECK-NEXT:br label %[[PRED_LOAD_CONTINUE]]
+; CHECK: [[PRED_LOAD_CONTINUE]]:
+; CHECK-NEXT:[[TMP12:%.*]] = phi <4 x double> [ poison, %[[VECTOR_BODY]]
], [ [[TMP11]], %[[PRED_LOAD_IF]] ]
+; CHECK-NEXT:[[TMP13:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1
+; CHECK-NEXT:br i1 [[TMP13]], label %[[PRED_LOAD_IF1:.*]], label
%[[PRED_LOAD_CONTINUE2:.*]]
+; CHECK: [[PRED_LOAD_IF1]]:
+; CHECK-NEXT:[[TMP14:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP15:%.*]] = insertelement <4 x double> [[TMP12]], double
[[TMP14]], i32 1
+; CHECK-NEXT:br label %[[PRED_LOAD_CONTINUE2]]
+; CHECK: [[PRED_LOAD_CONTINUE2]]:
+; CHECK-NEXT:[[TMP16:%.*]] = phi <4 x double> [ [[TMP12]],
%[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]
+; CHECK-NEXT:[[TMP17:%.*]] = extractelement <4 x i1> [[TMP4]], i32 2
+; CHECK-NEXT:br i1 [[TMP17]], label %[[PRED_LOAD_IF3:.*]], label
%[[PRED_LOAD_CONTINUE4:.*]]
+; CHECK: [[PRED_LOAD_IF3]]:
+; CHECK-NEXT:[[TMP18:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP19:%.*]] = insertelement <4 x double> [[TMP16]], doubl
[llvm-branch-commits] [llvm] release/20.x: [VPlan] Check VPWidenIntrinsicSC in VPRecipeWithIRFlags::classof. (PR #125363)
https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/125363
Backport 75b922dccfc35ec25a520b1941e6682a300802b8
Requested by: @fhahn
>From 23ec2271ba3dcf3fbfbc0b2cd31ea780c4da1d69 Mon Sep 17 00:00:00 2001
From: Florian Hahn
Date: Sat, 1 Feb 2025 21:40:58 +
Subject: [PATCH] [VPlan] Check VPWidenIntrinsicSC in
VPRecipeWithIRFlags::classof.
When VPWidenIntrinsicRecipe was changed to inhert from VPRecipeWithIRFlags,
VPRecipeWithIRFlags::classof wasn't updated accordingly. Also check for
VPWidenIntrinsicSC in VPRecipeWithIRFlags::classof.
Fixes https://github.com/llvm/llvm-project/issues/125301.
(cherry picked from commit 75b922dccfc35ec25a520b1941e6682a300802b8)
---
llvm/lib/Transforms/Vectorize/VPlan.h | 1 +
.../AArch64/drop-poison-generating-flags.ll | 151 ++
2 files changed, 152 insertions(+)
create mode 100644
llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h
b/llvm/lib/Transforms/Vectorize/VPlan.h
index a1ff684b2b8017..6c95b08a020146 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -1058,6 +1058,7 @@ class VPRecipeWithIRFlags : public VPSingleDefRecipe {
R->getVPDefID() == VPRecipeBase::VPWidenEVLSC ||
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
R->getVPDefID() == VPRecipeBase::VPWidenCastSC ||
+ R->getVPDefID() == VPRecipeBase::VPWidenIntrinsicSC ||
R->getVPDefID() == VPRecipeBase::VPReplicateSC ||
R->getVPDefID() == VPRecipeBase::VPReverseVectorPointerSC ||
R->getVPDefID() == VPRecipeBase::VPVectorPointerSC;
diff --git
a/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
b/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
new file mode 100644
index 00..53bd2d119c1ae4
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/drop-poison-generating-flags.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals none --version 5
+; RUN: opt -p loop-vectorize -mcpu=neoverse-v2 -force-vector-width=4 -S %s |
FileCheck %s
+
+target triple = "aarch64-unknown-linux"
+
+; Test case where we visit a VPWidenIntrinsic (for @llvm.fabs) with nnan flags.
+; For https://github.com/llvm/llvm-project/issues/125301.
+define void @check_widen_intrinsic_with_nnan(ptr noalias %dst.0, ptr noalias
%dst.1, ptr noalias %src.1, ptr %src.2) {
+; CHECK-LABEL: define void @check_widen_intrinsic_with_nnan(
+; CHECK-SAME: ptr noalias [[DST_0:%.*]], ptr noalias [[DST_1:%.*]], ptr
noalias [[SRC_1:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT:br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT:br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [
[[INDEX_NEXT:%.*]], %[[PRED_LOAD_CONTINUE6:.*]] ]
+; CHECK-NEXT:[[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:[[TMP1:%.*]] = getelementptr inbounds double, ptr [[SRC_1]],
i64 [[TMP0]]
+; CHECK-NEXT:[[TMP2:%.*]] = getelementptr inbounds double, ptr [[TMP1]],
i32 0
+; CHECK-NEXT:[[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP2]], align 8
+; CHECK-NEXT:[[TMP3:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x
double> [[WIDE_LOAD]])
+; CHECK-NEXT:[[TMP4:%.*]] = fcmp olt <4 x double> [[TMP3]], splat (double
1.00e+00)
+; CHECK-NEXT:[[TMP5:%.*]] = xor <4 x i1> [[TMP4]], splat (i1 true)
+; CHECK-NEXT:[[TMP6:%.*]] = add i64 [[TMP0]], -1
+; CHECK-NEXT:[[TMP7:%.*]] = getelementptr double, ptr [[DST_0]], i64
[[TMP6]]
+; CHECK-NEXT:[[TMP8:%.*]] = getelementptr double, ptr [[TMP7]], i32 0
+; CHECK-NEXT:call void @llvm.masked.store.v4f64.p0(<4 x double>
zeroinitializer, ptr [[TMP8]], i32 8, <4 x i1> [[TMP5]])
+; CHECK-NEXT:[[TMP9:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
+; CHECK-NEXT:br i1 [[TMP9]], label %[[PRED_LOAD_IF:.*]], label
%[[PRED_LOAD_CONTINUE:.*]]
+; CHECK: [[PRED_LOAD_IF]]:
+; CHECK-NEXT:[[TMP10:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP11:%.*]] = insertelement <4 x double> poison, double
[[TMP10]], i32 0
+; CHECK-NEXT:br label %[[PRED_LOAD_CONTINUE]]
+; CHECK: [[PRED_LOAD_CONTINUE]]:
+; CHECK-NEXT:[[TMP12:%.*]] = phi <4 x double> [ poison, %[[VECTOR_BODY]]
], [ [[TMP11]], %[[PRED_LOAD_IF]] ]
+; CHECK-NEXT:[[TMP13:%.*]] = extractelement <4 x i1> [[TMP4]], i32 1
+; CHECK-NEXT:br i1 [[TMP13]], label %[[PRED_LOAD_IF1:.*]], label
%[[PRED_LOAD_CONTINUE2:.*]]
+; CHECK: [[PRED_LOAD_IF1]]:
+; CHECK-NEXT:[[TMP14:%.*]] = load double, ptr [[SRC_2]], align 8
+; CHECK-NEXT:[[TMP15:%.*]] = insertelement <4 x double> [[TMP12]], double
[[TMP14]], i32 1
+; CHECK-NEXT:br label
[llvm-branch-commits] [clang] release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (PR #125368)
https://github.com/hubert-reinterpretcast created https://github.com/llvm/llvm-project/pull/125368 #110503 updates the scope of `-fclang-abi-compat` but did not make that clear in the release notes. This PR addresses that problem. >From 4b3e4d5f38cf0f58ee8e8384455c0a235041315c Mon Sep 17 00:00:00 2001 From: Hubert Tong Date: Sat, 1 Feb 2025 19:52:32 -0400 Subject: [PATCH] Document -fclang-abi-compat=19 re: #110503 #110503 updates the scope of `-fclang-abi-compat` but did not make that clear in the release notes. This PR addresses that problem. --- clang/docs/ReleaseNotes.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 88c9fc8f95e4a1..53534d821b2c9a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -252,7 +252,7 @@ ABI Changes in This Version - Fixed Microsoft name mangling of placeholder, auto and decltype(auto), return types for MSVC 1920+. This change resolves incompatibilities with code compiled by MSVC 1920+ but will introduce incompatibilities with code compiled by earlier versions of Clang unless such code is built with the compiler option -fms-compatibility-version=19.14 to imitate the MSVC 1914 mangling behavior. - Fixed the Itanium mangling of the construction vtable name. This change will introduce incompatibilities with code compiled by Clang 19 and earlier versions, unless the -fclang-abi-compat=19 option is used. (#GH108015) -- Mangle member-like friend function templates as members of the enclosing class. (#GH110247, #GH110503) +- Mangle member-like friend function templates as members of the enclosing class. This can be disabled using -fclang-abi-compat=19. (#GH110247, #GH110503) AST Dumping Potentially Breaking Changes ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (PR #125368)
llvmbot wrote: @llvm/pr-subscribers-clang Author: Hubert Tong (hubert-reinterpretcast) Changes #110503 updates the scope of `-fclang-abi-compat` but did not make that clear in the release notes. This PR addresses that problem. --- Full diff: https://github.com/llvm/llvm-project/pull/125368.diff 1 Files Affected: - (modified) clang/docs/ReleaseNotes.rst (+1-1) ``diff diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 88c9fc8f95e4a1..53534d821b2c9a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -252,7 +252,7 @@ ABI Changes in This Version - Fixed Microsoft name mangling of placeholder, auto and decltype(auto), return types for MSVC 1920+. This change resolves incompatibilities with code compiled by MSVC 1920+ but will introduce incompatibilities with code compiled by earlier versions of Clang unless such code is built with the compiler option -fms-compatibility-version=19.14 to imitate the MSVC 1914 mangling behavior. - Fixed the Itanium mangling of the construction vtable name. This change will introduce incompatibilities with code compiled by Clang 19 and earlier versions, unless the -fclang-abi-compat=19 option is used. (#GH108015) -- Mangle member-like friend function templates as members of the enclosing class. (#GH110247, #GH110503) +- Mangle member-like friend function templates as members of the enclosing class. This can be disabled using -fclang-abi-compat=19. (#GH110247, #GH110503) AST Dumping Potentially Breaking Changes `` https://github.com/llvm/llvm-project/pull/125368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [llvm] Introduce type id operand bundle (PR #87573)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87573
>From a8a5848885e12c771f12cfa33b4dbc6a0272e925 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:04 -0700
Subject: [PATCH 1/5] Update clang/lib/CodeGen/CodeGenModule.cpp
Cleaner if checks.
Co-authored-by: Matt Arsenault
---
clang/lib/CodeGen/CodeGenModule.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index e19bbee996f5829..ff1586d2fa8abeb 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2711,7 +2711,7 @@ void
CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
void CodeGenModule::CreateFunctionTypeMetadataForIcall(const QualType &QT,
llvm::CallBase *CB) {
// Only if needed for call graph section and only for indirect calls.
- if (!(CodeGenOpts.CallGraphSection && CB && CB->isIndirectCall()))
+ if (!CodeGenOpts.CallGraphSection || !CB || !CB->isIndirectCall())
return;
auto *MD = CreateMetadataIdentifierGeneralized(QT);
>From 019b2ca5e1c263183ed114e0b967b4e77b4a17a8 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:31 -0700
Subject: [PATCH 2/5] Update clang/lib/CodeGen/CodeGenModule.cpp
Update the comments as suggested.
Co-authored-by: Matt Arsenault
---
clang/lib/CodeGen/CodeGenModule.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index ff1586d2fa8abeb..5635a87d2358a70 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2680,9 +2680,9 @@ void
CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
bool EmittedMDIdGeneralized = false;
if (CodeGenOpts.CallGraphSection &&
(!F->hasLocalLinkage() ||
- F->getFunction().hasAddressTaken(nullptr, /* IgnoreCallbackUses */ true,
-/* IgnoreAssumeLikeCalls */ true,
-/* IgnoreLLVMUsed */ false))) {
+ F->getFunction().hasAddressTaken(nullptr, /*IgnoreCallbackUses=*/ true,
+/*IgnoreAssumeLikeCalls=*/ true,
+/*IgnoreLLVMUsed=*/ false))) {
F->addTypeMetadata(0, CreateMetadataIdentifierGeneralized(FD->getType()));
EmittedMDIdGeneralized = true;
}
>From 99242900c51778abd4b7e7f4361b09202b7abcda Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 29 Apr 2024 11:53:40 -0700
Subject: [PATCH 3/5] dyn_cast to isa
Created using spr 1.3.6-beta.1
---
clang/lib/CodeGen/CGCall.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 526a63b24ff8341..45033ced1d83448 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -5713,8 +5713,8 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
if (callOrInvoke && *callOrInvoke && (*callOrInvoke)->isIndirectCall()) {
if (const FunctionDecl *FD = dyn_cast_or_null(TargetDecl))
{
// Type id metadata is set only for C/C++ contexts.
-if (dyn_cast(FD) || dyn_cast(FD) ||
-dyn_cast(FD)) {
+if (isa(FD) || isa(FD) ||
+isa(FD)) {
CGM.CreateFunctionTypeMetadataForIcall(FD->getType(), *callOrInvoke);
}
}
>From 24882b15939b781bcf28d87fdf4f6e8834b6cfde Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Tue, 10 Dec 2024 14:54:27 -0800
Subject: [PATCH 4/5] Address review comments. Break llvm and clang patches.
Created using spr 1.3.6-beta.1
---
llvm/lib/IR/Verifier.cpp | 7 +++
llvm/test/Verifier/operand-bundles.ll | 4 ++--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 0ad7ba555bfade6..b72672e7b8e5614 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3707,10 +3707,9 @@ void Verifier::visitCallBase(CallBase &Call) {
if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID())
visitIntrinsicCall(ID, Call);
- // Verify that a callsite has at most one "deopt", at most one "funclet", at
- // most one "gc-transition", at most one "cfguardtarget", at most one "type",
- // at most one "preallocated" operand bundle, and at most one "ptrauth"
- // operand bundle.
+ // Verify that a callsite has at most one operand bundle for each of the
+ // following: "deopt", "funclet", "gc-transition", "cfguardtarget", "type",
+ // "preallocated", and "ptrauth".
bool FoundDeoptBundle = false, FoundFuncletBundle = false,
FoundGCTransitionBundle = false, FoundCFGuardTargetBundle = false,
FoundPreallocatedBundle = false, FoundGCLiveBundle = false,
diff --git a/llvm/test/Verifier/operand-bundles.ll
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to NPM (PR #118462)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/118462
>From a5c1a65dd4e7b3d77a7cc74febe17437144db46e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Tue, 3 Dec 2024 10:12:36 +
Subject: [PATCH 1/6] [CodeGen][NewPM] Port RegAllocPriorityAdvisor analysis to
NPM
---
.../llvm}/CodeGen/RegAllocPriorityAdvisor.h | 78 +++-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 1 +
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 6 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 184 +++---
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 9 +-
llvm/lib/CodeGen/RegAllocGreedy.h | 2 +-
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 155 +++
llvm/lib/Passes/PassBuilder.cpp | 1 +
10 files changed, 320 insertions(+), 120 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocPriorityAdvisor.h (57%)
diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
similarity index 57%
rename from llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
rename to llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
index 0758743c2b1403e..a53739fdc3fc40b 100644
--- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.h
+++ b/llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
@@ -9,8 +9,10 @@
#ifndef LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
#define LLVM_CODEGEN_REGALLOCPRIORITYADVISOR_H
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
namespace llvm {
@@ -68,12 +70,72 @@ class DummyPriorityAdvisor : public RegAllocPriorityAdvisor
{
unsigned getPriority(const LiveInterval &LI) const override;
};
-class RegAllocPriorityAdvisorAnalysis : public ImmutablePass {
+/// Common provider for getting the priority advisor and logging rewards.
+/// Legacy analysis forwards all calls to this provider.
+/// New analysis serves the provider as the analysis result.
+/// Expensive setup is done in the constructor, so that the advisor can be
+/// created quickly for every machine function.
+/// TODO: Remove once legacy PM support is dropped.
+class RegAllocPriorityAdvisorProvider {
public:
enum class AdvisorMode : int { Default, Release, Development, Dummy };
- RegAllocPriorityAdvisorAnalysis(AdvisorMode Mode)
- : ImmutablePass(ID), Mode(Mode){};
+ RegAllocPriorityAdvisorProvider(AdvisorMode Mode) : Mode(Mode) {}
+
+ virtual ~RegAllocPriorityAdvisorProvider() = default;
+
+ virtual void logRewardIfNeeded(const MachineFunction &MF,
+ llvm::function_ref GetReward) {};
+
+ virtual std::unique_ptr
+ getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
+
+ void setAnalyses(SlotIndexes *SI) { this->SI = SI; }
+
+ AdvisorMode getAdvisorMode() const { return Mode; }
+
+protected:
+ SlotIndexes *SI;
+
+private:
+ const AdvisorMode Mode;
+};
+
+RegAllocPriorityAdvisorProvider *createReleaseModePriorityAdvisorProvider();
+
+RegAllocPriorityAdvisorProvider *
+createDevelopmentModePriorityAdvisorProvider(LLVMContext &Ctx);
+
+class RegAllocPriorityAdvisorAnalysis
+: public AnalysisInfoMixin {
+ static AnalysisKey Key;
+ friend AnalysisInfoMixin;
+
+public:
+ struct Result {
+// Owned by this analysis.
+RegAllocPriorityAdvisorProvider *Provider;
+
+bool invalidate(MachineFunction &MF, const PreservedAnalyses &PA,
+MachineFunctionAnalysisManager::Invalidator &Inv) {
+ auto PAC = PA.getChecker();
+ return !PAC.preservedWhenStateless() ||
+ Inv.invalidate(MF, PA);
+}
+ };
+
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+
+private:
+ void initializeProvider(LLVMContext &Ctx);
+ std::unique_ptr Provider;
+};
+
+class RegAllocPriorityAdvisorAnalysisLegacy : public ImmutablePass {
+public:
+ using AdvisorMode = RegAllocPriorityAdvisorProvider::AdvisorMode;
+ RegAllocPriorityAdvisorAnalysisLegacy(AdvisorMode Mode)
+ : ImmutablePass(ID), Mode(Mode) {};
static char ID;
/// Get an advisor for the given context (i.e. machine function, etc)
@@ -81,7 +143,7 @@ class RegAllocPriorityAdvisorAnalysis : public ImmutablePass
{
getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
AdvisorMode getAdvisorMode() const { return Mode; }
virtual void logRewardIfNeeded(const MachineFunction &MF,
- llvm::function_ref GetReward){};
+ llvm::function_ref GetReward) {};
protected:
// This analysis preserves everything, and subclasses may have additional
@@ -97,11 +159,13 @@ class RegAllocPriorityAdvisorAnalysis : public
ImmutablePass {
/// Specialization for the API used by the analysis infrastructure to create
/// an inst
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RegAllocGreedy to NPM (PR #119540)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 57ec131a09f46b9f448dc00dc6cb1dc33dff21f1 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 08:51:55 +
Subject: [PATCH 1/5] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
llvm/include/llvm/CodeGen/MachineFunction.h | 1 +
llvm/include/llvm/CodeGen/Passes.h| 2 +-
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 185 ++
llvm/lib/CodeGen/RegAllocGreedy.h | 57 +++---
llvm/lib/Passes/PassBuilder.cpp | 1 +
8 files changed, 196 insertions(+), 63 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index c3eb27b9462879d..92acfa8e6bcf3f8 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -920,6 +920,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
+ /// TODO: Add the param LiveStks
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index b5d2a7e6bf035b0..0182f21bee5f551 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -171,7 +171,7 @@ namespace llvm {
extern char &LiveRangeShrinkID;
/// Greedy register allocator.
- extern char &RAGreedyID;
+ extern char &RAGreedyLegacyID;
/// Basic register allocator.
extern char &RABasicID;
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 1bbfaedc9f992dd..e071dc665dcaee1 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -250,7 +250,7 @@ void
initializeProfileSummaryInfoWrapperPassPass(PassRegistry &);
void initializePromoteLegacyPassPass(PassRegistry &);
void initializeRABasicPass(PassRegistry &);
void initializePseudoProbeInserterPass(PassRegistry &);
-void initializeRAGreedyPass(PassRegistry &);
+void initializeRAGreedyLegacyPass(PassRegistry &);
void initializeReachingDefAnalysisPass(PassRegistry &);
void initializeReassociateLegacyPassPass(PassRegistry &);
void initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 509895e956f6afc..e9b853735d9346b 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+"regallocgreedy", "RAGreedy",
+[](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+[PB = this](StringRef Params) {
+ // TODO: parseRegAllocFilter(*PB, Params);
+ return Expected(nullptr);
+}, ""
+)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index ed871519e33bc2c..69b5e0bce862eec 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -112,7 +112,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 72c38ab8c7d07bc..49d251b4fe4d57c 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -43,8 +43,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -55,6 +57,7 @@
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
[llvm-branch-commits] [llvm] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (PR #120557)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/120557
>From 0fdb9dfadb15855ffb7463d755958445da9f9333 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 11 Dec 2024 10:57:21 +
Subject: [PATCH 1/4] [RegAlloc][NewPM] Plug Greedy RA in codegen pipeline
---
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 18 +++-
.../llvm/Passes/MachinePassRegistry.def | 4 ++--
.../include/llvm/Target/CGPassBuilderOption.h | 2 +-
llvm/lib/Passes/PassBuilder.cpp | 13
...plicit-def-remat-requires-impdef-check.mir | 1 +
...implicit-def-with-impdef-greedy-assert.mir | 1 +
llvm/test/CodeGen/AArch64/pr51516.mir | 1 +
llvm/test/CodeGen/AArch64/spill-fold.mir | 2 ++
.../extend-phi-subrange-not-in-parent.mir | 1 +
llvm/test/CodeGen/MIR/Generic/runPass.mir | 1 +
.../SystemZ/clear-liverange-spillreg.mir | 1 +
llvm/test/CodeGen/Thumb/high-reg-clobber.mir | 1 +
llvm/test/CodeGen/X86/limit-split-cost.mir| 1 +
.../test/tools/llc/new-pm/regalloc-amdgpu.mir | 17 +--
llvm/tools/llc/NewPMDriver.cpp| 21 +++
15 files changed, 71 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index aca9b3b888acc30..971217923f7ef17 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -1056,7 +1056,7 @@ void CodeGenPassBuilder::addMachineSSAOptimization(
///
/// A target that uses the standard regalloc pass order for fast or optimized
/// allocation may still override this for per-target regalloc
-/// selection. But -regalloc=... always takes precedence.
+/// selection. But -regalloc-npm=... always takes precedence.
template
void CodeGenPassBuilder::addTargetRegisterAllocator(
AddMachinePass &addPass, bool Optimized) const {
@@ -1073,6 +1073,22 @@ template
void CodeGenPassBuilder::addRegAllocPass(
AddMachinePass &addPass, bool Optimized) const {
// TODO: Parse Opt.RegAlloc to add register allocator.
+ // Use the specified -regalloc-npm={basic|greedy|fast|pbqp}
+ if (Opt.RegAlloc > RegAllocType::Default) {
+switch (Opt.RegAlloc) {
+ case RegAllocType::Fast:
+addPass(RegAllocFastPass());
+break;
+ case RegAllocType::Greedy:
+addPass(RAGreedyPass());
+break;
+ default:
+llvm_unreachable("Register allocator not supported yet.");
+}
+return;
+ }
+ // -regalloc=default or unspecified, so pick based on the optimization level.
+ derived().addTargetRegisterAllocator(addPass, Optimized);
}
template
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 52fabeb361f706e..e6bb4c0de3d72c4 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -188,12 +188,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
},
"filter=reg-filter;no-clear-vregs")
+// 'all' is the default filter
MACHINE_FUNCTION_PASS_WITH_PARAMS(
"greedy", "RAGreedyPass",
[](RAGreedyPass::Options Opts) { return RAGreedyPass(Opts); },
[PB = this](StringRef Params) {
- // TODO: parseRegAllocGreedyFilterFunc(*PB, Params);
- return Expected(RAGreedyPass::Options{});
+ return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h
b/llvm/include/llvm/Target/CGPassBuilderOption.h
index d3d19c8a7dc9f23..c7c1572bcde6030 100644
--- a/llvm/include/llvm/Target/CGPassBuilderOption.h
+++ b/llvm/include/llvm/Target/CGPassBuilderOption.h
@@ -52,7 +52,7 @@ struct CGPassBuilderOption {
bool RequiresCodeGenSCCOrder = false;
RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault;
- StringRef RegAlloc = "default";
+ RegAllocType RegAlloc = RegAllocType::Default;
std::optional EnableGlobalISelAbort;
std::string FSProfileFile;
std::string FSRemappingFile;
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 73f45d9b73b2095..9ac536aa0870938 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1407,6 +1407,19 @@ parseBoundsCheckingOptions(StringRef Params) {
return Options;
}
+Expected parseRegAllocGreedyFilterFunc(PassBuilder &PB,
StringRef Params) {
+ if (Params.empty() || Params == "all") {
+return RAGreedyPass::Options();
+ }
+ std::optional Filter = PB.parseRegAllocFilter(Params);
+ if (!Filter) {
+return make_error(
+formatv("invalid regallocgreedy register filter '{0}' ", Params).str(),
+inconvertibleErrorCode());
+ }
+ return RAGreedyPass::Options{*Filter, Params};
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git
a/llvm/test/CodeGen/AAr
[llvm-branch-commits] [llvm] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (PR #125351)
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/125351
None
>From 7ef9eb592f3d84763de4d9a59cd6f6ea737e82f0 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Sat, 1 Feb 2025 18:21:24 +
Subject: [PATCH] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM
---
llvm/lib/Target/AMDGPU/AMDGPU.h | 2 +-
llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 2 +-
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 3 +-
.../AMDGPU/SIOptimizeExecMaskingPreRA.cpp | 42 ++-
.../AMDGPU/SIOptimizeExecMaskingPreRA.h | 24 +++
.../CodeGen/AMDGPU/collapse-endcf-broken.mir | 1 +
...ask-pre-ra-non-empty-but-used-interval.mir | 1 +
7 files changed, 62 insertions(+), 13 deletions(-)
create mode 100644 llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 31656c98ccd36fa..692eb937efa6743 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -368,7 +368,7 @@ struct AMDGPUUnifyMetadataPass :
PassInfoMixin {
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
};
-void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
+void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
extern char &SIOptimizeExecMaskingPreRAID;
void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 45e2f0d9097adfd..95d82ae407e6772 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -108,6 +108,7 @@ MACHINE_FUNCTION_PASS("si-lower-sgpr-spills",
SILowerSGPRSpillsPass())
MACHINE_FUNCTION_PASS("si-lower-wwm-copies", SILowerWWMCopiesPass())
MACHINE_FUNCTION_PASS("si-opt-vgpr-liverange", SIOptimizeVGPRLiveRangePass())
MACHINE_FUNCTION_PASS("si-optimize-exec-masking", SIOptimizeExecMaskingPass())
+MACHINE_FUNCTION_PASS("si-optimize-exec-masking-pre-ra",
SIOptimizeExecMaskingPreRAPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
@@ -127,7 +128,6 @@ DUMMY_MACHINE_FUNCTION_PASS("si-insert-waitcnts",
SIInsertWaitcntsPass())
DUMMY_MACHINE_FUNCTION_PASS("si-late-branch-lowering",
SILateBranchLoweringPass())
DUMMY_MACHINE_FUNCTION_PASS("si-memory-legalizer", SIMemoryLegalizerPass())
DUMMY_MACHINE_FUNCTION_PASS("si-mode-register", SIModeRegisterPass())
-DUMMY_MACHINE_FUNCTION_PASS("si-optimize-exec-masking-pre-ra",
SIOptimizeExecMaskingPreRAPass())
DUMMY_MACHINE_FUNCTION_PASS("si-pre-emit-peephole", SIPreEmitPeepholePass())
// TODO: Move amdgpu-preload-kern-arg-prolog to MACHINE_FUNCTION_PASS since it
// already exists.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index d21f9c846c95130..27dc5a502d109b2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -46,6 +46,7 @@
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
#include "SIOptimizeExecMasking.h"
+#include "SIOptimizeExecMaskingPreRA.h"
#include "SIOptimizeVGPRLiveRange.h"
#include "SIPeepholeSDWA.h"
#include "SIPreAllocateWWMRegs.h"
@@ -495,7 +496,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeAMDGPUTarget() {
initializeSIFoldOperandsLegacyPass(*PR);
initializeSIPeepholeSDWALegacyPass(*PR);
initializeSIShrinkInstructionsLegacyPass(*PR);
- initializeSIOptimizeExecMaskingPreRAPass(*PR);
+ initializeSIOptimizeExecMaskingPreRALegacyPass(*PR);
initializeSIOptimizeVGPRLiveRangeLegacyPass(*PR);
initializeSILoadStoreOptimizerLegacyPass(*PR);
initializeAMDGPUCtorDtorLoweringLegacyPass(*PR);
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
index 31f65d82a4d2bcb..2a8a398d7429d05 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -12,6 +12,7 @@
///
//===--===//
+#include "SIOptimizeExecMaskingPreRA.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
@@ -25,7 +26,7 @@ using namespace llvm;
namespace {
-class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
+class SIOptimizeExecMaskingPreRA {
private:
const SIRegisterInfo *TRI;
const SIInstrInfo *TII;
@@ -42,11 +43,18 @@ class SIOptimizeExecMaskingPreRA : public
MachineFunctionPass {
bool optimizeVcndVcmpPair(MachineBasicBlock &MBB);
bool optimizeElseBranch(MachineBasicBlock &MBB);
+public:
+ SIOptimizeExecMaskingPreRA(LiveIntervals *LIS) : LIS(LIS) {}
+ bool run(MachineFunction &MF);
+};
[llvm-branch-commits] [llvm] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (PR #125351)
optimisan wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/125351?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#125351** https://app.graphite.dev/github/pr/llvm/llvm-project/125351?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/125351?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#120557** https://app.graphite.dev/github/pr/llvm/llvm-project/120557?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119540** https://app.graphite.dev/github/pr/llvm/llvm-project/119540?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#118462** https://app.graphite.dev/github/pr/llvm/llvm-project/118462?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#117309** https://app.graphite.dev/github/pr/llvm/llvm-project/117309?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * **#119181** https://app.graphite.dev/github/pr/llvm/llvm-project/119181?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>: 1 other dependent PR ([#119672](https://github.com/llvm/llvm-project/pull/119672) https://app.graphite.dev/github/pr/llvm/llvm-project/119672?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/>) * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/125351 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (PR #125351)
github-actions[bot] wrote: :warning: C/C++ code formatter, clang-format found issues in your code. :warning: You can test this locally with the following command: ``bash git-clang-format --diff c31b0c4f057a2b91ea504356607b981f44bc5e62 7ef9eb592f3d84763de4d9a59cd6f6ea737e82f0 --extensions cpp,h -- llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp `` View the diff from clang-format here. ``diff diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h index eca79c0d8d..ae908e10ad 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.h @@ -1,5 +1,5 @@ //===- SIOptimizeExecMaskingPreRA.h.h ---*- -//C++- *-===// +// C++- *-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. `` https://github.com/llvm/llvm-project/pull/125351 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [CodeGen][NewPM] Port RenameIndependentSubregs to NPM (PR #125192)
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/125192
>From 99a5e6c73fb0886e3aa5fdb1131c6ee53c5aeb96 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Fri, 31 Jan 2025 04:57:41 +
Subject: [PATCH] [CodeGen][NewPM] Port RenameIndependentSubregs to NPM
---
.../llvm/CodeGen/RenameIndependentSubregs.h | 25 +++
llvm/include/llvm/InitializePasses.h | 2 +-
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 1 +
.../llvm/Passes/MachinePassRegistry.def | 2 +-
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/RenameIndependentSubregs.cpp | 69 ---
llvm/lib/Passes/PassBuilder.cpp | 1 +
.../coalescing-with-subregs-in-loop-bug.mir | 1 +
...ename-independent-subregs-mac-operands.mir | 1 +
9 files changed, 78 insertions(+), 26 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
diff --git a/llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
b/llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
new file mode 100644
index 00..2f6afe6bea6209
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RenameIndependentSubregs.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/RenameIndependentSubregs.h --*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef LLVM_CODEGEN_RENAME_INDEPENDENT_SUBREGS_H
+#define LLVM_CODEGEN_RENAME_INDEPENDENT_SUBREGS_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RenameIndependentSubregsPass
+: public PassInfoMixin {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_RENAME_INDEPENDENT_SUBREGS_H
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 46fcd17347f4e0..8beacde0151868 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -269,7 +269,7 @@ void initializeRegionViewerPass(PassRegistry &);
void initializeRegisterCoalescerLegacyPass(PassRegistry &);
void initializeRemoveLoadsIntoFakeUsesPass(PassRegistry &);
void initializeRemoveRedundantDebugValuesPass(PassRegistry &);
-void initializeRenameIndependentSubregsPass(PassRegistry &);
+void initializeRenameIndependentSubregsLegacyPass(PassRegistry &);
void initializeReplaceWithVeclibLegacyPass(PassRegistry &);
void initializeResetMachineFunctionPass(PassRegistry &);
void initializeSCEVAAWrapperPassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 9681368249a0f9..a3149e3d2f12bf 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -59,6 +59,7 @@
#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterCoalescerPass.h"
#include "llvm/CodeGen/RegisterUsageInfo.h"
+#include "llvm/CodeGen/RenameIndependentSubregs.h"
#include "llvm/CodeGen/ReplaceWithVeclib.h"
#include "llvm/CodeGen/SafeStack.h"
#include "llvm/CodeGen/SelectOptimize.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 1d978f2ea31228..66e218c3a9f35e 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -165,6 +165,7 @@ MACHINE_FUNCTION_PASS("print",
VirtRegMapPrinterPass(errs()))
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("register-coalescer", RegisterCoalescerPass())
+MACHINE_FUNCTION_PASS("rename-independent-subregs",
RenameIndependentSubregsPass())
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass())
@@ -263,7 +264,6 @@ DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass",
RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
DUMMY_MACHINE_FUNCTION_PASS("remove-loads-into-fake-uses",
RemoveLoadsIntoFakeUsesPass)
DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues",
RemoveRedundantDebugValuesPass)
-DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs",
RenameIndependentSubregsPass)
DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass)
DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass)
DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 5f0c7ec9c8d018..d019
[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
@@ -1721,7 +1738,10 @@ ParseResult InvokeOp::parse(OpAsmParser &parser,
OperationState &result) {
return failure();
// Parse the trailing type list and resolve the function operands.
- if (parseCallTypeAndResolveOperands(parser, result, isDirect, operands))
+ SmallVector argAttrs;
+ SmallVector resultAttrs;
+ if (parseCallTypeAndResolveOperands(parser, result, isDirect, operands,
+ argAttrs, resultAttrs))
gysit wrote:
Should we call `addArgAndResultAttrs` here as above?
What is actually the status of the invoke. It seems it is not really supported
in this pr? If we fully want to support it there should probably be tests as
well.
https://github.com/llvm/llvm-project/pull/123177
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[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
@@ -0,0 +1,17 @@
+// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
+
+llvm.func @somefunc(i32, !llvm.ptr)
+
+// CHECK-LABEL: define void @test_call_arg_attrs_direct
+llvm.func @test_call_arg_attrs_direct(%arg0: i32, %arg1: !llvm.ptr) {
+ // CHECK: call void @somefunc(i32 %{{.*}}, ptr byval(i64) %{{.*}})
+ llvm.call @somefunc(%arg0, %arg1) : (i32, !llvm.ptr {llvm.byval = i64}) -> ()
+ llvm.return
+}
+
+// CHECK-LABEL: define i16 @test_call_arg_attrs_indirec
gysit wrote:
```suggestion
// CHECK-LABEL: define i16 @test_call_arg_attrs_indirect
```
ultra nit:
https://github.com/llvm/llvm-project/pull/123177
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[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
@@ -265,6 +265,27 @@ convertOperationImpl(Operation &opInst,
llvm::IRBuilderBase &builder,
if (callOp.getWillReturnAttr())
call->addFnAttr(llvm::Attribute::WillReturn);
+if (ArrayAttr argAttrsArray = callOp.getArgAttrsAttr())
+ for (auto [argIdx, argAttrsAttr] : llvm::enumerate(argAttrsArray)) {
gysit wrote:
```suggestion
if (ArrayAttr argAttrsArray = callOp.getArgAttrsAttr()) {
for (auto [argIdx, argAttrsAttr] : llvm::enumerate(argAttrsArray)) {
```
nit: missing braces
https://github.com/llvm/llvm-project/pull/123177
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[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
@@ -1596,6 +1603,23 @@ ModuleTranslation::convertParameterAttrs(LLVMFuncOp func, int argIdx, return attrBuilder; } +FailureOr +ModuleTranslation::convertParameterAttrs(CallOp, int argIdx, gysit wrote: ```suggestion ModuleTranslation::convertParameterAttrs(CallOp, ``` nit: It looks like the argIdx is unused? https://github.com/llvm/llvm-project/pull/123177 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
https://github.com/gysit commented: Nice! I did leave some comments assuming the base commit will land soon. https://github.com/llvm/llvm-project/pull/123177 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
https://github.com/gysit edited https://github.com/llvm/llvm-project/pull/123177 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [mlir] [mlir][LLVM] add argument and result attributes to llvm.call (PR #123177)
@@ -265,6 +265,27 @@ convertOperationImpl(Operation &opInst,
llvm::IRBuilderBase &builder,
if (callOp.getWillReturnAttr())
call->addFnAttr(llvm::Attribute::WillReturn);
+if (ArrayAttr argAttrsArray = callOp.getArgAttrsAttr())
+ for (auto [argIdx, argAttrsAttr] : llvm::enumerate(argAttrsArray)) {
+if (auto argAttrs = llvm::cast(argAttrsAttr)) {
+ FailureOr attrBuilder =
+ moduleTranslation.convertParameterAttrs(callOp, argIdx,
argAttrs);
+ if (failed(attrBuilder))
+return failure();
+ call->addParamAttrs(argIdx, *attrBuilder);
+}
+ }
+
+ArrayAttr resAttrsArray = callOp.getResAttrsAttr();
+if (resAttrsArray && resAttrsArray.size() == 1)
+ if (auto resAttrs = llvm::cast(resAttrsArray[0])) {
gysit wrote:
```suggestion
if (resAttrsArray && resAttrsArray.size() == 1) {
if (auto resAttrs = llvm::cast(resAttrsArray[0])) {
```
nit: missing braces
https://github.com/llvm/llvm-project/pull/123177
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[llvm-branch-commits] [llvm] [llvm] Extend CallSiteInfo with TypeId (PR #87574)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
.../CodeGen/MIR/X86/call-site-info-typeid.mir | 21 ++-
1 file changed, 6 insertions(+), 15 deletions(-)
diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
index 5ab797bfcc18f6..a99ee50a608fbc 100644
--- a/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
+++ b/llvm/test/CodeGen/MIR/X86/call-site-info-typeid.mir
@@ -8,11 +8,6 @@
# CHECK-NEXT: 123456789 }
--- |
- ; ModuleID = 'test.ll'
- source_filename = "test.ll"
- target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
- target triple = "x86_64-unknown-linux-gnu"
-
define dso_local void @foo(i8 signext %a) {
entry:
ret void
@@ -21,10 +16,10 @@
define dso_local i32 @main() {
entry:
%retval = alloca i32, align 4
-%fp = alloca void (i8)*, align 8
-store i32 0, i32* %retval, align 4
-store void (i8)* @foo, void (i8)** %fp, align 8
-%0 = load void (i8)*, void (i8)** %fp, align 8
+%fp = alloca ptr, align 8
+store i32 0, ptr %retval, align 4
+store ptr @foo, ptr %fp, align 8
+%0 = load ptr, ptr %fp, align 8
call void %0(i8 signext 97)
ret i32 0
}
@@ -42,12 +37,8 @@ body: |
name:main
tracksRegLiveness: true
stack:
- - { id: 0, name: retval, type: default, offset: 0, size: 4, alignment: 4,
- stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
- - { id: 1, name: fp, type: default, offset: 0, size: 8, alignment: 8,
- stack-id: default, callee-saved-register: '', callee-saved-restored:
true,
- debug-info-variable: '', debug-info-expression: '', debug-info-location:
'' }
+ - { id: 0, name: retval, size: 4, alignment: 4 }
+ - { id: 1, name: fp, size: 8, alignment: 8 }
callSites:
- { bb: 0, offset: 6, fwdArgRegs: [], typeId:
123456789 }
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[llvm-branch-commits] [clang] 1eb7f4e - release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (#125368)
Author: Hubert Tong Date: 2025-02-01T17:04:18-08:00 New Revision: 1eb7f4e6b46179be2388529261502318a802ec84 URL: https://github.com/llvm/llvm-project/commit/1eb7f4e6b46179be2388529261502318a802ec84 DIFF: https://github.com/llvm/llvm-project/commit/1eb7f4e6b46179be2388529261502318a802ec84.diff LOG: release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (#125368) #110503 updates the scope of `-fclang-abi-compat` but did not make that clear in the release notes. This PR addresses that problem. Added: Modified: clang/docs/ReleaseNotes.rst Removed: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 88c9fc8f95e4a1..53534d821b2c9a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -252,7 +252,7 @@ ABI Changes in This Version - Fixed Microsoft name mangling of placeholder, auto and decltype(auto), return types for MSVC 1920+. This change resolves incompatibilities with code compiled by MSVC 1920+ but will introduce incompatibilities with code compiled by earlier versions of Clang unless such code is built with the compiler option -fms-compatibility-version=19.14 to imitate the MSVC 1914 mangling behavior. - Fixed the Itanium mangling of the construction vtable name. This change will introduce incompatibilities with code compiled by Clang 19 and earlier versions, unless the -fclang-abi-compat=19 option is used. (#GH108015) -- Mangle member-like friend function templates as members of the enclosing class. (#GH110247, #GH110503) +- Mangle member-like friend function templates as members of the enclosing class. This can be disabled using -fclang-abi-compat=19. (#GH110247, #GH110503) AST Dumping Potentially Breaking Changes ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (PR #125368)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/125368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/20.x: [Clang][ReleaseNotes] Document -fclang-abi-compat=19 re: #110503 (PR #125368)
https://github.com/tstellar milestoned https://github.com/llvm/llvm-project/pull/125368 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/20.x: [libcxx] Use _ftelli64/_fseeki64 on Windows (#123128) (PR #124922)
https://github.com/llvmbot updated
https://github.com/llvm/llvm-project/pull/124922
>From d777df5cbd35b301826b2b1500b5eb02d56818d5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Storsj=C3=B6?=
Date: Wed, 29 Jan 2025 15:25:43 +0200
Subject: [PATCH] [libcxx] Use _ftelli64/_fseeki64 on Windows (#123128)
This allows using the full 64 bit range for file offsets.
This should fix the issue reported downstream at
https://github.com/mstorsjo/llvm-mingw/issues/462.
(cherry picked from commit 86e20b00c313e96db3b69d440bfb2ca9063f08f0)
---
libcxx/include/fstream| 55 ++-
.../ifstream.members/offset_range.pass.cpp| 6 --
2 files changed, 29 insertions(+), 32 deletions(-)
diff --git a/libcxx/include/fstream b/libcxx/include/fstream
index f0e9425e0a53d9..de5c07035dba9c 100644
--- a/libcxx/include/fstream
+++ b/libcxx/include/fstream
@@ -216,12 +216,6 @@ typedef basic_fstream wfstream;
_LIBCPP_PUSH_MACROS
# include <__undef_macros>
-# if !defined(_LIBCPP_MSVCRT) && !defined(_NEWLIB_VERSION)
-#define _LIBCPP_HAS_OFF_T_FUNCTIONS 1
-# else
-#define _LIBCPP_HAS_OFF_T_FUNCTIONS 0
-# endif
-
# if _LIBCPP_HAS_FILESYSTEM && _LIBCPP_HAS_LOCALIZATION
_LIBCPP_BEGIN_NAMESPACE_STD
@@ -362,6 +356,9 @@ private:
bool __read_mode();
void __write_mode();
+ _LIBCPP_HIDE_FROM_ABI static int __fseek(FILE* __file, pos_type __offset,
int __whence);
+ _LIBCPP_HIDE_FROM_ABI static pos_type __ftell(FILE* __file);
+
_LIBCPP_EXPORTED_FROM_ABI friend FILE* __get_ostream_file(ostream&);
// There are multiple (__)open function, they use different C-API open
@@ -936,31 +933,42 @@ basic_filebuf<_CharT, _Traits>::seekoff(off_type __off,
ios_base::seekdir __way,
default:
return pos_type(off_type(-1));
}
-#if !_LIBCPP_HAS_OFF_T_FUNCTIONS
- if (fseek(__file_, __width > 0 ? __width * __off : 0, __whence))
+ if (__fseek(__file_, __width > 0 ? __width * __off : 0, __whence))
return pos_type(off_type(-1));
- pos_type __r = ftell(__file_);
-#else
- if (::fseeko(__file_, __width > 0 ? __width * __off : 0, __whence))
-return pos_type(off_type(-1));
- pos_type __r = ftello(__file_);
-#endif
+ pos_type __r = __ftell(__file_);
__r.state(__st_);
return __r;
}
+template
+int basic_filebuf<_CharT, _Traits>::__fseek(FILE* __file, pos_type __offset,
int __whence) {
+#if defined(_LIBCPP_MSVCRT_LIKE)
+ return _fseeki64(__file, __offset, __whence);
+#elif defined(_NEWLIB_VERSION)
+ return fseek(__file, __offset, __whence);
+#else
+ return ::fseeko(__file, __offset, __whence);
+#endif
+}
+
+template
+typename basic_filebuf<_CharT, _Traits>::pos_type basic_filebuf<_CharT,
_Traits>::__ftell(FILE* __file) {
+#if defined(_LIBCPP_MSVCRT_LIKE)
+ return _ftelli64(__file);
+#elif defined(_NEWLIB_VERSION)
+ return ftell(__file);
+#else
+ return ftello(__file);
+#endif
+}
+
template
typename basic_filebuf<_CharT, _Traits>::pos_type
basic_filebuf<_CharT, _Traits>::seekpos(pos_type __sp, ios_base::openmode) {
if (__file_ == nullptr || sync())
return pos_type(off_type(-1));
-#if !_LIBCPP_HAS_OFF_T_FUNCTIONS
- if (fseek(__file_, __sp, SEEK_SET))
+ if (__fseek(__file_, __sp, SEEK_SET))
return pos_type(off_type(-1));
-#else
- if (::fseeko(__file_, __sp, SEEK_SET))
-return pos_type(off_type(-1));
-#endif
__st_ = __sp.state();
return __sp;
}
@@ -1007,13 +1015,8 @@ int basic_filebuf<_CharT, _Traits>::sync() {
}
}
}
-#if !_LIBCPP_HAS_OFF_T_FUNCTIONS
-if (fseek(__file_, -__c, SEEK_CUR))
+if (__fseek(__file_, -__c, SEEK_CUR))
return -1;
-#else
-if (::fseeko(__file_, -__c, SEEK_CUR))
- return -1;
-#endif
if (__update_st)
__st_ = __state;
__extbufnext_ = __extbufend_ = __extbuf_;
diff --git
a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
index 6ffe750564c2c9..c6e07d045e1458 100644
---
a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
+++
b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
@@ -11,12 +11,6 @@
// Test that we can seek using offsets larger than 32 bit, and that we can
// retrieve file offsets larger than 32 bit.
-// On MSVC targets, we only use the 32 bit fseek/ftell functions. For MinGW
-// targets, we use fseeko/ftello, but the user needs to define
-// _FILE_OFFSET_BITS=64 to make them 64 bit.
-//
-// XFAIL: target={{.*}}-windows{{.*}}
-
// On 32 bit Android platforms, off_t is 32 bit by default. By defining
// _FILE_OFFSET_BITS=64, one gets a 64 bit off_t, but the corresponding
// 64 bit ftello/fseeko functions are only available since Android API 24
(7.0).
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[llvm-branch-commits] [libcxx] d777df5 - [libcxx] Use _ftelli64/_fseeki64 on Windows (#123128)
Author: Martin Storsjö
Date: 2025-02-01T13:32:39-08:00
New Revision: d777df5cbd35b301826b2b1500b5eb02d56818d5
URL:
https://github.com/llvm/llvm-project/commit/d777df5cbd35b301826b2b1500b5eb02d56818d5
DIFF:
https://github.com/llvm/llvm-project/commit/d777df5cbd35b301826b2b1500b5eb02d56818d5.diff
LOG: [libcxx] Use _ftelli64/_fseeki64 on Windows (#123128)
This allows using the full 64 bit range for file offsets.
This should fix the issue reported downstream at
https://github.com/mstorsjo/llvm-mingw/issues/462.
(cherry picked from commit 86e20b00c313e96db3b69d440bfb2ca9063f08f0)
Added:
Modified:
libcxx/include/fstream
libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
Removed:
diff --git a/libcxx/include/fstream b/libcxx/include/fstream
index f0e9425e0a53d9..de5c07035dba9c 100644
--- a/libcxx/include/fstream
+++ b/libcxx/include/fstream
@@ -216,12 +216,6 @@ typedef basic_fstream wfstream;
_LIBCPP_PUSH_MACROS
# include <__undef_macros>
-# if !defined(_LIBCPP_MSVCRT) && !defined(_NEWLIB_VERSION)
-#define _LIBCPP_HAS_OFF_T_FUNCTIONS 1
-# else
-#define _LIBCPP_HAS_OFF_T_FUNCTIONS 0
-# endif
-
# if _LIBCPP_HAS_FILESYSTEM && _LIBCPP_HAS_LOCALIZATION
_LIBCPP_BEGIN_NAMESPACE_STD
@@ -362,6 +356,9 @@ private:
bool __read_mode();
void __write_mode();
+ _LIBCPP_HIDE_FROM_ABI static int __fseek(FILE* __file, pos_type __offset,
int __whence);
+ _LIBCPP_HIDE_FROM_ABI static pos_type __ftell(FILE* __file);
+
_LIBCPP_EXPORTED_FROM_ABI friend FILE* __get_ostream_file(ostream&);
// There are multiple (__)open function, they use
diff erent C-API open
@@ -936,31 +933,42 @@ basic_filebuf<_CharT, _Traits>::seekoff(off_type __off,
ios_base::seekdir __way,
default:
return pos_type(off_type(-1));
}
-#if !_LIBCPP_HAS_OFF_T_FUNCTIONS
- if (fseek(__file_, __width > 0 ? __width * __off : 0, __whence))
+ if (__fseek(__file_, __width > 0 ? __width * __off : 0, __whence))
return pos_type(off_type(-1));
- pos_type __r = ftell(__file_);
-#else
- if (::fseeko(__file_, __width > 0 ? __width * __off : 0, __whence))
-return pos_type(off_type(-1));
- pos_type __r = ftello(__file_);
-#endif
+ pos_type __r = __ftell(__file_);
__r.state(__st_);
return __r;
}
+template
+int basic_filebuf<_CharT, _Traits>::__fseek(FILE* __file, pos_type __offset,
int __whence) {
+#if defined(_LIBCPP_MSVCRT_LIKE)
+ return _fseeki64(__file, __offset, __whence);
+#elif defined(_NEWLIB_VERSION)
+ return fseek(__file, __offset, __whence);
+#else
+ return ::fseeko(__file, __offset, __whence);
+#endif
+}
+
+template
+typename basic_filebuf<_CharT, _Traits>::pos_type basic_filebuf<_CharT,
_Traits>::__ftell(FILE* __file) {
+#if defined(_LIBCPP_MSVCRT_LIKE)
+ return _ftelli64(__file);
+#elif defined(_NEWLIB_VERSION)
+ return ftell(__file);
+#else
+ return ftello(__file);
+#endif
+}
+
template
typename basic_filebuf<_CharT, _Traits>::pos_type
basic_filebuf<_CharT, _Traits>::seekpos(pos_type __sp, ios_base::openmode) {
if (__file_ == nullptr || sync())
return pos_type(off_type(-1));
-#if !_LIBCPP_HAS_OFF_T_FUNCTIONS
- if (fseek(__file_, __sp, SEEK_SET))
+ if (__fseek(__file_, __sp, SEEK_SET))
return pos_type(off_type(-1));
-#else
- if (::fseeko(__file_, __sp, SEEK_SET))
-return pos_type(off_type(-1));
-#endif
__st_ = __sp.state();
return __sp;
}
@@ -1007,13 +1015,8 @@ int basic_filebuf<_CharT, _Traits>::sync() {
}
}
}
-#if !_LIBCPP_HAS_OFF_T_FUNCTIONS
-if (fseek(__file_, -__c, SEEK_CUR))
+if (__fseek(__file_, -__c, SEEK_CUR))
return -1;
-#else
-if (::fseeko(__file_, -__c, SEEK_CUR))
- return -1;
-#endif
if (__update_st)
__st_ = __state;
__extbufnext_ = __extbufend_ = __extbuf_;
diff --git
a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
index 6ffe750564c2c9..c6e07d045e1458 100644
---
a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
+++
b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/offset_range.pass.cpp
@@ -11,12 +11,6 @@
// Test that we can seek using offsets larger than 32 bit, and that we can
// retrieve file offsets larger than 32 bit.
-// On MSVC targets, we only use the 32 bit fseek/ftell functions. For MinGW
-// targets, we use fseeko/ftello, but the user needs to define
-// _FILE_OFFSET_BITS=64 to make them 64 bit.
-//
-// XFAIL: target={{.*}}-windows{{.*}}
-
// On 32 bit Android platforms, off_t is 32 bit by default. By defining
// _FILE_OFFSET_BITS=64, one gets a 64 bit off_t, but the corresponding
// 64 bit ftello/fseeko functions are only available since Android A
[llvm-branch-commits] [libcxx] release/20.x: [libcxx] Use _ftelli64/_fseeki64 on Windows (#123128) (PR #124922)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/124922 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/20.x: [libcxx] Use _ftelli64/_fseeki64 on Windows (#123128) (PR #124922)
github-actions[bot] wrote: @mstorsjo (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/124922 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Set version to 20.1.0-rc1 (PR #125367)
https://github.com/tstellar created https://github.com/llvm/llvm-project/pull/125367 None >From 2c9a2bdf98b82410a3a0df7995a3c21fb15e2c30 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 1 Feb 2025 15:05:51 -0800 Subject: [PATCH] Set version to 20.1.0-rc1 --- cmake/Modules/LLVMVersion.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/Modules/LLVMVersion.cmake b/cmake/Modules/LLVMVersion.cmake index 281d0444255bac7..fd7cc0868aa3cd3 100644 --- a/cmake/Modules/LLVMVersion.cmake +++ b/cmake/Modules/LLVMVersion.cmake @@ -10,6 +10,6 @@ if(NOT DEFINED LLVM_VERSION_PATCH) set(LLVM_VERSION_PATCH 0) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) - set(LLVM_VERSION_SUFFIX git) + set(LLVM_VERSION_SUFFIX -rc1) endif() ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Set version to 20.1.0-rc1 (PR #125367)
github-actions[bot] wrote: @tstellar (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/125367 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Set version to 20.1.0-rc1 (PR #125367)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/125367 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [SPARC][IAS] Add IAS flag handling for ISA levels (PR #125151)
brad0 wrote: @MaskRay https://github.com/llvm/llvm-project/pull/125151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [llvm] Extract and propagate indirect call type id (PR #87575)
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH] Fixed the tests and addressed most of the review comments.
Created using spr 1.3.6-beta.1
---
llvm/include/llvm/CodeGen/MachineFunction.h | 15 +++--
.../CodeGen/AArch64/call-site-info-typeid.ll | 28 +++--
.../test/CodeGen/ARM/call-site-info-typeid.ll | 28 +++--
.../CodeGen/MIR/X86/call-site-info-typeid.ll | 58 ---
.../CodeGen/MIR/X86/call-site-info-typeid.mir | 13 ++---
.../CodeGen/Mips/call-site-info-typeid.ll | 28 +++--
.../test/CodeGen/X86/call-site-info-typeid.ll | 28 +++--
7 files changed, 71 insertions(+), 127 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index bb0b87a3a04a37..44633df38a6516 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -493,7 +493,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
/// Callee type id.
ConstantInt *TypeId = nullptr;
-CallSiteInfo() {}
+CallSiteInfo() = default;
/// Extracts the numeric type id from the CallBase's type operand bundle,
/// and sets TypeId. This is used as type id for the indirect call in the
@@ -503,12 +503,11 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
if (!CB.isIndirectCall())
return;
- auto Opt = CB.getOperandBundle(LLVMContext::OB_type);
- if (!Opt.has_value()) {
-errs() << "warning: cannot find indirect call type operand bundle for
"
- "call graph section\n";
+ std::optional Opt =
+ CB.getOperandBundle(LLVMContext::OB_type);
+ // Return if the operand bundle for call graph section cannot be found.
+ if (!Opt.has_value())
return;
- }
// Get generalized type id string
auto OB = Opt.value();
@@ -520,9 +519,9 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
"invalid type identifier");
// Compute numeric type id from generalized type id string
- uint64_t TypeIdVal = llvm::MD5Hash(TypeIdStr->getString());
+ uint64_t TypeIdVal = MD5Hash(TypeIdStr->getString());
IntegerType *Int64Ty = Type::getInt64Ty(CB.getContext());
- TypeId = llvm::ConstantInt::get(Int64Ty, TypeIdVal, /*IsSigned=*/false);
+ TypeId = ConstantInt::get(Int64Ty, TypeIdVal, /*IsSigned=*/false);
}
};
diff --git a/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
b/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
index f0a6b44755c5c8..f3b98c2c7a395d 100644
--- a/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
+++ b/llvm/test/CodeGen/AArch64/call-site-info-typeid.ll
@@ -1,14 +1,9 @@
-; Tests that call site type ids can be extracted and set from type operand
-; bundles.
+;; Tests that call site type ids can be extracted and set from type operand
+;; bundles.
-; Verify the exact typeId value to ensure it is not garbage but the value
-; computed as the type id from the type operand bundle.
-; RUN: llc --call-graph-section -mtriple aarch64-linux-gnu %s
-stop-before=finalize-isel -o - | FileCheck %s
-
-; ModuleID = 'test.c'
-source_filename = "test.c"
-target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-target triple = "aarch64-unknown-linux-gnu"
+;; Verify the exact typeId value to ensure it is not garbage but the value
+;; computed as the type id from the type operand bundle.
+; RUN: llc --call-graph-section -mtriple aarch64-linux-gnu < %s
-stop-before=finalize-isel -o - | FileCheck %s
define dso_local void @foo(i8 signext %a) !type !3 {
entry:
@@ -19,10 +14,10 @@ entry:
define dso_local i32 @main() !type !4 {
entry:
%retval = alloca i32, align 4
- %fp = alloca void (i8)*, align 8
- store i32 0, i32* %retval, align 4
- store void (i8)* @foo, void (i8)** %fp, align 8
- %0 = load void (i8)*, void (i8)** %fp, align 8
+ %fp = alloca ptr, align 8
+ store i32 0, ptr %retval, align 4
+ store ptr @foo, ptr %fp, align 8
+ %0 = load ptr, ptr %fp, align 8
; CHECK: callSites:
; CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: [], typeId:
; CHECK-NEXT: 7854600665770582568 }
@@ -30,10 +25,5 @@ entry:
ret i32 0
}
-!llvm.module.flags = !{!0, !1, !2}
-
-!0 = !{i32 1, !"wchar_size", i32 4}
-!1 = !{i32 7, !"uwtable", i32 1}
-!2 = !{i32 7, !"frame-pointer", i32 2}
!3 = !{i64 0, !"_ZTSFvcE.generalized"}
!4 = !{i64 0, !"_ZTSFiE.generalized"}
diff --git a/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
b/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
index ec7f8a425051b8..9feeef9a564cc4 100644
--- a/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
+++ b/llvm/test/CodeGen/ARM/call-site-info-typeid.ll
@@ -1,14 +1,9 @@
-; Tests that call site type ids can be extracted and set from type operand
-; bundles.
+;; Tests that c
[llvm-branch-commits] [SPARC][IAS] Add support for `setsw` pseudoinstruction (PR #125150)
@@ -734,6 +737,69 @@ bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
return false;
}
+bool SparcAsmParser::expandSETSW(MCInst &Inst, SMLoc IDLoc,
+ SmallVectorImpl &Instructions) {
+ MCOperand MCRegOp = Inst.getOperand(0);
+ MCOperand MCValOp = Inst.getOperand(1);
+ assert(MCRegOp.isReg());
+ assert(MCValOp.isImm() || MCValOp.isExpr());
+
+ // the imm operand can be either an expression or an immediate.
+ bool IsImm = Inst.getOperand(1).isImm();
+ int64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
+ const MCExpr *ValExpr = IsImm ? MCConstantExpr::create(ImmValue,
getContext())
+: MCValOp.getExpr();
+
+ bool IsSmallImm = IsImm && isInt<13>(ImmValue);
s-barannikov wrote:
You're right, sorry
https://github.com/llvm/llvm-project/pull/125150
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