[llvm-branch-commits] [llvm-branch] r293070 - Merging r292444:
Author: hans
Date: Wed Jan 25 10:57:43 2017
New Revision: 293070
URL: http://llvm.org/viewvc/llvm-project?rev=293070&view=rev
Log:
Merging r292444:
r292444 | mkuper | 2017-01-18 15:05:58 -0800 (Wed, 18 Jan 2017) | 7 lines
Revert r291670 because it introduces a crash.
r291670 doesn't crash on the original testcase from PR31589,
but it crashes on a slightly more complex one.
PR31589 has the new reproducer.
Modified:
llvm/branches/release_40/ (props changed)
llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_40/test/CodeGen/X86/avx-trunc.ll
llvm/branches/release_40/test/CodeGen/X86/avx512-trunc.ll
Propchange: llvm/branches/release_40/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 25 10:57:43 2017
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,291858-291859,291863,291875,291909,291966,291968,291979,292133,292242,292254-292255,292280,292323,292467,292583,292625,292641,292667,292711,292758
+/llvm/trunk:155241,291858-291859,291863,291875,291909,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292583,292625,292641,292667,292711,292758
Modified: llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp?rev=293070&r1=293069&r2=293070&view=diff
==
--- llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_40/lib/Target/X86/X86ISelLowering.cpp Wed Jan 25
10:57:43 2017
@@ -31272,93 +31272,6 @@ static SDValue foldVectorXorShiftIntoCmp
return DAG.getNode(X86ISD::PCMPGT, SDLoc(N), VT, Shift.getOperand(0), Ones);
}
-/// Check if truncation with saturation form type \p SrcVT to \p DstVT
-/// is valid for the given \p Subtarget.
-static bool isSATValidOnAVX512Subtarget(EVT SrcVT, EVT DstVT,
-const X86Subtarget &Subtarget) {
- if (!Subtarget.hasAVX512())
-return false;
-
- // FIXME: Scalar type may be supported if we move it to vector register.
- if (!SrcVT.isVector() || !SrcVT.isSimple() || SrcVT.getSizeInBits() > 512)
-return false;
-
- EVT SrcElVT = SrcVT.getScalarType();
- EVT DstElVT = DstVT.getScalarType();
- if (SrcElVT.getSizeInBits() < 16 || SrcElVT.getSizeInBits() > 64)
-return false;
- if (DstElVT.getSizeInBits() < 8 || DstElVT.getSizeInBits() > 32)
-return false;
- if (SrcVT.is512BitVector() || Subtarget.hasVLX())
-return SrcElVT.getSizeInBits() >= 32 || Subtarget.hasBWI();
- return false;
-}
-
-/// Return true if VPACK* instruction can be used for the given types
-/// and it is avalable on \p Subtarget.
-static bool
-isSATValidOnSSESubtarget(EVT SrcVT, EVT DstVT, const X86Subtarget &Subtarget) {
- if (Subtarget.hasSSE2())
-// v16i16 -> v16i8
-if (SrcVT == MVT::v16i16 && DstVT == MVT::v16i8)
- return true;
- if (Subtarget.hasSSE41())
-// v8i32 -> v8i16
-if (SrcVT == MVT::v8i32 && DstVT == MVT::v8i16)
- return true;
- return false;
-}
-
-/// Detect a pattern of truncation with saturation:
-/// (truncate (umin (x, unsigned_max_of_dest_type)) to dest_type).
-/// Return the source value to be truncated or SDValue() if the pattern was not
-/// matched.
-static SDValue detectUSatPattern(SDValue In, EVT VT) {
- if (In.getOpcode() != ISD::UMIN)
-return SDValue();
-
- //Saturation with truncation. We truncate from InVT to VT.
- assert(In.getScalarValueSizeInBits() > VT.getScalarSizeInBits() &&
-"Unexpected types for truncate operation");
-
- APInt C;
- if (ISD::isConstantSplatVector(In.getOperand(1).getNode(), C)) {
-// C should be equal to UINT32_MAX / UINT16_MAX / UINT8_MAX according
-// the element size of the destination type.
-return APIntOps::isMask(VT.getScalarSizeInBits(), C) ? In.getOperand(0) :
- SDValue();
- }
- return SDValue();
-}
-
-/// Detect a pattern of truncation with saturation:
-/// (truncate (umin (x, unsigned_max_of_dest_type)) to dest_type).
-/// The types should allow to use VPMOVUS* instruction on AVX512.
-/// Return the source value to be truncated or SDValue() if the pattern was not
-/// matched.
-static SDValue detectAVX512USatPattern(SDValue In, EVT VT,
- const X86Subtarget &Subtarget) {
- if (!isSATValidOnAVX512Subtarget(In.getValueType(), VT, Subtarget))
-return SDValue();
- return detectUSatPattern(In, VT);
-}
-
-static SDValue
-combineTruncateWithUSat(SDValue In, EVT VT, SDLoc &DL, SelectionDAG &DAG,
-const X86Subtarget &Subtarget) {
- SDValue USatVal = detectUSatPattern(In, V
[llvm-branch-commits] [cfe-branch] r293072 - Merging r292991:
Author: hans
Date: Wed Jan 25 11:04:26 2017
New Revision: 293072
URL: http://llvm.org/viewvc/llvm-project?rev=293072&view=rev
Log:
Merging r292991:
r292991 | rsmith | 2017-01-24 15:18:28 -0800 (Tue, 24 Jan 2017) | 3 lines
PR31742: Don't emit a bogus "zero size array" extwarn when initializing a
runtime-sized array from an empty list in an array new.
Modified:
cfe/branches/release_40/ (props changed)
cfe/branches/release_40/lib/Sema/SemaInit.cpp
cfe/branches/release_40/test/SemaCXX/new-delete-cxx0x.cpp
Propchange: cfe/branches/release_40/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 25 11:04:26 2017
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:291850,291853,291865,291871,291877,291879,291881,291907,291955,291964,292032,292052,292183,292247,292265,292497,292555,292558-292559,292800,292847,292874
+/cfe/trunk:291850,291853,291865,291871,291877,291879,291881,291907,291955,291964,292032,292052,292183,292247,292265,292497,292555,292558-292559,292800,292847,292874,292991
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_40/lib/Sema/SemaInit.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_40/lib/Sema/SemaInit.cpp?rev=293072&r1=293071&r2=293072&view=diff
==
--- cfe/branches/release_40/lib/Sema/SemaInit.cpp (original)
+++ cfe/branches/release_40/lib/Sema/SemaInit.cpp Wed Jan 25 11:04:26 2017
@@ -1684,7 +1684,7 @@ void InitListChecker::CheckArrayType(con
// If this is an incomplete array type, the actual type needs to
// be calculated here.
llvm::APSInt Zero(maxElements.getBitWidth(), maxElements.isUnsigned());
-if (maxElements == Zero) {
+if (maxElements == Zero && !Entity.isVariableLengthArrayNew()) {
// Sizing an array implicitly to zero is not allowed by ISO C,
// but is supported by GNU.
SemaRef.Diag(IList->getLocStart(),
Modified: cfe/branches/release_40/test/SemaCXX/new-delete-cxx0x.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_40/test/SemaCXX/new-delete-cxx0x.cpp?rev=293072&r1=293071&r2=293072&view=diff
==
--- cfe/branches/release_40/test/SemaCXX/new-delete-cxx0x.cpp (original)
+++ cfe/branches/release_40/test/SemaCXX/new-delete-cxx0x.cpp Wed Jan 25
11:04:26 2017
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsyntax-only -verify %s -std=c++11
-triple=i686-pc-linux-gnu
+// RUN: %clang_cc1 -fsyntax-only -verify %s -std=c++11
-triple=i686-pc-linux-gnu -pedantic
void ugly_news(int *ip) {
(void)new int[-1]; // expected-error {{array size is negative}}
@@ -29,6 +29,7 @@ void fn(int n) {
(void) new int[2] {1, 2};
(void) new S[2] {1, 2};
(void) new S[3] {1, 2};
+ (void) new S[n] {};
// C++11 [expr.new]p19:
// If the new-expression creates an object or an array of objects of class
// type, access and ambiguity control are done for the allocation function,
@@ -44,6 +45,7 @@ void fn(int n) {
(void) new T[2] {1, 2}; // ok
(void) new T[3] {1, 2}; // expected-error {{no matching constructor}}
expected-note {{in implicit initialization of array element 2}}
(void) new T[n] {1, 2}; // expected-error {{no matching constructor}}
expected-note {{in implicit initialization of trailing array elements in
runtime-sized array new}}
+ (void) new T[n] {}; // expected-error {{no matching constructor}}
expected-note {{in implicit initialization of trailing array elements in
runtime-sized array new}}
}
struct U {
___
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[llvm-branch-commits] [llvm-branch] r293074 - Merging r293025:
Author: hans
Date: Wed Jan 25 11:14:48 2017
New Revision: 293074
URL: http://llvm.org/viewvc/llvm-project?rev=293074&view=rev
Log:
Merging r293025:
r293025 | ahatanak | 2017-01-24 22:21:51 -0800 (Tue, 24 Jan 2017) | 29 lines
[SimplifyCFG] Do not sink and merge inline-asm instructions.
Conservatively disable sinking and merging inline-asm instructions as doing so
can potentially create arguments that cannot satisfy the inline-asm constraints.
For example, SimplifyCFG used to do the following transformation:
(before)
if.then:
%0 = call i32 asm "rorl $2, $0", "=&r,0,n"(i32 %r6, i32 8)
br label %if.end
if.else:
%1 = call i32 asm "rorl $2, $0", "=&r,0,n"(i32 %r6, i32 6)
br label %if.end
(after)
%.sink = select i1 %tobool, i32 6, i32 8
%0 = call i32 asm "rorl $2, $0", "=&r,0,n"(i32 %r6, i32 %.sink)
This would result in a crash in the backend since only immediate integer
operands
are permitted for constraint "n".
rdar://problem/30110806
Differential Revision: https://reviews.llvm.org/D29111
Modified:
llvm/branches/release_40/ (props changed)
llvm/branches/release_40/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/branches/release_40/test/Transforms/SimplifyCFG/sink-common-code.ll
Propchange: llvm/branches/release_40/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 25 11:14:48 2017
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,291858-291859,291863,291875,291909,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292583,292625,292641,292667,292711,292758
+/llvm/trunk:155241,291858-291859,291863,291875,291909,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292583,292625,292641,292667,292711,292758,293025
Modified: llvm/branches/release_40/lib/Transforms/Utils/SimplifyCFG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Transforms/Utils/SimplifyCFG.cpp?rev=293074&r1=293073&r2=293074&view=diff
==
--- llvm/branches/release_40/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/branches/release_40/lib/Transforms/Utils/SimplifyCFG.cpp Wed Jan 25
11:14:48 2017
@@ -1436,6 +1436,14 @@ static bool canSinkInstructions(
if (isa(I) || I->isEHPad() || isa(I) ||
I->getType()->isTokenTy())
return false;
+
+// Conservatively return false if I is an inline-asm instruction. Sinking
+// and merging inline-asm instructions can potentially create arguments
+// that cannot satisfy the inline-asm constraints.
+if (const auto *C = dyn_cast(I))
+ if (C->isInlineAsm())
+return false;
+
// Everything must have only one use too, apart from stores which
// have no uses.
if (!isa(I) && !I->hasOneUse())
Modified:
llvm/branches/release_40/test/Transforms/SimplifyCFG/sink-common-code.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/Transforms/SimplifyCFG/sink-common-code.ll?rev=293074&r1=293073&r2=293074&view=diff
==
--- llvm/branches/release_40/test/Transforms/SimplifyCFG/sink-common-code.ll
(original)
+++ llvm/branches/release_40/test/Transforms/SimplifyCFG/sink-common-code.ll
Wed Jan 25 11:14:48 2017
@@ -768,6 +768,30 @@ if.end:
; CHECK-NOT: exact
; CHECK: }
+; Check that simplifycfg doesn't sink and merge inline-asm instructions.
+
+define i32 @test_inline_asm1(i32 %c, i32 %r6) {
+entry:
+ %tobool = icmp eq i32 %c, 0
+ br i1 %tobool, label %if.else, label %if.then
+
+if.then:
+ %0 = call i32 asm "rorl $2, $0", "=&r,0,n,~{dirflag},~{fpsr},~{flags}"(i32
%r6, i32 8)
+ br label %if.end
+
+if.else:
+ %1 = call i32 asm "rorl $2, $0", "=&r,0,n,~{dirflag},~{fpsr},~{flags}"(i32
%r6, i32 6)
+ br label %if.end
+
+if.end:
+ %r6.addr.0 = phi i32 [ %0, %if.then ], [ %1, %if.else ]
+ ret i32 %r6.addr.0
+}
+
+; CHECK-LABEL: @test_inline_asm1(
+; CHECK: call i32 asm "rorl $2, $0", "=&r,0,n,~{dirflag},~{fpsr},~{flags}"(i32
%r6, i32 8)
+; CHECK: call i32 asm "rorl $2, $0", "=&r,0,n,~{dirflag},~{fpsr},~{flags}"(i32
%r6, i32 6)
+
declare i32 @call_target()
define void @test_operand_bundles(i1 %cond, i32* %ptr) {
___
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[llvm-branch-commits] [llvm-branch] r293103 - Merging rr293088:
Author: tnorthover
Date: Wed Jan 25 16:10:07 2017
New Revision: 293103
URL: http://llvm.org/viewvc/llvm-project?rev=293103&view=rev
Log:
Merging rr293088:
r293088 | tnorthover | 2017-01-25 12:58:26 -0800 (Wed, 25 Jan 2017) | 5 lines
SDag: fix how initial loads are formed when splitting vector ops.
Later code expects the vector loads produced to be directly
concatenable, which means we shouldn't pad anything except the last load
produced with UNDEF.
Modified:
llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll
Modified:
llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=293103&r1=293102&r2=293103&view=diff
==
--- llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
(original)
+++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Wed Jan 25 16:10:07 2017
@@ -3439,7 +3439,10 @@ SDValue DAGTypeLegalizer::GenWidenVector
LD->getPointerInfo().getWithOffset(Offset),
MinAlign(Align, Increment), MMOFlags, AAInfo);
LdChain.push_back(L.getValue(1));
- if (L->getValueType(0).isVector()) {
+ if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
+// Later code assumes the vector loads produced will be mergeable, so
we
+// must pad the final entry up to the previous width. Scalars are
+// combined separately.
SmallVector Loads;
Loads.push_back(L);
unsigned size = L->getValueSizeInBits(0);
Modified: llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll?rev=293103&r1=293102&r2=293103&view=diff
==
--- llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll (original)
+++ llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll Wed Jan 25
16:10:07 2017
@@ -251,3 +251,13 @@ define <4 x i32> @zextload_v8i8tov8i32_f
%zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA
}
+
+; CHECK-LABEL: test_silly_load:
+; CHECK: ldr {{r[0-9]+}}, [r0, #24]
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:128]!
+; CHECK: vldr d{{[0-9]+}}, [r0]
+
+define void @test_silly_load(<28 x i8>* %addr) {
+ load volatile <28 x i8>, <28 x i8>* %addr
+ ret void
+}
___
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[llvm-branch-commits] [llvm-branch] r293118 - Merging r292651:
Author: hans
Date: Wed Jan 25 18:26:36 2017
New Revision: 293118
URL: http://llvm.org/viewvc/llvm-project?rev=293118&view=rev
Log:
Merging r292651:
r292651 | jvesely | 2017-01-20 13:24:26 -0800 (Fri, 20 Jan 2017) | 8 lines
AMDGPU/R600: Serialize vector trunc stores to private AS
Add DUMMY_CHAIN SDNode to denote stores of interest
Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=28915
Bugzilla: https://llvm.org/bugs/show_bug.cgi?id=30411
Differential Revision: https://reviews.llvm.org/D27964
Modified:
llvm/branches/release_40/ (props changed)
llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.h
llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUInstrInfo.td
llvm/branches/release_40/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/branches/release_40/lib/Target/AMDGPU/R600Instructions.td
llvm/branches/release_40/test/CodeGen/AMDGPU/load-local-i8.ll
Propchange: llvm/branches/release_40/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 25 18:26:36 2017
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,291858-291859,291863,291875,291909,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292583,292625,292641,292667,292711,292758,293025
+/llvm/trunk:155241,291858-291859,291863,291875,291909,291966,291968,291979,292133,292242,292254-292255,292280,292323,292444,292467,292583,292625,292641,292651,292667,292711,292758,293025
Modified: llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=293118&r1=293117&r2=293118&view=diff
==
--- llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Wed Jan
25 18:26:36 2017
@@ -3272,6 +3272,7 @@ const char* AMDGPUTargetLowering::getTar
NODE_NAME_CASE(CONST_DATA_PTR)
NODE_NAME_CASE(PC_ADD_REL_OFFSET)
NODE_NAME_CASE(KILL)
+ NODE_NAME_CASE(DUMMY_CHAIN)
case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
NODE_NAME_CASE(SENDMSG)
NODE_NAME_CASE(SENDMSGHALT)
Modified: llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.h?rev=293118&r1=293117&r2=293118&view=diff
==
--- llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.h (original)
+++ llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUISelLowering.h Wed Jan 25
18:26:36 2017
@@ -320,6 +320,7 @@ enum NodeType : unsigned {
INTERP_P2,
PC_ADD_REL_OFFSET,
KILL,
+ DUMMY_CHAIN,
FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
STORE_MSKOR,
LOAD_CONSTANT,
Modified: llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUInstrInfo.td?rev=293118&r1=293117&r2=293118&view=diff
==
--- llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUInstrInfo.td (original)
+++ llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUInstrInfo.td Wed Jan 25
18:26:36 2017
@@ -54,6 +54,9 @@ def AMDGPUconstdata_ptr : SDNode<
// This argument to this node is a dword address.
def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
+// Force dependencies for vector trunc stores
+def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone,
[SDNPHasChain]>;
+
def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
Modified: llvm/branches/release_40/lib/Target/AMDGPU/R600ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=293118&r1=293117&r2=293118&view=diff
==
--- llvm/branches/release_40/lib/Target/AMDGPU/R600ISelLowering.cpp (original)
+++ llvm/branches/release_40/lib/Target/AMDGPU/R600ISelLowering.cpp Wed Jan 25
18:26:36 2017
@@ -1115,7 +1115,10 @@ SDValue R600TargetLowering::lowerPrivate
llvm_unreachable("Unsupported private trunc store");
}
- SDValue Chain = Store->getChain();
+ SDValue OldChain = Store->getChain();
+ bool VectorTrunc = (OldChain.getOpcode() == AMDGPUISD::DUMMY_CHAIN);
+ // Skip dummy
+ SDValue Chain = VectorTrunc ? OldChain->getOperand(0) : OldChain;
SDValue BasePtr = Store-
