Author: tnorthover
Date: Wed Jan 25 16:10:07 2017
New Revision: 293103
URL: http://llvm.org/viewvc/llvm-project?rev=293103&view=rev
Log:
Merging rr293088:
------------------------------------------------------------------------
r293088 | tnorthover | 2017-01-25 12:58:26 -0800 (Wed, 25 Jan 2017) | 5 lines
SDag: fix how initial loads are formed when splitting vector ops.
Later code expects the vector loads produced to be directly
concatenable, which means we shouldn't pad anything except the last load
produced with UNDEF.
------------------------------------------------------------------------
Modified:
llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll
Modified:
llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=293103&r1=293102&r2=293103&view=diff
==============================================================================
--- llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
(original)
+++ llvm/branches/release_40/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Wed Jan 25 16:10:07 2017
@@ -3439,7 +3439,10 @@ SDValue DAGTypeLegalizer::GenWidenVector
LD->getPointerInfo().getWithOffset(Offset),
MinAlign(Align, Increment), MMOFlags, AAInfo);
LdChain.push_back(L.getValue(1));
- if (L->getValueType(0).isVector()) {
+ if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
+ // Later code assumes the vector loads produced will be mergeable, so
we
+ // must pad the final entry up to the previous width. Scalars are
+ // combined separately.
SmallVector<SDValue, 16> Loads;
Loads.push_back(L);
unsigned size = L->getValueSizeInBits(0);
Modified: llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll?rev=293103&r1=293102&r2=293103&view=diff
==============================================================================
--- llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll (original)
+++ llvm/branches/release_40/test/CodeGen/ARM/vector-load.ll Wed Jan 25
16:10:07 2017
@@ -251,3 +251,13 @@ define <4 x i32> @zextload_v8i8tov8i32_f
%zlA = zext <4 x i8> %lA to <4 x i32>
ret <4 x i32> %zlA
}
+
+; CHECK-LABEL: test_silly_load:
+; CHECK: ldr {{r[0-9]+}}, [r0, #24]
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0:128]!
+; CHECK: vldr d{{[0-9]+}}, [r0]
+
+define void @test_silly_load(<28 x i8>* %addr) {
+ load volatile <28 x i8>, <28 x i8>* %addr
+ ret void
+}
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