RE: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

[Li, Pan2 via Gcc-patches]

Sorry for disturbing but please help to take this PATCH in front of the 
reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.

Pan

-Original Message-
From: Li, Pan2  
Sent: Thursday, May 25, 2023 8:46 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 ; 
Wang, Yanzhang 
Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

From: Pan Li 

This patch would like to add new sub extension (aka ZVFHMIN) to the -march= 
option. To make it simple, only the sub extension itself is involved in this 
patch, and the underlying FP16 related RVV intrinsic API depends on the 
TARGET_ZVFHMIN.

You can locate more information about ZVFHMIN from below spec doc.

https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point

Signed-off-by: Pan Li 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/predef-26.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc|  3 ++
 gcc/config/riscv/riscv-opts.h  |  6 ++-
 gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++
 4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c2ec74b9d92..72f2f8f2753 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
+  {"zvfhmin", "f"},
 
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
@@ -216,6 +217,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h 
index 2a16402265a..f34ca993689 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -200,9 +200,11 @@ enum riscv_entity
 
 #define MASK_ZFHMIN   (1 << 0)
 #define MASK_ZFH  (1 << 1)
+#define MASK_ZVFHMIN  (1 << 2)
 
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
+#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
+#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
 
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 000..8f8da1ecd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 
+-mcmodel=medlow" } */ int foo() { }
diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
b/gcc/testsuite/gcc.target/riscv/predef-26.c
new file mode 100644
index 000..285f64bd6c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
+-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zvfhmin)
+#error "__riscv_zvfhmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if defined(__riscv_zfh)
+#error "__riscv_zfh"
+#endif
+
+#if defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+  return 0;
+}
--
2.34.1

RE: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

[Li, Pan2 via Gcc-patches]

Thanks Kito, update the PATCH v2 for addressing comments.

https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619868.html

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:18 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
Yanzhang 
Subject: Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option

On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches 
 wrote:
>
> Sorry for disturbing but please help to take this PATCH in front of the 
> reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot.
>
> Pan
>
> -Original Message-
> From: Li, Pan2 
> Sent: Thursday, May 25, 2023 8:46 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 
> ; Wang, Yanzhang 
> Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the -march= 
> option. To make it simple, only the sub extension itself is involved in this 
> patch, and the underlying FP16 related RVV intrinsic API depends on the 
> TARGET_ZVFHMIN.
>
> You can locate more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-
> vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc|  3 ++
>  gcc/config/riscv/riscv-opts.h  |  6 ++-
>  gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-26.c | 51 
> ++
>  4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/arch-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..72f2f8f2753 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t 
> riscv_implied_info[] =
>
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
> +  {"zvfhmin", "f"},

spec says: "The Zvfhmin extension depends on the Zve32f extension."
so this should be zve32f rather than f


>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},

RE: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:40 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
Yanzhang 
Subject: Re: [PATCH v2] RISC-V: Add ZVFHMIN extension to the -march= option

LGTM

On Mon, May 29, 2023 at 10:24 AM Pan Li via Gcc-patches 
 wrote:
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFHMIN) to the 
> -march= option. To make it simple, only the sub extension itself is 
> involved in this patch, and the underlying FP16 related RVV intrinsic 
> API depends on the TARGET_ZVFHMIN.
>
> The Zvfhmin extension depends on the Zve32f extension. You can locate 
> more information about ZVFHMIN from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-
> vector-extension-for-minimal-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfhmin item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
> (TARGET_ZFHMIN): Align indent.
> (TARGET_ZFH): Ditto.
> (TARGET_ZVFHMIN): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/predef-26.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc|  3 ++
>  gcc/config/riscv/riscv-opts.h  |  6 ++-
>  gcc/testsuite/gcc.target/riscv/arch-20.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-26.c | 51 
> ++
>  4 files changed, 63 insertions(+), 2 deletions(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/arch-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c2ec74b9d92..92edafb516d 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -104,6 +104,7 @@ static const riscv_implied_info_t 
> riscv_implied_info[] =
>
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
> +  {"zvfhmin", "zve32f"},
>
>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},
> @@ -216,6 +217,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>
>{"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>
>{"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>{"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
> +  {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>
>{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h 
> b/gcc/config/riscv/riscv-opts.h index 2a16402265a..f34ca993689 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -200,9 +200,11 @@ enum riscv_entity
>
>  #define MASK_ZFHMIN   (1 << 0)
>  #define MASK_ZFH  (1 << 1)
> +#define MASK_ZVFHMIN  (1 << 2)
>
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> +#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> +#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>
>  #define MASK_ZMMUL  (1 << 0)
>  #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
> b/gcc/testsuite/gcc.target/riscv/arch-20.c
> new file mode 100644
> index 000..8f8da1ecd65
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 
> +-mcmodel=medlow" } */ int foo() { }
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c 
> b/gcc/testsuite/gcc.target/riscv/predef-26.c
> new file mode 100644
> index 000..285f64bd6c0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c
> @@ -0,0 +1,51 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow 
> +-misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defined(__riscv_d)
> +#error "__riscv_d"
> +#endif
> +
> +#if defined(__ri

RE: [PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:22 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp@gmail.com; Li, Pan2 

Subject: Re: [PATCH V2] RISC-V: Fix incorrect VXRM configuration in mode 
switching for CALL and ASM

LGTM, thanks :)

On Thu, May 25, 2023 at 3:00 PM  wrote:
>
> From: Juzhe-Zhong 
>
> Currently mode switching incorrect codegen for the following case:
> void fn (void);
>
> void f (void * in, void *out, int32_t x, int n, int m) {
>   for (int i = 0; i < n; i++) {
> vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> fn ();
> v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
> __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
>   }
> }
>
> Before this patch:
>
> Preheader:
>   ...
>   csrwi vxrm,2
> Loop Body:
>   ... (no cswri vxrm,2)
>   vaadd.vx
>   ...
>   vaadd.vx
>   ...
>
> This codegen is incorrect.
>
> After this patch:
>
> Preheader:
>   ...
>   csrwi vxrm,2
> Loop Body:
>   ...
>   vaadd.vx
>   ...
>   csrwi vxrm,2
>   ...
>   vaadd.vx
>   ...
>
> cross-compile build PASS and regression PASS
>
> Ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (global_state_unknown_p): New function.
> (riscv_mode_after): Fix incorrect VXM.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vxrm-11.c: New test.
> * gcc.target/riscv/rvv/base/vxrm-12.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc | 29 ++-
>  .../gcc.target/riscv/rvv/base/vxrm-11.c   | 20 +
>  .../gcc.target/riscv/rvv/base/vxrm-12.c   | 18 
>  3 files changed, 66 insertions(+), 1 deletion(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc 
> index 09fc9e5d95e..406c5469425 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7549,6 +7549,31 @@ riscv_mode_needed (int entity, rtx_insn *insn)
>  }
>  }
>
> +/* Return true if the VXRM/FRM status of the INSN is unknown.  */ 
> +static bool global_state_unknown_p (rtx_insn *insn, unsigned int 
> +regno) {
> +  struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
> +  df_ref ref;
> +
> +  /* Return true if there is a definition of VXRM.  */  for (ref = 
> + DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref))
> +if (DF_REF_REGNO (ref) == regno)
> +  return true;
> +
> +  /* A CALL function may contain an instruction that modifies the VXRM,
> + return true in this situation.  */  if (CALL_P (insn))
> +return true;
> +
> +  /* Return true for all assembly since users may hardcode a assembly
> + like this: asm volatile ("csrwi vxrm, 0").  */
> +  extract_insn (insn);
> +  if (recog_data.is_asm)
> +return true;
> +  return false;
> +}
> +
>  /* Return the mode that an insn results in.  */
>
>  static int
> @@ -7557,7 +7582,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
>switch (entity)
>  {
>  case RISCV_VXRM:
> -  if (recog_memoized (insn) >= 0)
> +  if (global_state_unknown_p (insn, VXRM_REGNUM))
> +   return VXRM_MODE_NONE;
> +  else if (recog_memoized (insn) >= 0)
> return reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM),
> PATTERN (insn))
>  ? get_attr_vxrm_mode (insn) diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
> new file mode 100644
> index 000..7f637a8b7f5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +void fn (void);
> +
> +void f (void * in, void *out, int32_t x, int n, int m) {
> +  for (int i = 0; i < n; i++) {
> +vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
> +vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
> +vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
> +fn ();
> +v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
> +__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
> +  }
> +}
> +
> +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
> new file mode 100644
> index 000..c3ab509f106
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#inclu

RE: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[Li, Pan2 via Gcc-patches]

Committed with 2 patches, thanks Kito.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Monday, May 29, 2023 11:19 AM
To: kito.cheng 
Cc: gcc-patches ; Kito.cheng ; 
palmer ; Robin Dapp ; jeffreyalaw 
; Li, Pan2 
Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

This is existing bug in GCC 13. I think I should split into 2 patches.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-05-29 11:17
To: juzhe.zhong
CC: gcc-patches; 
kito.cheng; palmer; 
rdapp.gcc; 
jeffreyalaw; pan2.li
Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support
LGTM, but with one question.

On Fri, May 26, 2023 at 7:36 PM 
mailto:juzhe.zh...@rivai.ai>> wrote:
>
> From: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>
>
> This patch support FMA auto-vectorization pattern.
> 1. Let's RA decide vmacc or vmadd.
> 2. Fix bug of vector.md which generate incorrect information to VSETVL
>PASS when testing ternop-3.c.

Does this bug also appear in GCC 13? or this is new bug introduced at trunk

RE: [PATCH] RISC-V: Remove redundant printf of abs-run.c

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Monday, May 29, 2023 11:43 AM
To: 钟居哲 
Cc: GCC Patches ; Kito Cheng ; 
Palmer Dabbelt ; Palmer Dabbelt ; Jeff 
Law ; Robin Dapp 
Subject: Re: [PATCH] RISC-V: Remove redundant printf of abs-run.c

Ok

 於 2023年5月29日 週一 11:39 寫道：

> From: Juzhe-Zhong 
>
> Notice that this testcase cause unexpected fail:
> FAIL: gcc.target/riscv/rvv/autovec/unop/abs-run.c (test for excess 
> errors) Excess errors:
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: implicit declaration of function 'printf'
> [-Wimplicit-function-declaration]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
> /work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
> warning: incompatible implicit declaration of built-in function 'printf'
> [-Wbuiltin-declaration-mismatch]
>
> spawn /work/home/jzzhong/work/rvv-opensource/output/sim/bin/spike
> --isa=RV64GCVZfh
> /work/home/jzzhong/work/rvv-opensource/output/sim/riscv64-rivai-elf/bi
> n/pk
> ./abs-run.exe^M
> bbl loader^M^M
> 0 0 -64^M
> 1 63 -63^M
> 2 2 -62^M
> 3 61 -61^M
> 4 4 -60^M
> 5 59 -59^M
> 6 6 -58^M
> 7 57 -57^M
> 8 8 -56^M
> 9 55 -55^M
> 10 10 -54^M
> 11 53 -53^M
> 12 12 -52^M
> 13 51 -51^M
>
> Remove printf since it's unnecessary.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Remove 
> redundant printf.
>
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> index 7404dbe037e..d864b54229b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c
> @@ -19,7 +19,6 @@
>vabs_##TYPE (a##TYPE, a##TYPE, SZ);  \
>for (int i = 0; i < SZ; i++) \
>  {  \
> -  printf ("%d %d %d\n", i, a##TYPE[i], i - 64);\
>if (i & 1)   \
> assert (a##TYPE[i] == abs (i - 64));\
>else \
> --
> 2.36.3
>
>

RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

[Li, Pan2 via Gcc-patches]

Thanks Kito, will commit this after the vec_init repeated sequence patch.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 10:20 AM
To: Li, Pan2 
Cc: Robin Dapp ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

LGTM

On Fri, May 26, 2023 at 2:32 PM Li, Pan2 via Gcc-patches 
 wrote:
>
> Thanks Robin.
>
> Sorry for not mentioned that it depends on another patch 
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in 
> the reviewing queue.
>
> Yes, totally agree we can remove the comments for some parameters excepts the 
> Boolean ones, as well as the term data related. I can file another PATCH to 
> make it happen due to it is another thing besides magic number elimination.
>
> Pan
>
> -Original Message-
> From: Robin Dapp 
> Sent: Friday, May 26, 2023 2:24 PM
> To: Li, Pan2 ; gcc-patches@gcc.gnu.org
> Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; 
> Wang, Yanzhang 
> Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc
>
> Hi,
>
> > This patch would like to remove the magic number in the riscv-v.cc, 
> > and align the same value to one macro.
>
> > diff --git a/gcc/config/riscv/riscv-v.cc 
> > b/gcc/config/riscv/riscv-v.cc index 458020ce0a1..20b589bf51b 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -351,13 +351,15 @@ emit_vlmax_insn (unsigned icode, int op_num, 
> > rtx *ops, rtx vl)  {
> >machine_mode data_mode = GET_MODE (ops[0]);
> >machine_mode mask_mode = get_mask_mode (data_mode).require ();
> > -  /* We have a maximum of 11 operands for RVV instruction patterns 
> > according to
> > -   * vector.md.  */
> > -  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
> > -/*FULLY_UNMASKED_P*/ true,
> > -/*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true,
> > -/*VLMAX_P*/ true,
> > -/*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode);
> > +  insn_expander e (/*OP_NUM*/ op_num,
> > +   /*HAS_DEST_P*/ true,
> > +   /*FULLY_UNMASKED_P*/ true,
> > +   /*USE_REAL_MERGE_P*/ false,
> > +   /*HAS_AVL_P*/ true,
> > +   /*VLMAX_P*/ true,
> > +   /*DEST_MODE*/ data_mode,
> > +   /*MASK_MODE*/ mask_mode);
>
> I don't see where RVV_INSN_OPERANDS_MAX is defined.  Maybe you missed to 
> include that hunk?
>
> Apart from that maybe you could also remove the comments for dest_mode, 
> mask_mode and op_num?  I think the general "custom" is to just add them for 
> bool arguments and name non-bool arguments descriptively.  Here that could 
> mean renaming data_mode to dest_mode where appropriate (usually data_mode is 
> used to distinguish between data mode and comparison mode in conditionals, 
> not in regular insns where everything is "data").
>
> Regards
>  Robin

RE: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Monday, May 29, 2023 2:02 PM
To: kito.cheng 
Cc: Kito.cheng ; Robin Dapp ; 
gcc-patches ; jeffreyalaw ; 
palmer ; palmer ; Li, Pan2 

Subject: Re: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization

Yes.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-05-29 12:36
To: juzhe.zh...@rivai.ai
CC: Kito.cheng; Robin 
Dapp; gcc-patches; 
jeffreyalaw; palmer; 
palmer; pan2.li
Subject: Re: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
Ok, and just make sure this only appear for trunk, right?

juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>於 2023年5月29日 週一，12:19寫道：
This patch is fixing VSETVL PASS bug. Ok for trunk ?



juzhe.zh...@rivai.ai

From: juzhe.zhong
Date: 2023-05-26 11:01
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
pan2.li; Juzhe-Zhong
Subject: [PATCH] RISC-V: Fix VSETVL PASS ICE on SLP auto-vectorization
From: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

Fix bug reported here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109974

PR target/109974

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109974.c: New test.

---
gcc/config/riscv/riscv-vsetvl.cc  | 30 ++-
.../gcc.target/riscv/rvv/vsetvl/pr109974.c| 17 +++
2 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9847d649d1d..fe55f4ccd30 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1138,7 +1138,35 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 return false;
   if (!rtx_equal_p (SET_SRC (single_set1), SET_SRC (single_set2)))
 return false;
-  gcc_assert (insn1->uses ().size () == insn2->uses ().size ());
+  /* RTL_SSA uses include REG_NOTE. Consider this following case:
+
+ insn1 RTL:
+ (insn 41 39 42 4 (set (reg:DI 26 s10 [orig:159 loop_len_46 ] [159])
+   (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:201 _149 ] [201])
+ (const_int 2 [0x2]))
+ (nil)))
+ The RTL_SSA uses of this instruction has 2 uses:
+ 1. (reg:DI 15 a5 [orig:201 _149 ] [201]) - twice.
+ 2. (reg:DI 14 a4 [276]) - once.
+
+ insn2 RTL:
+ (insn 38 353 351 4 (set (reg:DI 27 s11 [orig:160 loop_len_47 ] [160])
+   (umin:DI (reg:DI 15 a5 [orig:199 _146 ] [199])
+ (reg:DI 14 a4 [276]))) 408 {*umindi3}
+ (expr_list:REG_EQUAL (umin:DI (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200])
+ (const_int 2 [0x2]))
+ (nil)))
+  The RTL_SSA uses of this instruction has 3 uses:
+ 1. (reg:DI 15 a5 [orig:199 _146 ] [199]) - once
+ 2. (reg:DI 14 a4 [276]) - once
+ 3. (reg:DI 28 t3 [orig:200 ivtmp_147 ] [200]) - once
+
+  Return false when insn1->uses ().size () != insn2->uses ().size ()
+  */
+  if (insn1->uses ().size () != insn2->uses ().size ())
+return false;
   for (size_t i = 0; i < insn1->uses ().size (); i++)
 if (insn1->uses ()[i] != insn2->uses ()[i])
   return false;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
new file mode 100644
index 000..06a8562ebab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zbb -mabi=ilp32d --param 
riscv-autovec-preference=fixed-vlmax -O3" } */
+
+#include 
+
+void
+func (int8_t *__restrict x, int64_t *__restrict y, int n)
+{
+  for (int i = 0, j = 0; i < n; i++, j +=2 )
+  {
+x[i + 0] += 1;
+y[j + 0] += 1;
+y[j + 1] += 2;
+  }
+}
+
+/* { dg-final { scan-assembler {vsetvli} { target { no-opts "-O0" no-opts 
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } 
*/
--
2.36.3

RE: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence

[Li, Pan2 via Gcc-patches]

Updated the PATCH v7 for comments addressing.

https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619939.html

Pan

From: Li, Pan2
Sent: Thursday, May 25, 2023 11:17 AM
To: juzhe.zh...@rivai.ai; gcc-patches 
Cc: Kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v6] RISC-V: Using merge approach to optimize repeating 
sequence

Oops, forget to remove it in previous version, will wait a while and update 
them together.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Thursday, May 25, 2023 11:14 AM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v6] RISC-V: Using merge approach to optimize repeating 
sequence


* machmode.h (VECTOR_BOOL_MODE_P): New macro.

--- a/gcc/machmode.h

+++ b/gcc/machmode.h

@@ -134,6 +134,10 @@ extern const unsigned char mode_class[NUM_MACHINE_MODES];

|| GET_MODE_CLASS (MODE) == MODE_VECTOR_ACCUM\

|| GET_MODE_CLASS (MODE) == MODE_VECTOR_UACCUM)



+/* Nonzero if MODE is a vector bool mode.  */

+#define VECTOR_BOOL_MODE_P(MODE)\

+  (GET_MODE_CLASS (MODE) == MODE_VECTOR_BOOL)   \

+
Why do you add this? But no use. You should drop this.


juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-05-25 11:09
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to optimize the VLS vector initialization like
repeating sequence. From the vslide1down to the vmerge with a simple
cost model, aka every instruction only has 1 cost.

Given code with -march=rv64gcv_zvl256b --param 
riscv-autovec-preference=fixed-vlmax
typedef int64_t vnx32di __attribute__ ((vector_size (256)));

__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
  vnx32di v = {
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
  };
  *(vnx32di *) out = v;
}

Before this patch:
vslide1down.vx (x31 times)

After this patch:
li a5,-1431654400
addi a5,a5,-1365
li a3,-1431654400
addi a3,a3,-1366
slli a5,a5,32
add a5,a5,a3
vsetvli a4,zero,e64,m8,ta,ma
vmv.v.x v8,a0
vmv.s.x v0,a5
vmerge.vxm v8,v8,a1,v0
vs8r.v v8,0(a2)

Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab into
SEW = 128 element and then broadcast this big element.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

gcc/ChangeLog:

* config/riscv/riscv-protos.h (enum insn_type): New type.
* config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
(rvv_builder::can_duplicate_repeating_sequence_p): Align the
referenced class member.
(rvv_builder::get_merged_repeating_sequence):
(rvv_builder::repeating_sequence_use_merge_profitable_p): New
function to evaluate the optimization cost.
(rvv_builder::get_merge_scalar_mask): New function to get the
merge mask.
(emit_scalar_move_insn): New function to emit vmv.s.x.
(emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
(emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
vmv.v.x.
(get_repeating_sequence_dup_machine_mode): New function to get
the dup machine mode.
(expand_vector_init_merge_repeating_sequence): New function to
perform the optimization.
(expand_vec_init): Add this vector init optimization.
* config/riscv/riscv.h (BITS_PER_WORD): New macro.
* machmode.h (VECTOR_BOOL_MODE_P): New macro.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
---
gcc/config/riscv/riscv-protos.h   |   1 +
gcc/config/riscv/riscv-v.cc   | 225 +-
gcc/config/riscv/riscv.h  |   1 +
gcc/machmode.h|   4 +
.../vls-vlmax/init-repeat-sequence-1.c|  21 ++
.../vls-vlmax/init-repeat-sequence-2.c|  24 ++
.../vls-vlmax/init-repeat-sequence-3.c|  25 

RE: [PATCH v7] RISC-V: Using merge approach to optimize repeating sequence in vec_init

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 5:33 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, 
Yanzhang 
Subject: Re: [PATCH v7] RISC-V: Using merge approach to optimize repeating 
sequence in vec_init

LGTM, thanks

On Mon, May 29, 2023 at 4:54 PM Pan Li via Gcc-patches 
 wrote:
>
> From: Pan Li 
>
> This patch would like to optimize the VLS vector initialization like 
> repeating sequence. From the vslide1down to the vmerge with a simple 
> cost model, aka every instruction only has 1 cost.
>
> Given code with -march=rv64gcv_zvl256b --param 
> riscv-autovec-preference=fixed-vlmax
> typedef int64_t vnx32di __attribute__ ((vector_size (256)));
>
> __attribute__ ((noipa)) void
> f_vnx32di (int64_t a, int64_t b, int64_t *out) {
>   vnx32di v = {
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
> a, b, a, b, a, b, a, b,
>   };
>   *(vnx32di *) out = v;
> }
>
> Before this patch:
> vslide1down.vx (x31 times)
>
> After this patch:
> li  a5,-1431654400
> addia5,a5,-1365
> li  a3,-1431654400
> addia3,a3,-1366
> sllia5,a5,32
> add a5,a5,a3
> vsetvli a4,zero,e64,m8,ta,ma
> vmv.v.x v8,a0
> vmv.s.x v0,a5
> vmerge.vxm  v8,v8,a1,v0
> vs8r.v  v8,0(a2)
>
> Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab 
> into SEW = 128 element and then broadcast this big element.
>
> Signed-off-by: Pan Li  Co-Authored by: Juzhe-Zhong 
> 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (enum insn_type): New type.
> * config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
> (rvv_builder::can_duplicate_repeating_sequence_p): Align the 
> referenced
> class member.
> (rvv_builder::get_merged_repeating_sequence): Ditto.
> (rvv_builder::repeating_sequence_use_merge_profitable_p): New function
> to evaluate the optimization cost.
> (rvv_builder::get_merge_scalar_mask): New function to get the merge
> mask.
> (emit_scalar_move_insn): New function to emit vmv.s.x.
> (emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
> (emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
> vmv.v.x.
> (get_repeating_sequence_dup_machine_mode): New function to get the dup
> machine mode.
> (expand_vector_init_merge_repeating_sequence): New function to perform
> the optimization.
> (expand_vec_init): Add this vector init optimization.
> * config/riscv/riscv.h (BITS_PER_WORD): New macro.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: 
> New test.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: 
> New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
> * 
> gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-protos.h   |   1 +
>  gcc/config/riscv/riscv-v.cc   | 225 +-
>  gcc/config/riscv/riscv.h  |   1 +
>  .../vls-vlmax/init-repeat-sequence-1.c|  21 ++
>  .../vls-vlmax/init-repeat-sequence-2.c|  24 ++
>  .../vls-vlmax/init-repeat-sequence-3.c|  25 ++
>  .../vls-vlmax/init-repeat-sequence-4.c|  15 ++
>  .../vls-vlmax/init-repeat-sequence-5.c|  17 ++
>  .../vls-vlmax/init-repeat-sequence-run-1.c|  47 
>  .../vls-vlmax/init-repeat-sequence-run-2.c|  46 
>  .../vls-vlmax/init-repeat-sequence-run-3.c|  41 
>  11 files changed, 457 insertions(+), 6 deletions(-)  create mode 
> 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-1.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-2.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-3.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-4.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-5.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-run-1.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seque
> nce-run-2.c  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat

RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Li, Pan2 
Sent: Monday, May 29, 2023 1:38 PM
To: Kito Cheng 
Cc: Robin Dapp ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: RE: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

Thanks Kito, will commit this after the vec_init repeated sequence patch.

Pan

-Original Message-
From: Kito Cheng 
Sent: Monday, May 29, 2023 10:20 AM
To: Li, Pan2 
Cc: Robin Dapp ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc

LGTM

On Fri, May 26, 2023 at 2:32 PM Li, Pan2 via Gcc-patches 
 wrote:
>
> Thanks Robin.
>
> Sorry for not mentioned that it depends on another patch 
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619536.html, which is in 
> the reviewing queue.
>
> Yes, totally agree we can remove the comments for some parameters excepts the 
> Boolean ones, as well as the term data related. I can file another PATCH to 
> make it happen due to it is another thing besides magic number elimination.
>
> Pan
>
> -Original Message-
> From: Robin Dapp 
> Sent: Friday, May 26, 2023 2:24 PM
> To: Li, Pan2 ; gcc-patches@gcc.gnu.org
> Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; 
> Wang, Yanzhang 
> Subject: Re: [PATCH] RISC-V: Eliminate the magic number in riscv-v.cc
>
> Hi,
>
> > This patch would like to remove the magic number in the riscv-v.cc, 
> > and align the same value to one macro.
>
> > diff --git a/gcc/config/riscv/riscv-v.cc 
> > b/gcc/config/riscv/riscv-v.cc index 458020ce0a1..20b589bf51b 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -351,13 +351,15 @@ emit_vlmax_insn (unsigned icode, int op_num, 
> > rtx *ops, rtx vl)  {
> >machine_mode data_mode = GET_MODE (ops[0]);
> >machine_mode mask_mode = get_mask_mode (data_mode).require ();
> > -  /* We have a maximum of 11 operands for RVV instruction patterns 
> > according to
> > -   * vector.md.  */
> > -  insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
> > -/*FULLY_UNMASKED_P*/ true,
> > -/*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true,
> > -/*VLMAX_P*/ true,
> > -/*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode);
> > +  insn_expander e (/*OP_NUM*/ op_num,
> > +   /*HAS_DEST_P*/ true,
> > +   /*FULLY_UNMASKED_P*/ true,
> > +   /*USE_REAL_MERGE_P*/ false,
> > +   /*HAS_AVL_P*/ true,
> > +   /*VLMAX_P*/ true,
> > +   /*DEST_MODE*/ data_mode,
> > +   /*MASK_MODE*/ mask_mode);
>
> I don't see where RVV_INSN_OPERANDS_MAX is defined.  Maybe you missed to 
> include that hunk?
>
> Apart from that maybe you could also remove the comments for dest_mode, 
> mask_mode and op_num?  I think the general "custom" is to just add them for 
> bool arguments and name non-bool arguments descriptively.  Here that could 
> mean renaming data_mode to dest_mode where appropriate (usually data_mode is 
> used to distinguish between data mode and comparison mode in conditionals, 
> not in regular insns where everything is "data").
>
> Regards
>  Robin

RE: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

[Li, Pan2 via Gcc-patches]

Looks there may be unnecessary due to  the release/gcc-13 has the code as is.

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 15f66efaa48..cd696da5d89 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -388,7 +388,7 @@ (define_attr "avl_type" ""
 (symbol_ref "INTVAL (operands[7])"))

 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
- viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\
+ viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
  
vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
  vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\
  
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 6:35 PM
To: Li, Pan2 
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Kito.cheng 
; palmer ; Robin Dapp 
; jeffreyalaw 
Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support

pushed the bug fixed part to gcc 13 branch

On Mon, May 29, 2023 at 12:52 PM Li, Pan2 via Gcc-patches 
 wrote:
>
> Committed with 2 patches, thanks Kito.
>
> Pan
>
> From: juzhe.zh...@rivai.ai 
> Sent: Monday, May 29, 2023 11:19 AM
> To: kito.cheng 
> Cc: gcc-patches ; Kito.cheng 
> ; palmer ; Robin Dapp 
> ; jeffreyalaw ; Li, Pan2 
> 
> Subject: Re: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization 
> support
>
> This is existing bug in GCC 13. I think I should split into 2 patches.
>
> 
> juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
>
> From: Kito Cheng<mailto:kito.ch...@gmail.com>
> Date: 2023-05-29 11:17
> To: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>
> CC: gcc-patches<mailto:gcc-patches@gcc.gnu.org>; 
> kito.cheng<mailto:kito.ch...@sifive.com>; 
> palmer<mailto:pal...@rivosinc.com>; 
> rdapp.gcc<mailto:rdapp@gmail.com>; 
> jeffreyalaw<mailto:jeffreya...@gmail.com>; 
> pan2.li<mailto:pan2...@intel.com>
> Subject: Re: [PATCH V2] RISC-V: Add RVV FMA auto-vectorization support 
> LGTM, but with one question.
>
> On Fri, May 26, 2023 at 7:36 PM 
> mailto:juzhe.zh...@rivai.ai>> wrote:
> >
> > From: Juzhe-Zhong 
> > mailto:juzhe.zh...@rivai.ai>>
> >
> > This patch support FMA auto-vectorization pattern.
> > 1. Let's RA decide vmacc or vmadd.
> > 2. Fix bug of vector.md which generate incorrect information to VSETVL
> >PASS when testing ternop-3.c.
>
> Does this bug also appear in GCC 13? or this is new bug introduced at 
> trunk
>

RE: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, May 29, 2023 9:30 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 
; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Refactor comments and naming of riscv-v.cc.

LGTM

On Mon, May 29, 2023 at 9:03 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to remove unnecessary comments of some self 
> explained parameters and try a better name to avoid misleading.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
> comments and rename local variables.
> (emit_nonvlmax_insn): Diito.
> (emit_vlmax_merge_insn): Ditto.
> (emit_vlmax_cmp_insn): Ditto.
> (emit_vlmax_cmp_mu_insn): Ditto.
> (emit_scalar_move_insn): Ditto.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-v.cc | 96 
> +++--
>  1 file changed, 49 insertions(+), 47 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc 
> index 20b589bf51b..6ec24dba98d 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -349,16 +349,16 @@ autovec_use_vlmax_p (void)  void  
> emit_vlmax_insn (unsigned icode, int op_num, rtx *ops, rtx vl)  {
> -  machine_mode data_mode = GET_MODE (ops[0]);
> -  machine_mode mask_mode = get_mask_mode (data_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ true,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ true,
> - /*DEST_MODE*/ data_mode,
> - /*MASK_MODE*/ mask_mode);
> +  machine_mode dest_mode = GET_MODE (ops[0]);  machine_mode mask_mode 
> + = get_mask_mode (dest_mode).require ();  
> + insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ true,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ true,
> + dest_mode,
> + mask_mode);
>
>e.set_policy (TAIL_ANY);
>e.set_policy (MASK_ANY);
> @@ -373,16 +373,16 @@ emit_vlmax_insn (unsigned icode, int op_num, rtx 
> *ops, rtx vl)  void  emit_nonvlmax_insn (unsigned icode, int op_num, 
> rtx *ops, rtx avl)  {
> -  machine_mode data_mode = GET_MODE (ops[0]);
> -  machine_mode mask_mode = get_mask_mode (data_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ true,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ false,
> - /*DEST_MODE*/ data_mode,
> - /*MASK_MODE*/ mask_mode);
> +  machine_mode dest_mode = GET_MODE (ops[0]);  machine_mode mask_mode 
> + = get_mask_mode (dest_mode).require ();  
> + insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ true,
> + /* USE_REAL_MERGE_P */ false,
> + /* HAS_AVL_P */ true,
> + /* VLMAX_P */ false,
> + dest_mode,
> + mask_mode);
>
>e.set_policy (TAIL_ANY);
>e.set_policy (MASK_ANY);
> @@ -396,14 +396,14 @@ emit_vlmax_merge_insn (unsigned icode, int 
> op_num, rtx *ops)  {
>machine_mode dest_mode = GET_MODE (ops[0]);
>machine_mode mask_mode = get_mask_mode (dest_mode).require ();
> -  insn_expander e (/*OP_NUM*/ op_num,
> - /*HAS_DEST_P*/ true,
> - /*FULLY_UNMASKED_P*/ false,
> - /*USE_REAL_MERGE_P*/ false,
> - /*HAS_AVL_P*/ true,
> - /*VLMAX_P*/ true,
> - /*DEST_MODE*/ dest_mode,
> - /*MASK_MODE*/ mask_mode);
> +  insn_expander e (op_num,
> + /* HAS_DEST_P */ true,
> + /* FULLY_UNMASKED_P */ f

RE: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:04 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches ; Kito.cheng ; 
palmer ; palmer ; jeffreyalaw 
; Robin Dapp 
Subject: Re: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support

LGTM

On Tue, May 30, 2023 at 8:30 AM juzhe.zh...@rivai.ai  
wrote:
>
> Hi, this patch is same implementation as FMA which has been merged.
> Ok for trunk?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-29 14:53
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> Juzhe-Zhong
> Subject: [PATCH V2] RISC-V: Add RVV FNMA auto-vectorization support
> From: Juzhe-Zhong 
>
> Like FMA, Add FNMA (VNMSAC or VNMSUB) auto-vectorization support.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (fnma4): New pattern.
> (*fnma): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.
>
> ---
> gcc/config/riscv/autovec.md   |  45 
> .../riscv/rvv/autovec/ternop/ternop-4.c   |  28 +
> .../riscv/rvv/autovec/ternop/ternop-5.c   |  34 ++
> .../riscv/rvv/autovec/ternop/ternop-6.c   |  33 ++
> .../riscv/rvv/autovec/ternop/ternop_run-4.c   |  84 ++
> .../riscv/rvv/autovec/ternop/ternop_run-5.c   | 104 ++
> .../riscv/rvv/autovec/ternop/ternop_run-6.c   | 104 ++
> 7 files changed, 432 insertions(+)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index eff3e484fb4..a1028d71467 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -606,3 +606,48 @@
>}
>[(set_attr "type" "vimuladd")
> (set_attr "mode" "")])
> +
> +;; 
> +-
> +
> +;;  [INT] VNMSAC and VNMSUB
> +;; 
> +-
> +
> +;; Includes:
> +;; - vnmsac
> +;; - vnmsub
> +;; 
> +-
> +
> +
> +(define_expand "fnma4"
> +  [(parallel
> +[(set (match_operand:VI 0 "register_operand" "=vr")
> +   (minus:VI
> + (match_operand:VI 3 "register_operand"   " vr")
> + (mult:VI
> +   (match_operand:VI 1 "register_operand" " vr")
> +   (match_operand:VI 2 "register_operand" " vr"
> + (clobber (match_scratch:SI 4))])]
> +  "TARGET_VECTOR"
> +  {})
> +
> +(define_insn_and_split "*fnma"
> +  [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr")
> + (minus:VI
> +   (match_operand:VI 3 "register_operand"   " vr,  0,   vr")
> +   (mult:VI
> + (match_operand:VI 1 "register_operand" " %0, vr,   vr")
> + (match_operand:VI 2 "register_operand" " vr, vr,   vr"
> +   (clobber (match_scratch:SI 4 "=r,r,r"))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& reload_completed"
> +  [(const_int 0)]
> +  {
> +PUT_MODE (operands[4], Pmode);
> +riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
> +if (which_alternative == 2)
> +  emit_insn (gen_rtx_SET (operands[0], operands[3]));
> +rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
> operands[0]};
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
> (mode),
> +riscv_vector::RVV_TERNOP, ops, operands[4]);
> +DONE;
> +  }
> +  [(set_attr "type" "vimuladd")
> +   (set_attr "mode" "")])
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> new file mode 100644
> index 000..22d11de89a1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d 
> +--param=riscv-autovec-preference=scalable" } */
> +
> +#include 
> +
> +#define TEST_TYPE(TYPE)  
>   \
> +  __attribute__ ((noipa)) void ternop_##TYPE

RE: [PATCH V2] RISC-V: Fix warning in riscv.md

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:10 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH V2] RISC-V: Fix warning in riscv.md

LGTM :)

On Tue, May 30, 2023 at 10:09 AM  wrote:
>
> From: Juzhe-Zhong 
>
> Notice there is warning:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* 
> gen_anddi3(rtx, rtx, rtx)’:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
>
> Add unsigned conversion to fix this warning.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Fix signed and unsigned comparison warning.
>
> ---
>  gcc/config/riscv/riscv.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md 
> index aba203318a7..f545874edc1 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1353,9 +1353,9 @@
>if (CONST_INT_P (operands[2]))
>  {
>enum machine_mode tmode = VOIDmode;
> -  if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> +  if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
> tmode = HImode;
> -  else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> +  else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
> tmode = SImode;
>
>if (tmode != VOIDmode)
> --
> 2.36.3
>

RE: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV auto-vectorization support

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:18 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches ; Kito.cheng ; 
palmer ; palmer ; jeffreyalaw 
; Robin Dapp 
Subject: Re: [PATCH V2] RISC-V: Add floating-point to integer conversion RVV 
auto-vectorization support

LGTM

On Tue, May 30, 2023 at 10:15 AM juzhe.zh...@rivai.ai  
wrote:
>
> Ok for trunk ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: juzhe.zhong
> Date: 2023-05-29 12:35
> To: gcc-patches
> CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> Juzhe-Zhong
> Subject: [PATCH V2] RISC-V: Add floating-point to integer conversion 
> RVV auto-vectorization support
> From: Juzhe-Zhong 
>
> Even though we can't support floating-point operations which are 
> depending on FRM yet, (for example vfadd support is blocked) since the 
> RVV intrinsic doc is not updated and we can't support mode switching for this.
>
> We can support floating-point to integer conversion now since it's not 
> depending on FRM and we don't need mode switching support for this ('rtz' 
> conversions independent FRM).
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (2): New pattern.
> * config/riscv/iterators.md: New attribute.
> * config/riscv/vector-iterators.md: New attribute.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New 
> test.
>
> ---
> gcc/config/riscv/autovec.md   | 23 
> gcc/config/riscv/iterators.md |  4 +-
> gcc/config/riscv/vector-iterators.md  |  5 ++
> .../rvv/autovec/conversions/vfcvt_rtz-run.c   | 52 +++
> .../autovec/conversions/vfcvt_rtz-rv32gcv.c   |  6 +++
> .../autovec/conversions/vfcvt_rtz-rv64gcv.c   |  6 +++
> .../autovec/conversions/vfcvt_rtz-template.h  | 15 ++
> 7 files changed, 110 insertions(+), 1 deletion(-) create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32g
> cv.c create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64g
> cv.c create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-templ
> ate.h
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index b24867ae4d0..3989ffb26ee 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -478,6 +478,29 @@
>DONE;
> })
> +;; 
> +=
> +
> +;; == Conversions
> +;; 
> +=
> +
> +
> +;; 
> +-
> +
> +;;  [INT<-FP] Conversions
> +;; 
> +-
> +
> +;; Includes:
> +;; - vfcvt.rtz.xu.f.v
> +;; - vfcvt.rtz.x.f.v
> +;; 
> +-
> +
> +
> +(define_expand "2"
> +  [(set (match_operand: 0 "register_operand")  
> +(any_fix:
> +   (match_operand:VF 1 "register_operand")))]
> +  "TARGET_VECTOR"
> +{
> +  insn_code icode = code_for_pred (, mode);
> +  riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, 
> +operands);
> +  DONE;
> +})
> +
> ;; 
> ==
> ===
> ;; == Unary arithmetic
> ;; 
> ==
> === diff --git a/gcc/config/riscv/iterators.md 
> b/gcc/config/riscv/iterators.md index 8afe98e4410..d374a10810c 100644
> --- a/gcc/config/riscv/iterators.md
> +++ b/gcc/config/riscv/iterators.md
> @@ -225,7 +225,9 @@
> (ss_minus "sssub")
> (us_minus "ussub")
> (sign_extend "extend")
> - (zero_extend "zero_extend")])
> + (zero_extend "zero_extend")
> + (fix "fix_trunc")
> + (unsigned_fix "fixuns_trunc")])
> ;;  code attributes
> (define_code_attr or_optab [(ior "ior") diff --git 
> a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 70fb5b80b1b..937ec3c7f67 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1208,6 +1208,11 @@
>(VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF 
> "VNx8DI") (VNx16DF "VNx16DI")
> ])
> +(define_mode_attr vconvert [
> +  (VNx1SF "vnx1si") (VNx2SF "vnx2si") (VNx4SF "vnx4si") (VNx8SF 
> +"vnx8si") (VNx16SF "vnx16si") (VNx32SF "vnx32si")
> +  (VNx1DF "vnx1di") (VNx2DF "vnx2di") (VNx4DF "vnx4di") (VNx8DF 
> +"vnx8di") (VNx16DF "vnx16di")
> +])
> +
> (def

RE: [PATCH] RISC-V: Fix unreachable test code for init repeat sequence.

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Wednesday, May 31, 2023 8:50 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 
; daisukeokahas...@gmail.com
Subject: Re: [PATCH] RISC-V: Fix unreachable test code for init repeat sequence.

OK

On Wed, May 31, 2023 at 8:29 AM  wrote:
>
> From: Pan Li 
>
> This patch fix one unreachable test code, which is for debugging 
> purpose without cleanup before commit.
>
> Signed-off-by: Pan Li 
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c:
> Remove debug code.
>
> Signed-off-by: Pan Li 
> ---
>  .../riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seq
> uence-run-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seq
> uence-run-1.c
> index 1931d3f5fa0..f7c2fdd040d 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-seq
> uence-run-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat
> +++ -sequence-run-1.c
> @@ -12,7 +12,6 @@ main ()
>double v_vnx8df[sizeof (vnx8df) / sizeof (double)];
>f_vnx8df (a, b, v_vnx8df);
>
> -  return 0;
>for (int i = 0; i < sizeof (vnx8df) / sizeof (double); i++)
>  {
>if (i % 2 == 0)
> --
> 2.34.1
>

RE: [PATCH] RISC-V: Add ZVFH extension to the -march= option

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Wednesday, May 31, 2023 3:06 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 

Subject: Re: [PATCH] RISC-V: Add ZVFH extension to the -march= option

LGTM

On Wed, May 31, 2023 at 2:58 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to add new sub extension (aka ZVFH) to the -march= 
> option.
> To make it simple, only the sub extension itself is involved in this 
> patch, and the underlying FP16 related RVV intrinsic API depends on the 
> TARGET_ZVFH.
>
> The Zvfh extension depends on the Zve32f and Zfhmin extensions. You 
> can locate more information about ZVFH from below spec doc.
>
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh
> -vector-extension-for-half-precision-floating-point
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfh item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv-opts.h (MASK_ZVFH): New macro.
> (TARGET_ZVFH): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-21.c: New test.
> * gcc.target/riscv/predef-27.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc|  4 ++
>  gcc/config/riscv/riscv-opts.h  |  2 +
>  gcc/testsuite/gcc.target/riscv/arch-21.c   |  5 ++
>  gcc/testsuite/gcc.target/riscv/predef-27.c | 55 
> ++
>  4 files changed, 66 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-27.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 92edafb516d..e6ed3df9ea6 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -105,6 +105,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"zfh", "zfhmin"},
>{"zfhmin", "f"},
>{"zvfhmin", "zve32f"},
> +  {"zvfh", "zve32f"},
> +  {"zvfh", "zfhmin"},
>
>{"zhinx", "zhinxmin"},
>{"zhinxmin", "zfinx"},
> @@ -218,6 +220,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1262,6 +1265,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>{"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
>{"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
> +  {"zvfh",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
>
>{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
>
> diff --git a/gcc/config/riscv/riscv-opts.h 
> b/gcc/config/riscv/riscv-opts.h index f34ca993689..5f387d0e393 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -201,10 +201,12 @@ enum riscv_entity
>  #define MASK_ZFHMIN   (1 << 0)
>  #define MASK_ZFH  (1 << 1)
>  #define MASK_ZVFHMIN  (1 << 2)
> +#define MASK_ZVFH (1 << 3)
>
>  #define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>  #define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
>  #define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
> +#define TARGET_ZVFH((riscv_zf_subext & MASK_ZVFH) != 0)
>
>  #define MASK_ZMMUL  (1 << 0)
>  #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c 
> b/gcc/testsuite/gcc.target/riscv/arch-21.c
> new file mode 100644
> index 000..8a239a9255c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv_zvfh -mabi=ilp32 -mcmodel=medlow" 
> +} */ int foo() { }
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c 
> b/gcc/testsuite/gcc.target/riscv/predef-27.c
> new file mode 100644
> index 000..0f9ab4417a6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/predef-27.c
> @@ -0,0 +1,55 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow 
> +-misa-spec=20191213" } */
> +
> +int main () {
> +
> +#ifndef __riscv_arch_test
> +#error "__riscv_arch_test"
> +#endif
> +
> +#if __riscv_xlen != 64
> +#error "__riscv_xlen"
> +#endif
> +
> +#if !defined(__riscv_i)
> +#error "__riscv_i"
> +#endif
> +
> +#if !defined(__riscv_f)
> +#error "__riscv_f"
> +#endif
> +
> +#if !defined(__riscv_zvfh)
> +#error "__riscv_zvfh"
> +#endif
> +
> +#if !defined(__riscv_zfhmin)
> +#error "__riscv_zfhmin"
> +#endif
> +
> +#if defined(__riscv_zvfhmin)
> +#error "__riscv_zvfhmin"
> +#endif
> +
> +#if defined(__riscv_v)
> +#error "__riscv_v"
> +#endif
> +
> +#if defin

RE: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:02 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction



On 5/31/23 04:47, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/vector.md: Remove FRM.
OK
jeff

RE: [PATCH] RISC-V: Remove FRM for vfwcvt.f.x.v (RVV integer to float widening conversion)

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:01 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfwcvt.f.x.v (RVV integer to 
float widening conversion)



On 5/31/23 04:43, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Base on the discussion here:
> https://github.com/riscv/riscv-v-spec/issues/884
> 
> vfwcvt.f.x.v doesn't depend on FRM. So remove FRM preparing for mode 
> switching support.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/vector.md: Remove FRM.
OK.
jeff

RE: [PATCH] RISC-V: Remove FRM for vfwcvt (RVV float to float widening conversion)

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:03 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfwcvt (RVV float to float widening 
conversion)



On 5/31/23 04:35, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Base on the discussion here:
> https://github.com/riscv/riscv-v-spec/issues/884
> 
> vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching 
> support.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/vector.md: Remove FRM.
OK
jeff

RE: [PATCH] RISC-V: Add testcase for vrsub.vi auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:07 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add testcase for vrsub.vi auto-vectorization



On 5/31/23 04:23, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Apparently, we are missing vrsub.vi tests.
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi.
>  * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.
>  * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.
>  * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto.
OK
jeff

RE: Re: [PATCH] RISC-V: Add vwadd/vwsub/vwmul/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed with that change, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of ???
Sent: Wednesday, May 31, 2023 9:24 PM
To: Jeff Law ; rdapp.gcc ; 
gcc-patches 
Cc: kito.cheng ; kito.cheng ; 
palmer ; palmer 
Subject: Re: Re: [PATCH] RISC-V: Add vwadd/vwsub/vwmul/vwmulsu.vv 
lowering optimizaiton for RVV auto-vectorization

I have sent V2 withing adding commen:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620243.html 
Could you take a look at it?




juzhe.zh...@rivai.ai
 
From: Jeff Law
Date: 2023-05-31 20:58
To: Robin Dapp; juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Add vwadd/vwsub/vwmul/vwmulsu.vv lowering 
optimizaiton for RVV auto-vectorization
 
 
On 5/31/23 05:55, Robin Dapp wrote:
> Hi Juzhe,
> 
>> The approach is quite simple and obvious, changing extension pattern
>> into define_insn_and_split will make combine PASS combine into widen
>> operations naturally.
> 
> looks good to me.  Tiny nit: I would add a comment above the patterns
> to clarify why insn_and_split instead of expand.  Something like "to help
> combine match...", no need for a V2 though.
OK with that change.
 
jeff
 

RE: [PATCH] RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs

[Li, Pan2 via Gcc-patches]

Committed as the doc updated, thanks Jeff.

Pan

-Original Message-
From: Jeff Law  
Sent: Tuesday, May 30, 2023 1:03 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com; Li, Pan2 
Subject: Re: [PATCH] RISC-V: Add RVV FRM enum for floating-point rounding mode 
intriniscs



On 5/25/23 01:54, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-vector-builtins.cc (register_frm): New function.
>  (DEF_RVV_FRM_ENUM): New macro.
>  (handle_pragma_vector): Add FRM enum
>  * config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New 
> macro.
>  (RNE): Ditto.
>  (RTZ): Ditto.
>  (RDN): Ditto.
>  (RUP): Ditto.
>  (RMM): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/base/frm-1.c: New test.
OK
jeff

RE: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine mode.

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

-Original Message-
From: Kito Cheng  
Sent: Thursday, June 1, 2023 3:21 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; 
Kito.cheng ; Wang, Yanzhang 
Subject: Re: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine mode.

LGTM, thanks :)

On Thu, Jun 1, 2023 at 3:20 PM juzhe.zh...@rivai.ai  
wrote:
>
> LGTM.
>
> We are waiting for FP16 vector to start floating-point 
> auto-vectorizations
>
> Thanks so much.
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-01 15:17
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine mode.
> From: Pan Li 
>
> This patch would like to introduce the built-in type vfloat16m{f}*_t, 
> as well as their machine mode VNx*HF. They depend on architecture 
> zvfhmin or zvfh.
>
> When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will 
> be true.
>
> The underlying PATCH will implement the zvfhmin extension based on this.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin and 
> zvfh.
> * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
> (main): Disable FP16 tuple.
> * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
> (TARGET_VECTOR_ELEN_FP_16): Ditto.
> * config/riscv/riscv-vector-builtins.cc (check_required_extensions):
> Add FP16.
> * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
> (vfloat16mf2_t): Ditto.
> (vfloat16m1_t): Ditto.
> (vfloat16m2_t): Ditto.
> (vfloat16m4_t): Ditto.
> (vfloat16m8_t): Ditto.
> * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
> New macro.
> * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16 machine 
> mode based on TARGET_VECTOR_ELEN_FP_16.
> ---
> gcc/common/config/riscv/riscv-common.cc|  2 ++
> gcc/config/riscv/genrvv-type-indexer.cc|  7 +--
> gcc/config/riscv/riscv-opts.h  |  4 
> gcc/config/riscv/riscv-vector-builtins.cc  |  2 ++ 
> gcc/config/riscv/riscv-vector-builtins.def | 20 +++
> gcc/config/riscv/riscv-vector-builtins.h   |  1 +
> gcc/config/riscv/riscv-vector-switch.def   | 23 ++
> 7 files changed, 49 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index e6ed3df9ea6..3247d526c0a 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1248,6 +1248,8 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
>{"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_32},
>{"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_64},
> +  {"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
> +  {"zvfh", &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
>{"zvl32b",&gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
>{"zvl64b",&gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc 
> b/gcc/config/riscv/genrvv-type-indexer.cc
> index 18e1b375396..8fc93ceaab4 100644
> --- a/gcc/config/riscv/genrvv-type-indexer.cc
> +++ b/gcc/config/riscv/genrvv-type-indexer.cc
> @@ -54,7 +54,7 @@ valid_type (unsigned sew, int lmul_log2, bool float_p)
>  case 8:
>return lmul_log2 >= -3 && !float_p;
>  case 16:
> -  return lmul_log2 >= -2 && !float_p;
> +  return lmul_log2 >= -2;
>  case 32:
>return lmul_log2 >= -1;
>  case 64:
> @@ -73,6 +73,9 @@ valid_type (unsigned sew, int lmul_log2, unsigned nf, bool 
> float_p)
>if (nf > 8 || nf < 1)
>  return false;
> +  if (sew == 16 && nf != 1 && float_p) // Disable FP16 tuple in temporarily.
> +return false;
> +
>switch (lmul_log2)
>  {
>  case 1:
> @@ -342,7 +345,7 @@ main (int argc, const char **argv)
> fprintf (fp, ")\n");
>   }
>// Build for vfloat
> -  for (unsigned sew : {32, 64})
> +  for (unsigned sew : {16, 32, 64})
>  for (int lmul_log2 : {-3, -2, -1, 0, 1, 2, 3})
>for (unsigned nf : {1, 2, 3, 4, 5, 6, 7, 8}) { diff --git 
> a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 
> 5f387d0e393..208a557b8ff 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -154,6 +154,8 @@ enum riscv_entity
> #define MASK_VECTOR_ELEN_64(1 << 1)
> #define MASK_VECTOR_ELEN_FP_32 (1 << 2) #define MASK_VECTOR_ELEN_FP_64 
> (1 << 3)
> +/* Align the bit index to riscv-vector-builtins.h.  */ #define 
> +MASK_VECTOR_ELEN_FP_16 (1 << 6)
> #define TARGET_VECTOR_ELEN_32 \
>((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0) @@ -163,6 
> +165,8 @@ enum riscv_entity
>((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0) #define 
> TARGET

RE: [PATCH] RISC-V: Add test for vfloat16*_t (non tuple) types

[Li, Pan2 via Gcc-patches]

Thanks Juzhe for pointing out this.

Pan

-Original Message-
From: Li, Pan2  
Sent: Thursday, June 1, 2023 8:09 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 ; 
Wang, Yanzhang 
Subject: [PATCH] RISC-V: Add test for vfloat16*_t (non tuple) types

From: Pan Li 

This patch would like to add some test cases of vfloat16*_t (non tuple), no 
'zvfh' or 'zvfhmin' will meet unknown type.

Signed-off-by: Pan Li 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/abi-16.c: Add test cases.
* gcc.target/riscv/rvv/base/user-7.c: Likewise.
---
 gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c | 6 ++  
gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
index be2cbb5efd7..9e962a70acf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
@@ -173,6 +173,12 @@ void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { 
dg-error {unknown type n  void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} 
/* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */  void 
f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name 
'__rvv_int64m4x2_t'} } */  void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} 
/* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */
+void f___rvv_float16mf4_t () {__rvv_float16mf4_t t;} /* { dg-error 
+{unknown type name '__rvv_float16mf4_t'} } */ void f___rvv_float16mf2_t 
+() {__rvv_float16mf2_t t;} /* { dg-error {unknown type name 
+'__rvv_float16mf2_t'} } */ void f___rvv_float16m1_t () 
+{__rvv_float16m1_t t;} /* { dg-error {unknown type name 
+'__rvv_float16m1_t'} } */ void f___rvv_float16m2_t () 
+{__rvv_float16m2_t t;} /* { dg-error {unknown type name 
+'__rvv_float16m2_t'} } */ void f___rvv_float16m4_t () 
+{__rvv_float16m4_t t;} /* { dg-error {unknown type name 
+'__rvv_float16m4_t'} } */ void f___rvv_float16m8_t () 
+{__rvv_float16m8_t t;} /* { dg-error {unknown type name 
+'__rvv_float16m8_t'} } */
 void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;}  void 
f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;}  void 
f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
index 2172a5c7c79..0620a728208 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
@@ -173,6 +173,12 @@ void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error 
{unknown type name 'vint6  void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { 
dg-error {unknown type name 'vuint64m2x4_t'} } */  void f_vint64m4x2_t () 
{vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */  void 
f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 
'vuint64m4x2_t'} } */
+void f_vfloat16mf4_t () {vfloat16mf4_t t;} /* { dg-error {unknown type 
+name 'vfloat16mf4_t'} } */ void f_vfloat16mf2_t () {vfloat16mf2_t t;} 
+/* { dg-error {unknown type name 'vfloat16mf2_t'} } */ void 
+f_vfloat16m1_t () {vfloat16m1_t t;} /* { dg-error {unknown type name 
+'vfloat16m1_t'} } */ void f_vfloat16m2_t () {vfloat16m2_t t;} /* { 
+dg-error {unknown type name 'vfloat16m2_t'} } */ void f_vfloat16m4_t () 
+{vfloat16m4_t t;} /* { dg-error {unknown type name 'vfloat16m4_t'} } */ 
+void f_vfloat16m8_t () {vfloat16m8_t t;} /* { dg-error {unknown type 
+name 'vfloat16m8_t'} } */
 void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type 
name 'vfloat32mf2x2_t'} } */  void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* 
{ dg-error {unknown type name 'vfloat32mf2x3_t'} } */  void f_vfloat32mf2x4_t 
() {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
--
2.34.1

RE: [PATCH V2] RISC-V: Support RVV permutation auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Friday, June 2, 2023 2:49 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH V2] RISC-V: Support RVV permutation auto-vectorization



On 5/31/23 20:36, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> This patch supports vector permutation for VLS only by vec_perm pattern.
> We will support TARGET_VECTORIZE_VEC_PERM_CONST to support VLA 
> permutation in the future.
> 
> Fixed following comments from Robin.
> Ok for trunk?
> 
> gcc/ChangeLog:
> 
>  * config/riscv/autovec.md (vec_perm): New pattern.
>  * config/riscv/predicates.md (vector_perm_operand): New predicate.
>  * config/riscv/riscv-protos.h (enum insn_type): New enum.
>  (expand_vec_perm): New function.
>  * config/riscv/riscv-v.cc (const_vec_all_in_range_p): Ditto.
>  (gen_const_vector_dup): Ditto.
>  (emit_vlmax_gather_insn): Ditto.
>  (emit_vlmax_masked_gather_mu_insn): Ditto.
>  (expand_vec_perm): Ditto.
OK.
jeff

RE: [PATCH] RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering optimization

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Friday, June 2, 2023 2:52 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering 
optimization



On 5/31/23 21:48, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> 1. This patch optimize the codegen of the following auto-vectorization codes:
> 
> void foo (int32_t * __restrict a, int64_t * __restrict b, int64_t * 
> __restrict c, int n) {
>  for (int i = 0; i < n; i++)
>c[i] = (int64_t)a[i] + b[i];
> }
> 
> Combine instruction from:
> 
> ...
> vsext.vf2
> vadd.vv
> ...
> 
> into:
> 
> ...
> vwadd.wv
> ...
> 
> Since for PLUS operation, GCC prefer the following RTL operand order when 
> combining:
> 
> (plus: (sign_extend:..)
> (reg:)
> 
> instead of
> 
> (plus: (reg:..)
> (sign_extend:)

> 
> which is different from MINUS pattern.
Right.  Canonicaliation rules will have the sign_extend as the first operand 
when the opcode is associative.
> 
> I split patterns of vwadd/vwsub, and add dedicated patterns for them.
> 
> 2. This patch not only optimize the case as above (1) mentioned, also enhance 
> vwadd.vv/vwsub.vv
> optimization for complicate PLUS/MINUS codes, consider this following 
> codes:
> 
> __attribute__ ((noipa)) void
> vwadd_int16_t_int8_t (int16_t *__restrict dst, int16_t *__restrict dst2,
> int16_t *__restrict dst3, int8_t *__restrict a,
> int8_t *__restrict b, int8_t *__restrict a2,
> int8_t *__restrict b2, int n)
> {
>for (int i = 0; i < n; i++)
>  {
>dst[i] = (int16_t) a[i] + (int16_t) b[i];
>dst2[i] = (int16_t) a2[i] + (int16_t) b[i];
>dst3[i] = (int16_t) a2[i] + (int16_t) a[i];
>  }
> }
> 
> Before this patch:
> ...
>  vsetvli zero,a6,e8,mf2,ta,ma
>  vle8.v  v2,0(a3)
>  vle8.v  v1,0(a4)
>  vsetvli t1,zero,e16,m1,ta,ma
>  vsext.vf2   v3,v2
>  vsext.vf2   v2,v1
>  vadd.vv v1,v2,v3
>  vsetvli zero,a6,e16,m1,ta,ma
>  vse16.v v1,0(a0)
>  vle8.v  v4,0(a5)
>  vsetvli t1,zero,e16,m1,ta,ma
>  vsext.vf2   v1,v4
>  vadd.vv v2,v1,v2
> ...
> 
> After this patch:
> ...
>  vsetvli  zero,a6,e8,mf2,ta,ma
>   vle8.v  v3,0(a4)
>   vle8.v  v1,0(a3)
>   vsetvli t4,zero,e8,mf2,ta,ma
>   vwadd.vvv2,v1,v3
>   vsetvli zero,a6,e16,m1,ta,ma
>   vse16.v v2,0(a0)
>   vle8.v  v2,0(a5)
>   vsetvli t4,zero,e8,mf2,ta,ma
>   vwadd.vvv4,v3,v2
>   vsetvli zero,a6,e16,m1,ta,ma
>   vse16.v v4,0(a1)
>   vsetvli t4,zero,e8,mf2,ta,ma
>   sub a7,a7,a6
>   vwadd.vvv3,v2,v1
>   vsetvli zero,a6,e16,m1,ta,ma
>   vse16.v v3,0(a2)
> ...
> 
> The reason why current upstream GCC can not optimize codes using vwadd 
> thoroughly is combine PASS needs intermediate RTL IR (extend one of 
> the operand pattern (vwadd.wv)), then base on this intermediate RTL IR, 
> extend the other operand to generate vwadd.vv.
> 
> So vwadd.wv/vwsub.wv definitely helps to vwadd.vv/vwsub.vv code optimizations.
>   
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-vector-builtins-bases.cc: Change 
> vwadd.wv/vwsub.wv intrinsic API expander
>  * config/riscv/vector.md 
> (@pred_single_widen_): Remove it.
>  (@pred_single_widen_sub): New pattern.
>  (@pred_single_widen_add): New pattern.
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/autovec/widen/widen-5.c: New test.
>  * gcc.target/riscv/rvv/autovec/widen/widen-6.c: New test.
>  * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: New test.
>  * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: New test.
>  * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: New test.
>  * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: New test.
OK
jeff

RE: [PATCH] RISC-V: Add __RISCV_ prefix to VXRM and FRM enum

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Friday, June 2, 2023 7:49 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add __RISCV_ prefix to VXRM and FRM enum



On 6/1/23 17:19, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> According to doc:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222/files
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
> 
> Add __RISCV_ prefix to VXRM and FRM enum.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add 
> __RISCV_ prefix.
>  (DEF_RVV_FRM_ENUM): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/base/frm-1.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-1.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-10.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-11.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-12.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-6.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-7.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-8.c: Ditto.
>  * gcc.target/riscv/rvv/base/vxrm-9.c: Ditto.
OK
jeff

RE: [PATCH] RISC-V: Add test for vfloat16*_t (non tuple) types

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

From: Kito Cheng 
Sent: Thursday, June 1, 2023 11:36 PM
To: Li, Pan2 
Cc: Wang, Yanzhang ; gcc-patches@gcc.gnu.org; 
juzhe.zh...@rivai.ai; kito.ch...@sifive.com
Subject: Re: [PATCH] RISC-V: Add test for vfloat16*_t (non tuple) types

Lgtm

Li, Pan2 via Gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>於 2023年6月1日 週四，20:10寫道：
Thanks Juzhe for pointing out this.

Pan

-Original Message-
From: Li, Pan2 mailto:pan2...@intel.com>>
Sent: Thursday, June 1, 2023 8:09 PM
To: gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>
Cc: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; 
kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: [PATCH] RISC-V: Add test for vfloat16*_t (non tuple) types

From: Pan Li mailto:pan2...@intel.com>>

This patch would like to add some test cases of vfloat16*_t (non tuple), no 
'zvfh' or 'zvfhmin' will meet unknown type.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/abi-16.c: Add test cases.
* gcc.target/riscv/rvv/base/user-7.c: Likewise.
---
 gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c | 6 ++  
gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
index be2cbb5efd7..9e962a70acf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c
@@ -173,6 +173,12 @@ void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { 
dg-error {unknown type n  void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} 
/* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */  void 
f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name 
'__rvv_int64m4x2_t'} } */  void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} 
/* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */
+void f___rvv_float16mf4_t () {__rvv_float16mf4_t t;} /* { dg-error
+{unknown type name '__rvv_float16mf4_t'} } */ void f___rvv_float16mf2_t
+() {__rvv_float16mf2_t t;} /* { dg-error {unknown type name
+'__rvv_float16mf2_t'} } */ void f___rvv_float16m1_t ()
+{__rvv_float16m1_t t;} /* { dg-error {unknown type name
+'__rvv_float16m1_t'} } */ void f___rvv_float16m2_t ()
+{__rvv_float16m2_t t;} /* { dg-error {unknown type name
+'__rvv_float16m2_t'} } */ void f___rvv_float16m4_t ()
+{__rvv_float16m4_t t;} /* { dg-error {unknown type name
+'__rvv_float16m4_t'} } */ void f___rvv_float16m8_t ()
+{__rvv_float16m8_t t;} /* { dg-error {unknown type name
+'__rvv_float16m8_t'} } */
 void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;}  void 
f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;}  void 
f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
index 2172a5c7c79..0620a728208 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c
@@ -173,6 +173,12 @@ void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error 
{unknown type name 'vint6  void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { 
dg-error {unknown type name 'vuint64m2x4_t'} } */  void f_vint64m4x2_t () 
{vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */  void 
f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 
'vuint64m4x2_t'} } */
+void f_vfloat16mf4_t () {vfloat16mf4_t t;} /* { dg-error {unknown type
+name 'vfloat16mf4_t'} } */ void f_vfloat16mf2_t () {vfloat16mf2_t t;}
+/* { dg-error {unknown type name 'vfloat16mf2_t'} } */ void
+f_vfloat16m1_t () {vfloat16m1_t t;} /* { dg-error {unknown type name
+'vfloat16m1_t'} } */ void f_vfloat16m2_t () {vfloat16m2_t t;} /* {
+dg-error {unknown type name 'vfloat16m2_t'} } */ void f_vfloat16m4_t ()
+{vfloat16m4_t t;} /* { dg-error {unknown type name 'vfloat16m4_t'} } */
+void f_vfloat16m8_t () {vfloat16m8_t t;} /* { dg-error {unknown type
+name 'vfloat16m8_t'} } */
 void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type 
name 'vfloat32mf2x2_t'} } */  void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* 
{ dg-error {unknown type name 'vfloat32mf2x3_t'} } */  void f_vfloat32mf2x4_t 
() {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */
--
2.34.1

RE: [PATCH] RISC-V: Fix warning in predicated.md

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Friday, June 2, 2023 1:13 PM
To: 钟居哲 
Cc: GCC Patches ; Kito Cheng ; 
Palmer Dabbelt ; Palmer Dabbelt ; Jeff 
Law ; Robin Dapp 
Subject: Re: [PATCH] RISC-V: Fix warning in predicated.md

Ok

 於 2023年6月2日 週五 11:05 寫道：

> From: Juzhe-Zhong 
>
> Notice there is warning in predicates.md:
> ../../../riscv-gcc/gcc/config/riscv/predicates.md: In function ‘bool 
> arith_operand_or_mode_mask(rtx, machine_mode)’:
> ../../../riscv-gcc/gcc/config/riscv/predicates.md:33:14: warning:
> comparison between signed and unsigned integer expressions [-Wsign-compare]
>  (match_test "INTVAL (op) == GET_MODE_MASK (HImode)
> ../../../riscv-gcc/gcc/config/riscv/predicates.md:34:20: warning:
> comparison between signed and unsigned integer expressions [-Wsign-compare]
>  || INTVAL (op) == GET_MODE_MASK (SImode)"
>
> gcc/ChangeLog:
>
> * config/riscv/predicates.md: Change INTVAL into UINTVAL.
>
> ---
>  gcc/config/riscv/predicates.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/predicates.md 
> b/gcc/config/riscv/predicates.md index 1ed84850e35..d14b1ca30bb 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -31,7 +31,7 @@
>(ior (match_operand 0 "arith_operand")
> (and (match_code "const_int")
>  (match_test "INTVAL (op) == GET_MODE_MASK (HImode)
> -|| INTVAL (op) == GET_MODE_MASK (SImode)"
> +|| UINTVAL (op) == GET_MODE_MASK 
> + (SImode)"
>
>  (define_predicate "lui_operand"
>(and (match_code "const_int")
> --
> 2.36.1
>
>

RE: [PATCH] RISC-V: Optimize reverse series index vector

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Friday, June 2, 2023 3:00 PM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com; 
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Optimize reverse series index vector

LGTM

On Fri, Jun 2, 2023 at 2:32 PM  wrote:
>
> From: Juzhe-Zhong 
>
> This patch optimizes the following seriese vector:
> [nunits - 1, nunits - 2, , 0]
>
> Before this patch:
> vid
> vmul
> vadd
>
> After this patch:
> vid
> vrsub
>
> This patch is an obvious and simple optimization, ok for trunk?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (expand_vec_series): Optimize reverse 
> series index vector.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Add assembly check.
>
> ---
>  gcc/config/riscv/riscv-v.cc | 17 +
>  .../riscv/rvv/autovec/vls-vlmax/perm-4.c|  2 ++
>  2 files changed, 19 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc 
> index 1cd3bd3438e..75cf00b7eba 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -530,6 +530,8 @@ expand_vec_series (rtx dest, rtx base, rtx step)
>machine_mode mode = GET_MODE (dest);
>machine_mode mask_mode;
>gcc_assert (get_mask_mode (mode).exists (&mask_mode));
> +  poly_int64 nunits_m1 = GET_MODE_NUNITS (mode) - 1;
> +  poly_int64 value;
>
>/* VECT_IV = BASE + I * STEP.  */
>
> @@ -545,6 +547,21 @@ expand_vec_series (rtx dest, rtx base, rtx step)
>rtx step_adj;
>if (rtx_equal_p (step, const1_rtx))
>  step_adj = vid;
> +  else if (rtx_equal_p (step, constm1_rtx) && poly_int_rtx_p (base, &value)
> +  && known_eq (nunits_m1, value))
> +{
> +  /* Special case:
> +  {nunits - 1, nunits - 2, ... , 0}.
> +  nunits can be either const_int or const_poly_int.
> +
> +Code sequence:
> +  vid.v v
> +  vrsub nunits - 1, v.  */
> +  rtx ops[] = {dest, vid, gen_int_mode (nunits_m1, GET_MODE_INNER 
> (mode))};
> +  insn_code icode = code_for_pred_sub_reverse_scalar (mode);
> +  emit_vlmax_insn (icode, RVV_BINOP, ops);
> +  return;
> +}
>else
>  {
>step_adj = gen_reg_rtx (mode);
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
> index 179c8274a92..aa328810c30 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
> @@ -56,3 +56,5 @@
>  TEST_ALL (PERMUTE)
>
>  /* { dg-final { scan-assembler-times 
> {vrgather\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 31 } } */
> +/* { dg-final { scan-assembler-times {vrsub\.vi} 24 } } */
> +/* { dg-final { scan-assembler-times {vrsub\.vx} 7 } } */
> --
> 2.36.1
>

RE: [PATCH V2] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Friday, June 2, 2023 3:25 PM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; jeffreya...@gmail.com; rdapp@gmail.com; 
best124...@gmail.com
Subject: Re: [PATCH V2] RISC-V: Add _mu C++ overloaded intrinsics for load && 
viota && vid

LGTM, thanks for fixing this :)

On Fri, Jun 2, 2023 at 10:05 AM  wrote:
>
> From: Juzhe-Zhong 
>
> Base on these:
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/232
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/233
>
> Add _mu C++ overloaded intrinsics for load && viota && vid.
>
> Co-authored-by: KuanLin Chen 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc: Add _mu overloaded 
> intrinsics.
> * config/riscv/riscv-vector-builtins-shapes.cc (struct 
> fault_load_def): Ditto.
>
> ---
>  gcc/config/riscv/riscv-vector-builtins-bases.cc | 17 +++--
>  .../riscv/riscv-vector-builtins-shapes.cc   |  5 ++---
>  2 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 3f92084929d..09870c327fa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -164,7 +164,7 @@ public:
>{
>  if (STORE_P || LST_TYPE == LST_INDEXED)
>return true;
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>rtx expand (function_expander &e) const override @@ -967,7 +967,7 
> @@ public:
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
>  return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum
> -  || pred == PRED_TYPE_tumu;
> +  || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu;
>}
>
>rtx expand (function_expander &e) const override @@ -983,7 +983,7 
> @@ public:
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
>  return pred == PRED_TYPE_tu || pred == PRED_TYPE_tum
> -  || pred == PRED_TYPE_tumu;
> +  || pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu;
>}
>
>rtx expand (function_expander &e) const override @@ -1715,6 
> +1715,11 @@ public:
>  return CP_READ_MEMORY | CP_WRITE_CSR;
>}
>
> +  bool can_be_overloaded_p (enum predication_type_index pred) const 
> + override  {
> +return pred != PRED_TYPE_none;
> +  }
> +
>gimple *fold (gimple_folder &f) const override
>{
>  return fold_fault_load (f);
> @@ -1753,7 +1758,7 @@ public:
>
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>rtx expand (function_expander &e) const override @@ -1798,7 +1803,7 
> @@ public:
>
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>rtx expand (function_expander &e) const override @@ -1888,7 +1893,7 
> @@ public:
>
>bool can_be_overloaded_p (enum predication_type_index pred) const override
>{
> -return pred != PRED_TYPE_none && pred != PRED_TYPE_mu;
> +return pred != PRED_TYPE_none;
>}
>
>gimple *fold (gimple_folder &f) const override diff --git 
> a/gcc/config/riscv/riscv-vector-builtins-shapes.cc 
> b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> index 76262f07ce4..c8daae01f91 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
> @@ -550,9 +550,8 @@ struct fault_load_def : public build_base
>char *get_name (function_builder &b, const function_instance &instance,
>   bool overloaded_p) const override
>{
> -if (overloaded_p)
> -  if (instance.pred == PRED_TYPE_none || instance.pred == PRED_TYPE_mu)
> -   return nullptr;
> +if (overloaded_p && !instance.base->can_be_overloaded_p (instance.pred))
> +  return nullptr;
>  tree type = builtin_types[instance.type.index].vector;
>  machine_mode mode = TYPE_MODE (type);
>  int sew = GET_MODE_BITSIZE (GET_MODE_INNER (mode));
> --
> 2.36.1
>

RE: [PATCH V3] VECT: Change flow of decrement IV

[Li, Pan2 via Gcc-patches]

Committed, thanks all.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Richard Sandiford via Gcc-patches
Sent: Friday, June 2, 2023 7:44 PM
To: juzhe.zh...@rivai.ai
Cc: rguenther ; gcc-patches ; linkw 

Subject: Re: [PATCH V3] VECT: Change flow of decrement IV

"juzhe.zh...@rivai.ai"  writes:
> Thanks Richi. I am gonna merge it after Richard's final approve.

Thanks for checking, but no need to wait for a second ack from me!
Please go ahead and commit.

Richard

RE: Re: [PATCH V2] RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations

[Li, Pan2 via Gcc-patches]

Committed, with Robin's suggestion for commit log, thanks Robin and Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Saturday, June 3, 2023 9:10 AM
To: 钟居哲 
Cc: Robin Dapp ; gcc-patches ; 
kito.cheng ; palmer ; palmer 
; jeffreyalaw 
Subject: Re: Re: [PATCH V2] RISC-V: Add pseudo vwmul.wv pattern to enhance 
vwmul.vv instruction optimizations

Lgtm, thanks:)

juzhe.zh...@rivai.ai  於 2023年6月2日 週五 15:20 寫道：

> Thanks. I am gonna wait for Jeff or Kito final approve.
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Robin Dapp 
> *Date:* 2023-06-02 15:18
> *To:* juzhe.zh...@rivai.ai; gcc-patches 
> *CC:* rdapp.gcc ; kito.cheng 
> ; Kito.cheng ; palmer 
> ; palmer ; jeffreyalaw 
> 
> *Subject:* Re: [PATCH V2] RISC-V: Add pseudo vwmul.wv pattern to 
> enhance vwmul.vv instruction optimizations
> >>> I like the code examples in general but find them hard to read at 
> >>> lengths > 5-10 or so.  Could we condense this a bit?
> > Ok, Do I need to send V2 ? Or condense the commit log when merged 
> > the
> patch?
>
> Sure, just condense a bit. No need for V2.
>
> Regards
> Robin
>
>
>

RE: [PATCH V2] RISC-V: Fix warning in predicated.md

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Saturday, June 3, 2023 4:57 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com; sch...@linux-m68k.org
Subject: Re: [PATCH V2] RISC-V: Fix warning in predicated.md



On 6/2/23 03:33, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Notice there is warning in predicates.md:
> ../../../riscv-gcc/gcc/config/riscv/predicates.md: In function ‘bool 
> arith_operand_or_mode_mask(rtx, machine_mode)’:
> ../../../riscv-gcc/gcc/config/riscv/predicates.md:33:14: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>   (match_test "INTVAL (op) == GET_MODE_MASK (HImode)
> ../../../riscv-gcc/gcc/config/riscv/predicates.md:34:20: warning: comparison 
> between signed and unsigned integer expressions [-Wsign-compare]
>   || INTVAL (op) == GET_MODE_MASK (SImode)"
> 
> gcc/ChangeLog:
> 
>  * config/riscv/predicates.md: Change INTVAL into UINTVAL.
> 
> ---
>   gcc/config/riscv/predicates.md | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gcc/config/riscv/predicates.md 
> b/gcc/config/riscv/predicates.md index d14b1ca30bb..04ca6ceabc7 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -30,7 +30,7 @@
>   (define_predicate "arith_operand_or_mode_mask"
> (ior (match_operand 0 "arith_operand")
>  (and (match_code "const_int")
> -(match_test "INTVAL (op) == GET_MODE_MASK (HImode)
> +(match_test "UINTVAL (op) == GET_MODE_MASK (HImode)
>|| UINTVAL (op) == GET_MODE_MASK (SImode)"
OK.

jeff

RE: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

[Li, Pan2 via Gcc-patches]

Great! Thanks Juzhe and let’s wait kito’s approval.

Pan

From: 钟居哲 
Sent: Sunday, June 4, 2023 7:36 AM
To: Li, Pan2 ; gcc-patches 
Cc: kito.cheng ; Li, Pan2 ; Wang, 
Yanzhang 
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM. Hope FP16 vector can be committed soon.
Since I would like to wait for FP16 vector and then start to support FP16 FP32 
FP64 autovec together.

Thanks.

juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-03 22:37
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/mov-14.c: New test.
* gcc.target/riscv/rvv/base/spill-13.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |   7 ++
gcc/config/riscv/riscv.md |   1 +
gcc/config/riscv/vector-iterators.md  |  25 
gcc/config/riscv/vector.md|  35 ++
.../gcc.target/riscv/rvv/base/mov-14.c|  81 +
.../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
6 files changed, 257 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index f7f650f7e95..65716b8c637 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f545874edc1..be960583101 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -175,6 +175,7 @@ (define_attr "mode" 
"unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
   VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
   VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
   VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
+  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
   VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
   VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,
   VNx2x64QI,VNx2x32QI,VNx3x32QI,VNx4x32QI,
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 937ec3c7f67..5fbaef89566 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -90,6 +90,15 @@ (define_mode_iterator V [
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI 
"TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTO

RE: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

From: Kito Cheng 
Sent: Sunday, June 4, 2023 9:01 AM
To: Li, Pan2 
Cc: 钟居哲 ; gcc-patches ; 
kito.cheng ; Wang, Yanzhang 
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM

Li, Pan2 via Gcc-patches 
mailto:gcc-patches@gcc.gnu.org>> 於 2023年6月4日 週日 08:36 
寫道：
Great! Thanks Juzhe and let’s wait kito’s approval.

Pan

From: 钟居哲 mailto:juzhe.zh...@rivai.ai>>
Sent: Sunday, June 4, 2023 7:36 AM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM. Hope FP16 vector can be committed soon.
Since I would like to wait for FP16 vector and then start to support FP16 FP32 
FP64 autovec together.

Thanks.

juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai><mailto:juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>

From: 
pan2.li<http://pan2.li><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>
Date: 2023-06-03 22:37
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>; 
kito.cheng<mailto:kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>>; 
pan2.li<http://pan2.li><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>; 
yanzhang.wang<mailto:yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>>
Subject: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
From: Pan Li 
mailto:pan2...@intel.com><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>>

This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.

Signed-off-by: Pan Li 
mailto:pan2...@intel.com><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>>
Co-Authored by: Juzhe-Zhong 
mailto:juzhe.zh...@rivai.ai><mailto:juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/mov-14.c: New test.
* gcc.target/riscv/rvv/base/spill-13.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |   7 ++
gcc/config/riscv/riscv.md |   1 +
gcc/config/riscv/vector-iterators.md  |  25 
gcc/config/riscv/vector.md|  35 ++
.../gcc.target/riscv/rvv/base/mov-14.c|  81 +
.../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
6 files changed, 257 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index f7f650f7e95..65716b8c637 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f545874edc1..be960583101 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -175,6 +175,7 @@ (define_attr "mode" 
"unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
   VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
   VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
   VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
+  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
   VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
   VNx1DF,VNx2DF,VNx4DF,VNx8

RE: [NFC] RISC-V: Move optimization patterns into autovec-opt.md

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Sunday, June 4, 2023 9:14 PM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com; pal...@rivosinc.com; 
rdapp@gmail.com
Subject: Re: [NFC] RISC-V: Move optimization patterns into autovec-opt.md

Lgtm

於 2023年6月4日 週日，17:37寫道：

> From: Juzhe-Zhong 
>
> Move all optimization patterns into autovec-opt.md to make 
> organization easier maintain.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*not): Move to 
> autovec-opt.md.
> (*n): Ditto.
> * config/riscv/autovec.md (*not): Ditto.
> (*n): Ditto.
> * config/riscv/vector.md: Ditto.
>
> ---
>  gcc/config/riscv/autovec-opt.md | 92 +
>  gcc/config/riscv/autovec.md | 52 ---
>  gcc/config/riscv/vector.md  | 39 --
>  3 files changed, 92 insertions(+), 91 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md 
> b/gcc/config/riscv/autovec-opt.md index 92cdc4e9a16..f6052b50572 
> 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -78,3 +78,95 @@
>"vwmulsu.vv\t%0,%3,%4%p1"
>[(set_attr "type" "viwmul")
> (set_attr "mode" "")])
> +
> +;;
> --
> ---
> +;;  Integer Compare Instructions Simplification ;;
> --
> ---
> +;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
> +;; - 1.  VMSNE
> +;; - 2.  VMSLT
> +;; - 3.  VMSLTU
> +;; - 4.  VMSGT
> +;; - 5.  VMSGTU
> +;;
> --
> ---
> +;; Simplify OP(V, V) Instructions to VMSET.m Includes:
> +;; - 1.  VMSEQ
> +;; - 2.  VMSLE
> +;; - 3.  VMSLEU
> +;; - 4.  VMSGE
> +;; - 5.  VMSGEU
> +;;
> --
> ---
> +
> +(define_split
> +  [(set (match_operand:VB  0 "register_operand")
> +   (if_then_else:VB
> + (unspec:VB
> +   [(match_operand:VB 1 "vector_all_trues_mask_operand")
> +(match_operand4 "vector_length_operand")
> +(match_operand5 "const_int_operand")
> +(match_operand6 "const_int_operand")
> +(reg:SI VL_REGNUM)
> +(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (match_operand:VB3 "vector_move_operand")
> + (match_operand:VB2 "vector_undef_operand")))]
> +  "TARGET_VECTOR"
> +  [(const_int 0)]
> +  {
> +emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX
> (mode),
> +RVV_VUNDEF (mode), operands[3],
> +operands[4], operands[5]));
> +DONE;
> +  }
> +)
> +
> +;;
> --
> ---
> +;;  [BOOL] Binary logical operations (inverted second input) ;;
> --
> ---
> +;; Includes:
> +;; - vmandnot.mm
> +;; - vmornot.mm
> +;;
> --
> ---
> +
> +(define_insn_and_split "*not"
> +  [(set (match_operand:VB 0 "register_operand"   "=vr")
> +   (bitmanip_bitwise:VB
> + (not:VB (match_operand:VB 2 "register_operand" " vr"))
> + (match_operand:VB 1 "register_operand" " vr")))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& can_create_pseudo_p ()"
> +  [(const_int 0)]
> +  {
> +insn_code icode = code_for_pred_not (, mode);
> +riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> +DONE;
> +  }
> +  [(set_attr "type" "vmalu")
> +   (set_attr "mode" "")])
> +
> +;;
> --
> ---
> +;;  [BOOL] Binary logical operations (inverted result) ;;
> --
> ---
> +;; Includes:
> +;; - vmnand.mm
> +;; - vmnor.mm
> +;; - vmxnor.mm
> +;;
> --
> ---
> +
> +(define_insn_and_split "*n"
> +  [(set (match_operand:VB 0 "register_operand" "=vr")
> +   (not:VB
> + (any_bitwise:VB
> +   (match_operand:VB 1 "register_operand" " vr")
> +   (match_operand:VB 2 "register_operand" " vr"]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& can_create_pseudo_p ()"
> +  [(const_int 0)]
> +  {
> +insn_code icode = code_for_pred_n (, mode);
> +riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> +DONE;
> +  }
> +  [(set_attr "type" "vmalu")
> +   (set_attr "mode" "")])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index ec038fe87cd..9f4492db23c 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -229,58 +229,6 @@
>[(set_at

RE: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

-Original Message-
From: Kito Cheng  
Sent: Sunday, June 4, 2023 9:38 PM
To: 钟居哲 
Cc: Li, Pan2 ; gcc-patches ; 
kito.cheng ; Wang, Yanzhang 
Subject: Re: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API

LGTM too, thanks

On Sun, Jun 4, 2023 at 3:36 PM 钟居哲  wrote:
>
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-04 15:19
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH] RISC-V: Support RVV FP16 ZVFHMIN intrinsic API
> From: Pan Li 
>
> This patch support the 2 intrinsic API of FP16 ZVFHMIN extension. Aka
> SEW=16 for below instructions
>
> vfwcvt.f.f.v
> vfncvt.f.f.w
>
> Then users can leverage the instrinsic APIs to perform the conversion 
> between RVV vector single float point and half float point.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
> (vfloat32m1_t): Likewise.
> (vfloat32m2_t): Likewise.
> (vfloat32m4_t): Likewise.
> (vfloat32m8_t): Likewise.
> * config/riscv/riscv-vector-builtins.def: Fix typo in comments.
> * config/riscv/vector-iterators.md: Add single to half machine mode 
> conversion.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: New test.
> ---
> .../riscv/riscv-vector-builtins-types.def |  6 +++
> gcc/config/riscv/riscv-vector-builtins.def|  2 +-
> gcc/config/riscv/vector-iterators.md  | 10 
> .../riscv/rvv/base/zvfhmin-intrinsic.c| 53 +++
> 4 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 65716b8c637..9cb3aca992e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -553,6 +553,12 @@ DEF_RVV_WCONVERT_U_OPS (vuint64m2_t, 
> RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_6 DEF_RVV_WCONVERT_U_OPS 
> (vuint64m4_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ELEN_64) 
> DEF_RVV_WCONVERT_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_FP_32 | 
> RVV_REQUIRE_ELEN_64)
> +DEF_RVV_WCONVERT_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
> +RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_WCONVERT_F_OPS (vfloat32m1_t, 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WCONVERT_F_OPS (vfloat32m2_t, 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WCONVERT_F_OPS (vfloat32m4_t, 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WCONVERT_F_OPS (vfloat32m8_t, 
> +RVV_REQUIRE_ELEN_FP_32)
> +
> DEF_RVV_WCONVERT_F_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) diff 
> --git a/gcc/config/riscv/riscv-vector-builtins.def 
> b/gcc/config/riscv/riscv-vector-builtins.def
> index 149835f36ac..310edeaf5a9 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -490,7 +490,7 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, 
> int64, VNx16DI, VNx8DI, VOID, _i6 DEF_RVV_TYPE (vuint64m8_t, 16, 
> __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, _u64m8,
>   _u64, _e64m8)
> -/* Enabled if TARGET_VECTOR_ELEN_FP_16 && 9TARGET_ZVFH or 
> TARGET_ZVFHMIN).  */
> +/* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or 
> +TARGET_ZVFHMIN).  */
> /* LMUL = 1/4.  */
> DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, 
> VOID,
>   _f16mf4, _f16, _e16mf4)
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 5fbaef89566..90743ed76c5 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -481,6 +481,13 @@ (define_mode_iterator VWEXTI [
> ])
> (define_mode_iterator VWEXTF [
> +  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")  
> + (VNx2SF "TARGET_VECTOR_ELEN_FP_32")  (VNx4SF 
> + "TARGET_VECTOR_ELEN_FP_32")  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")  
> + (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")  
> + (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> +
>(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
>(VNx4DF "TARGET_VECTOR_ELEN_FP_64") @@ -1145,6 +1152,8 @@ 
> (define_mode_attr V_DOUBLE_TRUNC [
>(VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
>(VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
>(VNx16DI "VNx16SI")
> +
> +  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF 
> + "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
>(VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
>(VNx16DF "VNx16SF")
> ])
> @@ -1169,6 +1178,7 @@ (define_mode_attr v_double_trunc [
>(VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
>(VNx1DI "vnx1si") (VNx2DI "vn

RE: [PATCH] RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Sunday, June 4, 2023 9:55 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Remove redundant vlmul_ext_* patterns to fix 
PR110109



On 6/4/23 02:51, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
>  PR target/110109
> 
> This patch is to fix PR110109 issue. This issue happens is because:
> 
> (define_insn_and_split "*vlmul_extx2"
>[(set (match_operand: 0 "register_operand"  "=vr, ?&vr")
> (subreg:
>   (match_operand:VLMULEXT2 1 "register_operand" " 0,   vr") 0))]
>"TARGET_VECTOR"
>"#"
>"&& reload_completed"
>[(const_int 0)]
> {
>emit_insn (gen_rtx_SET (gen_lowpart (mode, operands[0]), 
> operands[1]));
>DONE;
> })
So anytime you find yourself with an explicit subreg in a pattern, there's a 
very reasonable chance you've made a mistake somewhere else.

As a result every time I see an explicit subreg in a pattern I ask the author 
to describe in a fair amount of detail why the subreg was needed.

 From a first glance, they definitely look like you're papering over a 
problem elsewhere.These are just simple moves.  For scalar modes 
this would be clearly wrong, but I'm not sure we have the same restrictions on 
vector moves.

I would also caution against the way you're generating code here.  I'd have to 
sit down with it for a while, but I'm not 100% sure you can just change the 
location of the subreg like you did (it's going to move from wrapping operand1 
to wrapping operand0).  The semantics may be subtly different -- and that's one 
of the other reasons to avoid explicit subregs.  It's easy to get the semantics 
wrong.


> 
> I create that patterns is to optimize the following test:
> vfloat32m2_t test_vlmul_ext_v_f32mf2_f32m2(vfloat32mf2_t op1) {
>return __riscv_vlmul_ext_v_f32mf2_f32m2(op1);
> }
> 
> codegen:
> test_vlmul_ext_v_f32mf2_f32m2:
>  vsetvli a5,zero,e32,m2,ta,ma
>  vmv.v.i v2,0
>  vsetvli a5,zero,e32,mf2,ta,ma
>  vle32.v v2,0(a1)
>  vs2r.v  v2,0(a0)
>  ret
> 
> There is a redundant 'vmv.v.i' here, Since GCC doesn't undefine IR (unlike 
> LLVM, LLVM has undef/poison).
> For vlmul_ext_* RVV intrinsic, GCC will initiate all zeros into 
> register. However, I think it's not a big issue after we support subreg 
> livness tracking.
As I've suggested elsewhere, let's get the code correct and reasonably complete 
before we worry about this class of problems.  I'm not even convinced it's a 
big issue right now.



> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-vector-builtins-bases.cc: Change expand 
> approach.
>  * config/riscv/vector.md (@vlmul_extx2): Remove it.
>  (@vlmul_extx4): Ditto.
>  (@vlmul_extx8): Ditto.
>  (@vlmul_extx16): Ditto.
>  (@vlmul_extx32): Ditto.
>  (@vlmul_extx64): Ditto.
>  (*vlmul_extx2): Ditto.
>  (*vlmul_extx4): Ditto.
>  (*vlmul_extx8): Ditto.
>  (*vlmul_extx16): Ditto.
>  (*vlmul_extx32): Ditto.
>  (*vlmul_extx64): Ditto.
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/base/pr110109-1.c: New test.
>  * gcc.target/riscv/rvv/base/pr110109-2.c: New test.
Approved.  Please commit.

Jeff

RE: [PATCH] RISC-V: Split arguments of expand_vec_perm

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Sunday, June 4, 2023 11:28 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Split arguments of expand_vec_perm



On 6/4/23 03:25, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Since the following patch will calls expand_vec_perm with splitted 
> arguments, change the expand_vec_perm interface in this patch.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/autovec.md: Split arguments.
>  * config/riscv/riscv-protos.h (expand_vec_perm): Ditto.
>  * config/riscv/riscv-v.cc (expand_vec_perm): Ditto.
OK
jeff

RE: [NFC] RISC-V: Reorganize riscv-v.cc

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Sunday, June 4, 2023 11:40 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [NFC] RISC-V: Reorganize riscv-v.cc



On 6/4/23 03:11, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> This patch is just reorganizing the functions for the following patch.
> 
> I put rvv_builder and emit_* functions located before 
> expand_const_vector function since I will use them in expand_const_vector in 
> the following patch.
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-v.cc (class rvv_builder): Reorganize functions.
>  (rvv_builder::can_duplicate_repeating_sequence_p): Ditto.
>  (rvv_builder::repeating_sequence_use_merge_profitable_p): Ditto.
>  (rvv_builder::get_merged_repeating_sequence): Ditto.
>  (rvv_builder::get_merge_scalar_mask): Ditto.
>  (emit_scalar_move_insn): Ditto.
>  (emit_vlmax_integer_move_insn): Ditto.
>  (emit_nonvlmax_integer_move_insn): Ditto.
>  (emit_vlmax_gather_insn): Ditto.
>  (emit_vlmax_masked_gather_mu_insn): Ditto.
>  (get_repeating_sequence_dup_machine_mode): Ditto.
OK
jeff

RE: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

[Li, Pan2 via Gcc-patches]

Some nit comments.

+static bool
+riscv_frame_pointer_required (void)
+{
+  if (riscv_save_frame_pointer && !crtl->is_leaf)
+return true;
+
+  return false;
+}

Can be simplified to return riscv_save_frame_pointer && !crtl->is_leaf;

+  riscv_save_frame_pointer = false;
+  if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags))
+{
+  if (!global_options.x_flag_omit_frame_pointer)
+   riscv_save_frame_pointer = true;
+
+  global_options.x_flag_omit_frame_pointer = 1;
+}

Does this mean if omit_leaf_frame will also set the omit_frame_pointer 
implicitly?

Pan


-Original Message-
From: Wang, Yanzhang  
Sent: Friday, June 2, 2023 3:07 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 ; 
Wang, Yanzhang 
Subject: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.

From: Yanzhang Wang 

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
  when enabling -mno-omit-leaf-frame-pointer
(riscv_option_override): Override omit-frame-pointer.
(riscv_frame_pointer_required): Save s0 for non-leaf function
(TARGET_FRAME_POINTER_REQUIRED): Override defination
* config/riscv/riscv.opt: Add option support.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/omit-frame-pointer-1.c: New test.
* gcc.target/riscv/omit-frame-pointer-2.c: New test.
* gcc.target/riscv/omit-frame-pointer-3.c: New test.
* gcc.target/riscv/omit-frame-pointer-4.c: New test.
* gcc.target/riscv/omit-frame-pointer-test.c: New test.

Signed-off-by: Yanzhang Wang 
---
 gcc/config/riscv/riscv.cc | 31 ++-
 gcc/config/riscv/riscv.opt|  4 +++
 .../gcc.target/riscv/omit-frame-pointer-1.c   |  7 +
 .../gcc.target/riscv/omit-frame-pointer-2.c   |  7 +
 .../gcc.target/riscv/omit-frame-pointer-3.c   |  7 +
 .../gcc.target/riscv/omit-frame-pointer-4.c   |  7 +
 .../riscv/omit-frame-pointer-test.c   | 13 
 7 files changed, 75 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5d2550871c7..e02f9cb50a4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -408,6 +408,10 @@ static const struct riscv_tune_info 
riscv_tune_info_table[] = {
 #include "riscv-cores.def"
 };
 
+/* Global variable to distinguish whether we should save and restore s0/fp for
+   function.  */
+static bool riscv_save_frame_pointer;
+
 void riscv_frame_info::reset(void)
 {
   total_size = 0;
@@ -4744,7 +4748,11 @@ riscv_save_reg_p (unsigned int regno)
   if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
 return true;
 
-  if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
+  /* Need not to use ra for leaf when frame pointer is turned off by option
+ whatever the omit-leaf-frame's value.  */
+  bool keep_leaf_ra = frame_pointer_needed && crtl->is_leaf
+&& !TARGET_OMIT_LEAF_FRAME_POINTER;
+  if (regno == RETURN_ADDR_REGNUM && (crtl->calls_eh_return || keep_leaf_ra))
 return true;
 
   /* If this is an interrupt handler, then must save extra registers.  */
@@ -6287,6 +6295,15 @@ riscv_option_override (void)
   if (flag_pic)
 riscv_cmodel = CM_PIC;
 
+  riscv_save_frame_pointer = false;
+  if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags))
+{
+  if (!global_options.x_flag_omit_frame_pointer)
+   riscv_save_frame_pointer = true;
+
+  global_options.x_flag_omit_frame_pointer = 1;
+}
+
   /* We get better code with explicit relocs for CM_MEDLOW, but
  worse code for the others (for now).  Pick the best default.  */
   if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
@@ -7158,6 +7175,15 @@ riscv_zero_call_used_regs (HARD_REG_SET 
need_zeroed_hardregs)
& ~zeroed_hardregs);
 }
 
+static bool
+riscv_frame_pointer_required (void)
+{
+  if (riscv_save_frame_pointer && !crtl->is_leaf)
+return true;
+
+  return false;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -7412,6 +7438,9 @@ riscv_zero_call_used_regs (HARD_REG_SET 
need_zeroed_hardregs)
 #undef TARGET_ZERO_CALL_USED_REGS
 #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
 
+#undef TARGET_FRAME_POINTER_REQUIRED
+#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/config/riscv/riscv.opt b/g

RE: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API

[Li, Pan2 via Gcc-patches]

Thanks, make sense, will update V2 for this.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Monday, June 5, 2023 3:30 PM
To: Li, Pan2 ; gcc-patches 
Cc: Kito.cheng ; Li, Pan2 ; Wang, 
Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic 
API


+DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)

+DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)

+DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)

+DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
Is this used in vfwcvt ? convert FP16 -> FP32, if yes, you should add ZVFHMIN 
or ZVFH require checking.



+DEF_RVV_CONVERT_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_CONVERT_I_OPS (vint16mf2_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m1_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m2_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m4_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m8_t, 0)

same



+DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_CONVERT_U_OPS (vuint16mf2_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m1_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m2_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m4_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m8_t, 0

same


+DEF_RVV_WCONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_WCONVERT_I_OPS (vint32m1_t, 0)

+DEF_RVV_WCONVERT_I_OPS (vint32m2_t, 0)

+DEF_RVV_WCONVERT_I_OPS (vint32m4_t, 0)

+DEF_RVV_WCONVERT_I_OPS (vint32m8_t, 0)


same


+DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, 0)

+DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, 0)

+DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, 0)

+DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, 0)

same



Otherwise, LGTM.

juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-05 14:50
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li mailto:pan2...@intel.com>>

This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:

vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin vfmax
vfsgnj vfsgnjn vfsgnjx
vmfeq vmfne vmflt vmfle vmfgt vmfge
vfclass vfmerge
vfmv
vfcvt vfwcvt vfncvt

Then users can leverage the instrinsic APIs to perform the FP=16 related
operations. Please note not all the instrinsic APIs are coverred in the
test files, only pick some typical ones due to too many. We will perform
the FP16 related instrinsic API test entirely soon.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): New type for DEF_RVV_WEXTF_OPS.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vint16mf4_t): New type for DEF_RVV_CONVERT_I_OPS.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16mf4_t): New type for DEF_RVV_CONVERT_U_OPS.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): New type for DEF_RVV_WCONVERT_I_OPS.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32mf2_t): New type for DEF_RVV_WCONVERT_U_OPS.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
* config/riscv/vector-iterators.md: Add FP=16 support for V,
VWCONVERTI, VCONVERT, VNCONVERT, VMUL1 and vlmul1.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |  32 ++
gcc/config/riscv/vector-iterators.md  |  21 +
.../riscv/rvv/base/zvfh-intrinsic.c   | 418 ++
3 files changed, 471 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 9cb3aca992e..348aa05dd91 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -518,11 +518,24 @@ DEF_RVV_FULL_V_U_OPS (vuint64m2_t, RVV_REQUIRE_FULL_V)
DEF_RVV_FULL_V_U_OPS (vuint64m4_t, RVV_REQUIRE_FULL_V)
DEF_RVV_FULL_V_U_OPS (vuint64m8_t, RVV_REQUIRE_FULL_V)
+DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_3

RE: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API

[Li, Pan2 via Gcc-patches]

Updated the PATCH V2 for the ZVFH requirement.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620636.html

Pan

From: Li, Pan2
Sent: Monday, June 5, 2023 3:37 PM
To: juzhe.zh...@rivai.ai; gcc-patches 
Cc: Kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic 
API

Thanks, make sense, will update V2 for this.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Monday, June 5, 2023 3:30 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic 
API


+DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)

+DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)

+DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)

+DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
Is this used in vfwcvt ? convert FP16 -> FP32, if yes, you should add ZVFHMIN 
or ZVFH require checking.



+DEF_RVV_CONVERT_I_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_CONVERT_I_OPS (vint16mf2_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m1_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m2_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m4_t, 0)

+DEF_RVV_CONVERT_I_OPS (vint16m8_t, 0)

same



+DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_CONVERT_U_OPS (vuint16mf2_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m1_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m2_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m4_t, 0)

+DEF_RVV_CONVERT_U_OPS (vuint16m8_t, 0

same


+DEF_RVV_WCONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_WCONVERT_I_OPS (vint32m1_t, 0)

+DEF_RVV_WCONVERT_I_OPS (vint32m2_t, 0)

+DEF_RVV_WCONVERT_I_OPS (vint32m4_t, 0)

+DEF_RVV_WCONVERT_I_OPS (vint32m8_t, 0)


same


+DEF_RVV_WCONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)

+DEF_RVV_WCONVERT_U_OPS (vuint32m1_t, 0)

+DEF_RVV_WCONVERT_U_OPS (vuint32m2_t, 0)

+DEF_RVV_WCONVERT_U_OPS (vuint32m4_t, 0)

+DEF_RVV_WCONVERT_U_OPS (vuint32m8_t, 0)

same



Otherwise, LGTM.

juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-05 14:50
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API
From: Pan Li mailto:pan2...@intel.com>>

This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
SEW=16 for below instructions:

vfadd vfsub vfrsub vfwadd vfwsub
vfmul vfdiv vfrdiv vfwmul
vfmacc vfnmacc vfmsac vfnmsac vfmadd
vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac
vfsqrt vfrsqrt7 vfrec7
vfmin vfmax
vfsgnj vfsgnjn vfsgnjx
vmfeq vmfne vmflt vmfle vmfgt vmfge
vfclass vfmerge
vfmv
vfcvt vfwcvt vfncvt

Then users can leverage the instrinsic APIs to perform the FP=16 related
operations. Please note not all the instrinsic APIs are coverred in the
test files, only pick some typical ones due to too many. We will perform
the FP16 related instrinsic API test entirely soon.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): New type for DEF_RVV_WEXTF_OPS.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vint16mf4_t): New type for DEF_RVV_CONVERT_I_OPS.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16mf4_t): New type for DEF_RVV_CONVERT_U_OPS.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): New type for DEF_RVV_WCONVERT_I_OPS.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32mf2_t): New type for DEF_RVV_WCONVERT_U_OPS.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
* config/riscv/vector-iterators.md: Add FP=16 support for V,
VWCONVERTI, VCONVERT, VNCONVERT, VMUL1 and vlmul1.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |  32 ++
gcc/config/riscv/vector-iterators.md  |  21 +
.../riscv/rvv/base/zvfh-intrinsic.c   | 418 ++
3 files changed, 471 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 9cb3aca992e..348aa05dd91 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/ri

RE: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, June 5, 2023 4:47 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Wang, 
Yanzhang 
Subject: Re: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic 
API

LGTM too, thanks :)

On Mon, Jun 5, 2023 at 4:27 PM juzhe.zh...@rivai.ai  
wrote:
>
> LGTM,
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2023-06-05 16:20
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
> Subject: [PATCH v2] RISC-V: Support RVV FP16 ZVFH floating-point 
> intrinsic API
> From: Pan Li 
>
> This patch support the intrinsic API of FP16 ZVFH floating-point. Aka
> SEW=16 for below instructions:
>
> vfadd vfsub vfrsub vfwadd vfwsub
> vfmul vfdiv vfrdiv vfwmul
> vfmacc vfnmacc vfmsac vfnmsac vfmadd
> vfnmadd vfmsub vfnmsub vfwmacc vfwnmacc vfwmsac vfwnmsac vfsqrt 
> vfrsqrt7 vfrec7 vfmin vfmax vfsgnj vfsgnjn vfsgnjx vmfeq vmfne vmflt 
> vmfle vmfgt vmfge vfclass vfmerge vfmv vfcvt vfwcvt vfncvt
>
> Then users can leverage the instrinsic APIs to perform the FP=16 
> related operations. Please note not all the instrinsic APIs are 
> coverred in the test files, only pick some typical ones due to too 
> many. We will perform the FP16 related instrinsic API test entirely soon.
>
> Signed-off-by: Pan Li 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat32mf2_t): New type for DEF_RVV_WEXTF_OPS.
> (vfloat32m1_t): Ditto.
> (vfloat32m2_t): Ditto.
> (vfloat32m4_t): Ditto.
> (vfloat32m8_t): Ditto.
> (vint16mf4_t): New type for DEF_RVV_CONVERT_I_OPS.
> (vint16mf2_t): Ditto.
> (vint16m1_t): Ditto.
> (vint16m2_t): Ditto.
> (vint16m4_t): Ditto.
> (vint16m8_t): Ditto.
> (vuint16mf4_t): New type for DEF_RVV_CONVERT_U_OPS.
> (vuint16mf2_t): Ditto.
> (vuint16m1_t): Ditto.
> (vuint16m2_t): Ditto.
> (vuint16m4_t): Ditto.
> (vuint16m8_t): Ditto.
> (vint32mf2_t): New type for DEF_RVV_WCONVERT_I_OPS.
> (vint32m1_t): Ditto.
> (vint32m2_t): Ditto.
> (vint32m4_t): Ditto.
> (vint32m8_t): Ditto.
> (vuint32mf2_t): New type for DEF_RVV_WCONVERT_U_OPS.
> (vuint32m1_t): Ditto.
> (vuint32m2_t): Ditto.
> (vuint32m4_t): Ditto.
> (vuint32m8_t): Ditto.
> * config/riscv/vector-iterators.md: Add FP=16 support for V, 
> VWCONVERTI, VCONVERT, VNCONVERT, VMUL1 and vlmul1.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfh-intrinsic.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> .../riscv/riscv-vector-builtins-types.def |  32 ++
> gcc/config/riscv/vector-iterators.md  |  21 +
> .../riscv/rvv/base/zvfh-intrinsic.c   | 418 ++
> 3 files changed, 471 insertions(+)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 9cb3aca992e..1e2491de6d6 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -518,11 +518,24 @@ DEF_RVV_FULL_V_U_OPS (vuint64m2_t, 
> RVV_REQUIRE_FULL_V) DEF_RVV_FULL_V_U_OPS (vuint64m4_t, 
> RVV_REQUIRE_FULL_V) DEF_RVV_FULL_V_U_OPS (vuint64m8_t, 
> RVV_REQUIRE_FULL_V)
> +DEF_RVV_WEXTF_OPS (vfloat32mf2_t, TARGET_ZVFH | 
> +RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_WEXTF_OPS 
> +(vfloat32m1_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32) 
> +DEF_RVV_WEXTF_OPS (vfloat32m2_t, TARGET_ZVFH | 
> +RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WEXTF_OPS (vfloat32m4_t, TARGET_ZVFH 
> +| RVV_REQUIRE_ELEN_FP_32) DEF_RVV_WEXTF_OPS (vfloat32m8_t, 
> +TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32)
> +
> DEF_RVV_WEXTF_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WEXTF_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WEXTF_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) 
> DEF_RVV_WEXTF_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
> +DEF_RVV_CONVERT_I_OPS (vint16mf4_t, TARGET_ZVFH | 
> +RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_CONVERT_I_OPS (vint16mf2_t, 
> +TARGET_ZVFH) DEF_RVV_CONVERT_I_OPS (vint16m1_t, TARGET_ZVFH) 
> +DEF_RVV_CONVERT_I_OPS (vint16m2_t, TARGET_ZVFH) DEF_RVV_CONVERT_I_OPS 
> +(vint16m4_t, TARGET_ZVFH) DEF_RVV_CONVERT_I_OPS (vint16m8_t, 
> +TARGET_ZVFH)
> +
> DEF_RVV_CONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) 
> DEF_RVV_CONVERT_I_OPS (vint32m1_t, 0) DEF_RVV_CONVERT_I_OPS 
> (vint32m2_t, 0) @@ -533,6 +546,13 @@ DEF_RVV_CONVERT_I_OPS 
> (vint64m2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_CONVERT_I_OPS (vint64m4_t, 
> RVV_REQUIRE_ELEN_64) DEF_RVV_CONVERT_I_OPS (vint64m8_t, 
> RVV_REQUIRE_ELEN_64)
> +DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, TARGET_ZVFH | 
> +RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_CONVERT_U_OPS (vuint16mf2_t, 
> +TARGET_ZVFH) DEF_RVV_CONVERT_U_OPS (vuint16m1_t, TARGET_ZVFH) 
> +DEF_RVV_CONVERT_U_OPS (vuint16m2_t, TARGET_ZVFH) 
> +DEF_RVV_CONVERT_U_OPS (vuint16m4_t, TARGET_ZVFH) 
> +DEF_RVV_CONVERT_U_OPS (vuint16m8_t, TARGET_ZVFH)
> +
> DEF_RVV_CONVERT_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) 
> D

RE: [PATCH v1] RISC-V: Fix some typo in vector-iterators.md

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Jeff Law  
Sent: Tuesday, June 6, 2023 3:01 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang 

Subject: Re: [PATCH v1] RISC-V: Fix some typo in vector-iterators.md



On 6/5/23 09:07, Pan Li via Gcc-patches wrote:
> From: Pan Li 
> 
> This patch would like to fix some typo in vector-iterators.md, aka:
> 
> [-"vnx1DI")-]{+"vnx1di")+}
> [-"vnx2SI")-]{+"vnx2si")+}
> [-"vnx1SI")-]{+"vnx1si")+}
> 
> Signed-off-by: Pan Li 
> 
> gcc/ChangeLog:
> 
>   * config/riscv/vector-iterators.md: Fix typo in mode attr.
OK
jeff

RE: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md.

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Monday, June 5, 2023 4:39 PM
To: juzhe.zh...@rivai.ai
Cc: Li Xu ; gcc-patches ; 
palmer 
Subject: Re: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in 
vector-iterators.md.

LGTM

On Mon, Jun 5, 2023 at 4:27 PM juzhe.zh...@rivai.ai  
wrote:
>
> Thanks for catching this.
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Li Xu
> Date: 2023-06-05 16:18
> To: gcc-patches
> CC: kito.cheng; palmer; juzhe.zhong; Li Xu
> Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in 
> vector-iterators.md.
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for 
> machine_mode 'MODE'.
> * config/riscv/vector.md 
> (@pred_indexed_store): change 
> VNX16_QHSI to VNX16_QHSDI.
> (@pred_indexed_store): Ditto.
> ---
> gcc/config/riscv/vector-iterators.md | 26 +-
> gcc/config/riscv/vector.md   |  6 +++---
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 90743ed76c5..42cbbb49894 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -148,7 +148,7 @@
> ])
> (define_mode_iterator VEEWEXT8 [
> -  (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64")
> +  (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
> + "TARGET_VECTOR_ELEN_64")
>(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
> "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
>(VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>(VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -188,7 +188,7 @@
>(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
>(VNx8SF "TARGET_VECTOR_ELEN_FP_32")
>(VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> -  (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
> +  (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>(VNx2DF "TARGET_VECTOR_ELEN_FP_64")
>(VNx4DF "TARGET_VECTOR_ELEN_FP_64")
>(VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ 
> -199,7 +199,7 @@
>(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI 
> "TARGET_MIN_VLEN >= 128")
>(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 
> 128")
>(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
> "TARGET_VECTOR_ELEN_64")
> -  (VNx4DI "TARGET_VECTOR_ELEN_64")
> +  (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
>(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
>(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
>(VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -213,11 +213,11 @@
>(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI 
> "TARGET_MIN_VLEN >= 128")
>(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 
> 128")
>(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= 
> 128")
> -  (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && 
> TARGET_MIN_VLEN >= 128")
> +  (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
> + "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
>(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
>(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
>(VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> -  (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
> +  (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
>(VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
> ])
> @@ -400,26 +400,26 @@
> (define_mode_iterator VNX1_QHSDI [
>(VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") 
> (VNx1SI "TARGET_MIN_VLEN < 128")
> -  (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
> +  (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 
> + 128")
> ])
> (define_mode_iterator VNX2_QHSDI [
>VNx2QI VNx2HI VNx2SI
> -  (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
> +  (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64")
> ])
> (define_mode_iterator VNX4_QHSDI [
>VNx4QI VNx4HI VNx4SI
> -  (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
> +  (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64")
> ])
> (define_mode_iterator VNX8_QHSDI [
>VNx8QI VNx8HI VNx8SI
> -  (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32")
> +  (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64")
> ])
> -(define_mode_iterator VNX16_QHSI [
> -  VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI 
> "TARGET_MIN_VLEN >= 128")
> +(define_mode_iterator VNX16_QHSDI [
> +  VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI 
> +"TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> ])
> (define_mode_iterator VNX32_QHSI [
> @@ -435,7 +435,7 @@
>(VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI 
> "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128")
>(VNx1SI "TARGET_MIN_VLE

RE: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API

[Li, Pan2 via Gcc-patches]

I see. I restricted the ZVFH/ZVFHMIN from the riscv-vector-builtins-types.def 
for ops definition but lack the consideration of autovec part.



Do you prefer leave this PATCH as is and fix this issue in another PATCH 
entirely OR

update this PATCH V2 for predictor and send another PATCH for the previous one?



Both works for me.



Pan

From: juzhe.zh...@rivai.ai 
Sent: Tuesday, June 6, 2023 9:39 AM
To: kito.cheng 
Cc: Li, Pan2 ; gcc-patches ; 
Kito.cheng ; Wang, Yanzhang 
Subject: Re: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction 
floating-point intrinsic API

Oh. YES. Thanks for catching this.
VF will be used in autovec for example: vfadd.
When specify zfhmin, the vfadd autovec will be enabled unexpectedly.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-06-06 09:32
To: juzhe.zh...@rivai.ai
CC: pan2.li; 
gcc-patches; 
Kito.cheng; 
yanzhang.wang
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point 
intrinsic API
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index e4f2ba90799..c338e3c9003 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [
> ])
> (define_mode_iterator VWF [
> +  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> +  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> +  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")

I am little concern about using TARGET_VECTOR_ELEN_FP_16 as predictor here,
zvfhmin also set TARGET_VECTOR_ELEN_FP_16 flag,
so it means zvfhmin also enabled reduction?

and also has the same concern for V and VF in the last patch[1] too.

[1] 
https://patchwork.sourceware.org/project/gcc/patch/20230605082043.1707158-1-pan2...@intel.com/

Give a more practical example to explain my concern:

We've using V and VF iterators in autovec.md, and zvfhmin will set
MASK_VECTOR_ELEN_FP_16
which means zvfhmin WILL enable most autovec patterns with fp16,
that should not what we expected to do I think?

RE: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe, will fix the issue we discussed soon.

Pan

-Original Message-
From: Kito Cheng  
Sent: Tuesday, June 6, 2023 9:48 AM
To: juzhe.zh...@rivai.ai
Cc: kito.cheng ; Li, Pan2 ; 
gcc-patches ; Wang, Yanzhang 
Subject: Re: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction 
floating-point intrinsic API

OK for landing this patch first, and fix by follow up patches.

On Tue, Jun 6, 2023 at 9:41 AM juzhe.zh...@rivai.ai  
wrote:
>
> I think we should split instructions pattern which belongs to ZVFHMIN.
> And add ZVFH gating into all original iterator for example: VF VWFetc.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-06-06 09:32
> To: juzhe.zh...@rivai.ai
> CC: pan2.li; gcc-patches; Kito.cheng; yanzhang.wang
> Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 ZVFH Reduction 
> floating-point intrinsic API
> > diff --git a/gcc/config/riscv/vector-iterators.md 
> > b/gcc/config/riscv/vector-iterators.md
> > index e4f2ba90799..c338e3c9003 100644
> > --- a/gcc/config/riscv/vector-iterators.md
> > +++ b/gcc/config/riscv/vector-iterators.md
> > @@ -330,10 +330,18 @@ (define_mode_iterator VF_ZVE32 [
> > ])
> > (define_mode_iterator VWF [
> > +  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")  
> > + (VNx2HF "TARGET_VECTOR_ELEN_FP_16")  (VNx4HF 
> > + "TARGET_VECTOR_ELEN_FP_16")  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")  
> > + (VNx16HF "TARGET_VECTOR_ELEN_FP_16")  (VNx32HF 
> > + "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")  (VNx64HF 
> > + "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
>
> I am little concern about using TARGET_VECTOR_ELEN_FP_16 as predictor 
> here, zvfhmin also set TARGET_VECTOR_ELEN_FP_16 flag, so it means 
> zvfhmin also enabled reduction?
>
> and also has the same concern for V and VF in the last patch[1] too.
>
> [1] 
> https://patchwork.sourceware.org/project/gcc/patch/20230605082043.1707
> 158-1-pan2...@intel.com/
>
> Give a more practical example to explain my concern:
>
> We've using V and VF iterators in autovec.md, and zvfhmin will set
> MASK_VECTOR_ELEN_FP_16
> which means zvfhmin WILL enable most autovec patterns with fp16, that 
> should not what we expected to do I think?
>

RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

[Li, Pan2 via Gcc-patches]

IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, 
or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.

Pan

From: 钟居哲 
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 ; gcc-patches 
Cc: kito.cheng ; Li, Pan2 ; Wang, 
Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and 
pattern

+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-06 20:36
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend): New pattern for
the ZVFHMIN instruction.
(@pred_trunc): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 28 -
gcc/config/riscv/vector.md| 40 +++
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") 
(VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")
+  (VNx2SF "VNx2HF")
+  (VNx4SF "VNx4HF")
+  (VNx8SF "VNx8HF")
+  (VNx16SF "VNx16HF")
+  (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
   (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
   (VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
-  (VN

RE: [PATCH V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Tuesday, June 6, 2023 10:45 PM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; pal...@rivosinc.com; rdapp@gmail.com; 
jeffreya...@gmail.com
Subject: Re: [PATCH V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine 
lowering optmization

LGTM, we would like to improve that on the combine pass, but it could be 
improved later.

On Tue, Jun 6, 2023 at 8:04 PM  wrote:
>
> From: Juzhe-Zhong 
>
> Fix according to comments from Robin of V1 patch.
>
> This patch add combine optimization for following case:
> __attribute__ ((noipa)) void
> vwmaccsu (int16_t *__restrict dst, int8_t *__restrict a, uint8_t *__restrict 
> b,
>   int n)
> {
>   for (int i = 0; i < n; i++)
> dst[i] += (int16_t) a[i] * (int16_t) b[i]; }
>
> Before this patch:
> ...
> vsext.vf2
> vzext.vf2
> vmadd.vv
> ..
>
> After this patch:
> ...
> vwmaccsu.vv
> ...
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*_fma): New pattern.
> (*single_mult_plus): Ditto.
> (*double_mult_plus): Ditto.
> (*sign_zero_extend_fma): Ditto.
> (*zero_sign_extend_fma): Ditto.
> * config/riscv/riscv-protos.h (enum insn_type): New enum.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/widen/widen-8.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen-9.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 160 ++
>  gcc/config/riscv/riscv-protos.h   |   1 +
>  .../riscv/rvv/autovec/widen/widen-8.c |  27 +++
>  .../riscv/rvv/autovec/widen/widen-9.c |  23 +++
>  .../rvv/autovec/widen/widen-complicate-5.c|  32 
>  .../rvv/autovec/widen/widen-complicate-6.c|  30 
>  .../riscv/rvv/autovec/widen/widen_run-8.c |  38 +
>  .../riscv/rvv/autovec/widen/widen_run-9.c |  35 
>  8 files changed, 346 insertions(+)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md 
> b/gcc/config/riscv/autovec-opt.md index f6052b50572..7bb93eed220 
> 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -170,3 +170,163 @@
>}
>[(set_attr "type" "vmalu")
> (set_attr "mode" "")])
> +
> +;; 
> +=
> +
> +;; == Widening Ternary arithmetic
> +;; 
> +=
> +
> +
> +;; 
> +-
> +
> +;;  [INT] VWMACC
> +;; 
> +-
> +
> +;; Includes:
> +;; - vwmacc.vv
> +;; - vwmaccu.vv
> +;; 
> +-
> +
> +
> +;; Combine ext + ext + fma ===> widen fma.
> +;; Most of circumstantces, LoopVectorizer will generate the following IR:
> +;;   vect__8.64_40 = (vector([4,4]) int) vect__7.63_41;
> +;;   vect__11.68_35 = (vector([4,4]) int) vect__10.67_36;
> +;;   vect__13.70_33 = .FMA (vect__11.68_35, vect__8.64_40, vect__4.60_45);
> +(define_insn_and_split "*_fma"
> +  [(set (match_operand:VWEXTI 0 "register_operand")
> +   (plus:VWEXTI
> + (mult:VWEXTI
> +   (any_extend:VWEXTI
> + (match_operand: 2 "register_operand"))
> +   (any_extend:VWEXTI
> + (match_operand: 3 "register_operand")))
> + (match_operand:VWEXTI 1 "register_operand")))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +  {
> +riscv_vector::emit_vlmax_ternary_insn (code_for_pred_widen_mul_plus 
> (, mode),
> +  riscv_vector::RVV_WIDEN_TERNOP, 
> operands);
> +DONE;
> +  }
> +  [(set_attr "type" "viwmuladd")
> +   (set_attr "mode" "")])
> +
> +;; This helps to match ext + fma.
> +(define_insn_and_split "*single_mult_plus"
> +  [(set (match_operand:VWEXTI 0 "register_operand")
> +   (plus:VWEXTI
> + (mult:VWEXTI
> +   (any_extend:VWEXTI
> + (match_operand: 2

RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

[Li, Pan2 via Gcc-patches]

Update the PATCH V2 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620787.html

Pan

From: Li, Pan2
Sent: Tuesday, June 6, 2023 10:34 PM
To: 钟居哲 ; gcc-patches 
Cc: kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and 
pattern

IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, 
or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.

Pan

From: 钟居哲 mailto:juzhe.zh...@rivai.ai>>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and 
pattern

+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-06 20:36
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend): New pattern for
the ZVFHMIN instruction.
(@pred_trunc): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 28 -
gcc/config/riscv/vector.md| 40 +++
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && 
TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") 
(VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")

RE: Re: [PATCH] RISC-V: Fix ICE when include riscv_vector.h with rv64gcv

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 7, 2023 10:26 AM
To: kito.cheng ; Li, Pan2 
Cc: gcc-patches ; Kito.cheng ; 
Wang, Yanzhang ; Robin Dapp 
Subject: Re: Re: [PATCH] RISC-V: Fix ICE when include riscv_vector.h with 
rv64gcv

LGTM.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-06-07 10:22
To: pan2.li
CC: gcc-patches; 
juzhe.zhong; 
kito.cheng; 
yanzhang.wang; 
rdapp.gcc
Subject: Re: [PATCH] RISC-V: Fix ICE when include riscv_vector.h with rv64gcv
lgtm, thanks for fixing this :)

On Wed, Jun 7, 2023 at 10:19 AM Pan Li via Gcc-patches
mailto:gcc-patches@gcc.gnu.org>> wrote:
>
> From: Pan Li mailto:pan2...@intel.com>>
>
> This patch would like to fix the incorrect requirement of the vector
> builtin types for the ZVFH/ZVFHMIN extension. The incorrect requirement
> will result in the ops mismatch with iterators, and then ICE will be
> triggered if ZVFH/ZVFHMIN is not given.
>
> Sorry for inconviensient.
>
> Signed-off-by: Pan Li mailto:pan2...@intel.com>>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat32mf2_t): Take RVV_REQUIRE_ELEN_FP_16 as requirement.
> (vfloat32m1_t): Ditto.
> (vfloat32m2_t): Ditto.
> (vfloat32m4_t): Ditto.
> (vfloat32m8_t): Ditto.
> (vint16mf4_t): Ditto.
> (vint16mf2_t): Ditto.
> (vint16m1_t): Ditto.
> (vint16m2_t): Ditto.
> (vint16m4_t): Ditto.
> (vint16m8_t): Ditto.
> (vuint16mf4_t): Ditto.
> (vuint16mf2_t): Ditto.
> (vuint16m1_t): Ditto.
> (vuint16m2_t): Ditto.
> (vuint16m4_t): Ditto.
> (vuint16m8_t): Ditto.
> (vint32mf2_t): Ditto.
> (vint32m1_t): Ditto.
> (vint32m2_t): Ditto.
> (vint32m4_t): Ditto.
> (vint32m8_t): Ditto.
> (vuint32mf2_t): Ditto.
> (vuint32m1_t): Ditto.
> (vuint32m2_t): Ditto.
> (vuint32m4_t): Ditto.
> (vuint32m8_t): Ditto.
> ---
>  .../riscv/riscv-vector-builtins-types.def | 66 +--
>  1 file changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index bd3deae8340..589ea532727 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -518,23 +518,23 @@ DEF_RVV_FULL_V_U_OPS (vuint64m2_t, RVV_REQUIRE_FULL_V)
>  DEF_RVV_FULL_V_U_OPS (vuint64m4_t, RVV_REQUIRE_FULL_V)
>  DEF_RVV_FULL_V_U_OPS (vuint64m8_t, RVV_REQUIRE_FULL_V)
>
> -DEF_RVV_WEXTF_OPS (vfloat32mf2_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32 | 
> RVV_REQUIRE_MIN_VLEN_64)
> -DEF_RVV_WEXTF_OPS (vfloat32m1_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32)
> -DEF_RVV_WEXTF_OPS (vfloat32m2_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32)
> -DEF_RVV_WEXTF_OPS (vfloat32m4_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32)
> -DEF_RVV_WEXTF_OPS (vfloat32m8_t, TARGET_ZVFH | RVV_REQUIRE_ELEN_FP_32)
> +DEF_RVV_WEXTF_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_16 | 
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_WEXTF_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_WEXTF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_WEXTF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_WEXTF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_16)
>
>  DEF_RVV_WEXTF_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
>  DEF_RVV_WEXTF_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
>  DEF_RVV_WEXTF_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
>  DEF_RVV_WEXTF_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
>
> -DEF_RVV_CONVERT_I_OPS (vint16mf4_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64)
> -DEF_RVV_CONVERT_I_OPS (vint16mf2_t, TARGET_ZVFH)
> -DEF_RVV_CONVERT_I_OPS (vint16m1_t, TARGET_ZVFH)
> -DEF_RVV_CONVERT_I_OPS (vint16m2_t, TARGET_ZVFH)
> -DEF_RVV_CONVERT_I_OPS (vint16m4_t, TARGET_ZVFH)
> -DEF_RVV_CONVERT_I_OPS (vint16m8_t, TARGET_ZVFH)
> +DEF_RVV_CONVERT_I_OPS (vint16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_CONVERT_I_OPS (vint16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_CONVERT_I_OPS (vint16m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_CONVERT_I_OPS (vint16m2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_CONVERT_I_OPS (vint16m4_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_CONVERT_I_OPS (vint16m8_t, RVV_REQUIRE_ELEN_FP_16)
>
>  DEF_RVV_CONVERT_I_OPS (vint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
>  DEF_RVV_CONVERT_I_OPS (vint32m1_t, 0)
> @@ -546,12 +546,12 @@ DEF_RVV_CONVERT_I_OPS (vint64m2_t, RVV_REQUIRE_ELEN_64)
>  DEF_RVV_CONVERT_I_OPS (vint64m4_t, RVV_REQUIRE_ELEN_64)
>  DEF_RVV_CONVERT_I_OPS (vint64m8_t, RVV_REQUIRE_ELEN_64)
>
> -DEF_RVV_CONVERT_U_OPS (vuint16mf4_t, TARGET_ZVFH | RVV_REQUIRE_MIN_VLEN_64)
> -DEF_RVV_CONVERT_U_OPS (

RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

[Li, Pan2 via Gcc-patches]

Update the PATCH v3 with rvv.exp/riscv.exp all passed as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620855.html

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Li, Pan2 via Gcc-patches
Sent: Tuesday, June 6, 2023 11:34 PM
To: 钟居哲 ; gcc-patches 
Cc: kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and 
pattern

Update the PATCH V2 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620787.html

Pan

From: Li, Pan2
Sent: Tuesday, June 6, 2023 10:34 PM
To: 钟居哲 ; gcc-patches 
Cc: kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and 
pattern

IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, 
or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.

Pan

From: 钟居哲 mailto:juzhe.zh...@rivai.ai>>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and 
pattern

+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?



juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: pan2.li<mailto:pan2...@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@sifive.com>; pan2.li<mailto:pan2...@intel.com>; 
yanzhang.wang<mailto:yanzhang.w...@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the ZVFHMIN implementation by separated 
iterator and pattern. Thus, we can tell the sub extension between the ZVFHMIN 
and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one 
test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Move ZVFHMIN related items to separated 
iterators.
* config/riscv/vector.md (@pred_extend): New pattern for the ZVFHMIN 
instruction.
(@pred_trunc): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 28 -
gcc/config/riscv/vector.md| 40 +++
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 
3 files changed, 83 insertions(+), 10 deletions(-) create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (

RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Thanks JuZhe, make sense, will update the V4 for this change.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 ; gcc-patches 
Cc: Kito.cheng ; Li, Pan2 ; Wang, 
Yanzhang 
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

HI,

+  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")

Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.




juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-07 11:00
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 68 +--
gcc/config/riscv/vector.md| 46 ++---
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 +++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
-  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_ZVFH")
+  (VNx4HF "TARGET_ZVFH")
+  (VNx8HF "TARGET_ZVFH")
+  (VNx16HF "TARGET_ZVFH")
+  (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_ZVFH")
+  (VNx4SF "TARGET_ZVFH")
+  (VNx8SF "TARGET_ZVFH")
+  (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
-  (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
-  (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
-  (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+  (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2SI "TARGET_ZVFH")
+  (VNx4SI "TARGET_ZVFH")
+  (VNx8SI "TARGET_ZVFH")
+  (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx32SI "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && 
TARGET_MIN_VLEN < 128")
   (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
@@ -526,6 +526,21 @@ (define_mode_iterator VWCONVERTI [
   (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && 
TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator VCONVERTF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8SF

RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Update the PATCH V4 as below, sorry for missed the v4 prefix in subject.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620879.html

Pan

From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:21 PM
To: juzhe.zh...@rivai.ai; gcc-patches 
Cc: Kito.cheng ; Wang, Yanzhang 
Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

Thanks JuZhe, make sense, will update the V4 for this change.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

HI,

+  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")

Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.




juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-07 11:00
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 68 +--
gcc/config/riscv/vector.md| 46 ++---
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 +++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
-  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_ZVFH")
+  (VNx4HF "TARGET_ZVFH")
+  (VNx8HF "TARGET_ZVFH")
+  (VNx16HF "TARGET_ZVFH")
+  (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_ZVFH")
+  (VNx4SF "TARGET_ZVFH")
+  (VNx8SF "TARGET_ZVFH")
+  (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONVERTI [
-  (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
-  (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4SI "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8SI "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16SI "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
-  (VNx32SI "TARGET_MIN_VLEN >= 128 && TARGET_VECTOR_ELEN_FP_16")
+  (VNx1SI "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2SI "TARGET_ZVFH")
+  (VNx4SI "TARGET_ZVFH")
+  (VNx8SI "TARGET_ZVFH")
+  (VNx16SI "TARGET_ZVFH && TARGET_MIN_VLEN >

RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Minor change in PATCH V5, please help to turn to V5 as below, sorry for 
inconvenient.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620890.html

Pan

From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:57 PM
To: 'juzhe.zh...@rivai.ai' ; 'gcc-patches' 

Cc: 'Kito.cheng' ; Wang, Yanzhang 

Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

Update the PATCH V4 as below, sorry for missed the v4 prefix in subject.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620879.html

Pan

From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:21 PM
To: juzhe.zh...@rivai.ai; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Wang, 
Yanzhang mailto:yanzhang.w...@intel.com>>
Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

Thanks JuZhe, make sense, will update the V4 for this change.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

HI,

+  (VNx1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")

Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.




juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-07 11:00
To: gcc-patches
CC: juzhe.zhong; 
kito.cheng; pan2.li; 
yanzhang.wang
Subject: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 68 +--
gcc/config/riscv/vector.md| 46 ++---
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 +++
3 files changed, 97 insertions(+), 42 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..1dc82bd44d3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
-  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_ZVFH")
+  (VNx4HF "TARGET_ZVFH")
+  (VNx8HF "TARGET_ZVFH")
+  (VNx16HF "TARGET_ZVFH")
+  (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -497,12 +497,12 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
+  (VNx1SF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_ZVFH")
+  (VNx4SF "TARGET_ZVFH")
+  (VNx8SF "TARGET_ZVFH")
+  (VNx16SF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
@@ -512,12 +512,12 @@ (define_mode_iterator VWEXTF [
])
(define_mode_iterator VWCONV

RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Thanks Juzhe for reviewing. I see, this way may have even smaller code change 
which treats the zvfhmin as minimal base sub extension.
I will have a try for PATCH V6.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 7, 2023 4:27 PM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; Li, 
Pan2 ; Wang, Yanzhang 
Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

In this patch, you add TARGET_ZVFH into VF iterator which is not correct.

When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.

For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH
For vle16,  we should enable for TARGET_ZVFHMIN.
This patch will disable both "vle16" and "vfadd" for FP16 on ZVFHMIN which is 
not correct.

I think you should allow all FP16 vector modes in iterator enable by 
TARGET_VECTOR_FP_ELN_16 (TARGET_ZVFHMIN).

Then, when zvfhmin is enabled, all FP16 instructions are enabled by default.

To gate the situation only enable when TARGET_ZVFH, you add the predicate as 
below:

For example:
vfadd.vv (need

(define_insn "@pred_"
  [(set (match_operand:VF 0 "register_operand"   "=vd, vd, vr, vr")
  (if_then_else:VF
(unspec:
  [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
   (match_operand 5 "vector_length_operand"" rK, rK, rK, rK")
   (match_operand 6 "const_int_operand""  i,  i,  i,  i")
   (match_operand 7 "const_int_operand""  i,  i,  i,  i")
   (match_operand 8 "const_int_operand""  i,  i,  i,  i")
   (match_operand 9 "const_int_operand""  i,  i,  i,  i")
   (reg:SI VL_REGNUM)
   (reg:SI VTYPE_REGNUM)
   (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(any_float_binop:VF
  (match_operand:VF 3 "register_operand"   " vr, vr, vr, vr")
  (match_operand:VF 4 "register_operand"   " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu,  0, vu,  0")))]
  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)"
  "vf.vv\t%0,%3,%4%p1"
  [(set_attr "type" "")
   (set_attr "mode" "")])

bool
float_mode_supported_p (machine_mode mode)
{
  if (GET_MODE_INNER (mode) == HFmode)
 return TARGET_ZVFH;
   return true;
}



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-07 16:06
To: gcc-patches
CC: juzhe.zhong; 
rdapp.gcc; 
jeffreyalaw; pan2.li; 
yanzhang.wang
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 79 +--
gcc/config/riscv/vector.md| 46 +--
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 ++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
-  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_ZVFH")
+  (VNx4HF "TARGET_ZVFH")
+  (VNx8HF "TARGET_ZVFH")
+  (VNx16HF "TARGET_ZVFH")
+  (VNx32HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
-  (VNx1HF "TARGET_VEC

RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Update the PATCH v7 (please help to ignore v6) for this change, thanks Juzhe 
for the suggestion.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621012.html

Pan

From: Li, Pan2
Sent: Wednesday, June 7, 2023 4:43 PM
To: juzhe.zh...@rivai.ai; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; 
Wang, Yanzhang 
Subject: RE: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

Thanks Juzhe for reviewing. I see, this way may have even smaller code change 
which treats the zvfhmin as minimal base sub extension.
I will have a try for PATCH V6.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Wednesday, June 7, 2023 4:27 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp mailto:rdapp@gmail.com>>; jeffreyalaw 
mailto:jeffreya...@gmail.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

In this patch, you add TARGET_ZVFH into VF iterator which is not correct.

When TARGET_ZVFH is true, TARGET_ZVFHMIN is always true.

For vfadd, it is true we should enable "vfadd" for TARGET_ZVFH
For vle16,  we should enable for TARGET_ZVFHMIN.
This patch will disable both "vle16" and "vfadd" for FP16 on ZVFHMIN which is 
not correct.

I think you should allow all FP16 vector modes in iterator enable by 
TARGET_VECTOR_FP_ELN_16 (TARGET_ZVFHMIN).

Then, when zvfhmin is enabled, all FP16 instructions are enabled by default.

To gate the situation only enable when TARGET_ZVFH, you add the predicate as 
below:

For example:
vfadd.vv (need

(define_insn "@pred_"
  [(set (match_operand:VF 0 "register_operand"   "=vd, vd, vr, vr")
  (if_then_else:VF
(unspec:
  [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
   (match_operand 5 "vector_length_operand"" rK, rK, rK, rK")
   (match_operand 6 "const_int_operand""  i,  i,  i,  i")
   (match_operand 7 "const_int_operand""  i,  i,  i,  i")
   (match_operand 8 "const_int_operand""  i,  i,  i,  i")
   (match_operand 9 "const_int_operand""  i,  i,  i,  i")
   (reg:SI VL_REGNUM)
   (reg:SI VTYPE_REGNUM)
   (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(any_float_binop:VF
  (match_operand:VF 3 "register_operand"   " vr, vr, vr, vr")
  (match_operand:VF 4 "register_operand"   " vr, vr, vr, vr"))
(match_operand:VF 2 "vector_merge_operand" " vu,  0, vu,  0")))]
  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)"
  "vf.vv\t%0,%3,%4%p1"
  [(set_attr "type" "")
   (set_attr "mode" "")])

bool
float_mode_supported_p (machine_mode mode)
{
  if (GET_MODE_INNER (mode) == HFmode)
 return TARGET_ZVFH;
   return true;
}



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-07 16:06
To: gcc-patches
CC: juzhe.zhong; 
rdapp.gcc; 
jeffreyalaw; pan2.li; 
yanzhang.wang
Subject: [PATCH v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Add requirement to VF,
VWEXTF and VWCONVERTI, add V_CONVERT_F and VCONVERTF.
* config/riscv/vector.md: Adjust FP convert to V_CONVERT_F
and VCONVERTF, and fix V_WHOLE and V_FRACT.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md  | 79 +--
gcc/config/riscv/vector.md| 46 +--
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 25 ++
3 files changed, 104 insertions(+), 46 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..e6c2ecf7c86 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -296,13 +296,13 @@ (define_mode_iterator VWI_ZVE32 [
])
(define_mode_iterator VF [
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
-  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+  (VNx1HF "TARGET_ZVFH && TARGET_MIN_VLEN

RE: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Sure, update it in PATCH v8.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621016.html

Pan

From: juzhe.zh...@rivai.ai 
Sent: Thursday, June 8, 2023 2:09 PM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; Li, 
Pan2 ; Wang, Yanzhang 
Subject: Re: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

Rename float_point_mode_supported_p into float_mode_supported_p



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-08 14:06
To: gcc-patches
CC: juzhe.zhong; 
rdapp.gcc; 
jeffreyalaw; pan2.li; 
yanzhang.wang
Subject: [PATCH v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one function as
the gate for FP16 supported or not.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

gcc/ChangeLog:

* config/riscv/riscv-protos.h (float_point_mode_supported_p):
New function to float point is supported by extension.
* config/riscv/riscv-v.cc (float_point_mode_supported_p):
Ditto.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
* config/riscv/vector.md: Add condition to FP define insn.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv-protos.h   |   1 +
gcc/config/riscv/riscv-v.cc   |  12 ++
gcc/config/riscv/vector-iterators.md  |  23 +--
gcc/config/riscv/vector.md| 144 ++
.../riscv/rvv/base/zvfhmin-intrinsic.c|  15 +-
5 files changed, 118 insertions(+), 77 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ebbaac255f9..e4881786b53 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec, unsigned int,
   tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+bool float_point_mode_supported_p (machine_mode mode);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 49752cd8899..1cc157f1858 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
  && IN_RANGE (INTVAL (elt), minval, maxval));
}
+/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
+   float point machine mode.  */
+bool
+float_point_mode_supported_p (machine_mode mode)
+{
+  machine_mode inner_mode = GET_MODE_INNER (mode);
+
+  gcc_assert (FLOAT_MODE_P (inner_mode));
+
+  return inner_mode == HFmode ? TARGET_ZVFH : true;
+}
+
/* Return true if VEC is a constant in which every element is in the range
[MINVAL, MAXVAL].  The elements do not need to have the same value.
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index f4946d84449..234b712bc9d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
-  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
-  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
-  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
   (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
   (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
   (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
@@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
(define_mode_iterator V_FRACT [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") 
(VNx8QI "TARGET_MIN_VLEN >= 128")
   (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI 
"TARGET_MIN_VLEN >= 128")
-  (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF 
"TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+

RE: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Looks doable up to a point, I will have a try and keep you posted.

Pan

-Original Message-
From: Kito Cheng  
Sent: Thursday, June 8, 2023 3:58 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Robin 
Dapp ; jeffreyalaw ; Wang, Yanzhang 

Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

I am thinking, is it possible to use mode attr to remove the overhead of 
checking the mode for other FP modes other than FP16?

e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
  (VNx1HF "TARGET_ZVFH")
...
  (VNx1SF "1")
...
])


  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)"
->
  "TARGET_VECTOR && "


On Thu, Jun 8, 2023 at 2:35 PM juzhe.zh...@rivai.ai  
wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 
> autovec.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; 
> kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li 
>
> This patch would like to refactor the requirement of both the ZVFH and 
> ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the 
> iterators of RVV. And then the ZVFH will leverage one function as the 
> gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch 
> add one test for this.
>
> Signed-off-by: Pan Li  Co-Authored by: Juzhe-Zhong 
> 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test for 
> ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h   |   1 +
> gcc/config/riscv/riscv-v.cc   |  12 ++
> gcc/config/riscv/vector-iterators.md  |  23 +--
> gcc/config/riscv/vector.md| 144 ++
> .../riscv/rvv/base/zvfhmin-intrinsic.c|  15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h 
> b/gcc/config/riscv/riscv-protos.h index ebbaac255f9..1f606f59ce1 
> 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx); bool 
> check_builtin_call (location_t, vec, unsigned int,
>tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, 
> HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx); void 
> emit_hard_vlmax_vsetvl (machine_mode, rtx); diff --git 
> a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 
> 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -418,6 +418,18 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT 
> minval,
>   && IN_RANGE (INTVAL (elt), minval, maxval)); }
> +/* Return true if the inner of mode is HFmode when ZVFH enabled, or other
> +   float point machine mode.  */
> +bool
> +float_mode_supported_p (machine_mode mode) {
> +  machine_mode inner_mode = GET_MODE_INNER (mode);
> +
> +  gcc_assert (FLOAT_MODE_P (inner_mode));
> +
> +  return inner_mode == HFmode ? TARGET_ZVFH : true; }
> +
> /* Return true if VEC is a constant in which every element is in the range
> [MINVAL, MAXVAL].  The elements do not need to have the same value.
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
>(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
> "TARGET_VECTOR_ELEN_64")
>(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") 
> (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> -  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> -  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> -  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")  
> + (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
>(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
>(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
>(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ 
> -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [ 
> (define_mode_iterator V_FRACT [
>(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") 
> (VNx8QI "TARGET_MIN_VLEN >= 128")
>(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") 
> (VNx4HI "TARGET_MIN_VLEN >= 128")
> -  (VNx1HF "TARGET_MIN_VLEN

RE: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Thanks Juzhe for the idea. It looks work well as we expected, with the 
following try.


  1.  Allow all FP=16 types for vfadd, then _zvfh and _zvfhmin will be OK.
  2.  Add restriction define_attr as juzhe mentioned, then _zvfh works well, 
and _zvfhmin will meet error like unsatisfied insn.

I think only we need to do is the define_attr, and there will be no changes to 
vector.md. If no more concern, will have a try for this approach.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Thursday, June 8, 2023 4:32 PM
To: kito.cheng 
Cc: Li, Pan2 ; gcc-patches ; Robin 
Dapp ; jeffreyalaw ; Wang, Yanzhang 

Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

I have an idea base on what Kito said.
We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR && 

for each instruction.

We can reference riscv.md:
(define_attr "ext_enabled" "no,yes"
  (cond [(eq_attr "ext" "base")
   (const_string "yes")

   (and (eq_attr "ext" "f")
(match_test "TARGET_HARD_FLOAT"))
   (const_string "yes")

   (and (eq_attr "ext" "d")
(match_test "TARGET_DOUBLE_FLOAT"))
   (const_string "yes")

   (and (eq_attr "ext" "vector")
(match_test "TARGET_VECTOR"))
   (const_string "yes")
  ]
  (const_string "no")))

Define a new attribute as follows:
(define_attr "fp16_vector_enabled" "no,yes"
  (cond [
   (and (eq_attr "type" "vfalu")
 (and eq_attr "mode" "VNx1HF")
(match_test "!TARGET_ZVFH")))
   (const_string "no")
  ]
  (const_string "yes")))


I think you can do experiment with this to see whether it can disable MD 
pattern.


juzhe.zh...@rivai.ai

From: Kito Cheng
Date: 2023-06-08 15:58
To: juzhe.zh...@rivai.ai
CC: pan2.li; 
gcc-patches; Robin 
Dapp; jeffreyalaw; 
yanzhang.wang
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am thinking, is it possible to use mode attr to remove the overhead
of checking the mode for other FP modes other than FP16?

e.g.
(define_mode_attr TARGET_FP_FULL_OPERATION_CHECKING [
  (VNx1HF "TARGET_ZVFH")
...
  (VNx1SF "1")
...
])


  "TARGET_VECTOR && riscv_vector::float_mode_supported_p (mode)"
->
  "TARGET_VECTOR && "


On Thu, Jun 8, 2023 at 2:35 PM juzhe.zh...@rivai.ai
mailto:juzhe.zh...@rivai.ai>> wrote:
>
> LGTM. Let's wait for Jeff and Robin. After this patch, we can start FP16 
> autovec.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-08 14:29
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li mailto:pan2...@intel.com>>
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one function as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li mailto:pan2...@intel.com>>
> Co-Authored by: Juzhe-Zhong 
> mailto:juzhe.zh...@rivai.ai>>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (float_mode_supported_p):
> New function to float point is supported by extension.
> * config/riscv/riscv-v.cc (float_mode_supported_p):
> Ditto.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
> * config/riscv/vector.md: Add condition to FP define insn.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv-protos.h   |   1 +
> gcc/config/riscv/riscv-v.cc   |  12 ++
> gcc/config/riscv/vector-iterators.md  |  23 +--
> gcc/config/riscv/vector.md| 144 ++
> .../riscv/rvv/base/zvfhmin-intrinsic.c|  15 +-
> 5 files changed, 118 insertions(+), 77 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index ebbaac255f9..1f606f59ce1 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -177,6 +177,7 @@ rtx expand_builtin (unsigned int, tree, rtx);
> bool check_builtin_call (location_t, vec, unsigned int,
>tree, unsigned int, tree *);
> bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
> +bool float_mode_supported_p (machine_mode mode);
> bool legitimize_move (rtx, rtx);
> void emit_vlmax_vsetvl (machine_mode, rtx);
> void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 49752cd8899..fe4eb058ec0 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/

RE: [PATCH v2] RISC-V: Add more test cases for RVV FP16

[Li, Pan2 via Gcc-patches]

Committed as passed all riscv.exp rvv.exp tests, thanks Jeff.

Pan

-Original Message-
From: Jeff Law  
Sent: Thursday, June 8, 2023 10:01 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; rdapp@gmail.com; Wang, Yanzhang 
; kito.ch...@gmail.com
Subject: Re: [PATCH v2] RISC-V: Add more test cases for RVV FP16



On 6/8/23 01:52, pan2...@intel.com wrote:
> From: Pan Li 
> 
> This patch would like to add new test cases to make sure the RVV FP16 
> works well as expected.
> 
> Signed-off-by: Pan Li 
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Add new cases.
>   * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
OK.  If there are dependencies on the ZVFHMIN (or anything else) then please 
wait to commit.  If the current compiler can handle these new tests, then you 
can go ahead and commit them now.

jeff

RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type 
attr definition.

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

>> I think it should only add fp16_vector_disable. However, it seems the whole 
>> thing is removed?
The same as above, move to the place after than type attr definition and only 
add fp_vector_disable here.

>> This should be in vector.md instead of riscv.md
It will trigger "unknown attribute `fp_vector_disabled' in definition of 
attribute `enabled'", because riscv.md include the vector.md at the end of file.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; Li, 
Pan2 ; Wang, Yanzhang ; kito.cheng 

Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))


Why change this ?

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

I think it should only add fp16_vector_disable. However, it seems the whole 
thing is removed?

+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+  (cond [
+(and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+   vfwalu,vfwmul,vfmuladd,vfwmuladd,
+   vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+   vfclass,vfmerge,
+   vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+   vfredo,vfredu,vfwredo,vfwredu,
+   vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+   (match_test "!TARGET_ZVFH")))
+(const_string "yes")
+
+(and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+   (match_test "!TARGET_ZVFH")))
+(const_string "yes")
+  ]
+  (const_string "no")))
This should be in vector.md instead of riscv.md


juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-09 13:59
To: gcc-patches
CC: juzhe.zhong; 
rdapp.gcc; 
jeffreyalaw; pan2.li; 
yanzhang.wang; 
kito.cheng
Subject: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr
the gate for FP16 supported or not.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>
Co-Authored by: Kito Cheng mailto:kito.ch...@sifive.com>>

gcc/ChangeLog:

* config/riscv/riscv.md (ext): Move to another place.
(ext_enabled): Ditto.
(fp_vector_disabled): New define attr.
(enabled): Add fp_vector_disabled to the cond.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
for ZVFHMIN.
---
gcc/config/riscv/riscv.md | 84 ---
gcc/config/riscv/vector-iterators.md  | 23 ++---
.../riscv/rvv/base/zvfhmin-intrinsic.c| 15 +++-
3 files changed, 81 insertions(+), 41 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 38b8fba2a53..d1c7c3a3008 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -216,35 +216,6 @@ (define_attr "dword_mode" "no,yes"
(const_string "yes")]
(const_string "no"

RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

By logically, Yes, we should not change that but here I would like to put all 
enable related code together, will remove this part as it may has no 
relationship with this patch.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Friday, June 9, 2023 2:31 PM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; 
Wang, Yanzhang ; kito.cheng 
Subject: Re: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

OK. But why change the place of these

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.



juzhe.zh...@rivai.ai

From: Li, Pan2
Date: 2023-06-09 14:23
To: juzhe.zh...@rivai.ai; 
gcc-patches
CC: Robin Dapp; 
jeffreyalaw; Wang, 
Yanzhang; 
kito.cheng
Subject: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type 
attr definition.

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

>> I think it should only add fp16_vector_disable. However, it seems the whole 
>> thing is removed?
The same as above, move to the place after than type attr definition and only 
add fp_vector_disable here.

>> This should be in vector.md instead of riscv.md
It will trigger “unknown attribute `fp_vector_disabled' in definition of 
attribute `enabled'”, because riscv.md include the vector.md at the end of file.

Pan

From: juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp mailto:rdapp@gmail.com>>; jeffreyalaw 
mailto:jeffreya...@gmail.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>; kito.cheng 
mailto:kito.ch...@gmail.com>>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))


Why change this ?

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

I think it should only add fp16_vector_disable. However, it seems the whole 
thing is removed?

+;; True if the float point vector is disabled.
+(define_attr "fp_vector_disabled" "no,yes"
+  (cond [
+(and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
+   vfwalu,vfwmul,vfmuladd,vfwmuladd,
+   vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
+   vfclass,vfmerge,
+   vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
+   vfredo,vfredu,vfwredo,vfwredu,
+   vfslide1up,vfslide1down")
+ (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
+   (match_test "!TARGET_ZVFH")))
+(const_string "yes")
+
+(and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
+ (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
+   (match_test "!TARGET_ZVFH")))
+(const_string "yes")
+  ]
+  (const_string "no")))
This should be in vector.md instead of riscv.md


juzhe.zh...@rivai.ai

From: pan2.li

RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Thanks Juzhe and Kito for reviewing, update the PATCH v10 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621104.html

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Li, Pan2 via Gcc-patches
Sent: Friday, June 9, 2023 2:41 PM
To: juzhe.zh...@rivai.ai; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; 
Wang, Yanzhang ; kito.cheng 
Subject: RE: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

By logically, Yes, we should not change that but here I would like to put all 
enable related code together, will remove this part as it may has no 
relationship with this patch.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Friday, June 9, 2023 2:31 PM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; 
Wang, Yanzhang ; kito.cheng 
Subject: Re: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

OK. But why change the place of these

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
I think it should not be changed.



juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: Li, Pan2<mailto:pan2...@intel.com>
Date: 2023-06-09 14:23
To: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; 
gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: Robin Dapp<mailto:rdapp@gmail.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; Wang, 
Yanzhang<mailto:yanzhang.w...@intel.com>; 
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: RE: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARGET_VECTOR"))
- (const_string "yes")
- ]
- (const_string "no")))
>> Why change this ?
As the fp will reference the type attr, we should move this part after the type 
attr definition.

-;; Attribute to control enable or disable instructions.
-(define_attr "enabled" "no,yes"
-  (cond [(eq_attr "ext_enabled" "no")
- (const_string "no")]
- (const_string "yes")))

>> I think it should only add fp16_vector_disable. However, it seems the whole 
>> thing is removed?
The same as above, move to the place after than type attr definition and only 
add fp_vector_disable here.

>> This should be in vector.md instead of riscv.md
It will trigger “unknown attribute `fp_vector_disabled' in definition of 
attribute `enabled'”, because riscv.md include the vector.md at the end of file.

Pan

From: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> 
mailto:juzhe.zh...@rivai.ai>>
Sent: Friday, June 9, 2023 2:14 PM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp mailto:rdapp@gmail.com>>; jeffreyalaw 
mailto:jeffreya...@gmail.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>; kito.cheng 
mailto:kito.ch...@gmail.com>>
Subject: Re: [PATCH v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

-;; ISA attributes.
-(define_attr "ext" "base,f,d,vector"
-  (const_string "base"))
-
-;; True if the extension is enabled.
-(define_attr "ext_enabled" "no,yes"
-  (cond [(eq_attr "ext" "base")
- (const_string "yes")
-
- (and (eq_attr "ext" "f")
-   (match_test "TARGET_HARD_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "d")
-   (match_test "TARGET_DOUBLE_FLOAT"))
- (const_string "yes")
-
- (and (eq_attr "ext" "vector")
-   (match_test "TARG

RE: [PATCH v1] RISC-V: Fix one warning of frm enum.

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

From: Kito Cheng 
Sent: Friday, June 9, 2023 4:11 PM
To: juzhe.zh...@rivai.ai
Cc: Robin Dapp ; gcc-patches ; 
jeffreyalaw ; Li, Pan2 ; Wang, 
Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Fix one warning of frm enum.

Lgtm

juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>>於 2023年6月9日 週五，16:08寫道：
Ok.



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-09 15:53
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; 
yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one warning of frm enum.
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to fix one warning similar as below, and add the
link for where the values comes from.

./gcc/config/riscv/riscv-protos.h:260:13: warning: binary constants are
a C++14 feature or GCC extension
FRM_RNE = 0b000,
  ^

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv-protos.h (enum frm_field_enum): Adjust
literal to int.
---
gcc/config/riscv/riscv-protos.h | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 38e4125424b..66c1f535d60 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -254,15 +254,18 @@ enum vxrm_field_enum
   VXRM_RDN,
   VXRM_ROD
};
-/* Rounding mode bitfield for floating point FRM.  */
+/* Rounding mode bitfield for floating point FRM.  The value of enum comes
+   from the below link.
+   
https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register
+ */
enum frm_field_enum
{
-  FRM_RNE = 0b000,
-  FRM_RTZ = 0b001,
-  FRM_RDN = 0b010,
-  FRM_RUP = 0b011,
-  FRM_RMM = 0b100,
-  FRM_DYN = 0b111
+  FRM_RNE = 0, /* Aka 0b000.  */
+  FRM_RTZ = 1, /* Aka 0b001.  */
+  FRM_RDN = 2, /* Aka 0b010.  */
+  FRM_RUP = 3, /* Aka 0b011.  */
+  FRM_RMM = 4, /* Aka 0b100.  */
+  FRM_DYN = 7, /* Aka 0b111.  */
};
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
--
2.34.1

RE: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

[Li, Pan2 via Gcc-patches]

Committed, thanks Juzhe and Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Friday, June 9, 2023 4:28 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Robin 
Dapp ; jeffreyalaw ; Wang, Yanzhang 

Subject: Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.

lgtm too, thanks :)

On Fri, Jun 9, 2023 at 3:15 PM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-09 15:07
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
> From: Pan Li 
>
> This patch would like to refactor the requirement of both the ZVFH
> and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
> iterators of RVV. And then the ZVFH will leverage one define attr as
> the gate for FP16 supported or not.
>
> Please note the ZVFH will cover the ZVFHMIN instructions. This patch
> add one test for this.
>
> Signed-off-by: Pan Li 
> Co-Authored by: Juzhe-Zhong 
> Co-Authored by: Kito Cheng 
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md (enabled): Move to another place, and
> add fp_vector_disabled to the cond.
> (fp_vector_disabled): New attr defined for disabling fp.
> * config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add vle16 test
> for ZVFHMIN.
> ---
> gcc/config/riscv/riscv.md | 39 ---
> gcc/config/riscv/vector-iterators.md  | 23 ++-
> .../riscv/rvv/base/zvfhmin-intrinsic.c| 15 ++-
> 3 files changed, 59 insertions(+), 18 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 38b8fba2a53..d8e935cb934 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -239,12 +239,6 @@ (define_attr "ext_enabled" "no,yes"
> ]
> (const_string "no")))
> -;; Attribute to control enable or disable instructions.
> -(define_attr "enabled" "no,yes"
> -  (cond [(eq_attr "ext_enabled" "no")
> - (const_string "no")]
> - (const_string "yes")))
> -
> ;; Classification of each insn.
> ;; branch conditional branch
> ;; jump unconditional jump
> @@ -434,6 +428,39 @@ (define_attr "type"
> (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
> (const_string "unknown")))
> +;; True if the float point vector is disabled.
> +(define_attr "fp_vector_disabled" "no,yes"
> +  (cond [
> +(and (eq_attr "type" "vfmov,vfalu,vfmul,vfdiv,
> +   vfwalu,vfwmul,vfmuladd,vfwmuladd,
> +   vfsqrt,vfrecp,vfminmax,vfsgnj,vfcmp,
> +   vfclass,vfmerge,
> +   vfncvtitof,vfwcvtftoi,vfcvtftoi,vfcvtitof,
> +   vfredo,vfredu,vfwredo,vfwredu,
> +   vfslide1up,vfslide1down")
> + (and (eq_attr "mode" "VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF")
> +   (match_test "!TARGET_ZVFH")))
> +(const_string "yes")
> +
> +;; The mode records as QI for the FP16 <=> INT8 instruction.
> +(and (eq_attr "type" "vfncvtftoi,vfwcvtitof")
> + (and (eq_attr "mode" "VNx1QI,VNx2QI,VNx4QI,VNx8QI,VNx16QI,VNx32QI,VNx64QI")
> +   (match_test "!TARGET_ZVFH")))
> +(const_string "yes")
> +  ]
> +  (const_string "no")))
> +
> +;; Attribute to control enable or disable instructions.
> +(define_attr "enabled" "no,yes"
> +  (cond [
> +(eq_attr "ext_enabled" "no")
> +(const_string "no")
> +
> +(eq_attr "fp_vector_disabled" "yes")
> +(const_string "no")
> +  ]
> +  (const_string "yes")))
> +
> ;; Length of instruction in bytes.
> (define_attr "length" ""
> (cond [
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index f4946d84449..234b712bc9d 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -453,9 +453,8 @@ (define_mode_iterator V_WHOLE [
>(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
> "TARGET_VECTOR_ELEN_64")
>(VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
> "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
> -  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
> -  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
> -  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
> +  (VNx2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 32")
> +  (VNx4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN == 64")
>(VNx8HF "TARGET_VECTOR_ELEN_FP_16")
>(VNx16HF "TARGET_VECTOR_ELEN_FP_16")
>(VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
> @@ -477,7 +476,11 @@ (define_mode_iterator V_WHOLE [
> (define_mode_iterator V_FRACT [
>(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN > 32") 
> (VNx8QI "TARGET_MIN_VLEN >= 128")
>(VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI 
> "TARGET_MIN_VLEN >= 128")
> -  (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF 
> "TARGET_MIN_VLEN >= 128")
> +
> +  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_V

RE: [PATCH V6] VECT: Add SELECT_VL support

[Li, Pan2 via Gcc-patches]

Committed with bootstrap and regression test passed, thanks all.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Richard Sandiford via Gcc-patches
Sent: Saturday, June 10, 2023 1:44 AM
To: juzhe.zh...@rivai.ai
Cc: rguenther ; gcc-patches 
Subject: Re: [PATCH V6] VECT: Add SELECT_VL support

"juzhe.zh...@rivai.ai"  writes:
> Thanks, Richi.
>
> Should I wait for Richard ACK gain ? 
> Since the last email of this patch, he just asked me to adjust comment no 
> codes change.
> I am not sure whether he is ok.

Yeah, OK from my POV too, thanks.

Richard

RE: [PATCH] RISC-V: Enable select_vl for RVV auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Saturday, June 10, 2023 11:03 AM
To: juzhe.zh...@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; pal...@rivosinc.com; 
rdapp@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V: Enable select_vl for RVV auto-vectorization

LGTM, thanks for this

On Sat, Jun 10, 2023 at 8:42 AM  wrote:
>
> From: Juzhe-Zhong 
>
> Consider this following example:
> void vec_add(int32_t *restrict c, int32_t *restrict a, int32_t *restrict b,
>  int N) {
>   for (long i = 0; i < N; i++) {
> c[i] = a[i] + b[i];
>   }
> }
>
> After this patch:
> vec_add:
> ble a3,zero,.L5
> .L3:
> vsetvli a5,a3,e32,m1,ta,ma
> vle32.v v2,0(a1)
> vle32.v v1,0(a2)
> vsetvli a6,zero,e32,m1,ta,ma ===> redundant vsetvl.
> sllia4,a5,2
> vadd.vv v1,v1,v2
> sub a3,a3,a5
> vsetvli zero,a5,e32,m1,ta,ma ===> redundant vsetvl.
> vse32.v v1,0(a0)
> add a1,a1,a4
> add a2,a2,a4
> add a0,a0,a4
> bne a3,zero,.L3
> .L5:
> ret
>
> We can get close-to-optimal codegen but with some redundant vsetvls.
> This is not the big issue which will be easily addressed in RISC-V backend.
>
> I am going to add a standalone PASS "AVL propagation" (avlprop) to 
> addresse such issue.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (select_vl): New pattern.
> * config/riscv/riscv-protos.h (expand_select_vl): New function.
> * config/riscv/riscv-v.cc (expand_select_vl): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Adapt test.
> * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Ditto.
> * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   | 14 ++
>  gcc/config/riscv/riscv-protos.h   |  1 +
>  gcc/config/riscv/riscv-v.cc   | 12 +
>  .../riscv/rvv/autovec/partial/select_vl-1.c   | 26 +++
>  .../riscv/rvv/autovec/ternop/ternop-2.c   |  2 +-
>  .../riscv/rvv/autovec/ternop/ternop-5.c   |  2 +-
>  6 files changed, 55 insertions(+), 2 deletions(-)  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index 9f4492db23c..b7070099f29 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -626,3 +626,17 @@
>}
>[(set_attr "type" "vimuladd")
> (set_attr "mode" "")])
> +
> +;; 
> +=
> +
> +;; == SELECT_VL
> +;; 
> +=
> +
> +
> +(define_expand "select_vl"
> +  [(match_operand:P 0 "register_operand")
> +   (match_operand:P 1 "vector_length_operand")
> +   (match_operand:P 2 "")]
> +  "TARGET_VECTOR"
> +{
> +  riscv_vector::expand_select_vl (operands);
> +  DONE;
> +})
> diff --git a/gcc/config/riscv/riscv-protos.h 
> b/gcc/config/riscv/riscv-protos.h index 66c1f535d60..6db3a46c682 
> 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -246,6 +246,7 @@ void expand_vec_series (rtx, rtx, rtx);  void 
> expand_vec_init (rtx, rtx);  void expand_vcond (rtx *);  void 
> expand_vec_perm (rtx, rtx, rtx, rtx);
> +void expand_select_vl (rtx *);
>  /* Rounding mode bitfield for fixed point VXRM.  */  enum 
> vxrm_field_enum  { diff --git a/gcc/config/riscv/riscv-v.cc 
> b/gcc/config/riscv/riscv-v.cc index 477a22cd2b0..e1b85a5af91 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -2447,4 +2447,16 @@ expand_vec_perm_const (machine_mode vmode, 
> machine_mode op_mode, rtx target,
>return ret;
>  }
>
> +/* Generate no side effects vsetvl to get the vector length.  */ void 
> +expand_select_vl (rtx *ops) {
> +  poly_int64 nunits = rtx_to_poly_int64 (ops[2]);
> +  /* We arbitrary picked QImode as inner scalar mode to get vector mode.
> + since vsetvl only demand ratio. We let VSETVL PASS to optimize 
> +it.  */
> +  scalar_int_mode mode = QImode;
> +  machine_mode rvv_mode = get_vector_mode (mode, nunits).require ();
> +  emit_insn (gen_no_side_effects_vsetvl_rtx (rvv_mode, ops[0], 
> +ops[1])); }
> +
>  } // namespace riscv_vector
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
> new file mode 100644
> index 000..74bbf40ee9f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param 
> +riscv-autovec-preference=scalable -fno-vect-cost-model 
> +-fno-tree-loo

RE: [PATCH v1] RISC-V: Add test cases for RVV FP16 vreinterpret

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Saturday, June 10, 2023 11:03 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com; 
jeffreya...@gmail.com; Wang, Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 vreinterpret

LGTM :)

On Sat, Jun 10, 2023 at 7:59 AM Pan Li via Gcc-patches 
 wrote:
>
> From: Pan Li 
>
> This patch would like to add more tests for RVV FP16 vreinterpret, aka
>
> vfloat16*_t <==> v{u}int16*_t.
>
> There we allow FP16 vreinterpret in ZVFHMIN consider we have vle FP16 already.
> It doesn't break anything in SPEC as there is no such vreinterpret insn.
> From the user's perspective, it is reasonable to do some type convert 
> between vfloat16 and v{u}int16 when only ZVFHMIN is enabled.
>
> This patch would like to add new test cases to make sure the RVV FP16 
> vreinterpret works well as expected.
>
> Signed-off-by: Pan Li 
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new cases.
> * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Diito.
> ---
>  .../riscv/rvv/base/zvfh-over-zvfhmin.c| 14 ++-
>  .../riscv/rvv/base/zvfhmin-intrinsic.c| 38 ++-
>  2 files changed, 50 insertions(+), 2 deletions(-)
>
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> index 2afc105e2da..d5bcdd5156a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
> @@ -29,9 +29,21 @@ vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, 
> size_t vl) {
>return __riscv_vle16_v_f16m8(base, vl);  }
>
> +vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {
> +  return __riscv_vreinterpret_v_i16mf4_f16mf4(src);
> +}
> +
> +vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
> +  return __riscv_vreinterpret_v_f16m8_u16m8(src);
> +}
> +
>  /* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
>  /* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
>  /* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 } } 
> +*/
>  /* { dg-final { scan-assembler-times 
> {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
>  /* { dg-final { scan-assembler-times 
> {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
> -/* { dg-final { scan-assembler-times 
> {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times 
> +{vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 4 } } */
> +/* { dg-final { scan-assembler-times 
> +{vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> +/* { dg-final { scan-assembler-times 
> +{vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
> +/* { dg-final { scan-assembler-times 
> +{vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> index f1a29b639e0..e56b2751d4c 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
> @@ -53,12 +53,48 @@ vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, 
> size_t vl) {
>return __riscv_vle16_v_f16m8(base, vl);  }
>
> +vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {
> +  return __riscv_vreinterpret_v_i16mf4_f16mf4(src);
> +}
> +
> +vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {
> +  return __riscv_vreinterpret_v_i16m8_f16m8(src);
> +}
> +
> +vfloat16mf4_t test_vreinterpret_v_u16mf4_f16mf4(vuint16mf4_t src) {
> +  return __riscv_vreinterpret_v_u16mf4_f16mf4(src);
> +}
> +
> +vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {
> +  return __riscv_vreinterpret_v_u16m8_f16m8(src);
> +}
> +
> +vint16mf4_t test_vreinterpret_v_f16mf4_i16mf4(vfloat16mf4_t src) {
> +  return __riscv_vreinterpret_v_f16mf4_i16mf4(src);
> +}
> +
> +vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {
> +  return __riscv_vreinterpret_v_f16m8_i16m8(src);
> +}
> +
> +vuint16mf4_t test_vreinterpret_v_f16mf4_u16mf4(vfloat16mf4_t src) {
> +  return __riscv_vreinterpret_v_f16mf4_u16mf4(src);
> +}
> +
> +vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
> +  return __riscv_vreinterpret_v_f16m8_u16m8(src);
> +}
> +
>  /* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
>  /* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
>  /* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]} 2 } }

RE: [PATCH V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Sunday, June 11, 2023 12:49 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS



On 6/9/23 17:11, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> Address comments from Jeff.
> 
> This patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 
> 5 && Phase 6 are quite messy and cause some bugs discovered by my 
> downstream auto-vectorization test-generator.
> 
> Before this patch.
> 
> Phase 5 is cleanup_insns is the function remove AVL operand dependency from 
> each RVV instruction.
> E.g. vadd.vv (use a5), after Phase 5, > vadd.vv (use const_int 0). 
> Since "a5" is used in "vsetvl" instructions and after the correct 
> "vsetvl" instructions are inserted, each RVV instruction doesn't need AVL 
> operand "a5" anymore. Then, we remove this operand dependency helps for the 
> following scheduling PASS.
> 
> Phase 6 is propagate_avl do the following 2 things:
> 1. Local && Global user vsetvl instructions optimization.
> E.g.
>vsetvli a2, a2, e8, mf8   ==> Change it into vsetvli a2, a2, e32, 
> mf2
>vsetvli zero,a2, e32, mf2  ==> eliminate 2. Optimize user 
> vsetvl from "vsetvl a2,a2" into "vsetvl zero,a2" if "a2" is not used by any 
> instructions.
> Since from Phase 1 ~ Phase 4 which inserts "vsetvli" instructions base 
> on LCM which change the CFG, I re-new a new RTL_SSA framework (which is more 
> expensive than just using DF) for Phase 6 and optmize user vsetvli base on 
> the new RTL_SSA.
> 
> There are 2 issues in Phase 5 && Phase 6:
> 1. local_eliminate_vsetvl_insn was introduced by @kito which can do better 
> local user vsetvl optimizations better than
> Phase 6 do, such approach doesn't need to re-new the RTL_SSA framework. 
> So the local user vsetvli instructions optimizaiton
> in Phase 6 is redundant and should be removed.
> 2. A bug discovered by my downstream auto-vectorization test-generator (I 
> can't put the test in this patch since we are missing autovec
> patterns for it so we can't use the upstream GCC directly reproduce such 
> issue but I will remember put it back after I support the
> necessary autovec patterns). Such bug is causing by using RTL_SSA re-new 
> framework. The issue description is this:
> 
> Before Phase 6:
> ...
> insn1: vsetlvi a3, 17 <== generated by SELECT_VL auto-vec pattern.
> slli a4,a3,3
> ...
> insn2: vsetvli zero, a3, ...
> load (use const_int 0, before Phase 5, it's using a3, but the use of "a3" 
> is removed in Phase 5)
> ...
> 
> In Phase 6, we iterate to insn2, then get the def of "a3" which is the insn1.
> insn2 is the vsetvli instruction inserted in Phase 4 which is not 
> included in the RLT_SSA framework even though we renew it (I didn't take a 
> look at it and I don't think we need to now).
> Base on this situation, the def_info of insn2 has the information 
> "set->single_nondebug_insn_use ()"
> which return true. Obviously, this information is not correct, since insn1 
> has aleast 2 uses:
> 1). slli a4,a3,3 2).insn2: vsetvli zero, a3, ... Then, the test 
> generated by my downstream test-generator execution test failed.
> 
> Conclusion of RTL_SSA framework:
> Before this patch, we initialize RTL_SSA 2 times. One is at the 
> beginning of the VSETVL PASS which is absolutely correct, the other is re-new 
> after Phase 4 (LCM) has incorrect information that causes bugs.
> 
> Besides, we don't like to initialize RTL_SSA second time it seems to be a 
> waste since we just need to do a little optimization.
> 
> Base on all circumstances I described above, I rework and reorganize Phase 5 
> && Phase 6 as follows:
> 1. Phase 5 is called ssa_post_optimization which is doing the optimization 
> base on the RTL_SSA information (The RTL_SSA is initialized
> at the beginning of the VSETVL PASS, no need to re-new it again). This 
> phase includes 3 optimizaitons:
> 1). local_eliminate_vsetvl_insn we already have (no change).
> 2). global_eliminate_vsetvl_insn ---> new optimizaiton splitted from 
> orignal Phase 6 but with more powerful and reliable implementation.
>E.g.
>void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {
>  size_t avl;
>  if (m > 100)
>avl = __riscv_vsetvl_e16mf4(vl << 4);
>  else
>avl = __riscv_vsetvl_e32mf2(vl >> 8);
>  for (size_t i = 0; i < m; i++) {
>vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
>v0 = __riscv_vadd_vv_i8mf8 (v0, v0, avl);
>__riscv_vse8_v_i8mf8(out + i, v0, avl);
>  }
>}
> 
>This example failed to global user vsetvl optimize before this patch:
>f:
>li  a5,100
>   

RE: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

From: Kito Cheng 
Sent: Monday, June 12, 2023 11:32 AM
To: 钟居哲 
Cc: Li, Pan2 ; gcc-patches ; Robin 
Dapp ; jeffreyalaw ; Wang, Yanzhang 

Subject: Re: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul 
trunc

LGTM

juzhe.zh...@rivai.ai 
mailto:juzhe.zh...@rivai.ai>> 於 2023年6月12日 週一 10:58 寫道：
LGTM.



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-12 10:57
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; 
yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul 
trunc
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to add more tests for RVV FP16 undef and vlmul
trunc, aka

__riscv_vundefined_f16*();
__riscv_vlmul_trunc_v_f16*_f16*();

From the user's perspective, it is reasonable to do above operation
when only ZVFHMIN is enabled. This patch would like to add new test
cases to make sure the RVV FP16 vreinterpret works well as expected.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto.
---
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 28 ++--
.../riscv/rvv/base/zvfhmin-intrinsic.c| 66 +++
2 files changed, 78 insertions(+), 16 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index ff9e0156a68..c3ed4191a36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -45,15 +45,33 @@ vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t 
op1) {
   return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
}
+vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4(vfloat16mf2_t op1) {
+  return __riscv_vlmul_trunc_v_f16mf2_f16mf4(op1);
+}
+
+vfloat16m4_t test_vlmul_trunc_v_f16m8_f16m4(vfloat16m8_t op1) {
+  return __riscv_vlmul_trunc_v_f16m8_f16m4(op1);
+}
+
+vfloat16mf4_t test_vundefined_f16mf4() {
+  return __riscv_vundefined_f16mf4();
+}
+
+vfloat16m8_t test_vundefined_f16m8() {
+  return __riscv_vundefined_f16m8();
+}
+
/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 6 } } */
-/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 8 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */
/* { dg-final { scan-assembler-times 
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } 
} */
/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } 
} */
-/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 6 } 
} */
-/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 
4 } } */
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } 
} */
+/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 
6 } } */
+/* { dg-final { scan-assembler-times 
{vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */
/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 
1 } } */
-/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 4 
} } */
+/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 
} } */
+/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 
} } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
index 68720e64926..8d39a2ed4c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c
@@ -121,26 +121,70 @@ vfloat16m8_t test_vlmul_ext_v_f16mf4_f16m8(vfloat16mf4_t 
op1) {
   return __riscv_vlmul_ext_v_f16mf4_f16m8(op1);
}
+vfloat16mf4_t test_vlmul_trunc_v_f16mf2_f16mf4(vfloat16mf2_t op1) {
+  return __riscv_vlmul_trunc_v_f16mf2_f16mf4(op1);
+}
+
+vfloat16mf4_t test_vlmul_trunc_v_f16m1_f16mf4(vfloat16m1_t op1) {
+  return __riscv_vlmul_trunc_v_f16m1_f16mf4(op1);
+}
+
+vfloat16mf2_t test_vlmul_trunc_v_f16m1_f16mf2(vfloat16m1_t op1) {
+  return __riscv_vlmul_trunc_v_f16m1_f16mf2(op1);
+}
+
+vfloat16mf4_t test_vlmul_t

RE: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

From: Kito Cheng 
Sent: Monday, June 12, 2023 11:33 AM
To: 钟居哲 
Cc: Li, Pan2 ; gcc-patches ; 
rdapp.gcc ; Jeff Law ; Wang, 
Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

Lgtm too :)

钟居哲 mailto:juzhe.zh...@rivai.ai>> 於 2023年6月12日 週一 05:48 
寫道：
LGTM



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-11 08:33
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; 
yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API
From: Pan Li mailto:pan2...@intel.com>>

This patch support the intrinsic API of FP16 ZVFHMIN vlmul ext. Aka:

vfloat16*_t <==> vfloat16*_t.

From the user's perspective, it is reasonable to do some type convert
between vfloat16*_t and vfloat16*_t when only ZVFHMIN is enabled.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add new test cases.
---
.../riscv/riscv-vector-builtins-types.def | 15 ++
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 18 +--
.../riscv/rvv/base/zvfhmin-intrinsic.c| 54 +--
3 files changed, 79 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 589ea532727..db8e61fea6a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -978,6 +978,11 @@ DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
@@ -1014,6 +1019,10 @@ DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
@@ -1040,6 +1049,9 @@ DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
@@ -1056,6 +1068,8 @@ DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
@@ -1064,6 +1078,7 @@ DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X32_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X64_VLMUL_

RE: [PATCH V2] RISC-V: Add ZVFHMIN block autovec testcase

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Robin.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Monday, June 12, 2023 8:19 PM
To: Robin Dapp 
Cc: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; 
pal...@dabbelt.com; pal...@rivosinc.com; jeffreya...@gmail.com
Subject: Re: [PATCH V2] RISC-V: Add ZVFHMIN block autovec testcase

LGTM too, thanks

On Mon, Jun 12, 2023 at 5:46 PM Robin Dapp via Gcc-patches 
 wrote:
>
> > +/* We can't enable FP16 NEG/PLUS/MINUS/MULT/DIV auto-vectorization 
> > +when -march="*zvfhmin*".  */
> > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in 
> > +function" 0 "vect" } } */
>
> Thanks.  OK from my side.
>
> Regards
>  Robin

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Li, Pan2 via Gcc-patches]

Sure thing, will commit it after all riscv.exp rvv.exp pass.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, June 12, 2023 8:43 PM
To: Wang, Yanzhang 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Li, Pan2 
Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.

Hi Yan-Zhang:

OK with one minor, go ahead IF the regression is clean.

Hi Pan:

Could you help to verify this patch and commit if the regression is clean?

thanks :)

> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp 
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79d0e9a8d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -43,7 +43,7 @@ dg-init
>  # Main loop.
>  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"

Add -Wno-psabi here rather than below, and also add it for
g++.target/riscv/rvv/rvv.exp

>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> -   "" $CFLAGS
> +   "-Wno-psabi" $CFLAGS
>  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
> "" $CFLAGS
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

RE: Re: [PATCH] RISC-V: Add RVV narrow shift right lowering auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and will take care of the define_insn_and_split part in 
another PATCH.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Monday, June 12, 2023 8:45 PM
To: juzhe.zh...@rivai.ai
Cc: kito.cheng ; gcc-patches ; 
palmer ; palmer ; jeffreyalaw 
; Robin Dapp 
Subject: Re: Re: [PATCH] RISC-V: Add RVV narrow shift right lowering 
auto-vectorization

Yes, change all define_insn_and_split to that style, "TARGET_VECTOR && 
can_create_pseudo_p ()"/  "&& 1", my understanding is all those patterns should 
only work before RA, so all using "TARGET_VECTOR && can_create_pseudo_p ()" is 
more reasonable.

On Mon, Jun 12, 2023 at 8:41 PM juzhe.zh...@rivai.ai  
wrote:
>
> You mean change all split pattern like this ?
> ;; This helps to match zero_extend + sign_extend + fma.
> (define_insn_and_split "*zero_sign_extend_fma"
>   [(set (match_operand:VWEXTI 0 "register_operand")
>   (plus:VWEXTI
> (mult:VWEXTI
>   (zero_extend:VWEXTI
> (match_operand: 2 "register_operand"))
>   (sign_extend:VWEXTI
> (match_operand: 3 "register_operand")))
> (match_operand:VWEXTI 1 "register_operand")))]
>   "TARGET_VECTOR && can_create_pseudo_p ()"
>   "#"
>   "&& 1"
>   [(const_int 0)]
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-06-12 20:37
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches; Kito.cheng; palmer; palmer; jeffreyalaw; Robin Dapp
> Subject: Re: [PATCH] RISC-V: Add RVV narrow shift right lowering 
> auto-vectorization We have two style predictor for those 
> define_insn_and_split patterns, "TARGET_VECTOR"/"&& 
> can_create_pseudo_p ()" and "TARGET_VECTOR && can_create_pseudo_p 
> ()"/"&& 1", could you unify all to later form? I feel that would be 
> safer since those patterns are really only valid before 
> RA(can_create_pseudo_p() == true), although it's mostly used by 
> combine pass so it's mostly safe, but IMO we should fix this soon rather than 
> fix that until we hit this later.
>
> OK for this patch as it is, and I would like to have a separated patch 
> to fix all those issues.
>
> On Mon, Jun 12, 2023 at 8:27 PM juzhe.zh...@rivai.ai 
>  wrote:
> >
> > Is this patch ok for trunk?
> >
> >
> >
> > juzhe.zh...@rivai.ai
> >
> > From: juzhe.zhong
> > Date: 2023-06-12 10:41
> > To: gcc-patches
> > CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; 
> > Juzhe-Zhong
> > Subject: [PATCH] RISC-V: Add RVV narrow shift right lowering 
> > auto-vectorization
> > From: Juzhe-Zhong 
> >
> > Optimize the following auto-vectorization codes:
> > void foo (int16_t * __restrict a, int32_t * __restrict b, int32_t c, 
> > int n) {
> > for (int i = 0; i < n; i++)
> >   a[i] = b[i] >> c;
> > }
> >
> > Before this patch:
> > foo:
> > ble a3,zero,.L5
> > .L3:
> > vsetvli a5,a3,e32,m1,ta,ma
> > vle32.v v1,0(a1)
> > vsetvli a4,zero,e32,m1,ta,ma
> > vsra.vx v1,v1,a2
> > vsetvli zero,zero,e16,mf2,ta,ma
> > sllia7,a5,2
> > vncvt.x.x.w v1,v1
> > sllia6,a5,1
> > vsetvli zero,a5,e16,mf2,ta,ma
> > sub a3,a3,a5
> > vse16.v v1,0(a0)
> > add a1,a1,a7
> > add a0,a0,a6
> > bne a3,zero,.L3
> > .L5:
> > ret
> >
> > After this patch:
> > foo:
> > ble a3,zero,.L5
> > .L3:
> > vsetvli a5,a3,e32,m1,ta,ma
> > vle32.v v1,0(a1)
> > vsetvli a7,zero,e16,mf2,ta,ma
> > slli a6,a5,2
> > vnsra.wx v1,v1,a2
> > slli a4,a5,1
> > vsetvli zero,a5,e16,mf2,ta,ma
> > sub a3,a3,a5
> > vse16.v v1,0(a0)
> > add a1,a1,a6
> > add a0,a0,a4
> > bne a3,zero,.L3
> > .L5:
> > ret
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec-opt.md 
> > (*vtrunc): New pattern.
> > (*trunc): Ditto.
> > * config/riscv/autovec.md (3): Change to 
> > define_insn_and_split.
> > (v3): Ditto.
> > (trunc2): Ditto.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: New test.
> > * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: New test.
> > * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: New test.
> > * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: New test.
> > * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: New test.
> > * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: New test.
> >
> > ---
> > gcc/config/riscv/autovec-opt.md   | 46 +
> > gcc/config/riscv/autovec.md   | 43 ++--
> > .../riscv/rvv/autovec/binop/narrow-1.c| 31 
> > .../riscv/rvv/autovec/binop/narrow-2.c| 32 
> > .../riscv/rvv/autovec/binop/narrow-3.c| 31 
> > .../riscv/rvv/autovec/binop/narrow_run-1.c| 50 +++
> > .../riscv/rvv/autovec/binop/narrow_run-2.c| 46 +
> > .../riscv/rvv/autovec/binop/narrow_run-3.c| 46 

RE: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito and Juzhe.

Pan

From: Kito Cheng 
Sent: Monday, June 12, 2023 11:33 AM
To: 钟居哲 
Cc: Li, Pan2 ; gcc-patches ; 
rdapp.gcc ; Jeff Law ; Wang, 
Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

Lgtm too :)

钟居哲 mailto:juzhe.zh...@rivai.ai>> 於 2023年6月12日 週一 05:48 
寫道：
LGTM



juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-11 08:33
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; 
yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API
From: Pan Li mailto:pan2...@intel.com>>

This patch support the intrinsic API of FP16 ZVFHMIN vlmul ext. Aka:

vfloat16*_t <==> vfloat16*_t.

From the user's perspective, it is reasonable to do some type convert
between vfloat16*_t and vfloat16*_t when only ZVFHMIN is enabled.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add new test cases.
---
.../riscv/riscv-vector-builtins-types.def | 15 ++
.../riscv/rvv/base/zvfh-over-zvfhmin.c| 18 +--
.../riscv/rvv/base/zvfhmin-intrinsic.c| 54 +--
3 files changed, 79 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 589ea532727..db8e61fea6a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -978,6 +978,11 @@ DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X2_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
@@ -1014,6 +1019,10 @@ DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X4_VLMUL_EXT_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
@@ -1040,6 +1049,9 @@ DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0)
DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_X8_VLMUL_EXT_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
@@ -1056,6 +1068,8 @@ DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0)
DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
@@ -1064,6 +1078,7 @@ DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0)
DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X32_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | 
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_X64_VLMUL_

RE: [PATCH v1] RISC-V: Fix one potential test failure for RVV vsetvl

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Sounds good to me. Not sure if there are some tests focus on -O0/Os/Oz, we can 
refine this in another PATCH.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, June 12, 2023 8:30 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com; 
jeffreya...@gmail.com; Wang, Yanzhang 
Subject: Re: [PATCH v1] RISC-V: Fix one potential test failure for RVV vsetvl

OK for this patch, and I am thinking we should adjust rvv.exp to just exclude 
-O0, -Os and -Oz for some testcases run to simplify many testcases.


On Mon, Jun 12, 2023 at 8:20 PM Pan Li via Gcc-patches 
 wrote:
>
> From: Pan Li 
>
> The test will fail on below command with multi-thread like below.  
> However, it comes from one missed "Oz" option when check vsetvl.
>
> make -j $(nproc) report RUNTESTFLAGS="rvv.exp riscv.exp"
>
> To some reason, this failure cannot be reproduced by RUNTESTFLAGS="rvv.exp"
> or make without -j option. We would like to fix it and root cause the 
> reason later.
>
> Signed-off-by: Pan Li 
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Adjust test checking.
> ---
>  gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> index 66c90ac10e7..f3420be8ab6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c
> @@ -34,4 +34,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t 
> m, size_t k) {
>  /* { dg-final { scan-assembler-times 
> {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" 
> no-opts "-g" no-opts "-funroll-loops" } } } } */
>  /* { dg-final { scan-assembler-times 
> {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*8} 1 { target { no-opts "-O0" 
> no-opts "-g" no-opts "-funroll-loops" } } } } */
>  /* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts 
> "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts 
> "-funroll-loops" } } } } */
> -/* { dg-final { scan-assembler-times 
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target { 
> no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } 
> } } */
> +/* { dg-final { scan-assembler-times 
> +{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 5 { target 
> +{ no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts 
> +"-funroll-loops" } } } } */
> --
> 2.34.1
>

RE: [PATCH] RISC-V: Fix V_WHOLE && V_FRACT iterator requirement

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Tuesday, June 13, 2023 3:54 AM
To: juzhe.zh...@rivai.ai; Robin Dapp ; gcc-patches 

Cc: Kito.cheng ; palmer 
Subject: Re: [PATCH] RISC-V: Fix V_WHOLE && V_FRACT iterator requirement



On 6/12/23 03:58, juzhe.zh...@rivai.ai wrote:
> I'd like you to defer to you commit my patch with your test (Jeff has 
> approved my patch, just feel free to commit).
Then let's go with that.  Juzhe's patch + Robin's test.

jeff

RE: [PATCH V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Tuesday, June 13, 2023 3:43 AM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with 
decompress operation



On 6/12/23 09:11, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> According to RVV ISA:
> https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
> 
> We can enhance VLA SLP auto-vectorization with (16.5.1. Synthesizing 
> vdecompress) Decompress operation.
> 
> Case 1 (nunits = POLY_INT_CST [16, 16]):
> _48 = VEC_PERM_EXPR <_37, _35, { 0, POLY_INT_CST [16, 16], 1, 
> POLY_INT_CST [17, 16], 2, POLY_INT_CST [18, 16], ... }>; We can optimize such 
> VLA SLP permuation pattern into:
> _48 = vdecompress (_37, _35, mask = { 0, 1, 0, 1, ... };
> 
> Case 2 (nunits = POLY_INT_CST [16, 16]):
> _23 = VEC_PERM_EXPR <_46, _44, { POLY_INT_CST [1, 1], POLY_INT_CST [3, 
> 3], POLY_INT_CST [2, 1], POLY_INT_CST [4, 3], POLY_INT_CST [3, 1], 
> POLY_INT_CST [5, 3], ... }>; We can optimize such VLA SLP permuation pattern 
> into:
> _48 = vdecompress (slidedown(_46, 1/2 nunits), slidedown(_44, 1/2 
> nunits), mask = { 0, 1, 0, 1, ... };
> 
> For example:
> void __attribute__ ((noinline, noclone)) vec_slp (uint64_t *restrict 
> a, uint64_t b, uint64_t c, int n) {
>for (int i = 0; i < n; ++i)
>  {
>a[i * 2] += b;
>a[i * 2 + 1] += c;
>  }
> }
> 
> ASM:
> ...
>  vid.v   v0
>  vand.vi v0,v0,1
>  vmseq.viv0,v0,1  ===> mask = { 0, 1, 0, 1, ... }
> vdecompress:
>  viota.m v3,v0
>  vrgather.vv v2,v1,v3,v0.t
> Loop:
>  vsetvli zero,a5,e64,m1,ta,ma
>  vle64.v v1,0(a0)
>  vsetvli a6,zero,e64,m1,ta,ma
>  vadd.vv v1,v2,v1
>  vsetvli zero,a5,e64,m1,ta,ma
>  mv  a5,a3
>  vse64.v v1,0(a0)
>  add a3,a3,a1
>  add a0,a0,a2
>  bgtua5,a4,.L4
> 
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-v.cc (emit_vlmax_decompress_insn): New function.
>  (shuffle_decompress_patterns): New function.
>  (expand_vec_perm_const_1): Add decompress optimization.
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/autovec/partial/slp-8.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp-9.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: New test.
I've been wanting to get inside expand_vec_perm_const to see what opportunities 
might exist to improve code in there.  We had good success mining this space at 
a prior employer.  While we had a lot of weird idioms and costs to consider it 
was well worth the time.

So quite happy to see you diving into this code.

OK for the trunk,
Jeff

RE: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test

[Li, Pan2 via Gcc-patches]

Committed, thanks Robin and Juzhe.

Pan

-Original Message-
From: Robin Dapp  
Sent: Tuesday, June 13, 2023 3:24 PM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches 

Cc: rdapp@gmail.com; jeffreyalaw ; Wang, Yanzhang 
; kito.cheng 
Subject: Re: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test

> Oh. Sorry. Since I want to commit my patch so I asked Pan to commit 
> your test as well. I think you can resend a fix of this testcase and 
> drop this patch.

No problem, will fix it another time.  Pan can just go ahead with this fix now, 
no need to wait for a maintainer, it's obvious enough.

Thanks
 Robin

RE: [PATCH v5] RISC-V: Add vector psabi checking.

[Li, Pan2 via Gcc-patches]

Committed v6 with riscv.exp and rvv.exp passed, thanks Kito.

Pan

-Original Message-
From: Li, Pan2 
Sent: Monday, June 12, 2023 8:49 PM
To: Kito Cheng ; Wang, Yanzhang 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai
Subject: RE: [PATCH v5] RISC-V: Add vector psabi checking.

Sure thing, will commit it after all riscv.exp rvv.exp pass.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, June 12, 2023 8:43 PM
To: Wang, Yanzhang 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Li, Pan2 
Subject: Re: [PATCH v5] RISC-V: Add vector psabi checking.

Hi Yan-Zhang:

OK with one minor, go ahead IF the regression is clean.

Hi Pan:

Could you help to verify this patch and commit if the regression is clean?

thanks :)

> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp 
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> index 5e69235a268..ad79d0e9a8d 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
> @@ -43,7 +43,7 @@ dg-init
>  # Main loop.
>  set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"

Add -Wno-psabi here rather than below, and also add it for
g++.target/riscv/rvv/rvv.exp

>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
> -   "" $CFLAGS
> +   "-Wno-psabi" $CFLAGS
>  gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
> "" $CFLAGS
>  dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \

RE: [PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Tuesday, June 13, 2023 9:30 PM
To: Robin Dapp ; juzhe.zh...@rivai.ai; 
gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com
Subject: Re: [PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization



On 6/13/23 06:16, Robin Dapp wrote:
> Hi Juzhe,
> 
> LGTM.  You could also add the aarch64 test disclaimer here again, but 
> no need for a V2.
Agreed.

jeff

RE: [PATCH V3] RISC-V: Add more SLP tests

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Tuesday, June 13, 2023 9:26 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH V3] RISC-V: Add more SLP tests



On 6/13/23 05:38, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/autovec/partial/slp-10.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp-11.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp-13.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp-14.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp-15.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: New test.
>  * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: New test.
> 
> ---
OK
jeff

RE: [PATCH] RISC-V: Add comments of some functions

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Tuesday, June 13, 2023 10:06 PM
To: juzhe.zh...@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com; rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Add comments of some functions



On 6/12/23 20:26, juzhe.zh...@rivai.ai wrote:
> From: Juzhe-Zhong 
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-v.cc (rvv_builder::single_step_npatterns_p): 
> Add comment.
>  (shuffle_generic_patterns): Ditto.
>  (expand_vec_perm_const_1): Ditto.
OK.  Thanks!
jeff

RE: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"`

[Li, Pan2 via Gcc-patches]

Committed, thanks Juzhe.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of juzhe.zh...@rivai.ai
Sent: Tuesday, June 13, 2023 6:56 PM
To: 丁乐华 ; gcc-patches 
Subject: Re: [PATCH] RISC-V: Remove duplicate `#include 
"riscv-vector-switch.def"`

Send V2 patch with changelog.

Thanks.


juzhe.zh...@rivai.ai
 
From: Lehua Ding
Date: 2023-06-13 18:53
To: gcc-patches; juzhe.zhong
Subject: [PATCH] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` 
Hi,
 
This patch remove the duplicate `#include "riscv-vector-switch.def"` statement 
and add #undef for ENTRY and TUPLE_ENTRY macros later.
 
Best,
Lehua
 
---
gcc/config/riscv/riscv-v.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 
e1b85a5af91f..09c2abcbc623 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1210,7 +1210,6 @@ struct mode_vtype_group
   ratio_for_min_vlen64[MODE##mode] = RATIO_FOR_MIN_VLEN64; 
\
   vlmul_for_for_vlen128[MODE##mode] = VLMUL_FOR_MIN_VLEN128;   
\
   ratio_for_for_vlen128[MODE##mode] = RATIO_FOR_MIN_VLEN128; -#include 
"riscv-vector-switch.def"
#define TUPLE_ENTRY(MODE, REQUIREMENT, SUBPART_MODE, NF, VLMUL_FOR_MIN_VLEN32, \
RATIO_FOR_MIN_VLEN32, VLMUL_FOR_MIN_VLEN64,\
RATIO_FOR_MIN_VLEN64, VLMUL_FOR_MIN_VLEN128,   \
@@ -1224,6 +1223,8 @@ struct mode_vtype_group
   vlmul_for_for_vlen128[MODE##mode] = VLMUL_FOR_MIN_VLEN128;   
\
   ratio_for_for_vlen128[MODE##mode] = RATIO_FOR_MIN_VLEN128; #include 
"riscv-vector-switch.def"
+#undef ENTRY
+#undef TUPLE_ENTRY
   }
};
--
2.36.3
 

RE: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

[Li, Pan2 via Gcc-patches]

Thanks Juzhe, Just passed the RV64 riscv/rvv.exp but meet some failures in RV32 
the same as upstream. However, this patch may not introduce new failures but I 
am not quite sure if there is risk here.

lowlist `find build-gcc-newlib-stage2/gcc/testsuite/ -name *.sum |paste -sd "," 
-`
=== gcc: Unexpected fails for rv32imafdcv ilp32f medlow ===
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=c99 -O3 
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess 
errors)
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=c99 -O3 
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax execution test
FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3 -ftree-vectorize (test for 
excess errors)
=== g++: Unexpected fails for rv32imafdcv ilp32f medlow ===
FAIL: g++.target/riscv/rvv/base/bug-14.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-9.C (test for excess errors)

   = Summary of gcc testsuite =
| # of unexpected case / # of unique unexpected case
|  gcc |  g++ | gfortran |
rv32imafdcv/ ilp32f/ medlow |7 / 4 |2 / 2 |  - |

For RV32, mostly I take below commands for testing.

cd riscv-gnu-toolchain
cd gcc && git checkout master && git pull -p && cd -
cd spike && git checkout master && git pull -p && cd -
cd pk && git checkout master && git pull -p && cd -

./configure --prefix=`pwd`/__RISC-V_INSTALL_/ --with-arch=rv32imafdcv 
--with-abi=ilp32f --with-isa-spec=20191213 --with-sim=spike
make -j $(nproc) build-sim SIM=spike
make report -j $(nproc) RUNTESTFLAGS="rvv.exp"

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 14, 2023 10:31 AM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; Li, 
Pan2 ; Wang, Yanzhang ; kito.cheng 

Subject: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split

LGTM.


juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-14 10:15
To: gcc-patches
CC: juzhe.zhong; 
rdapp.gcc; 
jeffreyalaw; pan2.li; 
yanzhang.wang; 
kito.cheng
Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split
From: Pan Li mailto:pan2...@intel.com>>

This patch is considered as the follow up of the below PATCH.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html

We aligned the predictor style for the define_insn_and_split suggested
by Kito. To avoid potential issues before we hit.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Align the predictor sytle.
* config/riscv/autovec.md: Ditto.
---
gcc/config/riscv/autovec-opt.md | 20 ++--
gcc/config/riscv/autovec.md | 24 
2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index aef28e445e1..fb1b07205aa 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -37,9 +37,9 @@ (define_insn_and_split 
"@pred_single_widen_mul"
  (match_operand: 4 "register_operand" "   vr,   vr"))
(match_operand:VWEXTI 3 "register_operand" "   vr,   vr"))
  (match_operand:VWEXTI 2 "vector_merge_operand"   "   vu,0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
 insn_code icode = code_for_pred_vf2 (, mode);
@@ -132,9 +132,9 @@ (define_insn_and_split "*not"
(bitmanip_bitwise:VB
  (not:VB (match_operand:VB 2 "register_operand" " vr"))
  (match_operand:VB 1 "register_operand" " vr")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
 insn_code icode = code_for_pred_not (, mode);
@@ -159,9 +159,9 @@ (define_insn_and_split "*n"
  (any_bitwise:VB
(match_operand:VB 1 "register_operand" " vr")
(match_operand:VB 2 "register_operand" " vr"]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
-  "&& can_create_pseudo_p ()"
+  "&& 1"
   [(const_int 0)]
   {
 insn_code icode = code_for_pred_n (, mode);
@@ -346,9 +346,9 @@ (define_insn_and_split 
"*vtrunc"
 (match_operand:VWEXTI 1 "register_operand" " vr,vr")
(any_e

RE: Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

[Li, Pan2 via Gcc-patches]

Thanks Juzhe for explanation, that make more sense to me and sorry for 
disturbing.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 14, 2023 2:31 PM
To: Robin Dapp ; Li, Pan2 ; gcc-patches 

Cc: Robin Dapp ; jeffreyalaw ; 
Wang, Yanzhang ; kito.cheng 
Subject: Re: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split

All failures with (test for excess errors) are not big issues which are created 
by testcase themselves.

For example:
FAIL: g++.target/riscv/rvv/base/bug-14.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-9.C (test for excess errors)
These 2 failures are because RV32 doesn't have indexed load/store with indexed 
EEW = 64.
Like __riscv_vsuxei64_v_i32mf2in bug-14.C, this intrinsic is valid in RV64 
but invalid in RV32 which
is totally correct since according to RVV ISA:
The V extension supports all vector load and store instructions (Section Vector 
Loads and 
Stores),
 except the V extension does not support EEW=64 for index values when XLEN=32.

So these 2 failures in RV32 are not the compile's bugs. I have seen:  /* { 
dg-do run { target { { {riscv_vector} && {rv64} } } } } */
in these testcases which can not work to block execution in RV32 (Since such 
testcase only needs to be tested on RV64). I think this is the issue we need to 
figure out.

So, to conclude:
All these failures:
=== gcc: Unexpected fails for rv32imafdcv ilp32f medlow ===
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=c99 -O3 
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess 
errors)
FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3 -ftree-vectorize (test for 
excess errors)
=== g++: Unexpected fails for rv32imafdcv ilp32f medlow ===
FAIL: g++.target/riscv/rvv/base/bug-14.C (test for excess errors)
FAIL: g++.target/riscv/rvv/base/bug-9.C (test for excess errors)

These failures are not compiler's bugs, should be testcase or test framework 
issues.

The only issues related to compiler are these:
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=c99 -O3 
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax execution test

These 2 issues I already noticed which should be already fixed by your another 
patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621610.html


Overal, this patch doesn't cause any issues.  So, we can go ahead.


Thanks.

juzhe.zh...@rivai.ai

From: Robin Dapp
Date: 2023-06-14 14:09
To: Li, Pan2; 
juzhe.zh...@rivai.ai; 
gcc-patches
CC: rdapp.gcc; 
jeffreyalaw; Wang, 
Yanzhang; 
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split
Hi Pan,

these failures were present before the patch I suppose? They
don't look related.  Is this what you meant by "the same as upstream"?

> FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=c99 -O3 
> -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for 
> excess errors)

This one should probably be 64-bit only.  Would you mind adjusting it?

> FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-run.c -O3 -ftree-vectorize (test 
> for excess errors)

What's happening here?  Any details on the output?

I don't have a proper sim environment setup yet.  How long does the testsuite 
take
with spike?  Have you tried qemu as well?

Regards
Robin

RE: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

[Li, Pan2 via Gcc-patches]

> Any numbers on this Pan? How many cores do you use for running the testsuite?
Sorry for missing this part. It takes about 4-6 minutes with spike and 16 cores.

Pan

-Original Message-
From: Robin Dapp  
Sent: Wednesday, June 14, 2023 2:47 PM
To: Li, Pan2 ; juzhe.zh...@rivai.ai; gcc-patches 

Cc: rdapp@gmail.com; jeffreyalaw ; Wang, Yanzhang 
; kito.cheng 
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split

> I don't have a proper sim environment setup yet.  How long does the 
> testsuite take
> with spike?  Have you tried qemu as well?
Any numbers on this Pan? How many cores do you use for running the testsuite?

Regards
 Robin

RE: Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

[Li, Pan2 via Gcc-patches]

Sure, working on the V2 as well as the RV32 testing, will reply the bugfix 
PATCH once ready.

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 14, 2023 3:01 PM
To: Robin Dapp ; Li, Pan2 ; gcc-patches 

Cc: Robin Dapp ; jeffreyalaw ; 
Wang, Yanzhang ; kito.cheng 
Subject: Re: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split

>> Yeah sure, we need to be able to run tests only for specific targets.
>> Why does {riscv_vector} && {rv64} not work?
I am not sure. These testcases were added by kito long time ago.
Frankly, I am not familiar with GCC test framework.

I think the highest priority is to fix the "real" compiler bugs which I have 
noticed yesterday:
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=c99 -O3 
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax execution test

@Li Pan could you verify whether your patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621610.html can fix these 2 
issues?
If yes, please send V2 patch with append these information into patch log.


Thanks.

juzhe.zh...@rivai.ai

From: Robin Dapp
Date: 2023-06-14 14:52
To: juzhe.zh...@rivai.ai; 
pan2.li; gcc-patches
CC: rdapp.gcc; 
jeffreyalaw; 
yanzhang.wang; 
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split
Yes, I agree with the general assessment (and didn't mean to insinuate
that the FAILs are compiler's or a fault of the patch.

> So these 2 failures in RV32 are not the compile's bugs. I have seen:
> /* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ in
> these testcases which can not work to block execution in RV32 (Since
> such testcase only needs to be tested on RV64). I think this is the
> issue we need to figure out.

Yeah sure, we need to be able to run tests only for specific targets.
Why does {riscv_vector} && {rv64} not work?

For zvfh I'm testing something like the following:

proc check_effective_target_riscv_zvfh { } {
if { ![istarget rv32*-*-*] && ![istarget rv64*-*-*] } then {
return 0;
}

if !check_effective_target_riscv_vector then {
return 0;
}

return [
[check_runtime riscv_check_zvfh {
int main (void)
{
asm ("vsetivli zero,8,e16,m1,ta,ma");
asm ("vfadd.vv %%v8,%%v8,%%v16" : : : "%%v8");
return 0;
}
} "-march=rv64gcv_zvfh" ]
|| ... ]

Regards
Robin

RE: [PATCH v1] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32

[Li, Pan2 via Gcc-patches]

Thanks Juzhe for reviewing, update the PATCH v2 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621645.html

Pan

From: juzhe.zh...@rivai.ai 
Sent: Wednesday, June 14, 2023 9:07 AM
To: Li, Pan2 ; gcc-patches 
Cc: Robin Dapp ; jeffreyalaw ; Li, 
Pan2 ; Wang, Yanzhang ; kito.cheng 

Subject: Re: [PATCH v1] RISC-V: Bugfix for vec_init repeating auto 
vectorization in RV32


>> unsigned int elen = TARGET_VECTOR_ELEN_64 ? 64 : 32;
Add comment here to demonstrate why you pick up elen to set the LIMIT.
I understand:
1. -march=zve32* ===> ELEN = 32
-march=zve64* ===> ELEN = 64
2. both vmv.v.x/vmv.s.x is restrict to the ELEN
For example, When ELEN=32 (-march=zve32*)
vsetvli ...e64,m1
vmv.v.x/vmv.s.x
We can't support such code sequence.

You should demonstrate it clearly in the comments.

Otherwise, this patch LGTM.

juzhe.zh...@rivai.ai

From: pan2.li
Date: 2023-06-14 08:58
To: gcc-patches
CC: juzhe.zhong; 
rdapp.gcc; 
jeffreyalaw; pan2.li; 
yanzhang.wang; 
kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for vec_init repeating auto vectorization in 
RV32
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to fix one bug exported by RV32 test case
multiple_rgroup_run-2.c. The mask should be restricted by elen in
vector, and the condition between the vmv.s.x and the vmv.v.x should
take inner_bits_size rather than constants.

Passed both the rv32 and rv64 riscv/rvv tests.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask):
Take elen instead of scalar BITS_PER_WORD.
(expand_vector_init_merge_repeating_sequence): Use inner_bits_size
instead of scaler BITS_PER_WORD.
---
gcc/config/riscv/riscv-v.cc | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index fb970344521..9270e258ca3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -399,10 +399,11 @@ rvv_builder::get_merge_scalar_mask (unsigned int 
index_in_pattern) const
{
   unsigned HOST_WIDE_INT mask = 0;
   unsigned HOST_WIDE_INT base_mask = (1ULL << index_in_pattern);
+  unsigned int elen = TARGET_VECTOR_ELEN_64 ? 64 : 32;
-  gcc_assert (BITS_PER_WORD % npatterns () == 0);
+  gcc_assert (elen % npatterns () == 0);
-  int limit = BITS_PER_WORD / npatterns ();
+  int limit = elen / npatterns ();
   for (int i = 0; i < limit; i++)
 mask |= base_mask << (i * npatterns ());
@@ -1923,7 +1924,7 @@ expand_vector_init_merge_repeating_sequence (rtx target,
   rtx mask = gen_reg_rtx (mask_mode);
   rtx dup = gen_reg_rtx (dup_mode);
-  if (full_nelts <= BITS_PER_WORD) /* vmv.s.x.  */
+  if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x.  */
{
  rtx ops[] = {dup, gen_scalar_move_mask (dup_mask_mode),
RVV_VUNDEF (dup_mode), merge_mask};
@@ -1933,7 +1934,8 @@ expand_vector_init_merge_repeating_sequence (rtx target,
   else /* vmv.v.x.  */
{
  rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)};
-   rtx vl = gen_int_mode (CEIL (full_nelts, BITS_PER_WORD), Pmode);
+   rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()),
+ Pmode);
  emit_nonvlmax_integer_move_insn (code_for_pred_broadcast (dup_mode),
   ops, vl);
}
--
2.34.1

RE: [PATCH v2] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32

[Li, Pan2 via Gcc-patches]

Thanks Robin, that looks like much better than the v2, let me update it to 
PATCH v3.

Pan

-Original Message-
From: Robin Dapp  
Sent: Wednesday, June 14, 2023 4:27 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; jeffreya...@gmail.com; Wang, 
Yanzhang ; kito.ch...@gmail.com
Subject: Re: [PATCH v2] RISC-V: Bugfix for vec_init repeating auto 
vectorization in RV32

Hi Pan,

> This patch would like to fix one bug exported by RV32 test case
> multiple_rgroup_run-2.c. The mask should be restricted by elen in
> vector, and the condition between the vmv.s.x and the vmv.v.x should
> take inner_bits_size rather than constants.

exported -> exposed.

How about something like:

"When constructing a vector mask from individual elements we wrongly
assumed that we can broadcast BITS_PER_WORD (i.e. XLEN).  The maximum
is actually the vector element length (i.e. ELEN).  This patch fixes
this."?

> +  /* We restrict the limit to the elen of RVV. For example:
> + -march=zve32*, the ELEN is 32.
> + -march=zve64*, the ELEN is 64.
> + The related vmv.v.x/vmv.s.x is restricted to ELEN as above, we cannot
> + take care of case like below when ELEN=32
> + vsetvil e64,m1
> + vmv.v.x/vmv.s.x
> +   */

/* Here we construct a mask pattern that will later be broadcast
   to a vector register.  The maximum broadcast size for vmv.v.x/vmv.s.x
   is determined by the length of a vector element (ELEN) and not by
   XLEN so make sure we do not exceed it.  One example is -march=zve32*
   which mandates ELEN == 32 but can be combined with -march=rv64
   with XLEN == 64.  */

Regards
 Robin

RE: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

[Li, Pan2 via Gcc-patches]

Nit for test.

+/* { dg-options "-march=rv64gczve32x 
+--param=riscv-autovec-preference=fixed-vlmax" } */

To

+/* { dg-options "-march=rv64gc_zve32x 
--param=riscv-autovec-preference=fixed-vlmax" } */

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of juzhe.zh...@rivai.ai
Sent: Wednesday, June 14, 2023 7:21 PM
To: 丁乐华 ; gcc-patches 
Cc: jeffreyalaw ; Robin Dapp ; 
palmer 
Subject: 回复: Re: [PATCH] RISC-V: Ensure vector args and return use function 
stack to pass [PR110119]

Also
p110119-1.c
change name of test into
pr110119-1.c


juzhe.zh...@rivai.ai
 
发件人： juzhe.zh...@rivai.ai
发送时间： 2023-06-14 19:17
收件人： 丁乐华; gcc-patches
抄送： jeffreyalaw; Robin Dapp; palmer
主题： Re: [PATCH] RISC-V: Ensure vector args and return use function stack to 
pass [PR110119] Oh. I see.

Change  if (riscv_v_ext_mode_p (arg.mode) || riscv_v_ext_tuple_mode_p 
(arg.mode))

into 

if (riscv_v_ext_mode_p (arg.mode))

since riscv_v_ext_mode_p (arg.mode) includes riscv_v_ext_vector_mode_p 
(arg.mode) and riscv_v_ext_tuple_mode_p (arg.mode)

no need has riscv_v_ext_tuple_mode_p


juzhe.zh...@rivai.ai
 
From: Lehua Ding
Date: 2023-06-14 19:03
To: gcc-patches; juzhe.zhong
Subject: [PATCH] RISC-V: Ensure vector args and return use function stack to 
pass [PR110119] Hi,
 
The reason for this bug is that in the case where the vector register is set to 
a fixed length (with `--param=riscv-autovec-preference=fixed-vlmax` option), 
TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be passed 
through two scalar registers, but when GCC calls FUNCTION_VALUE (call function 
riscv_get_arg_info inside) it returns NULL_RTX. These two functions are not 
unified. The current treatment is to pass all vector arguments and returns 
through the function stack, and a new calling convention for vector registers 
will be added in the future.
 
Best,
Lehua
 
  PR target/110119
 
gcc/ChangeLog:
 
* config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for 
vector mode
(riscv_pass_by_reference): Return true for vector mode
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/p110119-1.c: New test.
* gcc.target/riscv/rvv/base/p110119-2.c: New test.
 
---
gcc/config/riscv/riscv.cc | 19 +-
.../gcc.target/riscv/rvv/base/p110119-1.c | 26 +++
.../gcc.target/riscv/rvv/base/p110119-2.c | 26 +++
3 files changed, 65 insertions(+), 6 deletions(-) create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/p110119-2.c
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 
dd5361c2bd2a..be868c7b6127 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3915,13 +3915,13 @@ riscv_get_arg_info (struct riscv_arg_info *info, const 
CUMULATIVE_ARGS *cum,
   riscv_pass_in_vector_p (type);
 }
-  /* TODO: Currently, it will cause an ICE for --param
- riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here
- let GCC generate loads/stores. Ideally, we should either warn the user not
- to use an RVV vector type as function argument or support the calling
- convention directly.  */
-  if (riscv_v_ext_mode_p (mode))
+  /* All current vector arguments and return values are passed through the
+ function stack. Ideally, we should either warn the user not to use an RVV
+ vector type as function argument or support a calling convention
+ with better performance.  */
+  if (riscv_v_ext_mode_p (mode) || riscv_v_ext_tuple_mode_p (mode))
 return NULL_RTX;
+
   if (named)
 {
   riscv_aggregate_field fields[2];
@@ -4106,6 +4106,13 @@ riscv_pass_by_reference (cumulative_args_t cum_v, const 
function_arg_info &arg) return false;
 }
+  /* All current vector arguments and return values are passed through the
+ function stack. Ideally, we should either warn the user not to use an RVV
+ vector type as function argument or support a calling convention
+ with better performance.  */
+  if (riscv_v_ext_mode_p (arg.mode) || riscv_v_ext_tuple_mode_p (arg.mode))
+return true;
+
   /* Pass by reference if the data do not fit in two integer registers.  */
   return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); } diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c
new file mode 100644
index ..0edbb0626299
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/p110119-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv 
+--param=riscv-autovec-preference=fixed-vlmax" } */
+
+#include "riscv_vector.h"
+
+typedef int8_t vnx2qi __attribute__ ((vector_size (2)));
+
+__attribute__ ((noipa)) vnx2qi
+f_vnx2qi (int8_t a, int8_t b, int8_t *out) {
+  vnx2qi v = {a, b};
+  return v;
+}
+
+__attribute__ ((noipa)) vnx2qi
+f_vnx2qi_2 (vnx2qi a, int8_t *out)
+{
+  return a;
+}
+
+__attribute__ 

RE: [PATCH v3] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff and Juzhe.

Pan

-Original Message-
From: Jeff Law  
Sent: Thursday, June 15, 2023 2:56 AM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches 

Cc: Robin Dapp ; Wang, Yanzhang ; 
kito.cheng 
Subject: Re: [PATCH v3] RISC-V: Bugfix for vec_init repeating auto 
vectorization in RV32



On 6/14/23 03:01, juzhe.zh...@rivai.ai wrote:
> LGTM
Agreed.  Commit when convenient.

jeff

RE: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

[Li, Pan2 via Gcc-patches]

Committed, thanks Jeff and Juzhe, sorry for misleading.

Pan

-Original Message-
From: Jeff Law  
Sent: Thursday, June 15, 2023 2:51 AM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches 

Cc: Robin Dapp ; Wang, Yanzhang ; 
kito.cheng 
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split



On 6/13/23 20:31, juzhe.zh...@rivai.ai wrote:
> LGTM.
Similarly.  If I've interpreted the thread correctly, there aren't any issues 
created by this patch, though there are some existing issues that need to be 
addressed independently.  The patch itself is definitely the right thing to be 
doing.

I'd suggest going forward with the commit whenever it's convenient Pan.

Thanks,
Jeff

RE: [PATCH V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

[Li, Pan2 via Gcc-patches]

Committed with the comment update,, thanks Jeff and Juzhe.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Thursday, June 15, 2023 3:08 AM
To: Lehua Ding ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; rdapp@gamil.com; jeffreya...@gamil.com; 
pal...@rivosinc.com
Subject: Re: [PATCH V2] RISC-V: Ensure vector args and return use function 
stack to pass [PR110119]



On 6/14/23 05:56, Lehua Ding wrote:
> The V2 patch address comments from Juzhe, thanks.
> 
> Hi,
>   
> The reason for this bug is that in the case where the vector register 
> is set to a fixed length (with 
> `--param=riscv-autovec-preference=fixed-vlmax` option), 
> TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be 
> passed through two scalar registers, but when GCC calls FUNCTION_VALUE 
> (call function riscv_get_arg_info inside) it returns NULL_RTX. These 
> two functions are not unified. The current treatment is to pass all 
> vector arguments and returns through the function stack, and a new calling 
> convention for vector registers will be added in the future.
>   
> Best,
> Lehua
> 
>  PR target/110119
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for 
> vector mode
>  (riscv_pass_by_reference): Return true for vector mode
> 
> gcc/testsuite/ChangeLog:
> 
>  * gcc.target/riscv/rvv/base/pr110119-1.c: New test.
>  * gcc.target/riscv/rvv/base/pr110119-2.c: New test.
And just to be clear, I've asked for a minor comment update.  The usual 
procedure is to go ahead and post a V3.  In this case I'll also give that V3 
pre-approval.  So no need to wait for additional acks.  Post it and it can be 
committed immediately.

jeff

RE: [PATCH] RISC-V: Use merge approach to optimize vector permutation

[Li, Pan2 via Gcc-patches]

Addressed the comments in PATCH v2 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621789.html

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Jeff Law via Gcc-patches
Sent: Thursday, June 15, 2023 3:11 AM
To: Robin Dapp ; juzhe.zh...@rivai.ai; 
gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; kito.ch...@sifive.com; pal...@dabbelt.com; 
pal...@rivosinc.com
Subject: Re: [PATCH] RISC-V: Use merge approach to optimize vector permutation



On 6/14/23 09:00, Robin Dapp wrote:
> Hi Juzhe,
> 
> the general method seems sane and useful (it's not very complicated).
> I was just distracted by
> 
>> Selector = { 0, 17, 2, 19, 4, 21, 6, 23, 8, 9, 10, 27, 12, 29, 14, 31 }, the 
>> common expression:
>> { 0, nunits + 1, 1, nunits + 2, 2, nunits + 3, ...  }
>>
>> For this selector, we can use vmsltu + vmerge to optimize the codegen.
> 
> because it's actually { 0, nunits + 1, 2, nunits + 3, ... } or maybe
> { 0, nunits, 0, nunits, ... } + { 0, 1, 2, 3, ..., nunits - 1 }.
> 
> Because of the ascending/monotonic? selector structure we can use vmerge
> instead of vrgather.
> 
>> +/* Recognize the patterns that we can use merge operation to shuffle the
>> +   vectors. The value of Each element (index i) in selector can only be
>> +   either i or nunits + i.
>> +
>> +   E.g.
>> +   v = VEC_PERM_EXPR (v0, v1, selector),
>> +   selector = { 0, nunits + 1, 1, nunits + 2, 2, nunits + 3, ...  }
> 
> Same.
> 
>> +
>> +   We can transform such pattern into:
>> +
>> +   v = vcond_mask (v0, v1, mask),
>> +   mask = { 0, 1, 0, 1, 0, 1, ... }.  */
>> +
>> +static bool
>> +shuffle_merge_patterns (struct expand_vec_perm_d *d)
>> +{
>> +  machine_mode vmode = d->vmode;
>> +  machine_mode sel_mode = related_int_vector_mode (vmode).require ();
>> +  int n_patterns = d->perm.encoding ().npatterns ();
>> +  poly_int64 vec_len = d->perm.length ();
>> +
>> +  for (int i = 0; i < n_patterns; ++i)
>> +if (!known_eq (d->perm[i], i) && !known_eq (d->perm[i], vec_len + i))
>> +  return false;
>> +
>> +  for (int i = n_patterns; i < n_patterns * 2; i++)
>> +if (!d->perm.series_p (i, n_patterns, i, n_patterns)
>> +&& !d->perm.series_p (i, n_patterns, vec_len + i, n_patterns))
>> +  return false;
> 
> Maybe add a comment that we check that the pattern is actually monotonic
> or however you prefet to call it?
> 
> I didn't go through all tests in detail but skimmed several.  All in all
> looks good to me.
So I think that means we want a V2 for the comment updates.  But I think 
we can go ahead and consider V2 pre-approved.

jeff