*PING**2 – Re: [Patch] Fortran: Fix Bind(C) char-len check, add ptr-contiguous check
PING**2 On 25.08.21 20:58, Tobias Burnus wrote: Early *PING*. (I also should still review several Fortan patches... There are lots of patches waiting for review :-/) On 20.08.21 19:24, Tobias Burnus wrote: The following is about interoperability (BIND(C)) only. * The patch adds a missing check for pointer + contiguous. (Rejected to avoid copy-in issues? Or checking issues?) * And it corrects an issue regarding len > 1 characters. While subroutine foo(x) character(len=2) :: x(*) is valid Fortran code (the argument can be "abce" or ['a','b','c','d'] or ...) – and would work also with bind(C) as the len=2 does not need to be passed as hidden argument as len is a constant. However, it is not valid nonetheless. OK? Comments? Tobias PS: Referenced locations in the standard (F2018): C1554 If proc-language-binding-spec is specified for a procedure, each of its dummy arguments shall be an interoperable procedure (18.3.6) or a variable that is interoperable (18.3.4, 18.3.5), assumed-shape, assumed-rank, assumed-type, of type CHARACTER with assumed length, or that has the ALLOCATABLE or POINTER attribute. 18.3.1: "... If the type is character, the length type parameter is interoperable if and only if its value is one. ..." "18.3.4 Interoperability of scalar variables": "... A named scalar Fortran variable is interoperable ... if it is of type character12its length is not assumed or declared by an expression that is not a constant expression." 18.3.5: Likewise but for arrays. 18.3.6 "... Fortran procedure interface is interoperable with a C function prototype ..." "(5) any dummy argument without the VALUE attribute corresponds to a formal parameter of the prototype that is of a pointer type, and either • the dummy argument is interoperable with an entity of the referenced type ..." (Remark: those are passed as byte stream) "• the dummy argument is a nonallocatable nonpointer variable of type CHARACTER with assumed character length and the formal parameter is a pointer to CFI_cdesc_t, • the dummy argument is allocatable, assumed-shape, assumed-rank, or a pointer without the CONTIGUOUS attribute, and the formal parameter is a pointer to CFI_cdesc_t, or (Remark: those two use an array descriptor, also for explicit-size/assumed-size arrays or for scalars.) • the dummy argument is assumed-type ..." - Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht München, HRB 106955
[PATCH] Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI)))
SUBREG_PROMOTED_VAR_P is a mechanism for tracking that a partial subreg
is correctly zero-extended or sign-extended in the parent register. For
example, the RTL (subreg/s/v:QI (reg/v:SI 23 [ x ]) 0) indicates that the
byte x is zero extended in reg:SI 23, which is useful for optimization.
An example is that zero extending the above QImode value to HImode can
simply use a wider subreg, i.e. (subreg:HI (reg/v:SI 23 [ x ]) 0).
This patch addresses the oversight/missed optimization opportunity that
the new HImode subreg above should retain its SUBREG_PROMOTED_VAR_P
annotation as its value is guaranteed to be correctly extended in the
SImode parent. The code below to preserve SUBREG_PROMOTED_VAR_P is already
present in the middle-end (e.g. simplify-rtx.c:7232-7242) but missing
from one or two (precisely three) places that (accidentally) strip it.
Whilst there I also added another optimization. If we need to extend
the above QImode value beyond the SImode register holding it, say to
DImode, we can eliminate the SUBREG and simply extend from the SImode
register to DImode.
This patch has been tested on x86_64-pc-linux-gnu with "make bootstrap"
and "make -k check" with no new failures, and on a cross-compiler to
nvptx-none, where the function "long foo(char x) { return x; }" now
requires one less instruction.
OK for mainline?
2021-08-29 Roger Sayle
gcc/ChangeLog
* expr.c (convert_modes): Preserve SUBREG_PROMOTED_VAR_P when
creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
subreg.
* simplify-rtx.c (simplify_unary_operation_1) [SIGN_EXTEND]:
Likewise, preserve SUBREG_PROMOTED_VAR_P when creating a (wider)
partial subreg from a SUBREG_PROMOTED_VAR_P subreg. Generate
SIGN_EXTEND of the SUBREG_REG when a subreg would be paradoxical.
[ZERO_EXTEND]: Likewise, preserve SUBREG_PROMOTED_VAR_P when
creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
subreg. Generate ZERO_EXTEND of the SUBREG_REG when a subreg
would be paradoxical.
Roger
--
diff --git a/gcc/expr.c b/gcc/expr.c
index 096c031..5dd98a9 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -688,7 +688,24 @@ convert_modes (machine_mode mode, machine_mode oldmode,
rtx x, int unsignedp)
&& (GET_MODE_PRECISION (subreg_promoted_mode (x))
>= GET_MODE_PRECISION (int_mode))
&& SUBREG_CHECK_PROMOTED_SIGN (x, unsignedp))
-x = gen_lowpart (int_mode, SUBREG_REG (x));
+{
+ scalar_int_mode int_orig_mode;
+ machine_mode orig_mode = GET_MODE (x);
+ x = gen_lowpart (int_mode, SUBREG_REG (x));
+
+ /* Preserve SUBREG_PROMOTED_VAR_P if the new mode is wider than
+the original mode, but narrower than the inner mode. */
+ if (GET_CODE (x) == SUBREG
+ && GET_MODE_PRECISION (subreg_promoted_mode (x))
+> GET_MODE_PRECISION (int_mode)
+ && is_a (orig_mode, &int_orig_mode)
+ && GET_MODE_PRECISION (int_mode)
+> GET_MODE_PRECISION (int_orig_mode))
+ {
+ SUBREG_PROMOTED_VAR_P (x) = 1;
+ SUBREG_PROMOTED_SET (x, unsignedp);
+ }
+}
if (GET_MODE (x) != VOIDmode)
oldmode = GET_MODE (x);
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index c81e27e..a75f6b2 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1511,12 +1511,28 @@ simplify_context::simplify_unary_operation_1 (rtx_code
code, machine_mode mode,
target mode is the same as the variable's promotion. */
if (GET_CODE (op) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op)
- && SUBREG_PROMOTED_SIGNED_P (op)
- && !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op
+ && SUBREG_PROMOTED_SIGNED_P (op))
{
- temp = rtl_hooks.gen_lowpart_no_emit (mode, SUBREG_REG (op));
- if (temp)
- return temp;
+ rtx subreg = SUBREG_REG (op);
+ machine_mode subreg_mode = GET_MODE (subreg);
+ if (!paradoxical_subreg_p (mode, subreg_mode))
+ {
+ temp = rtl_hooks.gen_lowpart_no_emit (mode, subreg);
+ if (temp)
+ {
+ /* Preserve SUBREG_PROMOTED_VAR_P. */
+ if (partial_subreg_p (temp))
+ {
+ SUBREG_PROMOTED_VAR_P (temp) = 1;
+ SUBREG_PROMOTED_SET (temp, 1);
+ }
+ return temp;
+ }
+ }
+ else
+ /* Sign-extending a sign-extended subreg. */
+ return simplify_gen_unary (SIGN_EXTEND, mode,
+ subreg, subreg_mode);
}
/* (sign_extend:M (sign_extend:N )) is (sign_extend:M ).
@@ -1630,12 +1646,28 @@ simplify_context::simplify_unary_operation_1 (rtx_code
code, machine_mode mode,
target mode is the same as the variable's promotion. */
if (GET_CODE (op) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op)
Re: [RFH] ME optimizes variable assignment away / Fortran bind(C) descriptor conversion
Hi all, hi Richard,
On 27.08.21 21:48, Richard Biener wrote:
It looks really nice with "-O1 -fno-inline" :-)
The callee 'rank_p()' is mostly optimized and in the
caller only those struct elements are set, which are used:
integer(kind=4) rank_p (struct CFI_cdesc_t & _this)
{
_1 = _this_11(D)->base_addr;
_2 = _this_11(D)->rank;
...
rnk_13 = (integer(kind=4)) _2;
return rnk_13;
}
void selr_p ()
{
...
struct CFI_cdesc_t01 cfi.7;
...
[local count: 537730764]:
cfi.7.rank = 1;
cfi.7.base_addr = 0B;
You need to do the accesses above using the generic 't' type as well, otherwise
they are non-conflicting TBAA wise.
First, I wonder why the following works with C:
struct gen_t { int n; int dim[]; }
int f (struct gen_t *x) {
if (x->n > 1) x->dim[0] = 5;
return x->n;
}
void test() {
struct { int n; int dim[2]; } y;
y.n = 2;
f ((struct gen_t*) &y);
}
Or doesn't it? In any case, that's how it is suggested
and 'y.n' is not accessed using 'gen_t' – there is only
a cast in the function call. (Which is not sufficient
in the Fortran FE-code generated code – as tried)
* * *
Otherwise, I can confirm that the following works.
Does this original dump now looks fine?
struct CFI_cdesc_t01 cfi.2;
...
((struct CFI_cdesc_t *) &cfi.2)->version = 1;
((struct CFI_cdesc_t *) &cfi.2)->rank = 1;
((struct CFI_cdesc_t *) &cfi.2)->type = 1025;
((struct CFI_cdesc_t *) &cfi.2)->attribute = 0;
((struct CFI_cdesc_t *) &cfi.2)->base_addr = intp.data;
((struct CFI_cdesc_t *) &cfi.2)->elem_len = 4;
...
irnk = rank_p ((struct CFI_cdesc_t *) &cfi.2);
Thanks,
Tobias
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas
Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht
München, HRB 106955
[PATCH take 3] Experimental -fpreserve-traps option
This is another attempt to add an -fpreserve-traps command line option to GCC. Many thanks to Richard Beiner for approving the code clean-up pieces of my earlier submission: This revision contains just the actual functional change(s). My recent attempt at humour in comment #8 of PR 77980 has reminded me that we still really need to tackle/improve the semantics of trapping instructions. Firstly, I completely agree with Richard (and Eric) that the current situation with the semantics of -fexceptions and -fnon-call-exceptions (especially the latter without the former) is a mess. Alas, the testsuite (and source) is full of checks that the current status quo is preserved, so any attempts to tweak exception handling leads to a world of pain. The most relevant thing that I would like to point out is that this proposed option, -fpreserve-traps, and the semantics of trapping instructions are completely orthogonal to exception handling. As the term EH implies, exceptions are a form of flow control (on those targets that support it). Traps, signals(?), segmentation faults, illegal accesses and invalid instructions are things that can't (always?) be controlled. Exceptional yes, but not handleable. I also agree with Richard's sentiment that GCC should aim to store semantics in the representation, not in global variables. Interestingly, whether a tree or rtx can trap has been explicitly represented in every allocated node for decades; it's what the compiler should do (or is allowed to do) with that information that has been missing. My proposal is to treat -fpreserve-traps as an experiment for the time being. Allowing all the places in the compiler that make assumptions about traps to be found/documented (by searching for flag_perserve_traps in the source code), and their influence on performance benchmarked. If things don't work out, there's the option to revert these patches, or #define flag_perserve_traps 0 with no run-time overhead. If this option proves useful, we can figure out how to serialize it in LTO, whether it's controlled by some language front-ends (e.g. Ada) or target backends, etc. I think it was Wittgenstein that explained that you need to have a name for a concept to reason or argue about it. -fpreserve-traps is a concept that GCC has never had, which is why it has been conflated with exceptions and exception handling over the years. In C++, division by zero is undefined behaviour; having a flag brings us one step closer to implementation defined. This patch has been tested on x86_64-pc-linux-gnu with a "make bootstrap" and "make -k check" with no new failures. Ok for mainline? 2021-08-29 Roger Sayle Eric Botcazou Richard Biener gcc/ChangeLog PR tree-optimization/38943 * common.opt (fpreserve-traps): New code generation option. * doc/invoke.texi (-fpreserve-traps): Document new option. * gimple.c (gimple_has_side_effects): Consider trapping to be a side-effect when -fpreserve-traps is specified. * ipa-pure-const.c (check_stmt): When preserving traps, a trapping statement should be considered a side-effect, so the function is neither const nor pure. gcc/testsuite/ChangeLog PR tree-optimization/38943 * gcc.dg/pr38943.c: New test case. Roger -- Roger -Original Message- From: Richard Biener Sent: 12 July 2021 12:26 To: Roger Sayle Cc: Eric Botcazou ; GCC Patches Subject: Re: [PATCH take 2] PR tree-optimization/38943: Preserve trapping instructions with -fpreserve-traps ... I've reviewed the cited PRs and most of them would have individual fixes and are not fixed by your patch, though -fpreserve-traps would offer a workaround in some cases. Now, -fpreserve-traps follows the unfortunate precedence of tieing IL semantics to a (global) flag rather than to individual stmts. I'm not sure -fpreserve-traps is something good to offer since on its own it looks not too useful and for making use of it one still needs -fnon-call-exceptions [-fexceptions]. There's still the open question what -fnon-call-exceptions on its own should do - IMHO it doesn't make sense to allow unwiding from a trapping memory reference but not from the call it resides in which means -fnon-call-exceptions should better enable -fexceptions? There's also valid points made in some of the PRs (some of which look like dups of each other) that an asm with memory operands should be trapping and thus throwing with -fnon-call-exceptions even when it is not volatile and that some builtin functions like memcpy should not be nothrow with -fnon-call-exceptions. There's const-correctness pieces in your patch - those are OK under the obvious rule and you might want to push them separately. Thanks, Richard. patche.log Description: Binary data
[PATCH] x86-64: Add ABI warning for 64-bit vectors
TYPE_MODE of record and union depends on whether vector_mode_supported_p
returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass
a parameter and return a value in a function. 64-bit integer vectors
were supported only by MMX and 64-bit float vector was supported only by
3DNOW. GCC 10 enabled 64-bit integer vectors without MMX by:
commit dfa61b9ed06d71901c4c430caa89820972ad68fe
Author: H.J. Lu
Date: Wed May 15 15:02:54 2019 +
i386: Allow MMX register modes in SSE registers
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
GCC 11 enabled 64-bit float vector without 3DNOW by:
commit 7c355156aa20eaec7401d7c66f6a6cfbe597abc2
Author: Uros Bizjak
Date: Mon May 11 11:16:31 2020 +0200
i386: Vectorize basic V2SFmode operations [PR94913]
Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
MINUS, MULT, MIN and MAX operations using XMM registers.
Add ABI warnings for 64-bit integer vectors without MMX and 64-bit float
vector without 3DNOW.
gcc/
PR target/102027
PR target/102105
* config/i386/i386.c (single_m64_base_type): New function.
(type_natural_mode): Add ABI warnings for 64-bit vectors.
gcc/testsuite/
PR target/102027
PR target/102105
* gcc.target/i386/pr102027-1.c: New test.
* gcc.target/i386/pr102027-2.c: Likewise.
* gcc.target/i386/pr102027-3.c: Likewise.
* gcc.target/i386/pr102105-1.c: Likewise.
* gcc.target/i386/pr102105-2.c: Likewise.
* gcc.target/i386/pr102105-3.c: Likewise.
* gcc.target/i386/pr102105-4.c: Likewise.
* gcc.target/i386/sse2-mmx-4.c: Add -Wno-psabi.
---
gcc/config/i386/i386.c | 98 ++
gcc/testsuite/gcc.target/i386/pr102027-1.c | 15
gcc/testsuite/gcc.target/i386/pr102027-2.c | 15
gcc/testsuite/gcc.target/i386/pr102027-3.c | 17
gcc/testsuite/gcc.target/i386/pr102105-1.c | 15
gcc/testsuite/gcc.target/i386/pr102105-2.c | 15
gcc/testsuite/gcc.target/i386/pr102105-3.c | 17
gcc/testsuite/gcc.target/i386/pr102105-4.c | 17
gcc/testsuite/gcc.target/i386/sse2-mmx-4.c | 2 +-
9 files changed, 210 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr102027-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102027-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102027-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-4.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3bb2cab57a3..5d9cad7468b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1840,6 +1840,54 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument
info to initialize */
cfun->machine->arg_reg_available = (cum->nregs > 0);
}
+/* Return the single 64-bit vector type of TYPE. */
+
+static const_tree
+single_m64_base_type (const_tree type)
+{
+ if ((TREE_CODE (type) == RECORD_TYPE
+ || TREE_CODE (type) == UNION_TYPE
+ || TREE_CODE (type) == QUAL_UNION_TYPE)
+ && int_size_in_bytes (type) == 8)
+{
+ const_tree field;
+ const_tree first_field = nullptr;
+
+ for (field = TYPE_FIELDS (type);
+ field;
+ field = DECL_CHAIN (field))
+ if (TREE_CODE (field) == FIELD_DECL)
+ {
+ if (TREE_TYPE (field) == error_mark_node)
+ continue;
+
+ /* Skip if structure has more than one field. */
+ if (first_field)
+ return nullptr;
+
+ first_field = field;
+ }
+
+ /* Skip if structure doesn't have any fields. */
+ if (!first_field)
+ return nullptr;
+
+ type = TREE_TYPE (first_field);
+
+ /* Skip if structure size isn't 64 bits. */
+ if (int_size_in_bytes (type) != 8)
+ return nullptr;
+
+ /* Return if a 64-bit vector is found. */
+ if (TREE_CODE (type) == VECTOR_TYPE)
+ return type;
+
+ return single_m64_base_type (type);
+}
+
+ return nullptr;
+}
+
/* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
But in the case of vector types, it is some vector mode.
@@ -1863,6 +1911,56 @@ type_natural_mode (const_tree type, const
CUMULATIVE_ARGS *cum,
{
machine_mode mode = TYPE_MODE (type);
+ const_tree m64_type = single_m64_base_type (type);
+ if (m64_type)
+{
+ mode = TYPE_MODE (m64_type);
+
+ int gcc_version = 0;
+ if (mode == V2SFmode)
+ {
+ /* GCC 11 enables V2SFmode without TARGET_3DNOW. */
+ if (!TARGET_3DNOW)
+ gcc_version = 11;
+ }
+ else
+ {
+ /* GCC 10 enables other MMX modes without TARGET_MMX. */
+ if (!TARGET
Re: [PATCH] x86-64: Add ABI warning for 64-bit vectors
On Sun, Aug 29, 2021 at 08:24:10AM -0700, H.J. Lu via Gcc-patches wrote:
> + if (gcc_version)
> + {
> + if (in_return)
> + {
> + static bool warnedm64_ret;
> + if (!warnedm64_ret)
> + {
> + if (warning (OPT_Wpsabi,
> +"the ABI of returning structure with a "
> +"64-bit vector has changed in GCC %d.1",
> +gcc_version))
> + warnedm64_ret = true;
> + }
> + }
> + else
> + {
> + static bool warnedm64;
> + if (!warnedm64)
> + {
> + if (warning (OPT_Wpsabi,
> +"the ABI of passing structure with a "
> +"64-bit vector has changed in GCC %d.1",
> +gcc_version))
> + warnedm64 = true;
> + }
> + }
> + }
Other -Wpsabi diagnostics in i386.c seems to be done using inform rather
than warning, why the change?
And, can you add wwwdocs description of the ABI change and use
in %{GCC %d.1%}, so that on recent terminals people can find out the
details by clicking on it?
See
if (!warned && warn_psabi)
{
const char *url
= CHANGES_ROOT_URL "gcc-11/changes.html#ia32_atomic";
warned = true;
inform (input_location, "the alignment of %<_Atomic %T%> "
"fields changed in %{GCC 11.1%}",
TYPE_MAIN_VARIANT (type), url);
}
Jakub
Re: [PATCH] x86-64: Add ABI warning for 64-bit vectors
On Sun, Aug 29, 2021 at 8:34 AM Jakub Jelinek wrote:
>
> On Sun, Aug 29, 2021 at 08:24:10AM -0700, H.J. Lu via Gcc-patches wrote:
> > + if (gcc_version)
> > + {
> > + if (in_return)
> > + {
> > + static bool warnedm64_ret;
> > + if (!warnedm64_ret)
> > + {
> > + if (warning (OPT_Wpsabi,
> > +"the ABI of returning structure with a "
> > +"64-bit vector has changed in GCC %d.1",
> > +gcc_version))
> > + warnedm64_ret = true;
> > + }
> > + }
> > + else
> > + {
> > + static bool warnedm64;
> > + if (!warnedm64)
> > + {
> > + if (warning (OPT_Wpsabi,
> > +"the ABI of passing structure with a "
> > +"64-bit vector has changed in GCC %d.1",
> > +gcc_version))
> > + warnedm64 = true;
> > + }
> > + }
> > + }
>
> Other -Wpsabi diagnostics in i386.c seems to be done using inform rather
> than warning, why the change?
I will fix it.
> And, can you add wwwdocs description of the ABI change and use
> in %{GCC %d.1%}, so that on recent terminals people can find out the
> details by clicking on it?
How does it work?
[hjl@gnu-tgl-2 gcc]$ gcc -S -m32
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/pr65146.c
/export/gnu/import/git/gitlab/x86-gcc/gcc/testsuite/gcc.target/i386/pr65146.c:5:8:
note: the alignment of ‘_Atomic long long int’ fields changed in GCC
11.1
5 | struct A { char a; _Atomic long long b; };
|^
[hjl@gnu-tgl-2 gcc]$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/libexec/gcc/x86_64-redhat-linux/11/lto-wrapper
OFFLOAD_TARGET_NAMES=nvptx-none
OFFLOAD_TARGET_DEFAULT=1
Target: x86_64-redhat-linux
Configured with: ../configure --enable-bootstrap
--enable-languages=c,c++,fortran,objc,obj-c++,ada,go,d,lto
--prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info
--with-bugurl=http://bugzilla.redhat.com/bugzilla --enable-shared
--enable-threads=posix --enable-checking=release --enable-multilib
--with-system-zlib --enable-__cxa_atexit
--disable-libunwind-exceptions --enable-gnu-unique-object
--enable-linker-build-id --with-gcc-major-version-only
--with-linker-hash-style=gnu --enable-plugin --enable-initfini-array
--with-isl=/builddir/build/BUILD/gcc-11.2.1-20210728/obj-x86_64-redhat-linux/isl-install
--enable-offload-targets=nvptx-none --without-cuda-driver
--enable-gnu-indirect-function --enable-cet --with-tune=generic
--with-arch_32=i686 --with-multilib-list=m32,m64,mx32
--build=x86_64-redhat-linux
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 11.2.1 20210728 (Red Hat 11.2.1-1) (GCC)
[hjl@gnu-tgl-2 gcc]$
There is no URL to click.
> See
> if (!warned && warn_psabi)
> {
> const char *url
> = CHANGES_ROOT_URL "gcc-11/changes.html#ia32_atomic";
>
> warned = true;
> inform (input_location, "the alignment of %<_Atomic %T%> "
> "fields changed in %{GCC 11.1%}",
> TYPE_MAIN_VARIANT (type), url);
> }
>
> Jakub
>
--
H.J.
[committed] d: ICE in gimple_register_canonical_type_1, at lto/lto-common.c:430 (PR102094)
Hi,
User defined types have the TYPE_CXX_ODR_P flag set, but closure frames
did not. This mismatch led to an ICE in the conflict detection for ODR
and interoperable non-ODR types. As a given closure frame is tied
explicitly to a function, it already conforms to ODR.
Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32,
committed to mainline.
Regards,
Iain
---
gcc/d/ChangeLog:
PR d/102094
* d-codegen.cc (build_frame_type): Set TYPE_CXX_ODR_P.
gcc/testsuite/ChangeLog:
PR d/102094
* gdc.dg/lto/pr102094_0.d: New test.
---
gcc/d/d-codegen.cc| 1 +
gcc/testsuite/gdc.dg/lto/pr102094_0.d | 18 ++
2 files changed, 19 insertions(+)
create mode 100644 gcc/testsuite/gdc.dg/lto/pr102094_0.d
diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc
index fe2ad98e60a..ad20bd15403 100644
--- a/gcc/d/d-codegen.cc
+++ b/gcc/d/d-codegen.cc
@@ -2563,6 +2563,7 @@ build_frame_type (tree ffi, FuncDeclaration *fd)
TYPE_FIELDS (frame_rec_type) = fields;
TYPE_READONLY (frame_rec_type) = 1;
+ TYPE_CXX_ODR_P (frame_rec_type) = 1;
layout_type (frame_rec_type);
d_keep (frame_rec_type);
diff --git a/gcc/testsuite/gdc.dg/lto/pr102094_0.d
b/gcc/testsuite/gdc.dg/lto/pr102094_0.d
new file mode 100644
index 000..f83631a1158
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/lto/pr102094_0.d
@@ -0,0 +1,18 @@
+// { dg-lto-do link }
+module pr102094_0;
+
+extern(C) int printf(char* s, ...);
+
+struct S102094
+{
+int a;
+}
+
+void main()
+{
+S102094 x;
+void nested()
+{
+printf(cast(char*)0, x);
+}
+}
--
2.30.2
[committed] d: Use POINTER_SIZE for testing whether to predefine D_LP64
Hi,
This patch removes uses of global.params to get information about the
target. Using POINTER_SIZE is assumed to be reliably set at the point
where predefined version conditions are inserted into the compilation.
Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32,
committed to mainline.
Regards,
Iain
---
gcc/d/ChangeLog:
* d-builtins.cc (d_init_versions): Use POINTER_SIZE for testing
whether to predefine D_LP64.
---
gcc/d/d-builtins.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/d/d-builtins.cc b/gcc/d/d-builtins.cc
index 328711fc745..ab39d69c294 100644
--- a/gcc/d/d-builtins.cc
+++ b/gcc/d/d-builtins.cc
@@ -462,7 +462,7 @@ d_init_versions (void)
VersionCondition::addPredefinedGlobalIdent ("GNU_InlineAsm");
/* LP64 only means 64bit pointers in D. */
- if (global.params.isLP64)
+ if (POINTER_SIZE == 64)
VersionCondition::addPredefinedGlobalIdent ("D_LP64");
/* Setting `global.params.cov' forces module info generation which is
--
2.30.2
[committed] d: Convert convert_for_rvalue switch statement into if condition
Hi,
This patch replaces the switch statement in convert_for_rvalue with an
if condition. In the D implementation of the D front-end, the condition
value has been changed to an `enum class` type.
Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32,
committed to mainline.
Regards,
Iain
---
gcc/d/ChangeLog:
* d-convert.cc (convert_for_rvalue): Convert switch statement into if
condition.
---
gcc/d/d-convert.cc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/d/d-convert.cc b/gcc/d/d-convert.cc
index d43485dca77..3b4790298a5 100644
--- a/gcc/d/d-convert.cc
+++ b/gcc/d/d-convert.cc
@@ -613,9 +613,8 @@ convert_for_rvalue (tree expr, Type *etype, Type *totype)
Type *ebtype = etype->toBasetype ();
Type *tbtype = totype->toBasetype ();
- switch (ebtype->ty)
+ if (ebtype->ty == Tbool)
{
-case Tbool:
/* If casting from bool, the result is either 0 or 1, any other value
violates @safe code, so enforce that it is never invalid. */
if (CONSTANT_CLASS_P (expr))
@@ -633,7 +632,6 @@ convert_for_rvalue (tree expr, Type *etype, Type *totype)
}
result = convert (build_ctype (tbtype), result);
- break;
}
return result ? result : convert_expr (expr, etype, totype);
--
2.30.2
[committed] d: Get __c_wchar_t type from build_frontend_type
Hi This patch uses build_frontend_type to get the underlying type for __c_wchar_t. The previous field has been removed from the upstream D implementation of the D front-end. Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32, committed to mainline. Regards, Iain --- gcc/d/ChangeLog: * types.cc (TypeVisitor::visit(TypeEnum*)): Get wchar_t type from build_frontend_type. --- gcc/d/types.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/d/types.cc b/gcc/d/types.cc index 8e674618004..fc8a1330696 100644 --- a/gcc/d/types.cc +++ b/gcc/d/types.cc @@ -886,7 +886,8 @@ public: else if (strcmp (ident, "ulong") == 0) underlying = build_frontend_type (long_unsigned_type_node); else if (strcmp (ident, "wchar_t") == 0) - underlying = target.c.twchar_t; + underlying = + build_frontend_type (make_unsigned_type (WCHAR_TYPE_SIZE)); else if (strcmp (ident, "longlong") == 0) underlying = build_frontend_type (long_long_integer_type_node); else if (strcmp (ident, "ulonglong") == 0) -- 2.30.2
[committed] d: Use `int` to store class and struct flags
Hi, This patch replaces ClassFlags and StructFlags with an int. In the D implementation of the D front-end, this type has been changed to an `enum class`. Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32, committed to mainline. Regards, Iain --- gcc/d/ChangeLog: * typeinfo.cc (TypeInfoVisitor::visit(TypeInfoClassDeclaration *)): Use int to store type flags. (TypeInfoVisitor::visit(TypeInfoStructDeclaration *)): Likewise. --- gcc/d/typeinfo.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/d/typeinfo.cc b/gcc/d/typeinfo.cc index 978c73e65f6..04e228abf7c 100644 --- a/gcc/d/typeinfo.cc +++ b/gcc/d/typeinfo.cc @@ -868,7 +868,7 @@ public: this->layout_field (inv); /* ClassFlags m_flags; */ - ClassFlags::Type flags = ClassFlags::hasOffTi; + int flags = ClassFlags::hasOffTi; if (cd->isCOMclass ()) flags |= ClassFlags::isCOMclass; @@ -962,7 +962,7 @@ public: this->layout_field (null_pointer_node); /* ClassFlags m_flags; */ - ClassFlags::Type flags = ClassFlags::hasOffTi; + int flags = ClassFlags::hasOffTi; flags |= ClassFlags::hasTypeInfo; if (cd->isCOMinterface ()) flags |= ClassFlags::isCOMclass; @@ -1091,7 +1091,7 @@ public: this->layout_field (null_pointer_node); /* StructFlags m_flags; */ -StructFlags::Type m_flags = 0; +int m_flags = StructFlags::none; if (ti->hasPointers ()) m_flags |= StructFlags::hasPointers; this->layout_field (build_integer_cst (m_flags, d_uint_type)); -- 2.30.2
[committed] d: Update comment for TypeInfoVisitor::layout_base
Hi,
This patch updates the comment for TypeInfoVisitor::layout_base to
reflect a recent change that made the emission of a __monitor optional.
Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32,
committed to mainline.
Regards,
Iain
---
gcc/d/ChangeLog:
* typeinfo.cc (class TypeInfoVisitor::layout_base): Update comment.
---
gcc/d/typeinfo.cc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/d/typeinfo.cc b/gcc/d/typeinfo.cc
index 04e228abf7c..fd8c746a307 100644
--- a/gcc/d/typeinfo.cc
+++ b/gcc/d/typeinfo.cc
@@ -411,8 +411,7 @@ class TypeInfoVisitor : public Visitor
this->layout_field (value);
}
-
- /* Write out the __vptr and __monitor fields of class CD. */
+ /* Write out the __vptr and optionally __monitor fields of class CD. */
void layout_base (ClassDeclaration *cd)
{
--
2.30.2
[committed] d: Call the assertp and boundsp variants for assert and array contract failures.
Hi,
This patch updates the code generator to call _d_assertp or
_d_arrayboundsp when an assert or array bounds check fails respectively.
These functions accept an `immutable(char)*` instead of an
`immutable(char)[]`. The subtle difference being that the length of the
string no longer has to be included in the generated code.
Bootstrapped and regression tested on x86_64-linux-gnu/-m32/-mx32,
committed to mainline.
Regards,
Iain
---
gcc/d/ChangeLog:
* d-codegen.cc: Include dmd/module.h.
(build_filename_from_loc): New function.
(d_assert_call): Rename to...
(build_assert_call): ...this.
(build_array_bounds_call): Call arrayboundsp variant of the array
bounds failure callback.
(build_bounds_condition): Rename to...
(build_bounds_index_condition): ...this. Update signature.
(build_bounds_slice_condition): New function.
(checkaction_trap_p): New function.
(d_assert_call): Call assertp variant of assert failure callback.
* d-tree.h (class IndexExp): Declare.
(class SliceExp): Declare.
(build_bounds_condition): Remove.
(build_assert_call): Declare.
(build_bounds_index_condition): Declare.
(build_bounds_slice_condition): Declare.
(checkaction_trap_p): Declare.
(d_assert_call): Remove.
* expr.cc (ExprVisitor::visit(IndexExp *)): Call
build_bounds_index_condition.
(ExprVisitor::visit(SliceExp *)): Call build_bounds_slice_condition.
(ExprVisitor::visit(AssertExp *)): Update setting of libcall.
* runtime.cc (enum d_libcall_type): Add LCT_IMMUTABLE_CHARPTR.
(get_libcall_type): Handle LCT_IMMUTABLE_CHARPTR.
* runtime.def (ASSERT): Rename to...
(ASSERTP): ...this. Update signature.
(UNITTEST): Rename to...
(UNITTESTP): ...this. Update signature.
(ARRAY_BOUNDS): Rename to...
(ARRAYBOUNDSP): ...this. Updates signature.
* toir.cc (IRVisitor::visit(SwitchErrorStatement *)): Update call.
---
gcc/d/d-codegen.cc | 185 ++---
gcc/d/d-tree.h | 8 +-
gcc/d/expr.cc | 58 ++
gcc/d/runtime.cc | 5 ++
gcc/d/runtime.def | 24 +++---
gcc/d/toir.cc | 2 +-
6 files changed, 173 insertions(+), 109 deletions(-)
diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc
index ad20bd15403..e63365055d3 100644
--- a/gcc/d/d-codegen.cc
+++ b/gcc/d/d-codegen.cc
@@ -23,6 +23,7 @@ along with GCC; see the file COPYING3. If not see
#include "dmd/ctfe.h"
#include "dmd/declaration.h"
#include "dmd/identifier.h"
+#include "dmd/module.h"
#include "dmd/target.h"
#include "dmd/template.h"
@@ -1831,50 +1832,149 @@ void_okay_p (tree t)
return t;
}
-/* Builds a CALL_EXPR at location LOC in the source file to execute when an
- array bounds check fails. */
+/* Builds a STRING_CST representing the filename of location LOC. When the
+ location is not valid, the name of the source module is used instead. */
+
+static tree
+build_filename_from_loc (const Loc &loc)
+{
+ const char *filename = loc.filename
+? loc.filename : d_function_chain->module->srcfile->toChars ();
+
+ unsigned length = strlen (filename);
+ tree str = build_string (length, filename);
+ TREE_TYPE (str) = make_array_type (Type::tchar, length + 1);
+
+ return build_address (str);
+}
+
+/* Builds a CALL_EXPR at location LOC in the source file to call LIBCALL when
+ an assert check fails. When calling the msg variant functions, MSG is the
+ error message supplied by the user. */
tree
-build_array_bounds_call (const Loc &loc)
+build_assert_call (const Loc &loc, libcall_fn libcall, tree msg)
{
- switch (global.params.checkAction)
+ tree file;
+ tree line = size_int (loc.linnum);
+
+ switch (libcall)
{
-case CHECKACTION_D:
- return d_assert_call (loc, LIBCALL_ARRAY_BOUNDS);
+case LIBCALL_ASSERT_MSG:
+case LIBCALL_UNITTEST_MSG:
+case LIBCALL_SWITCH_ERROR:
+ /* File location is passed as a D string. */
+ if (loc.filename)
+ {
+ unsigned len = strlen (loc.filename);
+ tree str = build_string (len, loc.filename);
+ TREE_TYPE (str) = make_array_type (Type::tchar, len);
-case CHECKACTION_C:
-case CHECKACTION_halt:
- return build_call_expr (builtin_decl_explicit (BUILT_IN_TRAP), 0);
+ file = d_array_value (build_ctype (Type::tchar->arrayOf ()),
+ size_int (len), build_address (str));
+ }
+ else
+ file = null_array_node;
+ break;
+
+case LIBCALL_ASSERTP:
+case LIBCALL_UNITTESTP:
+ file = build_filename_from_loc (loc);
+ break;
default:
gcc_unreachable ();
}
+
+
+ if (msg != NULL_TREE)
+return build_libcall (libcall, Type::tvoid, 3, msg, file, line);
+ else
+return build_libcall (libcall, Type::tvoid, 2, file, line);
}
-/* Builds a bounds condition
[wwwdocs] [PATCH] x86-64: Document ABI changes for structures with a 64-bit vector
TYPE_MODE of record and union depends on whether vector_mode_supported_p returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass a parameter and return a value in a function. 64-bit integer vectors were supported only by MMX and 64-bit float vector was supported only by 3DNOW. GCC 10.1 enabled 64-bit integer vectors without MMX by: commit dfa61b9ed06d71901c4c430caa89820972ad68fe Author: H.J. Lu Date: Wed May 15 15:02:54 2019 + i386: Allow MMX register modes in SSE registers In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. GCC 10.4 is changed to diagnose this ABI change with -Wpsabi. GCC 11.1 enabled 64-bit float vector without 3DNOW by: commit 7c355156aa20eaec7401d7c66f6a6cfbe597abc2 Author: Uros Bizjak Date: Mon May 11 11:16:31 2020 +0200 i386: Vectorize basic V2SFmode operations [PR94913] Enable V2SFmode vectorization and vectorize V2SFmode PLUS, MINUS, MULT, MIN and MAX operations using XMM registers. GCC 11.3 is changed to diagnose this ABI change with -Wpsabi. --- htdocs/gcc-10/changes.html | 18 ++ htdocs/gcc-11/changes.html | 15 +++ 2 files changed, 33 insertions(+) diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index 5f386792..e3d8bed9 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -1155,6 +1155,24 @@ are not listed here). via -march=znver3. + + + +GCC 10.4 + +Target Specific Changes + +x86-64 + + +The x86-64 ABI +of passing and returning structures with a 64-bit integer vector +changed in GCC 10.1 when MMX is disabled. Disabling MMX no longer +changes how they are passed nor returned. This ABI change is now +diagnosed with -Wpsabi. + + + diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index 6dec8856..220a415c 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -1116,5 +1116,20 @@ are not listed here). +GCC 11.3 + +Target Specific Changes + +x86-64 + + +The x86-64 ABI +of passing and returning structure with a 64-bit single precision +vector changed in GCC 11.1 when 3DNOW is disabled. Disabling 3DNOW +no longer changes how they are passed nor returned. This ABI change +is now diagnosed with -Wpsabi. + + + -- 2.31.1
[PATCH 1/3] libiberty: Add support for D `typeof(*null)' types
Hi,
The D language has a new bottom type `typeof(*null)'. Null types were
also incorrectly being demangled as `none', this has been fixed to be
`typeof(null)'.
Bootstrapped and regression tested on x86_64-linux-gnu.
OK for mainline?
Regards,
Iain.
---
libiberty/ChangeLog:
* d-demangle.c (dlang_attributes): Handle typeof(*null).
(dlang_type): Likewise. Demangle 'n' as typeof(null).
* testsuite/d-demangle-expected: Update tests.
---
libiberty/d-demangle.c | 12 ++--
libiberty/testsuite/d-demangle-expected | 6 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/libiberty/d-demangle.c b/libiberty/d-demangle.c
index 822c7580782..c34f91843de 100644
--- a/libiberty/d-demangle.c
+++ b/libiberty/d-demangle.c
@@ -573,9 +573,11 @@ dlang_attributes (string *decl, const char *mangled)
case 'g':
case 'h':
case 'k':
+ case 'n':
/* inout parameter is represented as 'Ng'.
vector parameter is represented as 'Nh'.
-return paramenter is represented as 'Nk'.
+return parameter is represented as 'Nk'.
+typeof(*null) parameter is represented as 'Nn'.
If we see this, then we know we're really in the
parameter list. Rewind and break. */
mangled--;
@@ -787,6 +789,12 @@ dlang_type (string *decl, const char *mangled, struct
dlang_info *info)
string_append (decl, ")");
return mangled;
}
+ else if (*mangled == 'n') /* typeof(*null) */
+ {
+ mangled++;
+ string_append (decl, "typeof(*null)");
+ return mangled;
+ }
else
return NULL;
case 'A': /* dynamic array (T[]) */
@@ -884,7 +892,7 @@ dlang_type (string *decl, const char *mangled, struct
dlang_info *info)
/* Basic types */
case 'n':
mangled++;
- string_append (decl, "none");
+ string_append (decl, "typeof(null)");
return mangled;
case 'v':
mangled++;
diff --git a/libiberty/testsuite/d-demangle-expected
b/libiberty/testsuite/d-demangle-expected
index ba0ffed5c8d..00036e7810a 100644
--- a/libiberty/testsuite/d-demangle-expected
+++ b/libiberty/testsuite/d-demangle-expected
@@ -83,7 +83,11 @@ demangle.test(ulong)
#
--format=dlang
_D8demangle4testFnZv
-demangle.test(none)
+demangle.test(typeof(null))
+#
+--format=dlang
+_D8demangle4testFNnZv
+demangle.test(typeof(*null))
#
--format=dlang
_D8demangle4testFoZv
--
2.30.2
[PATCH 2/3] libiberty: Add support for demangling D function literals as template value parameters
Hi,
The D language now allows instantiating templates using struct literals
that have function literal fields as a value argument.
Bootstrapped and regression tested on x86_64-linux-gnu.
OK for mainline?
Regards,
Iain.
---
libiberty/ChangeLog:
* d-demangle.c (dlang_parse_arrayliteral): Add 'info' parameter.
(dlang_parse_assocarray): Likewise.
(dlang_parse_structlit): Likewise.
(dlang_value): Likewise. Handle function literal symbols.
(dlang_template_args): Pass 'info' to dlang_value.
* testsuite/d-demangle-expected: Add new test.
---
libiberty/d-demangle.c | 40 +
libiberty/testsuite/d-demangle-expected | 4 +++
2 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/libiberty/d-demangle.c b/libiberty/d-demangle.c
index c34f91843de..d74cf47b1a9 100644
--- a/libiberty/d-demangle.c
+++ b/libiberty/d-demangle.c
@@ -191,7 +191,8 @@ static const char *dlang_function_args (string *, const
char *,
static const char *dlang_type (string *, const char *, struct dlang_info *);
-static const char *dlang_value (string *, const char *, const char *, char);
+static const char *dlang_value (string *, const char *, const char *, char,
+ struct dlang_info *);
static const char *dlang_parse_qualified (string *, const char *,
struct dlang_info *, int);
@@ -1386,7 +1387,8 @@ dlang_parse_string (string *decl, const char *mangled)
/* Extract the static array value from MANGLED and append it to DECL.
Return the remaining string on success or NULL on failure. */
static const char *
-dlang_parse_arrayliteral (string *decl, const char *mangled)
+dlang_parse_arrayliteral (string *decl, const char *mangled,
+ struct dlang_info *info)
{
unsigned long elements;
@@ -1397,7 +1399,7 @@ dlang_parse_arrayliteral (string *decl, const char
*mangled)
string_append (decl, "[");
while (elements--)
{
- mangled = dlang_value (decl, mangled, NULL, '\0');
+ mangled = dlang_value (decl, mangled, NULL, '\0', info);
if (mangled == NULL)
return NULL;
@@ -1412,7 +1414,8 @@ dlang_parse_arrayliteral (string *decl, const char
*mangled)
/* Extract the associative array value from MANGLED and append it to DECL.
Return the remaining string on success or NULL on failure. */
static const char *
-dlang_parse_assocarray (string *decl, const char *mangled)
+dlang_parse_assocarray (string *decl, const char *mangled,
+ struct dlang_info *info)
{
unsigned long elements;
@@ -1423,12 +1426,12 @@ dlang_parse_assocarray (string *decl, const char
*mangled)
string_append (decl, "[");
while (elements--)
{
- mangled = dlang_value (decl, mangled, NULL, '\0');
+ mangled = dlang_value (decl, mangled, NULL, '\0', info);
if (mangled == NULL)
return NULL;
string_append (decl, ":");
- mangled = dlang_value (decl, mangled, NULL, '\0');
+ mangled = dlang_value (decl, mangled, NULL, '\0', info);
if (mangled == NULL)
return NULL;
@@ -1443,7 +1446,8 @@ dlang_parse_assocarray (string *decl, const char *mangled)
/* Extract the struct literal value for NAME from MANGLED and append it to
DECL.
Return the remaining string on success or NULL on failure. */
static const char *
-dlang_parse_structlit (string *decl, const char *mangled, const char *name)
+dlang_parse_structlit (string *decl, const char *mangled, const char *name,
+ struct dlang_info *info)
{
unsigned long args;
@@ -1457,7 +1461,7 @@ dlang_parse_structlit (string *decl, const char *mangled,
const char *name)
string_append (decl, "(");
while (args--)
{
- mangled = dlang_value (decl, mangled, NULL, '\0');
+ mangled = dlang_value (decl, mangled, NULL, '\0', info);
if (mangled == NULL)
return NULL;
@@ -1472,7 +1476,8 @@ dlang_parse_structlit (string *decl, const char *mangled,
const char *name)
/* Extract the value from MANGLED and append it to DECL.
Return the remaining string on success or NULL on failure. */
static const char *
-dlang_value (string *decl, const char *mangled, const char *name, char type)
+dlang_value (string *decl, const char *mangled, const char *name, char type,
+struct dlang_info *info)
{
if (mangled == NULL || *mangled == '\0')
return NULL;
@@ -1533,15 +1538,24 @@ dlang_value (string *decl, const char *mangled, const
char *name, char type)
case 'A':
mangled++;
if (type == 'H')
- mangled = dlang_parse_assocarray (decl, mangled);
+ mangled = dlang_parse_assocarray (decl, mangled, info);
else
- mangled = dlang_parse_arrayliteral (decl, mangled);
+ mangled = dlang_parse_arrayliteral (decl, mangled, info);
break;
/* Struct values. */
case 'S':
mangled++;
- mangled =
[PATCH 3/3] libiberty: Add support for demangling local D template declarations
Hi,
The D language now allows multiple different template declarations in
the same function that have the same mangled name. To make the mangled
names unique, a fake parent in the form `__Sddd' is added to the symbol.
This information is not important for the user, so the demangler now
handles and ignores it.
Bootstrapped and regression tested on x86_64-linux-gnu.
OK for mainline?
Regards,
Iain.
---
libiberty/ChangeLog:
* d-demangle.c (dlang_identifier): Skip over fake parent manglings.
* testsuite/d-demangle-expected: Add tests.
---
libiberty/d-demangle.c | 19 +++
libiberty/testsuite/d-demangle-expected | 24
2 files changed, 43 insertions(+)
diff --git a/libiberty/d-demangle.c b/libiberty/d-demangle.c
index d74cf47b1a9..a2152cc6551 100644
--- a/libiberty/d-demangle.c
+++ b/libiberty/d-demangle.c
@@ -1044,6 +1044,25 @@ dlang_identifier (string *decl, const char *mangled,
struct dlang_info *info)
&& (mangled[2] == 'T' || mangled[2] == 'U'))
return dlang_parse_template (decl, mangled, info, len);
+ /* There can be multiple different declarations in the same function that
have
+ the same mangled name. To make the mangled names unique, a fake parent in
+ the form `__Sddd' is added to the symbol. */
+ if (len >= 4 && mangled[0] == '_' && mangled[1] == '_' && mangled[2] == 'S')
+{
+ const char *numptr = mangled + 3;
+ while (numptr < (mangled + len) && ISDIGIT (*numptr))
+ numptr++;
+
+ if (mangled + len == numptr)
+ {
+ /* Skip over the fake parent. */
+ mangled += len;
+ return dlang_identifier (decl, mangled, info);
+ }
+
+ /* else demangle it as a plain identifier. */
+}
+
return dlang_lname (decl, mangled, len);
}
diff --git a/libiberty/testsuite/d-demangle-expected
b/libiberty/testsuite/d-demangle-expected
index 87ed8d330a8..c35185c3e1e 100644
--- a/libiberty/testsuite/d-demangle-expected
+++ b/libiberty/testsuite/d-demangle-expected
@@ -1420,5 +1420,29 @@
_D3std3uni__T6toCaseS_DQvQt12toLowerIndexFNaNbNiNewZtVii1043S_DQCjQCi10toLowerTa
std.uni.toCase!(std.uni.toLowerIndex(dchar), 1043, std.uni.toLowerTab(ulong),
std.ascii.toLower,
immutable(char)[]).toCase(immutable(char)[]).__foreachbody2(ref ulong, ref
dchar).__foreachbody3(ref dchar)
#
--format=dlang
+_D8demangle4mainFZ1xi
+demangle.main().x
+#
+--format=dlang
+_D8demangle4mainFZ4__S11xi
+demangle.main().x
+#
+--format=dlang
+_D8demangle4mainFZ1fMFNaNbNiNfZv
+demangle.main().f()
+#
+--format=dlang
+_D8demangle4mainFZ4__S11fMFNaNbNiNfZv
+demangle.main().f()
+#
+--format=dlang
+_D3mod4funcFZ__T6nestedTiZQkMFNaNbNiNfZi
+mod.func().nested!(int).nested()
+#
+--format=dlang
+_D3mod4funcFZ__T6nestedTiZ4__S1QpMFNaNbNiNfZi
+mod.func().nested!(int).nested()
+#
+--format=dlang
_D6mangle__T8fun21753VSQv6S21753S1f_DQBj10__lambda71MFNaNbNiNfZvZQCbQp
mangle.fun21753!(mangle.S21753(mangle.__lambda71())).fun21753
--
2.30.2
Re: [PATCH] x86-64: Add ABI warning for 64-bit vectors
On Sun, Aug 29, 2021 at 09:17:10AM -0700, H.J. Lu wrote: > How does it work? Depends on the terminal. E.g. in recent, at most a few years old gnome-terminal, that GCC 11.1 is dotted underlined and hovering with mouse on it shows it normal underlined and prints the URL, right click shows a menu in which one can Open Hyperlink. See https://gist.github.com/egmontkob/eb114294efbcd5adb1944c9f3cb5feda Jakub
[PATCH v2] x86-64: Add ABI warning for 64-bit vectors
TYPE_MODE of record and union depends on whether vector_mode_supported_p
returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass
a parameter and return a value in a function. 64-bit integer vectors
were supported only by MMX and 64-bit float vector was supported only by
3DNOW. GCC 10 enabled 64-bit integer vectors without MMX by:
commit dfa61b9ed06d71901c4c430caa89820972ad68fe
Author: H.J. Lu
Date: Wed May 15 15:02:54 2019 +
i386: Allow MMX register modes in SSE registers
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
GCC 11 enabled 64-bit float vector without 3DNOW by:
commit 7c355156aa20eaec7401d7c66f6a6cfbe597abc2
Author: Uros Bizjak
Date: Mon May 11 11:16:31 2020 +0200
i386: Vectorize basic V2SFmode operations [PR94913]
Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
MINUS, MULT, MIN and MAX operations using XMM registers.
Add ABI warnings for 64-bit integer vectors without MMX and 64-bit float
vector without 3DNOW.
gcc/
PR target/102027
PR target/102105
* config/i386/i386.c (single_m64_base_type): New function.
(type_natural_mode): Add ABI warnings for 64-bit vectors.
gcc/testsuite/
PR target/102027
PR target/102105
* gcc.target/i386/pr102027-1.c: New test.
* gcc.target/i386/pr102027-2.c: Likewise.
* gcc.target/i386/pr102027-3.c: Likewise.
* gcc.target/i386/pr102105-1.c: Likewise.
* gcc.target/i386/pr102105-2.c: Likewise.
* gcc.target/i386/pr102105-3.c: Likewise.
* gcc.target/i386/pr102105-4.c: Likewise.
* gcc.target/i386/sse2-mmx-4.c: Add -Wno-psabi.
---
gcc/config/i386/i386.c | 131 -
gcc/testsuite/gcc.target/i386/pr102027-1.c | 15 +++
gcc/testsuite/gcc.target/i386/pr102027-2.c | 15 +++
gcc/testsuite/gcc.target/i386/pr102027-3.c | 17 +++
gcc/testsuite/gcc.target/i386/pr102105-1.c | 15 +++
gcc/testsuite/gcc.target/i386/pr102105-2.c | 15 +++
gcc/testsuite/gcc.target/i386/pr102105-3.c | 17 +++
gcc/testsuite/gcc.target/i386/pr102105-4.c | 17 +++
gcc/testsuite/gcc.target/i386/sse2-mmx-4.c | 2 +-
9 files changed, 242 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr102027-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102027-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102027-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr102105-4.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3bb2cab57a3..cd69e466ca7 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1840,6 +1840,54 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument
info to initialize */
cfun->machine->arg_reg_available = (cum->nregs > 0);
}
+/* Return the single 64-bit vector type of TYPE. */
+
+static const_tree
+single_m64_base_type (const_tree type)
+{
+ if ((TREE_CODE (type) == RECORD_TYPE
+ || TREE_CODE (type) == UNION_TYPE
+ || TREE_CODE (type) == QUAL_UNION_TYPE)
+ && int_size_in_bytes (type) == 8)
+{
+ const_tree field;
+ const_tree first_field = nullptr;
+
+ for (field = TYPE_FIELDS (type);
+ field;
+ field = DECL_CHAIN (field))
+ if (TREE_CODE (field) == FIELD_DECL)
+ {
+ if (TREE_TYPE (field) == error_mark_node)
+ continue;
+
+ /* Skip if structure has more than one field. */
+ if (first_field)
+ return nullptr;
+
+ first_field = field;
+ }
+
+ /* Skip if structure doesn't have any fields. */
+ if (!first_field)
+ return nullptr;
+
+ type = TREE_TYPE (first_field);
+
+ /* Skip if structure size isn't 64 bits. */
+ if (int_size_in_bytes (type) != 8)
+ return nullptr;
+
+ /* Return if a 64-bit vector is found. */
+ if (TREE_CODE (type) == VECTOR_TYPE)
+ return type;
+
+ return single_m64_base_type (type);
+}
+
+ return nullptr;
+}
+
/* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
But in the case of vector types, it is some vector mode.
@@ -1861,7 +1909,88 @@ static machine_mode
type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
bool in_return)
{
- machine_mode mode = TYPE_MODE (type);
+ machine_mode mode;
+
+ const_tree m64_type = single_m64_base_type (type);
+ if (m64_type)
+{
+ mode = TYPE_MODE (m64_type);
+
+ if (!warn_psabi)
+ return mode;
+
+ const char *url;
+ if (mode == V2SFmode)
+ {
+ /* GCC 11 enables V2SFmode without TARGET_3DNOW. */
+ if (TARGET_3DNOW)
+ return mode;
+
+
[pushed] Darwin: Fixes for darwin_libc_has_function.
Hi,
Firstly, the checks for availability need not be run for any
currently supported Darwin version (or for any version of
Darwin on x86). In fact, the only test that is needed that
differs from the default is for the availability of sincos.
Test that and then fall back to the default implementation.
Secondly, the function appears to be called from the Jit library
before the value of darwin_macosx_version_min has been set up -
at present we work around this by guarding the checks on having
a non-null pointer for darwin_macosx_version_min.
tested on powerpc, i686, x86_64-darwin (and x86-64-linux),
pushed to master, thanks
Iain
Signed-off-by: Iain Sandoe
gcc/ChangeLog:
* config/darwin.c (darwin_libc_has_function): Do not run
the checks for x86 or modern Darwin. Make sure that there
is a value set for darwin_macosx_version_min before testing.
---
gcc/config/darwin.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 667fda79a60..781742fe46f 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -42,6 +42,7 @@ along with GCC; see the file COPYING3. If not see
#include "explow.h"
#include "expr.h"
#include "langhooks.h"
+#include "targhooks.h"
#include "toplev.h"
#include "lto-section-names.h"
#include "intl.h"
@@ -3661,19 +3662,22 @@ darwin_rename_builtins (void)
}
}
+/* Implementation for the TARGET_LIBC_HAS_FUNCTION hook. */
+
bool
darwin_libc_has_function (enum function_class fn_class,
tree type ATTRIBUTE_UNUSED)
{
- if (fn_class == function_sincos)
+ if (fn_class == function_sincos && darwin_macosx_version_min)
return (strverscmp (darwin_macosx_version_min, "10.9") >= 0);
-
+#if DARWIN_PPC && SUPPORT_DARWIN_LEGACY
if (fn_class == function_c99_math_complex
|| fn_class == function_c99_misc)
return (TARGET_64BIT
- || strverscmp (darwin_macosx_version_min, "10.3") >= 0);
-
- return true;
+ || (darwin_macosx_version_min &&
+ strverscmp (darwin_macosx_version_min, "10.3") >= 0));
+#endif
+ return default_libc_has_function (fn_class, type);
}
hashval_t
Re: [PATCH 1/3] libiberty: Add support for D `typeof(*null)' types
On 8/29/2021 12:46 PM, Iain Buclaw via Gcc-patches wrote: Hi, The D language has a new bottom type `typeof(*null)'. Null types were also incorrectly being demangled as `none', this has been fixed to be `typeof(null)'. Bootstrapped and regression tested on x86_64-linux-gnu. OK for mainline? Regards, Iain. --- libiberty/ChangeLog: * d-demangle.c (dlang_attributes): Handle typeof(*null). (dlang_type): Likewise. Demangle 'n' as typeof(null). * testsuite/d-demangle-expected: Update tests. I'd argue anything in d-demangle would fall under your maintainership for D. So, OK and similarly for the other two D demangling patches. jeff
Re: [PATCH] Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI)))
On 8/29/2021 1:46 AM, Roger Sayle wrote:
SUBREG_PROMOTED_VAR_P is a mechanism for tracking that a partial subreg
is correctly zero-extended or sign-extended in the parent register. For
example, the RTL (subreg/s/v:QI (reg/v:SI 23 [ x ]) 0) indicates that the
byte x is zero extended in reg:SI 23, which is useful for optimization.
An example is that zero extending the above QImode value to HImode can
simply use a wider subreg, i.e. (subreg:HI (reg/v:SI 23 [ x ]) 0).
This patch addresses the oversight/missed optimization opportunity that
the new HImode subreg above should retain its SUBREG_PROMOTED_VAR_P
annotation as its value is guaranteed to be correctly extended in the
SImode parent. The code below to preserve SUBREG_PROMOTED_VAR_P is already
present in the middle-end (e.g. simplify-rtx.c:7232-7242) but missing
from one or two (precisely three) places that (accidentally) strip it.
Whilst there I also added another optimization. If we need to extend
the above QImode value beyond the SImode register holding it, say to
DImode, we can eliminate the SUBREG and simply extend from the SImode
register to DImode.
This patch has been tested on x86_64-pc-linux-gnu with "make bootstrap"
and "make -k check" with no new failures, and on a cross-compiler to
nvptx-none, where the function "long foo(char x) { return x; }" now
requires one less instruction.
OK for mainline?
2021-08-29 Roger Sayle
gcc/ChangeLog
* expr.c (convert_modes): Preserve SUBREG_PROMOTED_VAR_P when
creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
subreg.
* simplify-rtx.c (simplify_unary_operation_1) [SIGN_EXTEND]:
Likewise, preserve SUBREG_PROMOTED_VAR_P when creating a (wider)
partial subreg from a SUBREG_PROMOTED_VAR_P subreg. Generate
SIGN_EXTEND of the SUBREG_REG when a subreg would be paradoxical.
[ZERO_EXTEND]: Likewise, preserve SUBREG_PROMOTED_VAR_P when
creating a (wider) partial subreg from a SUBREG_PROMOTED_VAR_P
subreg. Generate ZERO_EXTEND of the SUBREG_REG when a subreg
would be paradoxical.
OK
jeff
Re: [PATCH] libffi: Fix MIPS r6 support
On 8/28/2021 1:23 AM, Xi Ruoyao wrote: On Fri, 2021-08-27 at 15:28 -0600, Jeff Law via Gcc-patches wrote: On 8/26/2021 10:58 PM, YunQiang Su wrote: for some instructions, MIPS r6 uses different encoding other than the previous releases. 1. mips/n32.S disable .set mips4: since it casuses old insn encoding is used. https://github.com/libffi/libffi/pull/396 2. mips/ffi.c: the encoding for JR is hardcoded: we need to use different value for r6 and pre-r6. https://github.com/libffi/libffi/pull/401 libffi/ PR libffi/83636 * src/mips/n32.S: disable .set mips4 * src/mips/ffi.c: use different JR encoding for r6. These should go to the upstream libffi project. Once accepted there you can add them to GCC. Hi Jeff, The two PRs are already merged, and released since libffi-3.3.0 (now the upstream latest release is 3.4.2). ACK. Thanks for confirming. It's always OK to cherrypick/backport from libffi back to GCC. I don't have a MIPSr6 so I can't test though. Understood. Me neither, but I really should get a tiny chroot for mipsr6 so that my tester can validate it regularly. Jeff
Re: Committed: [PATCH] MIPS: use N64 ABI by default if the triple end with -gnuabi64
On 8/28/2021 1:17 AM, Xi Ruoyao wrote: On Fri, 2021-08-27 at 15:38 -0600, Jeff Law wrote: On 8/26/2021 10:20 PM, Xi Ruoyao via Gcc-patches wrote: On Thu, 2021-08-26 at 23:56 -0400, YunQiang Su wrote: gcc/ChangeLog: PR target/102089 * config.gcc: MIPS: use N64 ABI by default if the triple end with -gnuabi64, which is used by Debian since 2013. --- gcc/config.gcc | 14 ++ 1 file changed, 14 insertions(+) diff --git a/gcc/config.gcc b/gcc/config.gcc index 0ff5cac15..0c91be6f3 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2553,16 +2553,30 @@ mips*-*-linux*) # Linux MIPS, either endian. target_cpu_default=MASK_SOFT_FLOAT_ABI enable_mips_multilibs="yes" ;; + mipsisa64r6*-*-linux-gnuabi64) + default_mips_abi=64 + default_mips_arch=mips64r6 + enable_mips_multilibs="yes" + ;; mipsisa64r6*-*-linux*) default_mips_abi=n32 default_mips_arch=mips64r6 enable_mips_multilibs="yes" ;; + mipsisa64r2*-*-linux-gnuabi64) + default_mips_abi=64 + default_mips_arch=mips64r2 + enable_mips_multilibs="yes" + ;; mipsisa64r2*-*-linux*) default_mips_abi=n32 default_mips_arch=mips64r2 enable_mips_multilibs="yes" ;; + mips64*-*-linux-gnuabi64 | mipsisa64*-*-linux- gnuabi64) + default_mips_abi=64 + enable_mips_multilibs="yes" + ;; mips64*-*-linux* | mipsisa64*-*-linux*) default_mips_abi=n32 enable_mips_multilibs="yes" LGTM, but I don't have the privilege to approve any change so you'll still need to wait for approval :) Yea, but having a second pair of eyes chime in is definitely helpful. And I think the behavior change should be announced in https://gcc.gnu.org/gcc-12/changes.html, if it's approved. Agreed. The configure change is approved. Pushed to trunk as 91f78b67. Jeff: YunQiang is working on compilers for CIP United, a company producing MIPS IPs, chips, and toolchains. Is it possible to grant him a write-after-approval? Of course. There's a link to the proper form here: https://gcc.gnu.org/gitwrite.html#authenticated YunQiang can fill that out, list me a sponsor and the overseers will get an account set up. Thanks, jeff
Re: [PATCH 1/3] libiberty: Add support for D `typeof(*null)' types
Excerpts from Jeff Law's message of August 29, 2021 10:55 pm: > > > On 8/29/2021 12:46 PM, Iain Buclaw via Gcc-patches wrote: >> Hi, >> >> The D language has a new bottom type `typeof(*null)'. Null types were >> also incorrectly being demangled as `none', this has been fixed to be >> `typeof(null)'. >> >> Bootstrapped and regression tested on x86_64-linux-gnu. >> >> OK for mainline? >> >> Regards, >> Iain. >> >> --- >> libiberty/ChangeLog: >> >> * d-demangle.c (dlang_attributes): Handle typeof(*null). >> (dlang_type): Likewise. Demangle 'n' as typeof(null). >> * testsuite/d-demangle-expected: Update tests. > I'd argue anything in d-demangle would fall under your maintainership > for D. So, OK and similarly for the other two D demangling patches. > > jeff > OK, I'll keep that in mind for future ABI updates. Thanks, Iain.
Re: [PATCH 2/3] MIPS: use mips_isa enum instead hardcoded numbers
Xi Ruoyao 于2021年8月29日周日 下午1:54写道：
>
> On Sat, 2021-08-28 at 08:05 -0400, YunQiang Su wrote:
> > Currently mips-cpu.defs and mips.h are using hardcoded numbers
> > for isa level.
> >
> > Let's replace them with more readable enum mips_isa.
>
> Good, but there is something like "mips_isa_rev >= 32 && mips_isa_rev <
> 64" in mips.h and netbsd.h. Not sure if they should be replaced
> altogether.
>
Yes. It is my fault. I missed them.
And we also need to replace the similar lines in config.gcc.
> If they are replaced as well, it will be not necessary to set special
> enum values.
>
no. mips_isa is a predefined macro exposed to C programmer.
Some existing code may depend on this behavior.
syq@XXX:~$ gcc -mabi=32 -mips64 -dM -E - < /dev/null | grep '__mips '
#define __mips 64
syq@XXX:~$ gcc -mabi=32 -mips3 -dM -E - < /dev/null | grep '__mips '
#define __mips 3
syq@XXX:~$ gcc -mabi=32 -mips32 -dM -E - < /dev/null | grep '__mips '
#define __mips 32
And codesearch give us some examples:
http://codesearch.debian.net/search?q=__mips+%3E&literal=1
> How do the others think?
>
> > gcc/ChangeLog:
> > * config/mips/mips.md: define_enum "mips_isa".
> > * config/mips/mips.h (struct mips_cpu_info): use enum
> > instead of int for 'isa' member.
> > * config/mips/mips{.h,-cpus.def}: replace hardcoded
> > numbers with enum.
> > ---
> > gcc/config/mips/mips-cpus.def | 228 +
> > -
> > gcc/config/mips/mips.h| 50
> > gcc/config/mips/mips.md | 17 +++
> > 3 files changed, 156 insertions(+), 139 deletions(-)
> >
> > diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-
> > cpus.def
> > index b02294be4..45fb6bc8b 100644
> > --- a/gcc/config/mips/mips-cpus.def
> > +++ b/gcc/config/mips/mips-cpus.def
> > @@ -33,146 +33,146 @@ along with GCC; see the file COPYING3. If not
> > see
> > where the arguments are the fields of struct mips_cpu_info. */
> >
> > /* Entries for generic ISAs. */
> > -MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("mips2", PROCESSOR_R6000, 2, PTF_AVOID_BRANCHLIKELY_SIZE)
> > -MIPS_CPU ("mips3", PROCESSOR_R4000, 3, PTF_AVOID_BRANCHLIKELY_SIZE)
> > -MIPS_CPU ("mips4", PROCESSOR_R1, 4, PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips1", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
> > +MIPS_CPU ("mips2", PROCESSOR_R6000, MIPS_ISA_MIPS2,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips3", PROCESSOR_R4000, MIPS_ISA_MIPS3,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > +MIPS_CPU ("mips4", PROCESSOR_R1, MIPS_ISA_MIPS4,
> > PTF_AVOID_BRANCHLIKELY_SIZE)
> > /* Prefer not to use branch-likely instructions for generic MIPS32rX
> > and MIPS64rX code. The instructions were officially deprecated
> > in revisions 2 and earlier, but revision 3 is likely to downgrade
> > that to a recommendation to avoid the instructions in code that
> > isn't tuned to a specific processor. */
> > -MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32", PROCESSOR_4KC, MIPS_ISA_MIPS32,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > /* mips32r3 is micromips hense why it uses the M4K processor. */
> > -MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0)
> > -MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0)
> > +MIPS_CPU ("mips64", PROCESSOR_5KC, MIPS_ISA_MIPS64,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > /* ??? For now just tune the generic MIPS64r2 and above for 5KC as
> > well. */
> > -MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > -MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, 0)
> > +MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5,
> > PTF_AVOID_BRANCHLIKELY_ALWAYS)
> > +MIPS_CPU ("mips64r6", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0)
> >
> > /* MIPS I processors. */
> > -MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
> > -MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
> > +MIPS_CPU ("r3000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0)
>
Re: [PATCH] rs6000: Add missing unsigned info for some P10 bifs
on 2021/8/11 下午1:44, Kewen.Lin via Gcc-patches wrote: > Hi, > > This patch is to make prototypes of some Power10 built-in > functions consistent with what's in the documentation, as > well as the vector version. Otherwise, useless conversions > can be generated in gimple IR, and the vectorized versions > will have inconsistent types. > > Bootstrapped & regtested on powerpc64le-linux-gnu P9 and > powerpc64-linux-gnu P8. > > Is it ok for trunk? > This has been approved by Segher offline, thanks Segher! Committed in r12-3179. BR, Kewen > BR, > Kewen > - > gcc/ChangeLog: > > * config/rs6000/rs6000-call.c (builtin_function_type): Add unsigned > signedness for some Power10 bifs. >
[PATCH v2] MIPS: add .module mipsREV to all output asm file
Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
assembler is mips1 by default,
gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.
gcc/ChangeLog:
* gcc/config/mips/mips.c (mips_module_isa_name): New.
mips_file_start: add .module mipsREV to all asm output
---
gcc/config/mips/mips.c | 41 +
1 file changed, 41 insertions(+)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 493d3de48..a7087ec0a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
}
}
+static const char *
+mips_module_isa_name ()
+{
+ switch (mips_isa)
+{
+case MIPS_ISA_MIPS1:
+ return "mips1";
+case MIPS_ISA_MIPS2:
+ return "mips2";
+case MIPS_ISA_MIPS3:
+ return "mips3";
+case MIPS_ISA_MIPS4:
+ return "mips4";
+case MIPS_ISA_MIPS32:
+ return "mips32";
+case MIPS_ISA_MIPS32R2:
+ return "mips32r2";
+case MIPS_ISA_MIPS32R3:
+ return "mips32r3";
+case MIPS_ISA_MIPS32R5:
+ return "mips32r5";
+case MIPS_ISA_MIPS32R6:
+ return "mips32r6";
+case MIPS_ISA_MIPS64:
+ return "mips64";
+case MIPS_ISA_MIPS64R2:
+ return "mips64r2";
+case MIPS_ISA_MIPS64R3:
+ return "mips64r3";
+case MIPS_ISA_MIPS64R5:
+ return "mips64r5";
+case MIPS_ISA_MIPS64R6:
+ return "mips64r6";
+default:
+ gcc_unreachable ();
+}
+}
+
/* Implement TARGET_ASM_FILE_START. */
static void
@@ -9873,6 +9911,9 @@ mips_file_start (void)
mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
#ifdef HAVE_AS_DOT_MODULE
+ fprintf (asm_out_file, "\t.module\t%s\n",
+ mips_module_isa_name ());
+
/* Record the FP ABI. See below for comments. */
if (TARGET_NO_FLOAT)
#ifdef HAVE_AS_GNU_ATTRIBUTE
--
2.30.2
Re: [PATCH v2] MIPS: add .module mipsREV to all output asm file
Please ignore this post, as I mistakenly used -1 instead of -2.
YunQiang Su 于2021年8月30日周一 上午10:57写道：
>
> Currently, the asm output file for MIPS has no rev info.
> It can make some trouble, for example:
> assembler is mips1 by default,
> gcc is fpxx by default.
> To assemble the output of gcc -S, we have to pass -mips2
> to assembler.
>
> gcc/ChangeLog:
>
> * gcc/config/mips/mips.c (mips_module_isa_name): New.
> mips_file_start: add .module mipsREV to all asm output
> ---
> gcc/config/mips/mips.c | 41 +
> 1 file changed, 41 insertions(+)
>
> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
> index 493d3de48..a7087ec0a 100644
> --- a/gcc/config/mips/mips.c
> +++ b/gcc/config/mips/mips.c
> @@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
> }
> }
>
> +static const char *
> +mips_module_isa_name ()
> +{
> + switch (mips_isa)
> +{
> +case MIPS_ISA_MIPS1:
> + return "mips1";
> +case MIPS_ISA_MIPS2:
> + return "mips2";
> +case MIPS_ISA_MIPS3:
> + return "mips3";
> +case MIPS_ISA_MIPS4:
> + return "mips4";
> +case MIPS_ISA_MIPS32:
> + return "mips32";
> +case MIPS_ISA_MIPS32R2:
> + return "mips32r2";
> +case MIPS_ISA_MIPS32R3:
> + return "mips32r3";
> +case MIPS_ISA_MIPS32R5:
> + return "mips32r5";
> +case MIPS_ISA_MIPS32R6:
> + return "mips32r6";
> +case MIPS_ISA_MIPS64:
> + return "mips64";
> +case MIPS_ISA_MIPS64R2:
> + return "mips64r2";
> +case MIPS_ISA_MIPS64R3:
> + return "mips64r3";
> +case MIPS_ISA_MIPS64R5:
> + return "mips64r5";
> +case MIPS_ISA_MIPS64R6:
> + return "mips64r6";
> +default:
> + gcc_unreachable ();
> +}
> +}
> +
> /* Implement TARGET_ASM_FILE_START. */
>
> static void
> @@ -9873,6 +9911,9 @@ mips_file_start (void)
> mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
>
> #ifdef HAVE_AS_DOT_MODULE
> + fprintf (asm_out_file, "\t.module\t%s\n",
> + mips_module_isa_name ());
> +
>/* Record the FP ABI. See below for comments. */
>if (TARGET_NO_FLOAT)
> #ifdef HAVE_AS_GNU_ATTRIBUTE
> --
> 2.30.2
>
[PATCH v2 1/2] MIPS: use mips_isa enum instead hardcoded numbers
Currently mips-cpu.defs, mips.h, netbsd.h and config.gcc are
using hardcoded numbers for isa level.
Let's replace them with more readable enum mips_isa.
gcc/ChangeLog:
* config/mips/mips.h (struct mips_cpu_info): define enum mips_isa;
use enum instead of int for 'isa' member.
* config/config.gcc, config/mips/mips{.h,-cpus.def},
config/mips/netbsd.h: replace hardcoded numbers with enum.
---
gcc/config.gcc| 62 -
gcc/config/mips/mips-cpus.def | 228 +-
gcc/config/mips/mips.c| 5 +-
gcc/config/mips/mips.h| 84 -
gcc/config/mips/netbsd.h | 5 +-
5 files changed, 203 insertions(+), 181 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0c91be6f3..0eba332bd 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2512,7 +2512,7 @@ mips*-img-linux*)
tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h
glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h
mips/mti-linux.h"
extra_options="${extra_options} linux-android.opt"
tmake_file="${tmake_file} mips/t-img-linux"
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r6"
with_arch_64="mips64r6"
gnu_ld=yes
@@ -2522,7 +2522,7 @@ mips*-mti-linux*)
tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h
glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h
mips/mti-linux.h"
extra_options="${extra_options} linux-android.opt"
tmake_file="${tmake_file} mips/t-mti-linux"
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r2"
with_arch_64="mips64r2"
gnu_ld=yes
@@ -2592,14 +2592,14 @@ mips*-*-linux*) # Linux MIPS,
either endian.
mips*-mti-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h
mips/sde.h mips/mti-elf.h"
tmake_file="mips/t-mti-elf"
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r2"
with_arch_64="mips64r2"
;;
mips*-img-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h
mips/sde.h mips/mti-elf.h"
tmake_file="mips/t-img-elf"
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6
MIPS_ABI_DEFAULT=ABI_32"
with_arch_32="mips32r6"
with_arch_64="mips64r6"
;;
@@ -2624,22 +2624,22 @@ mips*-sde-elf*)
esac
case ${target} in
mipsisa32r6*)
- tm_defines="MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6
MIPS_ABI_DEFAULT=ABI_32"
;;
mipsisa32r2*)
- tm_defines="MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2
MIPS_ABI_DEFAULT=ABI_32"
;;
mipsisa32*)
- tm_defines="MIPS_ISA_DEFAULT=32 MIPS_ABI_DEFAULT=ABI_32"
+ tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32
MIPS_ABI_DEFAULT=ABI_32"
;;
mipsisa64r6*)
- tm_defines="MIPS_ISA_DEFAULT=69 MIPS_ABI_DEFAULT=ABI_N32"
+ tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6
MIPS_ABI_DEFAULT=ABI_N32"
;;
mipsisa64r2*)
- tm_defines="MIPS_ISA_DEFAULT=65 MIPS_ABI_DEFAULT=ABI_N32"
+ tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2
MIPS_ABI_DEFAULT=ABI_N32"
;;
mipsisa64*)
- tm_defines="MIPS_ISA_DEFAULT=64 MIPS_ABI_DEFAULT=ABI_N32"
+ tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64
MIPS_ABI_DEFAULT=ABI_N32"
;;
esac
;;
@@ -2653,22 +2653,22 @@ mipsisa64r6-*-elf* | mipsisa64r6el-*-elf*)
tmake_file="mips/t-isa3264"
case ${target} in
mipsisa32r6*)
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6"
;;
mipsisa32r2*)
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2"
;;
mipsisa32*)
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=32"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32"
;;
mipsisa64r6*)
- tm_defines="${tm_defines} MIPS_ISA_DEFAULT=69"
+ tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6"
;;
mipsis
[PATCH v2 2/2] MIPS: add .module mipsREV to all output asm file
Currently, the asm output file for MIPS has no rev info.
It can make some trouble, for example:
assembler is mips1 by default,
gcc is fpxx by default.
To assemble the output of gcc -S, we have to pass -mips2
to assembler.
gcc/ChangeLog:
* gcc/config/mips/mips.c (mips_module_isa_name): New.
mips_file_start: add .module mipsREV to all asm output
---
gcc/config/mips/mips.c | 41 +
1 file changed, 41 insertions(+)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 493d3de48..a7087ec0a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -9841,6 +9841,44 @@ mips_mdebug_abi_name (void)
}
}
+static const char *
+mips_module_isa_name ()
+{
+ switch (mips_isa)
+{
+case MIPS_ISA_MIPS1:
+ return "mips1";
+case MIPS_ISA_MIPS2:
+ return "mips2";
+case MIPS_ISA_MIPS3:
+ return "mips3";
+case MIPS_ISA_MIPS4:
+ return "mips4";
+case MIPS_ISA_MIPS32:
+ return "mips32";
+case MIPS_ISA_MIPS32R2:
+ return "mips32r2";
+case MIPS_ISA_MIPS32R3:
+ return "mips32r3";
+case MIPS_ISA_MIPS32R5:
+ return "mips32r5";
+case MIPS_ISA_MIPS32R6:
+ return "mips32r6";
+case MIPS_ISA_MIPS64:
+ return "mips64";
+case MIPS_ISA_MIPS64R2:
+ return "mips64r2";
+case MIPS_ISA_MIPS64R3:
+ return "mips64r3";
+case MIPS_ISA_MIPS64R5:
+ return "mips64r5";
+case MIPS_ISA_MIPS64R6:
+ return "mips64r6";
+default:
+ gcc_unreachable ();
+}
+}
+
/* Implement TARGET_ASM_FILE_START. */
static void
@@ -9873,6 +9911,9 @@ mips_file_start (void)
mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
#ifdef HAVE_AS_DOT_MODULE
+ fprintf (asm_out_file, "\t.module\t%s\n",
+ mips_module_isa_name ());
+
/* Record the FP ABI. See below for comments. */
if (TARGET_NO_FLOAT)
#ifdef HAVE_AS_GNU_ATTRIBUTE
--
2.30.2
[PATCH] Set bound/cmp/control for until wrap loop.
Hi,
In patch r12-3136, niter->control, niter->bound and niter->cmp are
derived from number_of_iterations_lt. While for 'until wrap condition',
the calculation in number_of_iterations_lt is not align the requirements
on the define of them and requirements in determine_exit_conditions.
This patch calculate niter->control, niter->bound and niter->cmp in
number_of_iterations_until_wrap.
The ICEs in the PR are pass with this patch.
Bootstrap and reg-tests pass on ppc64/ppc64le and x86.
Is this ok for trunk?
BR.
Jiufu Guo
---
gcc/tree-ssa-loop-niter.c | 14 +-
gcc/testsuite/gcc.dg/pr102087.c| 25 +
gcc/testsuite/gcc.dg/vect/pr101145_3.c | 4 +++-
3 files changed, 41 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr102087.c
diff --git a/gcc/tree-ssa-loop-niter.c b/gcc/tree-ssa-loop-niter.c
index 7af92d1c893..747f04d3ce0 100644
--- a/gcc/tree-ssa-loop-niter.c
+++ b/gcc/tree-ssa-loop-niter.c
@@ -1482,7 +1482,7 @@ number_of_iterations_until_wrap (class loop *, tree type,
affine_iv *iv0,
affine_iv *iv1, class tree_niter_desc *niter)
{
tree niter_type = unsigned_type_for (type);
- tree step, num, assumptions, may_be_zero;
+ tree step, num, assumptions, may_be_zero, span;
wide_int high, low, max, min;
may_be_zero = fold_build2 (LE_EXPR, boolean_type_node, iv1->base, iv0->base);
@@ -1513,6 +1513,8 @@ number_of_iterations_until_wrap (class loop *, tree type,
affine_iv *iv0,
low = wi::to_wide (iv0->base);
else
low = min;
+
+ niter->control = *iv1;
}
/* {base, -C} < n. */
else if (tree_int_cst_sign_bit (iv0->step) && integer_zerop (iv1->step))
@@ -1533,6 +1535,8 @@ number_of_iterations_until_wrap (class loop *, tree type,
affine_iv *iv0,
high = wi::to_wide (iv1->base);
else
high = max;
+
+ niter->control = *iv0;
}
else
return false;
@@ -1556,6 +1560,14 @@ number_of_iterations_until_wrap (class loop *, tree
type, affine_iv *iv0,
niter->assumptions, assumptions);
niter->control.no_overflow = false;
+ niter->control.base = fold_build2 (MINUS_EXPR, niter_type,
+niter->control.base, niter->control.step);
+ span = fold_build2 (MULT_EXPR, niter_type, niter->niter,
+ fold_convert (niter_type, niter->control.step));
+ niter->bound = fold_build2 (PLUS_EXPR, niter_type, span,
+ fold_convert (niter_type, niter->control.base));
+ niter->bound = fold_convert (type, niter->bound);
+ niter->cmp = NE_EXPR;
return true;
}
diff --git a/gcc/testsuite/gcc.dg/pr102087.c b/gcc/testsuite/gcc.dg/pr102087.c
new file mode 100644
index 000..ef1f9f5cba9
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr102087.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+unsigned __attribute__ ((noinline))
+foo (int *__restrict__ a, int *__restrict__ b, unsigned l, unsigned n)
+{
+ while (n < ++l)
+*a++ = *b++ + 1;
+ return l;
+}
+
+volatile int a[1];
+unsigned b;
+int c;
+
+int
+check ()
+{
+ int d;
+ for (; b > 1; b++)
+for (c = 0; c < 2; c++)
+ for (d = 0; d < 2; d++)
+ a[0];
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/vect/pr101145_3.c
b/gcc/testsuite/gcc.dg/vect/pr101145_3.c
index 99289afec0b..40cb0240aaa 100644
--- a/gcc/testsuite/gcc.dg/vect/pr101145_3.c
+++ b/gcc/testsuite/gcc.dg/vect/pr101145_3.c
@@ -1,5 +1,6 @@
/* { dg-require-effective-target vect_int } */
/* { dg-options "-O3 -fdump-tree-vect-details" } */
+
#define TYPE int *
#define MIN ((TYPE)0)
#define MAX ((TYPE)((long long)-1))
@@ -10,4 +11,5 @@
#include "pr101145.inc"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
+/* pointer size may not be vectorized, checking niter is ok. */
+/* { dg-final { scan-tree-dump "Symbolic number of iterations is" "vect" } } */
--
2.17.1
Re: [Patch v2] C, C++, Fortran, OpenMP: Add support for device-modifiers for 'omp target device'
On Wed, Aug 25, 2021 at 12:14:09PM +0200, Marcel Vollweiler wrote: > Add support for device-modifiers for 'omp target device'. > > 'device_num' and 'ancestor' are now parsed on target device constructs for C, > C++, and Fortran (see OpenMP specification 5.0, p. 170). When 'ancestor' is > used, then 'sorry, not supported' is output. Moreover, the restrictions for > 'ancestor' are implemented (see OpenMP specification 5.0, p. 174f). > > gcc/c/ChangeLog: > > * c-parser.c (c_parser_omp_clause_device): Parse device-modifiers > 'device_num' > and 'ancestor' in 'target device' clauses. > > gcc/cp/ChangeLog: > > * parser.c (cp_parser_omp_clause_device): Parse device-modifiers > 'device_num' > and 'ancestor' in 'target device' clauses. > * semantics.c (finish_omp_clauses): Error handling. Constant device ids > must > evaluate to '1' if 'ancestor' is used. > > gcc/fortran/ChangeLog: > > * gfortran.h: Add variable for 'ancestor' in struct gfc_omp_clauses. > * openmp.c (gfc_match_omp_clauses): Parse device-modifiers 'device_num' > and 'ancestor' in 'target device' clauses. > * trans-openmp.c (gfc_trans_omp_clauses): Set > OMP_CLAUSE_DEVICE_ANCESTOR. > > gcc/ChangeLog: > > * gimplify.c (gimplify_scan_omp_clauses): Error handling. 'ancestor' > only > allowed on target constructs and only with particular other clauses. > * omp-expand.c (expand_omp_target): Output of 'sorry, not supported' if > 'ancestor' is used. > * omp-low.c (check_omp_nesting_restrictions): Error handling. No nested > OpenMP > structs when 'ancestor' is used. > (scan_omp_1_stmt): No usage of OpenMP runtime routines in a target > region when > 'ancestor' is used. > * tree-pretty-print.c (dump_omp_clause): Append 'ancestor'. > * tree.h (OMP_CLAUSE_DEVICE_ANCESTOR): Define macro. > > gcc/testsuite/ChangeLog: > > * c-c++-common/gomp/target-device-1.c: New test. > * c-c++-common/gomp/target-device-2.c: New test. > * c-c++-common/gomp/target-device-ancestor-1.c: New test. > * c-c++-common/gomp/target-device-ancestor-2.c: New test. > * c-c++-common/gomp/target-device-ancestor-3.c: New test. > * c-c++-common/gomp/target-device-ancestor-4.c: New test. > * gfortran.dg/gomp/target-device-1.f90: New test. > * gfortran.dg/gomp/target-device-2.f90: New test. > * gfortran.dg/gomp/target-device-ancestor-1.f90: New test. > * gfortran.dg/gomp/target-device-ancestor-2.f90: New test. > * gfortran.dg/gomp/target-device-ancestor-3.f90: New test. > * gfortran.dg/gomp/target-device-ancestor-4.f90: New test. Ok, thanks. Jakub
Re: [RFH] ME optimizes variable assignment away / Fortran bind(C) descriptor conversion
On Sun, Aug 29, 2021 at 10:07 AM Tobias Burnus wrote:
>
> Hi all, hi Richard,
>
> On 27.08.21 21:48, Richard Biener wrote:
> >> It looks really nice with "-O1 -fno-inline" :-)
> >>The callee 'rank_p()' is mostly optimized and in the
> >>caller only those struct elements are set, which are used:
> >>
> >> integer(kind=4) rank_p (struct CFI_cdesc_t & _this)
> >> {
> >>_1 = _this_11(D)->base_addr;
> >>_2 = _this_11(D)->rank;
> >> ...
> >>rnk_13 = (integer(kind=4)) _2;
> >>return rnk_13;
> >> }
> >>
> >> void selr_p ()
> >> {
> >> ...
> >>struct CFI_cdesc_t01 cfi.7;
> >> ...
> >> [local count: 537730764]:
> >>cfi.7.rank = 1;
> >>cfi.7.base_addr = 0B;
> > You need to do the accesses above using the generic 't' type as well,
> > otherwise they are non-conflicting TBAA wise.
>
> First, I wonder why the following works with C:
>
> struct gen_t { int n; int dim[]; }
>
> int f (struct gen_t *x) {
> if (x->n > 1) x->dim[0] = 5;
> return x->n;
> }
>
> void test() {
> struct { int n; int dim[2]; } y;
> y.n = 2;
> f ((struct gen_t*) &y);
> }
>
> Or doesn't it?
It probably doesn't and suffers from the same issue as your
original fortran code.
>In any case, that's how it is suggested
> and 'y.n' is not accessed using 'gen_t' – there is only
> a cast in the function call. (Which is not sufficient
> in the Fortran FE-code generated code – as tried)
>
> * * *
>
> Otherwise, I can confirm that the following works.
> Does this original dump now looks fine?
>
> struct CFI_cdesc_t01 cfi.2;
> ...
> ((struct CFI_cdesc_t *) &cfi.2)->version = 1;
> ((struct CFI_cdesc_t *) &cfi.2)->rank = 1;
> ((struct CFI_cdesc_t *) &cfi.2)->type = 1025;
> ((struct CFI_cdesc_t *) &cfi.2)->attribute = 0;
> ((struct CFI_cdesc_t *) &cfi.2)->base_addr = intp.data;
> ((struct CFI_cdesc_t *) &cfi.2)->elem_len = 4;
> ...
> irnk = rank_p ((struct CFI_cdesc_t *) &cfi.2);
Yes, that looks OK now. The idea is you can use the complete
types for storage allocation but you _always_ have to use the
incomplete (with flexarray member) type for all accesses.
Richard.
> Thanks,
>
> Tobias
>
> -
> Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634
> München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas
> Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht
> München, HRB 106955
Re: [PATCH] Set bound/cmp/control for until wrap loop.
On 2021-08-30 14:15, Jiufu Guo wrote:
Hi,
In patch r12-3136, niter->control, niter->bound and niter->cmp are
derived from number_of_iterations_lt. While for 'until wrap
condition',
the calculation in number_of_iterations_lt is not align the
requirements
on the define of them and requirements in determine_exit_conditions.
This patch calculate niter->control, niter->bound and niter->cmp in
number_of_iterations_until_wrap.
The ICEs in the PR are pass with this patch.
Bootstrap and reg-tests pass on ppc64/ppc64le and x86.
Is this ok for trunk?
BR.
Jiufu Guo
Add ChangeLog:
gcc/ChangeLog:
2021-08-30 Jiufu Guo
PR tree-optimization/102087
* tree-ssa-loop-niter.c (number_of_iterations_until_wrap):
Set bound/cmp/control for niter.
gcc/testsuite/ChangeLog:
2021-08-30 Jiufu Guo
PR tree-optimization/102087
* gcc.dg/vect/pr101145_3.c: Update tests.
* gcc.dg/pr102087.c: New test.
---
gcc/tree-ssa-loop-niter.c | 14 +-
gcc/testsuite/gcc.dg/pr102087.c| 25 +
gcc/testsuite/gcc.dg/vect/pr101145_3.c | 4 +++-
3 files changed, 41 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr102087.c
diff --git a/gcc/tree-ssa-loop-niter.c b/gcc/tree-ssa-loop-niter.c
index 7af92d1c893..747f04d3ce0 100644
--- a/gcc/tree-ssa-loop-niter.c
+++ b/gcc/tree-ssa-loop-niter.c
@@ -1482,7 +1482,7 @@ number_of_iterations_until_wrap (class loop *,
tree type, affine_iv *iv0,
affine_iv *iv1, class tree_niter_desc *niter)
{
tree niter_type = unsigned_type_for (type);
- tree step, num, assumptions, may_be_zero;
+ tree step, num, assumptions, may_be_zero, span;
wide_int high, low, max, min;
may_be_zero = fold_build2 (LE_EXPR, boolean_type_node, iv1->base,
iv0->base);
@@ -1513,6 +1513,8 @@ number_of_iterations_until_wrap (class loop *,
tree type, affine_iv *iv0,
low = wi::to_wide (iv0->base);
else
low = min;
+
+ niter->control = *iv1;
}
/* {base, -C} < n. */
else if (tree_int_cst_sign_bit (iv0->step) && integer_zerop
(iv1->step))
@@ -1533,6 +1535,8 @@ number_of_iterations_until_wrap (class loop *,
tree type, affine_iv *iv0,
high = wi::to_wide (iv1->base);
else
high = max;
+
+ niter->control = *iv0;
}
else
return false;
@@ -1556,6 +1560,14 @@ number_of_iterations_until_wrap (class loop *,
tree type, affine_iv *iv0,
niter->assumptions, assumptions);
niter->control.no_overflow = false;
+ niter->control.base = fold_build2 (MINUS_EXPR, niter_type,
+niter->control.base, niter->control.step);
+ span = fold_build2 (MULT_EXPR, niter_type, niter->niter,
+ fold_convert (niter_type, niter->control.step));
+ niter->bound = fold_build2 (PLUS_EXPR, niter_type, span,
+ fold_convert (niter_type, niter->control.base));
+ niter->bound = fold_convert (type, niter->bound);
+ niter->cmp = NE_EXPR;
return true;
}
diff --git a/gcc/testsuite/gcc.dg/pr102087.c
b/gcc/testsuite/gcc.dg/pr102087.c
new file mode 100644
index 000..ef1f9f5cba9
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr102087.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+unsigned __attribute__ ((noinline))
+foo (int *__restrict__ a, int *__restrict__ b, unsigned l, unsigned n)
+{
+ while (n < ++l)
+*a++ = *b++ + 1;
+ return l;
+}
+
+volatile int a[1];
+unsigned b;
+int c;
+
+int
+check ()
+{
+ int d;
+ for (; b > 1; b++)
+for (c = 0; c < 2; c++)
+ for (d = 0; d < 2; d++)
+ a[0];
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/vect/pr101145_3.c
b/gcc/testsuite/gcc.dg/vect/pr101145_3.c
index 99289afec0b..40cb0240aaa 100644
--- a/gcc/testsuite/gcc.dg/vect/pr101145_3.c
+++ b/gcc/testsuite/gcc.dg/vect/pr101145_3.c
@@ -1,5 +1,6 @@
/* { dg-require-effective-target vect_int } */
/* { dg-options "-O3 -fdump-tree-vect-details" } */
+
#define TYPE int *
#define MIN ((TYPE)0)
#define MAX ((TYPE)((long long)-1))
@@ -10,4 +11,5 @@
#include "pr101145.inc"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } }
*/
+/* pointer size may not be vectorized, checking niter is ok. */
+/* { dg-final { scan-tree-dump "Symbolic number of iterations is"
"vect" } } */
Re: [committed] Reduce vector comparison of uniform vectors to a scalar comparison
On Fri, Aug 27, 2021 at 9:31 PM Jeff Law via Gcc-patches
wrote:
>
>
> I was working some aspects of our port's vector support and stumbled
> across a bit of silly code. We were comparing two vectors that were
> both uniform.
>
> We can simplify a comparison of uniform vectors to a comparison of a
> representative element from each. That in turn may expose const/copy
> propagation opportunities or even jump threading opportunities.
>
> And that's precisely what this patch does inside DOM. At the start of
> statement processing we see if we can reduce a vector comparison to a
> scalar comparison.
>
> You can see this in pr95308.C on x86. As we enter dom3 we have:
>
>
> ;; basic block 2, loop depth 0
> ;;pred: ENTRY
>e.1_1 = e;
>_27 = f_26(D) != 0;
>_163 = e.1_1 != 0;
>_164 = _27 & _163;
>_196 = _164 ? -1 : 0;
>vect_cst__194 = {_196, _196, _196, _196, _196, _196, _196, _196};
>
> [ ... ]
>
> ;; basic block 8, loop depth 1
> ;;pred: 7
> ;;6
>if (vect_cst__194 == { 0, 0, 0, 0, 0, 0, 0, 0 })
> goto ; [100.00%]
>else
> goto ; [20.00%]
> ;;succ: 10
> ;;9
>
>
> There's another similar comparison later. We transform the comparison into:
>
> ;; basic block 8, loop depth 1
> ;;pred: 7
> ;;6
>if (_196 == 0)
> goto ; [100.00%]
>else
> goto ; [20.00%]
> ;;succ: 13
> ;;9
>
> There's nice secondary effects that show up after the transformation as
> well.
It's an interesting case indeed, but I think a match.pd rule would have
been better to address this. Sth like
(for cmp (eq ne)
(simplify
(cmp vec_same_elem_p@0 vec_same_elem_p@1)
(if (INTEGRAL_TYPE_P (type)
&& (TREE_CODE (type) == BOOLEAN_TYPE
|| TYPE_PRECISION (type) == 1))
(cmp { uniform_vector_p (@0); } { uniform_vector_p (@1); }
should do the trick. That makes the transform available to more places
(and DOM should also pick it up this way).
Richard.
>
> Bootstrapped and regression tested on x86_64. It'll go through the
> rest of the public targets as well as our internal port over the next
> 24-48 hrs.
>
>
> Committed to the trunk,
>
> Jeff
Re: [PATCH v2 1/2] MIPS: use mips_isa enum instead hardcoded numbers
These two patches look good to me. Still, need a maintainer's approval.
On Sun, 2021-08-29 at 22:59 -0400, YunQiang Su wrote:
> Currently mips-cpu.defs, mips.h, netbsd.h and config.gcc are
> using hardcoded numbers for isa level.
>
> Let's replace them with more readable enum mips_isa.
>
> gcc/ChangeLog:
> * config/mips/mips.h (struct mips_cpu_info): define enum mips_isa;
> use enum instead of int for 'isa' member.
> * config/config.gcc, config/mips/mips{.h,-cpus.def},
> config/mips/netbsd.h: replace hardcoded numbers with enum.
> ---
> gcc/config.gcc | 62 -
> gcc/config/mips/mips-cpus.def | 228 +-
> gcc/config/mips/mips.c | 5 +-
> gcc/config/mips/mips.h | 84 -
> gcc/config/mips/netbsd.h | 5 +-
> 5 files changed, 203 insertions(+), 181 deletions(-)
