Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626
Thank you Richard, Made the required changes ,ok to commit ? Thank you ~Umesh On Thu, Nov 15, 2018 at 4:02 PM Richard Biener wrote: > > On Thu, Nov 15, 2018 at 10:02 AM Umesh Kalappa > wrote: > > > > Hi All, > > > > The attached patch (pr85667.patch) fixes the subjected issue . > > we tested on x86_64(linux and windows both) and no regress found . > > > > ok to commit ? > > I wonder if you can turn the testcase into a dg-run one, making the > functions noinline/noipa and check the correct values are returned. > > Richard. > > > Thank you > > ~Umesh
[PATCH] Reject too large string literals (PR middle-end/87854)
Hi!
Both C and C++ FE diagnose arrays larger than half of the address space:
/tmp/1.c:1:6: error: size of array ‘a’ is too large
char a[__SIZE_MAX__ / 2 + 1];
^
because one can't do pointer arithmetics on them. But we don't have
anything similar for string literals. As internally we use host int
as TREE_STRING_LENGTH, this is relevant to targets that have < 32-bit
size_t only.
The following patch adds that diagnostics and truncates the string literals.
Bootstrapped/regtested on x86_64-linux and i686-linux and tested with
a cross to avr. I'll defer adjusting testcases to the maintainers of 16-bit
ports. From the PR it seems gcc.dg/concat2.c, g++.dg/parse/concat1.C and
pr46534.c tests are affected.
Ok for trunk?
2018-11-16 Jakub Jelinek
PR middle-end/87854
* c-common.c (fix_string_type): Reject string literals larger than
TYPE_MAX_VALUE (ssizetype) bytes.
--- gcc/c-family/c-common.c.jj 2018-11-14 13:37:46.921050615 +0100
+++ gcc/c-family/c-common.c 2018-11-15 15:20:31.138056115 +0100
@@ -737,31 +737,44 @@ tree
fix_string_type (tree value)
{
int length = TREE_STRING_LENGTH (value);
- int nchars;
+ int nchars, charsz;
tree e_type, i_type, a_type;
/* Compute the number of elements, for the array type. */
if (TREE_TYPE (value) == char_array_type_node || !TREE_TYPE (value))
{
- nchars = length;
+ charsz = 1;
e_type = char_type_node;
}
else if (TREE_TYPE (value) == char16_array_type_node)
{
- nchars = length / (TYPE_PRECISION (char16_type_node) / BITS_PER_UNIT);
+ charsz = TYPE_PRECISION (char16_type_node) / BITS_PER_UNIT;
e_type = char16_type_node;
}
else if (TREE_TYPE (value) == char32_array_type_node)
{
- nchars = length / (TYPE_PRECISION (char32_type_node) / BITS_PER_UNIT);
+ charsz = TYPE_PRECISION (char32_type_node) / BITS_PER_UNIT;
e_type = char32_type_node;
}
else
{
- nchars = length / (TYPE_PRECISION (wchar_type_node) / BITS_PER_UNIT);
+ charsz = TYPE_PRECISION (wchar_type_node) / BITS_PER_UNIT;
e_type = wchar_type_node;
}
+ /* This matters only for targets where ssizetype has smaller precision
+ than 32 bits. */
+ if (wi::lts_p (wi::to_wide (TYPE_MAX_VALUE (ssizetype)), length))
+{
+ error ("size of string literal is too large");
+ length = tree_to_shwi (TYPE_MAX_VALUE (ssizetype)) / charsz * charsz;
+ char *str = CONST_CAST (char *, TREE_STRING_POINTER (value));
+ memset (str + length, '\0',
+ MIN (TREE_STRING_LENGTH (value) - length, charsz));
+ TREE_STRING_LENGTH (value) = length;
+}
+ nchars = length / charsz;
+
/* C89 2.2.4.1, C99 5.2.4.1 (Translation limits). The analogous
limit in C++98 Annex B is very large (65536) and is not normative,
so we do not diagnose it (warn_overlength_strings is forced off
Jakub
[PATCH] Fix expand_binop (PR middle-end/88032)
Hi!
On Wed, Nov 14, 2018 at 09:35:30AM -0700, Jeff Law wrote:
> + * optabs.c (expand_binop): Pass INT_MODE to operand_subword_force
> + iff the operand is a constant.
This broke gcc.target/i386/pr80173.c testcase. The problem is
that while operand_subword handles VOIDmode last argument just fine
by using GET_MODE (op), so it is only important to use non-VOIDmode if
op has VOIDmode. But, operand_subword_force actually has a different
behavior, if mode is VOIDmode (or BLKmode), it acts just as operand_subword
followed by assertion that it succeeded, rather than by trying to deal with
failed operand_subword by forcing it into a pseudo.
In the testcase, op is a hard register, on which operand_subword fails, but
if it is forced into pseudo, it succeeds.
The following patch arranges it by never passing VOIDmode to
operand_subword_force, pass int_mode as previously if opN has VOIDmode, but
instead of passing VOIDmode otherwise pass the actual mode of the opN
operand.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2018-11-16 Jakub Jelinek
PR middle-end/88032
* optabs.c (expand_binop): For op0_mode use GET_MODE (op0), unless it
is VOIDmode, in which case use int_mode. Similarly for op1_mode.
--- gcc/optabs.c.jj 2018-11-14 17:42:53.044049213 +0100
+++ gcc/optabs.c2018-11-15 15:45:35.949378049 +0100
@@ -1377,8 +1377,12 @@ expand_binop (machine_mode mode, optab b
start_sequence ();
/* Do the actual arithmetic. */
- enum machine_mode op0_mode = CONSTANT_P (op0) ? int_mode : VOIDmode;
- enum machine_mode op1_mode = CONSTANT_P (op1) ? int_mode : VOIDmode;
+ enum machine_mode op0_mode = GET_MODE (op0);
+ enum machine_mode op1_mode = GET_MODE (op1);
+ if (op0_mode == VOIDmode)
+ op0_mode = int_mode;
+ if (op1_mode == VOIDmode)
+ op1_mode = int_mode;
for (i = 0; i < GET_MODE_BITSIZE (int_mode) / BITS_PER_WORD; i++)
{
rtx target_piece = operand_subword (target, i, 1, int_mode);
Jakub
[PATCH] Allow giving up when redirecting a CROSSING_JUMP_P (PR rtl-optimization/87475)
Hi!
On this testcase on aarch64-linux, we have a bb end like:
(insn 119 80 120 5 (set (reg:DI 110)
(high:DI (label_ref:DI 19))) -1
(insn_list:REG_LABEL_OPERAND 19 (nil)))
(insn 120 119 121 5 (set (reg:DI 109)
(lo_sum:DI (reg:DI 110)
(label_ref:DI 19))) -1
(insn_list:REG_LABEL_OPERAND 19 (expr_list:REG_EQUAL (label_ref:DI 19)
(nil
(jump_insn/j 121 120 19 5 (set (pc)
(reg:DI 109)) -1
(nil)
-> 19)
and try to redirect that CROSSING_JUMP_P to another label. As it is not
considered a computed jump (as it has a JUMP_LABEL), but it is hard to
adjust it (we'd need to generate new insns to compute that label into a
register and replace the old ones with it (and find them)), redirect_jump
fails, but patch_jump_insn assumes it must not fail.
I think it is best to allow it to fail, at least until somebody writes code
to redirect_jump even this kind of calls.
Bootstrapped/regtested on x86_64-linux and i686-linux + tested with
aarch64-linux cross on the testcase. Ok for trunk?
2018-11-16 Jakub Jelinek
PR rtl-optimization/87475
* cfgrtl.c (patch_jump_insn): Allow redirection failure for
CROSSING_JUMP_P insns.
(cfg_layout_redirect_edge_and_branch): Don't ICE if ret is NULL.
* g++.dg/opt/pr87475.C: New test.
--- gcc/cfgrtl.c.jj 2018-11-15 09:46:46.383739915 +0100
+++ gcc/cfgrtl.c2018-11-15 16:58:08.972980656 +0100
@@ -1268,11 +1268,13 @@ patch_jump_insn (rtx_insn *insn, rtx_ins
/* If the substitution doesn't succeed, die. This can happen
if the back end emitted unrecognizable instructions or if
-target is exit block on some arches. */
+target is exit block on some arches. Or for crossing
+jumps. */
if (!redirect_jump (as_a (insn),
block_label (new_bb), 0))
{
- gcc_assert (new_bb == EXIT_BLOCK_PTR_FOR_FN (cfun));
+ gcc_assert (new_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
+ || CROSSING_JUMP_P (insn));
return false;
}
}
@@ -4460,6 +4462,9 @@ cfg_layout_redirect_edge_and_branch (edg
else
ret = redirect_branch_edge (e, dest);
+ if (!ret)
+return NULL;
+
fixup_partition_crossing (ret);
/* We don't want simplejumps in the insn stream during cfglayout. */
gcc_assert (!simplejump_p (BB_END (src)) || CROSSING_JUMP_P (BB_END (src)));
--- gcc/testsuite/g++.dg/opt/pr87475.C.jj 2018-11-15 17:05:51.793393450
+0100
+++ gcc/testsuite/g++.dg/opt/pr87475.C 2018-11-15 17:05:34.713673436 +0100
@@ -0,0 +1,7 @@
+// PR rtl-optimization/87475
+// { dg-do compile { target freorder } }
+// { dg-options "-O2 -freorder-blocks-and-partition -fmodulo-sched" }
+
+struct A { A (); ~A (); };
+int foo (A, A);
+void bar (bool x) { x ? foo (A (), A ()) : 0; }
Jakub
[C++ PATCH] Don't incorrectly reject {un,}signed char constexpr array initialization in templates (PR c++/87476)
Hi!
The following two testcases, one is a regression from GCC 8 (introduced by
the constructor to STRING_CST optimization), the other seems to fail since
C++11 support has been introduced (but is accepted by clang++) fail,
because during parsing with processing_template_decl we end up with creating
a STRING_CST with type of {un,}signed char array and later during
instantiation digest_init_r rejects it, because it already has such a type
rather than what it expects (char array) and bogusly complains that it is a
wide string.
The following patch fixes that.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2018-11-16 Jakub Jelinek
PR c++/87476
* typeck2.c (digest_init_r): Re-add handing of signed/unsigned char
strings and add it to the initialization of wide array from non-wide
string diagnostics too.
* g++.dg/cpp0x/pr87476-1.C: New test.
* g++.dg/cpp0x/pr87476-2.C: New test.
--- gcc/cp/typeck2.c.jj 2018-09-25 15:14:43.961258143 +0200
+++ gcc/cp/typeck2.c2018-11-15 22:04:46.723230224 +0100
@@ -1063,7 +1063,9 @@ digest_init_r (tree type, tree init, int
if (TYPE_PRECISION (typ1) == BITS_PER_UNIT)
{
- if (char_type != char_type_node)
+ if (char_type != char_type_node
+ && char_type != signed_char_type_node
+ && char_type != unsigned_char_type_node)
{
if (complain & tf_error)
error_at (loc, "char-array initialized from wide string");
@@ -1072,7 +1074,9 @@ digest_init_r (tree type, tree init, int
}
else
{
- if (char_type == char_type_node)
+ if (char_type == char_type_node
+ || char_type == signed_char_type_node
+ || char_type == unsigned_char_type_node)
{
if (complain & tf_error)
error_at (loc,
--- gcc/testsuite/g++.dg/cpp0x/pr87476-1.C.jj 2018-11-15 17:52:13.736758511
+0100
+++ gcc/testsuite/g++.dg/cpp0x/pr87476-1.C 2018-11-15 17:42:03.50280
+0100
@@ -0,0 +1,13 @@
+// PR c++/87476
+// { dg-do compile { target c++11 } }
+
+template
+struct S {
+ void operator () () { constexpr unsigned char p[1] {}; }
+};
+
+void
+foo ()
+{
+ S<0>{} ();
+}
--- gcc/testsuite/g++.dg/cpp0x/pr87476-2.C.jj 2018-11-15 22:06:27.615571180
+0100
+++ gcc/testsuite/g++.dg/cpp0x/pr87476-2.C 2018-11-15 22:06:36.768420670
+0100
@@ -0,0 +1,23 @@
+// PR c++/87476
+// { dg-do compile { target c++11 } }
+
+void f0 () { constexpr char p[] = "1"; }
+void f1 () { constexpr unsigned char p[] = "1"; }
+void f2 () { constexpr signed char p[] = "1"; }
+template
+void f3 () { constexpr char p[] = "1"; }
+template
+void f4 () { constexpr unsigned char p[] = "1"; }
+template
+void f5 () { constexpr signed char p[] = "1"; }
+
+void
+baz ()
+{
+ f0 ();
+ f1 ();
+ f2 ();
+ f3<0> ();
+ f4<0> ();
+ f5<0> ();
+}
Jakub
Re: [PING #4][PATCH] avoid warning on constant strncpy until next statement is reachable (PR 87028)
On Fri, Nov 16, 2018 at 4:12 AM Martin Sebor wrote:
>
> Ping: https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01818.html
>
> Please let me know if there is something I need to change here
> to make the fix acceptable or if I should stop trying.
I have one more comment about
+ /* Defer warning (and folding) until the next statement in the basic
+ block is reachable. */
+ if (!gimple_bb (stmt))
+return false;
+
it's not about the next statement in the basic-block being "reachable"
(even w/o a CFG you can use gsi_next()) but rather that the next
stmt isn't yet gimplified and thus not inserted into the gimple sequence,
right? You apply this to gimple_fold_builtin_strncpy but I'd rather
see us not sprinkling this over gimple-fold.c but instead do this
in gimplify.c:maybe_fold_stmt, delaying folding until say lowering.
See the attached (untested).
Richard.
> On 10/31/2018 10:33 AM, Martin Sebor wrote:
> > Ping: https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01818.html
> >
> > On 10/20/2018 06:01 PM, Martin Sebor wrote:
> >> On 10/16/2018 03:21 PM, Jeff Law wrote:
> >>> On 10/4/18 9:51 AM, Martin Sebor wrote:
> On 10/04/2018 08:58 AM, Jeff Law wrote:
> > On 8/27/18 9:42 AM, Richard Biener wrote:
> >> On Mon, Aug 27, 2018 at 5:32 PM Jeff Law wrote:
> >>>
> >>> On 08/27/2018 02:29 AM, Richard Biener wrote:
> On Sun, Aug 26, 2018 at 7:26 AM Jeff Law wrote:
> >
> > On 08/24/2018 09:58 AM, Martin Sebor wrote:
> >> The warning suppression for -Wstringop-truncation looks for
> >> the next statement after a truncating strncpy to see if it
> >> adds a terminating nul. This only works when the next
> >> statement can be reached using the Gimple statement iterator
> >> which isn't until after gimplification. As a result, strncpy
> >> calls that truncate their constant argument that are being
> >> folded to memcpy this early get diagnosed even if they are
> >> followed by the nul assignment:
> >>
> >> const char s[] = "12345";
> >> char d[3];
> >>
> >> void f (void)
> >> {
> >> strncpy (d, s, sizeof d - 1); // -Wstringop-truncation
> >> d[sizeof d - 1] = 0;
> >> }
> >>
> >> To avoid the warning I propose to defer folding strncpy to
> >> memcpy until the pointer to the basic block the strnpy call
> >> is in can be used to try to reach the next statement (this
> >> happens as early as ccp1). I'm aware of the preference to
> >> fold things early but in the case of strncpy (a relatively
> >> rarely used function that is often misused), getting
> >> the warning right while folding a bit later but still fairly
> >> early on seems like a reasonable compromise. I fear that
> >> otherwise, the false positives will drive users to adopt
> >> other unsafe solutions (like memcpy) where these kinds of
> >> bugs cannot be as readily detected.
> >>
> >> Tested on x86_64-linux.
> >>
> >> Martin
> >>
> >> PS There still are outstanding cases where the warning can
> >> be avoided. I xfailed them in the test for now but will
> >> still try to get them to work for GCC 9.
> >>
> >> gcc-87028.diff
> >>
> >>
> >> PR tree-optimization/87028 - false positive -Wstringop-truncation
> >> strncpy with global variable source string
> >> gcc/ChangeLog:
> >>
> >> PR tree-optimization/87028
> >> * gimple-fold.c (gimple_fold_builtin_strncpy): Avoid
> >> folding when
> >> statement doesn't belong to a basic block.
> >> * tree-ssa-strlen.c (maybe_diag_stxncpy_trunc): Handle
> >> MEM_REF on
> >> the left hand side of assignment.
> >>
> >> gcc/testsuite/ChangeLog:
> >>
> >> PR tree-optimization/87028
> >> * c-c++-common/Wstringop-truncation.c: Remove xfails.
> >> * gcc.dg/Wstringop-truncation-5.c: New test.
> >>
> >> diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c
> >> index 07341eb..284c2fb 100644
> >> --- a/gcc/gimple-fold.c
> >> +++ b/gcc/gimple-fold.c
> >> @@ -1702,6 +1702,11 @@ gimple_fold_builtin_strncpy
> >> (gimple_stmt_iterator *gsi,
> >>if (tree_int_cst_lt (ssize, len))
> >> return false;
> >>
> >> + /* Defer warning (and folding) until the next statement in the
> >> basic
> >> + block is reachable. */
> >> + if (!gimple_bb (stmt))
> >> +return false;
> > I think you want cfun->cfg as the test here. They should be
> > equivalent
> > in practice.
>
> Please do not add 'cfun' refer
Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626
On Fri, Nov 16, 2018 at 9:07 AM Umesh Kalappa wrote: > > Thank you Richard, > > Made the required changes ,ok to commit ? Can you attach the adjusted patch? Thanks, Richard. > Thank you > ~Umesh > On Thu, Nov 15, 2018 at 4:02 PM Richard Biener > wrote: > > > > On Thu, Nov 15, 2018 at 10:02 AM Umesh Kalappa > > wrote: > > > > > > Hi All, > > > > > > The attached patch (pr85667.patch) fixes the subjected issue . > > > we tested on x86_64(linux and windows both) and no regress found . > > > > > > ok to commit ? > > > > I wonder if you can turn the testcase into a dg-run one, making the > > functions noinline/noipa and check the correct values are returned. > > > > Richard. > > > > > Thank you > > > ~Umesh
Introduce TARGET_VXWORKS_HAVE_CTORS_DTORS
Hello, The support for constructors/destructors on VxWorks evolves and the current distinction between RTP vs kernel mode isn't precise enough any more. The attached patch, originally contributed by Jerome Lambourg for gcc-7, introduces a TARGET_VXWORKS_HAVE_CTORS_DTORS internal macro which allows target ports to state their own setting, propagated to both targetm.have_ctors_dtors and SUPPORTS_INIT_PRIORITY in a synchronized fashion. This helps fix problems we observed on the aarch64 port we're working on without introducing any visible regression in our nightly testing of other ports based on gcc-7. I adapted the patch to mainline, verified that I could build a powerpc-wrs-vxworks compiler and that a constructor attribute still operates as expected for this target, producing a .ctors entry with -mrtp and a specially named (GLOBAL_I) wrapper function otherwise. Olivier 2018-11-16 Jerome Lambourg Olivier Hainque * config/vxworks.h (TARGET_VXWORKS_HAVE_CTORS_DTORS): New macro. Default to TARGET_VXWORKS_RTP. (SUPPORTS_INIT_PRIORITY): Use TARGET_VXWORKS_HAVE_CTORS_DTORS instead of TARGET_VXWORKS_RTP. * config/vxworksae.h: Also define TARGET_VXWORKS_HAVE_CTORS_DTORS. * config/vxworks.c: Use TARGET_VXWORKS_HAVE_CTORS_DTORS instead of TARGET_VXWORKS_RTP to set targetm.have_ctors_dtors. diff --git a/gcc/config/vxworks.c b/gcc/config/vxworks.c index 3b6b234..f0d1974 100644 --- a/gcc/config/vxworks.c +++ b/gcc/config/vxworks.c @@ -145,11 +145,14 @@ vxworks_override_options (void) targetm.emutls.debug_form_tls_address = true; } - /* We can use .ctors/.dtors sections only in RTP mode. But, if the - compiler was built with --enable-initfini-array, assume the - toolchain implements the proper glue to make .init_array and - .fini_array work. */ - targetm.have_ctors_dtors = TARGET_VXWORKS_RTP || HAVE_INITFINI_ARRAY_SUPPORT; + /* Arrange to use .ctors/.dtors sections if the target VxWorks configuration + and mode supports it, or the init/fini_array sections if we were + configured with --enable-initfini-array explicitly. In the latter case, + the toolchain user is expected to provide whatever linker level glue is + required to get things to operate properly. */ + + targetm.have_ctors_dtors = +TARGET_VXWORKS_HAVE_CTORS_DTORS || HAVE_INITFINI_ARRAY_SUPPORT; /* PIC is only supported for RTPs. */ if (flag_pic && !TARGET_VXWORKS_RTP) diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index 2c4c796..156fcc0 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -142,13 +142,18 @@ along with GCC; see the file COPYING3. If not see #define VXWORKS_OVERRIDE_OPTIONS vxworks_override_options () extern void vxworks_override_options (void); -/* RTPs support prioritized constructors and destructors: the - implementation relies on numbered .ctors* sections. If the compiler - was built with --enable-initfini-array, we assume the user uses a - linker script that sorts and merges the .init_array.* sections - appropriately. */ +/* Whether the VxWorks variant and mode supports constructors/destructors + placed in .ctors/.dtors section or if we should generate proxy functions + for them, with special names which munch knows how to collect. On most + versions of VxWorks, only the RTP loader supports .ctors/.dtors sections, + not the kernel module loader. */ +#define TARGET_VXWORKS_HAVE_CTORS_DTORS TARGET_VXWORKS_RTP + +/* Support for prioritized ctors/dtors is in sync with the support for sections + on the VxWorks front, and is assumed to be provided by whatever linker level + glue is required if we were configured with --enable-initfini-array. */ #define SUPPORTS_INIT_PRIORITY \ - (TARGET_VXWORKS_RTP || HAVE_INITFINI_ARRAY_SUPPORT) + (TARGET_VXWORKS_HAVE_CTORS_DTORS || HAVE_INITFINI_ARRAY_SUPPORT) #if !HAVE_INITFINI_ARRAY_SUPPORT /* VxWorks requires special handling of constructors and destructors.
Re: [PATCH] Allow giving up when redirecting a CROSSING_JUMP_P (PR rtl-optimization/87475)
On Fri, Nov 16, 2018 at 9:55 AM Jakub Jelinek wrote:
>
> Hi!
>
> On this testcase on aarch64-linux, we have a bb end like:
> (insn 119 80 120 5 (set (reg:DI 110)
> (high:DI (label_ref:DI 19))) -1
> (insn_list:REG_LABEL_OPERAND 19 (nil)))
> (insn 120 119 121 5 (set (reg:DI 109)
> (lo_sum:DI (reg:DI 110)
> (label_ref:DI 19))) -1
> (insn_list:REG_LABEL_OPERAND 19 (expr_list:REG_EQUAL (label_ref:DI 19)
> (nil
> (jump_insn/j 121 120 19 5 (set (pc)
> (reg:DI 109)) -1
> (nil)
> -> 19)
> and try to redirect that CROSSING_JUMP_P to another label. As it is not
> considered a computed jump (as it has a JUMP_LABEL), but it is hard to
> adjust it (we'd need to generate new insns to compute that label into a
> register and replace the old ones with it (and find them)), redirect_jump
> fails, but patch_jump_insn assumes it must not fail.
>
> I think it is best to allow it to fail, at least until somebody writes code
> to redirect_jump even this kind of calls.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux + tested with
> aarch64-linux cross on the testcase. Ok for trunk?
LGTM.
Richard.
> 2018-11-16 Jakub Jelinek
>
> PR rtl-optimization/87475
> * cfgrtl.c (patch_jump_insn): Allow redirection failure for
> CROSSING_JUMP_P insns.
> (cfg_layout_redirect_edge_and_branch): Don't ICE if ret is NULL.
>
> * g++.dg/opt/pr87475.C: New test.
>
> --- gcc/cfgrtl.c.jj 2018-11-15 09:46:46.383739915 +0100
> +++ gcc/cfgrtl.c2018-11-15 16:58:08.972980656 +0100
> @@ -1268,11 +1268,13 @@ patch_jump_insn (rtx_insn *insn, rtx_ins
>
> /* If the substitution doesn't succeed, die. This can happen
> if the back end emitted unrecognizable instructions or if
> -target is exit block on some arches. */
> +target is exit block on some arches. Or for crossing
> +jumps. */
> if (!redirect_jump (as_a (insn),
> block_label (new_bb), 0))
> {
> - gcc_assert (new_bb == EXIT_BLOCK_PTR_FOR_FN (cfun));
> + gcc_assert (new_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
> + || CROSSING_JUMP_P (insn));
> return false;
> }
> }
> @@ -4460,6 +4462,9 @@ cfg_layout_redirect_edge_and_branch (edg
>else
> ret = redirect_branch_edge (e, dest);
>
> + if (!ret)
> +return NULL;
> +
>fixup_partition_crossing (ret);
>/* We don't want simplejumps in the insn stream during cfglayout. */
>gcc_assert (!simplejump_p (BB_END (src)) || CROSSING_JUMP_P (BB_END
> (src)));
> --- gcc/testsuite/g++.dg/opt/pr87475.C.jj 2018-11-15 17:05:51.793393450
> +0100
> +++ gcc/testsuite/g++.dg/opt/pr87475.C 2018-11-15 17:05:34.713673436 +0100
> @@ -0,0 +1,7 @@
> +// PR rtl-optimization/87475
> +// { dg-do compile { target freorder } }
> +// { dg-options "-O2 -freorder-blocks-and-partition -fmodulo-sched" }
> +
> +struct A { A (); ~A (); };
> +int foo (A, A);
> +void bar (bool x) { x ? foo (A (), A ()) : 0; }
>
> Jakub
[PATCH] Fix PR88053
Committed.
(dg-additional-options wanted for lto.exp)
Richard.
2018-11-16 Richard Biener
PR testsuite/88053
* g++.dg/lto/pr54625-1_0.c: Add -w.
Index: gcc/testsuite/g++.dg/lto/pr54625-1_0.c
===
--- gcc/testsuite/g++.dg/lto/pr54625-1_0.c (revision 266200)
+++ gcc/testsuite/g++.dg/lto/pr54625-1_0.c (working copy)
@@ -1,4 +1,5 @@
/* { dg-lto-do link } */
+/* { dg-lto-options { { -O0 -flto -w } { -O2 -flto -w } } } */
/* { dg-extra-ld-options { -r -nostdlib -flinker-output=nolto-rel } } */
float a;
Re: [PATCH], Remove power9 fusion support, version 2
Hi Mike, Thanks for the changes. On Thu, Nov 08, 2018 at 04:28:52PM -0500, Michael Meissner wrote: > * config/rs6000/constraints.md (wF constraint): Update constraint > documentation for power8 fusion only. "so it is for ...", maybe? It is hard to understand your sentence. > +/* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they > + are not common. */ Trailing whitespace. (twice) Okay for trunk with those trivialities fixed. Thanks! Segher
[PATCH] S/390: Add a new pattern for r{o,x}sbg
Bootstrapped and regtested on s390x-redhat-linux.
Fixes rXsbg_mode_sXl test failures.
Combine used to give us
(set (reg:SI 65)
(ior:SI (lshiftrt:SI (reg:SI 3 %r3 [ bD.2238 ])
(const_int 2 [0x2]))
(reg:SI 2 %r2 [ aD.2237 ])))
but now we get
(set (reg:SI 65)
(ior:SI (subreg:SI (zero_extract:DI (reg:DI 69)
(const_int 32 [0x20])
(const_int 30 [0x1e])) 4)
(subreg:SI (reg:DI 68) 4)))
or
(set (reg:SI 65)
(ior:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 69)
(const_int 2 [0x2]))
(const_int 4294967295 [0x])) 4)
(subreg:SI (reg:DI 68) 4)))
with an extra subreg, which appears because pseudos, unlike hard
registers, can be accessed only using their natural mode.
This patch adds a special case for that. Also, it performs r*sbg
bit index computations during gcc run, so that expectations do not
depend on which concrete pattern was matched.
gcc/ChangeLog:
2018-11-15 Ilya Leoshkevich
* config/s390/s390.md
(*rsbg__srl_bitmask): Do not delegate arithmetic to
assembler.
(*rsbg__sll): Likewise.
(*rsbg__srl): Likewise.
(*rsbg_sidi_srl): New pattern.
* gcc.target/s390/md/rXsbg_mode_sXl.c: Do not use arithmetic in
r{o,x}sbg expectations.
* gcc.target/s390/risbg-ll-2.c: Likewise.
---
gcc/config/s390/s390.md | 42 +--
.../gcc.target/s390/md/rXsbg_mode_sXl.c | 16 +++
gcc/testsuite/gcc.target/s390/risbg-ll-2.c| 2 +-
3 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 957c378e34f..7a556d40224 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -4276,7 +4276,12 @@
"TARGET_Z10
&& s390_extzv_shift_ok (, 64 - INTVAL (operands[3]),
INTVAL (operands[2]))"
- "rsbg\t%0,%1,%2,%2,64-%3"
+ {
+static char buffer[256];
+sprintf (buffer, "rsbg\t%%0,%%1,%%2,%%2,%ld",
+ 64 - INTVAL (operands[3]));
+return buffer;
+ }
[(set_attr "op_type" "RIE")])
; rosbg, rxsbg
@@ -4309,7 +4314,12 @@
(match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
- "rsbg\t%0,%1,,63-%2,%2"
+ {
+static char buffer[256];
+sprintf (buffer, "rsbg\t%%0,%%1,,%ld,%%2",
+ 63 - INTVAL (operands[2]));
+return buffer;
+ }
[(set_attr "op_type" "RIE")])
;; unsigned {int,long} a, b
@@ -4325,7 +4335,33 @@
(match_operand:GPR 3 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
- "rsbg\t%0,%1,%2,63,64-%2"
+ {
+static char buffer[256];
+sprintf (buffer, "rsbg\t%%0,%%1,%ld,63,%ld",
+ INTVAL (operands[2]), 64 - INTVAL (operands[2]));
+return buffer;
+ }
+ [(set_attr "op_type" "RIE")])
+
+; rosbg, rxsbg
+(define_insn "*rsbg_sidi_srl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+(IXOR:SI
+ (subreg:SI
+(zero_extract:DI
+ (match_operand:DI 1 "nonimmediate_operand" "d")
+ (const_int 32)
+ (match_operand:DI 2 "immediate_operand" ""))
+4)
+ (match_operand:SI 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ {
+static char buffer[256];
+sprintf (buffer, "rsbg\t%%0,%%1,%ld,63,%ld",
+ 64 - INTVAL (operands[2]), 32 + INTVAL (operands[2]));
+return buffer;
+ }
[(set_attr "op_type" "RIE")])
;; These two are generated by combine for s.bf &= val.
diff --git a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
index 824ce39dfd9..600914280e5 100644
--- a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
+++ b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
@@ -39,28 +39,28 @@ rosbg_si_sll (unsigned int a, unsigned int b)
{
return a | (b << 1);
}
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,63-1,1" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,62,1" 1 } } */
__attribute__ ((noinline)) unsigned int
rosbg_si_srl (unsigned int a, unsigned int b)
{
return a | (b >> 2);
}
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,34,63,62" 1 } } */
__attribute__ ((noinline)) unsigned int
rxsbg_si_sll (unsigned int a, unsigned int b)
{
return a ^ (b << 1);
}
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,63-1,1" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,62,1" 1 } } */
__attribute__ ((noinline)) unsigned int
rxsbg_si_srl (unsigned int a, unsigned int b)
{
return a ^ (b >> 2);
}
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,34,63,62" 1 } } */
__attribute__ ((noinline)) unsigned l
[PATCH] Fix PR88011
Bootstrap & regtest running on x86_64-unknown-linux-gnu.
Richard.
2018-11-16 Richard Biener
PR tree-optimization/88011
* tree-vrp.c (extract_range_from_binary_expr): Fix error in
replacing set_value_range_to_undefined and
set_value_range_to_varying with method calls.
Index: gcc/tree-vrp.c
===
--- gcc/tree-vrp.c (revision 266202)
+++ gcc/tree-vrp.c (working copy)
@@ -1905,7 +1905,7 @@ extract_range_from_binary_expr (value_ra
TYPE_OVERFLOW_UNDEFINED (expr_type),
extra_range_p, extra_min, extra_max))
{
- vr->set_undefined ();
+ vr->set_varying ();
return;
}
vr->set (VR_RANGE, wide_int_to_tree (expr_type, wmin),
[Patch, libstdc++.exp]Update the usage of cached result, rebuild nlocale wrapper for each variant.
Hi all,
Tejas noticed that libstdc++.exp currently builds nlocale driver
(libstc++.exp:check_v3_target_namedlocale())
once for a test run. This is done irrespective of the number of variants in the
site.exp file.
For eg. if we have more than one variant for different target profiles i.e.
/-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard
/-mthumb/-mcpu=cortex-m0
nlocale.cpp is built once and is reused for all the variants.
This is incorrect as the same binary may not work on all target profiles - eg.
nlocale.x built for arm A-profile
may not work on M-profile targets. nlocale needs to be rebuilt for each
variant in site.exp. This patch fixes that.
Meanwhile, it updates all the usage of cached value with the new method.
This is similar to the recent change in gcc/testsuite/lib/target-support.exp
A global dictionary is used to store a property for a particular target,
instead of the target check and update approach.
This factors the common code out of each procedure, reduce the length of
libstdc++.exp file.
Tested on arm-none-eabi with the following variants in site.exp:
/-marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp
/-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard
/-mthumb/-mcpu=cortex-m0
/-mthumb/-mcpu=cortex-m3
/-mthumb/-mcpu=cortex-m4
/-mthumb/-mcpu=cortex-m7
/-mthumb/-mcpu=cortex-m23
/-mthumb/-march=armv8-m.main
Tested on native x86_64,
make check-target-libstdc++-v3
with default unix variant. There is no change on the result.
Okay to commit?
Regards,
Renlin
gcc/libstdc++-v3/:
2018-11-16 Renlin Li
Tejas Belagod
testsuite/lib/libstdc++.exp (check_v3_target_prop_cached): New proc.
(check_v3_target): Use the check_v3_target_prop_cached.
diff --git a/libstdc++-v3/testsuite/lib/libstdc++.exp b/libstdc++-v3/testsuite/lib/libstdc++.exp
index 79d8e0130dcefdd8ccb67ad45f81ff12a3703600..7047b8f7b2233911445abaed54337bc46b37b7e5 100644
--- a/libstdc++-v3/testsuite/lib/libstdc++.exp
+++ b/libstdc++-v3/testsuite/lib/libstdc++.exp
@@ -688,31 +688,38 @@ proc v3-build_support { } {
}
}
-proc check_v3_target_fileio { } {
-global et_fileio_saved
-global et_fileio_target_name
-global tool
-global srcdir
+# Implement an target check for property PROP by invoking
+# the Tcl command ARGS and seeing if it returns true.
-if { ![info exists et_fileio_target_name] } {
- set et_fileio_target_name ""
-}
+proc check_v3_target_prop_cached { prop args } {
+global et_cache
-# If the target has changed since we set the cached value, clear it.
-set current_target [current_target_name]
-if { $current_target != $et_fileio_target_name } {
- verbose "check_v3_target_fileio: `$et_fileio_target_name'" 2
- set et_fileio_target_name $current_target
- if [info exists et_fileio_saved] {
- verbose "check_v3_target_fileio: removing cached result" 2
- unset et_fileio_saved
+set target [current_target_name]
+if {![info exists et_cache($prop,$target)]} {
+ verbose "check_v3_target_prop_cached $prop: checking $target" 2
+ if {[string is true -strict $args] || [string is false -strict $args]} {
+ error {check_v3_target_prop_cached condition already evaluated; did you pass [...] instead of the expected {...}?}
+ } else {
+ set code [catch {uplevel eval $args} result]
+ if {$code != 0 && $code != 2} {
+ verbose "check_v3_target_prop_cached $prop: evaluation failed for $target" 2
+ return -code $code $result
+ }
+ set et_cache($prop,$target) $result
}
+} else {
+ verbose "check_v3_target_prop_cached $prop $target: using cached result" 2
}
-if [info exists et_fileio_saved] {
- verbose "check_v3_target_fileio: using cached result" 2
-} else {
- set et_fileio_saved 0
+set value $et_cache($prop,$target)
+verbose "check_v3_target_prop_cached $prop: returning $value for $target" 2
+return $value
+}
+
+proc check_v3_target_fileio { } {
+return [check_v3_target_prop_cached et_fileio {
+ global tool
+ global srcdir
# Set up, compile, and execute a C++ test program that tries to use
# the file functions
@@ -766,41 +773,19 @@ proc check_v3_target_fileio { } {
verbose "check_v3_target_fileio: status is <$status>" 2
if { $status == "pass" } {
- set et_fileio_saved 1
+ return 1
}
} else {
verbose "check_v3_target_fileio: compilation failed" 2
}
-}
-return $et_fileio_saved
+ return 0
+}]
}
# Eventually we want C90/C99 determining and switching from this.
proc check_v3_target_c_std { } {
-global et_c_std_saved
-global et_c_std_target_name
-global tool
-
-if { ![info exists et_c_std_target_name] } {
- set et_c_std_target_name ""
-}
-
-# If the target has changed since we set the cached value, clear it.
-set current_target [current_target_name]
-if { $current_target != $et_c_std_target_name } {
- verbose "check_v3_target_c
[patch] Propagate location into decision tree for switches
Hi,
since the expansion of switches statement into decision trees was moved from
RTL to GIMPLE, the location information of the comparison statements has been
lost, i.e. GIMPLE generates comparison statements with UNKNOWN_LOCATION and
they are expanded as-is into RTL. Now this can be problematic for coverage
analysis because the statements can inherit a wrong location in the assembly.
Therefore the attached patch propagates the location from the switch statement
to every comparison statement generated for the decision tree.
Tested on x86_64-suse-linux, OK for mainline and 8 branch?
2018-11-16 Eric Botcazou
* tree-switch-conversion.h (switch_decision_tree::emit_case_nodes): Add
location_t parameter.
(switch_decision_tree::emit_cmp_and_jump_insns): Likewise.
(switch_decision_tree::do_jump_if_equal): Likewise.
* tree-switch-conversion.c (switch_decision_tree::emit): Pass location
of switch statement to emit_case_nodes.
(switch_decision_tree::emit_cmp_and_jump_insns): Add LOC parameter and
set it on the newly built GIMPLE comparison statement.
(switch_decision_tree::do_jump_if_equal): Likewise.
(switch_decision_tree::emit_case_nodes): Add LOC parameter and pass it
into calls to do_jump_if_equal as well as recursive calls.
--
Eric BotcazouIndex: tree-switch-conversion.c
===
--- tree-switch-conversion.c (revision 266178)
+++ tree-switch-conversion.c (working copy)
@@ -1942,7 +1942,8 @@ switch_decision_tree::emit (basic_block
dump_case_nodes (dump_file, m_case_list, indent_step, 0);
}
- bb = emit_case_nodes (bb, index_expr, m_case_list, default_prob, index_type);
+ bb = emit_case_nodes (bb, index_expr, m_case_list, default_prob, index_type,
+ gimple_location (m_switch));
if (bb)
emit_jump (bb, m_default_bb);
@@ -2085,12 +2086,14 @@ basic_block
switch_decision_tree::emit_cmp_and_jump_insns (basic_block bb, tree op0,
tree op1, tree_code comparison,
basic_block label_bb,
- profile_probability prob)
+ profile_probability prob,
+ location_t loc)
{
// TODO: it's once called with lhs != index.
op1 = fold_convert (TREE_TYPE (op0), op1);
gcond *cond = gimple_build_cond (comparison, op0, op1, NULL_TREE, NULL_TREE);
+ gimple_set_location (cond, loc);
gimple_stmt_iterator gsi = gsi_last_bb (bb);
gsi_insert_after (&gsi, cond, GSI_NEW_STMT);
@@ -2114,11 +2117,13 @@ switch_decision_tree::emit_cmp_and_jump_
basic_block
switch_decision_tree::do_jump_if_equal (basic_block bb, tree op0, tree op1,
basic_block label_bb,
- profile_probability prob)
+ profile_probability prob,
+ location_t loc)
{
op1 = fold_convert (TREE_TYPE (op0), op1);
gcond *cond = gimple_build_cond (EQ_EXPR, op0, op1, NULL_TREE, NULL_TREE);
+ gimple_set_location (cond, loc);
gimple_stmt_iterator gsi = gsi_last_bb (bb);
gsi_insert_before (&gsi, cond, GSI_SAME_STMT);
@@ -2145,7 +2150,7 @@ basic_block
switch_decision_tree::emit_case_nodes (basic_block bb, tree index,
case_tree_node *node,
profile_probability default_prob,
- tree index_type)
+ tree index_type, location_t loc)
{
profile_probability p;
@@ -2160,7 +2165,7 @@ switch_decision_tree::emit_case_nodes (b
this node and then check our children, if any. */
p = node->m_c->m_prob / (node->m_c->m_subtree_prob + default_prob);
bb = do_jump_if_equal (bb, index, node->m_c->get_low (),
- node->m_c->m_case_bb, p);
+ node->m_c->m_case_bb, p, loc);
/* Since this case is taken at this point, reduce its weight from
subtree_weight. */
node->m_c->m_subtree_prob -= p;
@@ -2181,12 +2186,12 @@ switch_decision_tree::emit_case_nodes (b
p = (node->m_right->m_c->m_prob
/ (node->m_c->m_subtree_prob + default_prob));
bb = do_jump_if_equal (bb, index, node->m_right->m_c->get_low (),
- node->m_right->m_c->m_case_bb, p);
+ node->m_right->m_c->m_case_bb, p, loc);
p = (node->m_left->m_c->m_prob
/ (node->m_c->m_subtree_prob + default_prob));
bb = do_jump_if_equal (bb, index, node->m_left->m_c->get_low (),
- node->m_left->m_c->m_case_bb, p);
+ node->m_left->m_c->m_case_bb, p, loc);
}
else
{
@@ -2199,12 +2204,12 @@ switch_decision_tree::emit_case_nodes (b
+ default_prob.apply_scale (1, 2))
/ (node->m_c->m_subtree_prob + default_prob));
bb = emit_cmp_and_jump_insns (bb, index, node->m_c->get_high (),
- GT_EXPR, test_bb, p);
+ GT_EXPR, test_bb, p, loc);
default_prob = default_prob.apply_scale (1, 2);
/* Handle the left-hand subtree. */
bb = emit_case_nodes (bb, index, node->m_left,
-default_prob, index_type);
+default_prob, index_type, loc);
/* If
Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626
My bad , attached the same now . ~Umesh On Fri, Nov 16, 2018 at 2:38 PM Richard Biener wrote: > > On Fri, Nov 16, 2018 at 9:07 AM Umesh Kalappa > wrote: > > > > Thank you Richard, > > > > Made the required changes ,ok to commit ? > > Can you attach the adjusted patch? > > Thanks, > Richard. > > > Thank you > > ~Umesh > > On Thu, Nov 15, 2018 at 4:02 PM Richard Biener > > wrote: > > > > > > On Thu, Nov 15, 2018 at 10:02 AM Umesh Kalappa > > > wrote: > > > > > > > > Hi All, > > > > > > > > The attached patch (pr85667.patch) fixes the subjected issue . > > > > we tested on x86_64(linux and windows both) and no regress found . > > > > > > > > ok to commit ? > > > > > > I wonder if you can turn the testcase into a dg-run one, making the > > > functions noinline/noipa and check the correct values are returned. > > > > > > Richard. > > > > > > > Thank you > > > > ~Umesh pr85667.patch Description: Binary data
Re: [patch] Propagate location into decision tree for switches
On Fri, Nov 16, 2018 at 11:45 AM Eric Botcazou wrote: > > Hi, > > since the expansion of switches statement into decision trees was moved from > RTL to GIMPLE, the location information of the comparison statements has been > lost, i.e. GIMPLE generates comparison statements with UNKNOWN_LOCATION and > they are expanded as-is into RTL. Now this can be problematic for coverage > analysis because the statements can inherit a wrong location in the assembly. > > Therefore the attached patch propagates the location from the switch statement > to every comparison statement generated for the decision tree. > > Tested on x86_64-suse-linux, OK for mainline and 8 branch? OK. Thanks, Richard. > > 2018-11-16 Eric Botcazou > > * tree-switch-conversion.h (switch_decision_tree::emit_case_nodes): > Add > location_t parameter. > (switch_decision_tree::emit_cmp_and_jump_insns): Likewise. > (switch_decision_tree::do_jump_if_equal): Likewise. > * tree-switch-conversion.c (switch_decision_tree::emit): Pass location > of switch statement to emit_case_nodes. > (switch_decision_tree::emit_cmp_and_jump_insns): Add LOC parameter and > set it on the newly built GIMPLE comparison statement. > (switch_decision_tree::do_jump_if_equal): Likewise. > (switch_decision_tree::emit_case_nodes): Add LOC parameter and pass it > into calls to do_jump_if_equal as well as recursive calls. > > -- > Eric Botcazou
Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626
On Fri, Nov 16, 2018 at 04:21:25PM +0530, Umesh Kalappa wrote:
> My bad ,
> attached the same now .
+2018-11-15 Lokesh Janghel
Two spaces before < instead of just one.
+
+ PR target/85667
Only a single space between PR and target.
+ * i386.c (function_value_ms_64): ms_abi insist to use the eax
The filename is relative to the directory with ChangeLog file, so
* config/i386/i386.c
in this case. The description should say what you've changed, so
something like:
* config/i386/i386.c (function_value_ms_64): Return AX_REG instead
of FIRST_SSE_REG for 4 or 8 byte modes.
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -9008,7 +9008,7 @@ function_value_ms_64 (machine_mode orig_mode,
machine_mode mode,
case 8:
case 4:
if (mode == SFmode || mode == DFmode)
- regno = FIRST_SSE_REG;
+ regno = AX_REG;
break;
Is there something to back that up, say godbolt.org link with some testcases
showing how does MSVC, clang etc. handle those?
And, because the function starts with:
unsigned int regno = AX_REG;
the change isn't right, you should remove all of:
case 8:
case 4:
if (mode == SFmode || mode == DFmode)
regno = FIRST_SSE_REG;
break;
because the default will do what you want.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 50e53f0..ec54330 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-15 Lokesh Janghel
Two spaces between date and name.
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr85667.c
@@ -0,0 +1,29 @@
+/* { dg-options "-O2 " } */
+/* { dg-final { scan-assembler-times "movl\[\t
\]\.\[a-zA-Z\]\[a-zA-Z\]\[0-9\]\\(%rip\\), %eax" 1} } */
First of all, the test is misplaced, it is clearly x86_64 specific
and probably lp64 only, so it shouldn't be in gcc.dg/ where it will
be run on all targets, but in gcc.target/i386/ and be guarded with
{ target lp64 }.
Second, seems like you'd like to run the testcase, so you'd better have it
/* { dg-do run { target lp64 } } */
The assembler scanning will work only with -masm=att, not -masm=intel
and seems to be very fragile, so I'd suggest have one runtime test and one
compile time test in which you put just the fn1 function. Why two arbitrary
letters after dot? That makes on sense. Either you are looking for .LC\[0-9]*
specifically, or for arbitrary symbol, then use something like
"movl\[^\n\r]*, %eax"
or so (and make sure to use -masm=intel).
More interesting would be
make check ALT_CC_UNDER_TEST=msvc ALT_CXX_UNDER_TEST=msvc++
RUNTESTFLAGS='compat.exp struct-layout-1.exp'
(or whatever MSVC driver names are), i.e. try to run the compat testsuites
between MSVC and newly built gcc.
Jakub
Re: [PATCH] S/390: Add a new pattern for r{o,x}sbg
On 16.11.18 11:15, Ilya Leoshkevich wrote:
> Bootstrapped and regtested on s390x-redhat-linux.
>
> Fixes rXsbg_mode_sXl test failures.
>
> Combine used to give us
>
> (set (reg:SI 65)
> (ior:SI (lshiftrt:SI (reg:SI 3 %r3 [ bD.2238 ])
> (const_int 2 [0x2]))
> (reg:SI 2 %r2 [ aD.2237 ])))
>
> but now we get
>
> (set (reg:SI 65)
> (ior:SI (subreg:SI (zero_extract:DI (reg:DI 69)
> (const_int 32 [0x20])
> (const_int 30 [0x1e])) 4)
> (subreg:SI (reg:DI 68) 4)))
>
> or
>
> (set (reg:SI 65)
> (ior:SI (subreg:SI (and:DI (lshiftrt:DI (reg:DI 69)
> (const_int 2 [0x2]))
> (const_int 4294967295 [0x])) 4)
> (subreg:SI (reg:DI 68) 4)))
>
> with an extra subreg, which appears because pseudos, unlike hard
> registers, can be accessed only using their natural mode.
>
> This patch adds a special case for that. Also, it performs r*sbg
> bit index computations during gcc run, so that expectations do not
> depend on which concrete pattern was matched.
>
> gcc/ChangeLog:
>
> 2018-11-15 Ilya Leoshkevich
>
> * config/s390/s390.md
> (*rsbg__srl_bitmask): Do not delegate arithmetic to
> assembler.
> (*rsbg__sll): Likewise.
> (*rsbg__srl): Likewise.
> (*rsbg_sidi_srl): New pattern.
> * gcc.target/s390/md/rXsbg_mode_sXl.c: Do not use arithmetic in
> r{o,x}sbg expectations.
> * gcc.target/s390/risbg-ll-2.c: Likewise.
Ok. Thanks!
Andreas
Re: [PATCH] Reject too large string literals (PR middle-end/87854)
On 11/16/18 3:43 AM, Jakub Jelinek wrote: Hi! Both C and C++ FE diagnose arrays larger than half of the address space: /tmp/1.c:1:6: error: size of array ‘a’ is too large char a[__SIZE_MAX__ / 2 + 1]; ^ because one can't do pointer arithmetics on them. But we don't have anything similar for string literals. As internally we use host int as TREE_STRING_LENGTH, this is relevant to targets that have < 32-bit size_t only. The following patch adds that diagnostics and truncates the string literals. Ok by me. nathan -- Nathan Sidwell
Re: Tweak ALAP calculation in SCHED_PRESSURE_MODEL
Hi Jeff, On 10/11/18 00:04, Jeff Law wrote: On 11/8/18 5:10 AM, Kyrill Tkachov wrote: This patch fixes a flaw in the relationship between the way that SCHED_PRESSURE_MODEL calculates the alap and depth vs how it uses them in model_order_p. A comment in model_order_p says: /* Combine the length of the longest path of satisfied true dependencies that leads to each instruction (depth) with the length of the longest path of any dependencies that leads from the instruction (alap). Prefer instructions with the greatest combined length. If the combined lengths are equal, prefer instructions with the greatest depth. The idea is that, if we have a set S of "equal" instructions that each have ALAP value X, and we pick one such instruction I, any true-dependent successors of I that have ALAP value X - 1 should be preferred over S. This encourages the schedule to be "narrow" rather than "wide". However, if I is a low-priority instruction that we decided to schedule because of its model_classify_pressure, and if there is a set of higher-priority instructions T, the aforementioned successors of I should not have the edge over T. */ The expectation was that scheduling an instruction X would give a greater priority to the highest-priority successor instructions Y than X had: Y.depth would be X.depth + 1 and Y.alap would be X.alap - 1, giving an equal combined height, but with the greater depth winning as a tie-breaker. But this doesn't work if the alap value was ultimately determined by an anti-dependence. This is particularly bad when --param max-pending-list-length kicks in, since we then start adding fake anti-dependencies in order to keep the list length down. These fake dependencies tend to be on the critical path. The attached patch avoids that by making the alap calculation only look at true dependencies. This shouldn't be too bad, since we use INSN_PRIORITY as the final tie-breaker than that does take anti-dependencies into account. This reduces the number of spills in the hot function from 436.cactusADM by 14% on aarch64 at -O3 (and the number of instructions in general). SPEC2017 shows a minor improvement on Cortex-A72 (about 0.1% overall). Thanks to Wilco for the benchmarking. Bootstrapped and tested on aarch64-none-linux-gnu. Is this ok for trunk? Thanks, Kyrill 2018-11-08 Richard Sandiford gcc/ * haifa-sched.c (model_analyze_insns): Only add 1 to the consumer's ALAP if the dependence is a true dependence. So at the least the documentation of the ALAP field would need to be updated as well as the comment you referenced (the "any dependencies"). Ah, I can easily update the patch for that. But more importantly, it seems like blindly ignoring anti dependencies is just a hack that happens to work. I wonder if we could somehow mark the fake dependencies we add, and avoid bumping the ALAP when we encounter those fake dependencies. I did experiment with this. I added a new property to dep_t to mark it as "artificial", that is created in the parts of sched-deps.c that add dependencies when MAX_PENDING_LIST_LENGTH is exceeded. Then ALAP is bumped only when the dependency is not artificial in this way. This didn't help much on the testcase we were looking at (the hot function in cactus from SPEC2006). The code size increase and number of spills decreased by only 6 (out of ~800) whereas with Richards' patch it improved much more (~140 decrease, with a corresponding improvement in stack usage and code size). Richard did suggest that anti-dependencies are already taken into account in the INSN_PRIORITY tie-breaker, so perhaps that is a better scheme indeed? It probably wouldn't be a bad idea to look at the default for MAX_PENDING_LIST_LENGTH. Based on the current default value and the comments in the code that value could well have been tuned 25 or more years ago! Probably. I see that s390 and spu increase that param in their backends to much larger values than the default I played around with increasing it on aarch64. It improved things somewhat, but Richard's patch still gave superior results. Thanks, Kyrill How often are we falling over that during a bootstrap and during spec builds? Jeff
[PATCH] Fix ICE in lto_symtab_merge_symbols_1 (PR lto/88004).
Hi.
This is fix for the PR which we cooked with Honza.
He pre-approved that.
Survives regression tests and bootstrap on x86_64-linux-gnu.
I'm going to install it.
Martin
gcc/lto/ChangeLog:
2018-11-16 Martin Liska
PR lto/88004
* lto-symtab.c (lto_symtab_merge_symbols_1): Do not call
lto_symtab_symbol_p as it does checking of transparent alias.
These needs to be also merged in the function.
---
gcc/lto/lto-symtab.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/lto/lto-symtab.c b/gcc/lto/lto-symtab.c
index 4b24b84774d..18437eb2841 100644
--- a/gcc/lto/lto-symtab.c
+++ b/gcc/lto/lto-symtab.c
@@ -894,10 +894,11 @@ lto_symtab_merge_symbols_1 (symtab_node *prevailing)
e = next)
{
next = e->next_sharing_asm_name;
+ cgraph_node *ce = dyn_cast (e);
- if (!lto_symtab_symbol_p (e))
+ if ((!TREE_PUBLIC (e->decl) && !DECL_EXTERNAL (e->decl))
+ || (ce != NULL && ce->global.inlined_to))
continue;
- cgraph_node *ce = dyn_cast (e);
symtab_node *to = symtab_node::get (lto_symtab_prevailing_decl (e->decl));
/* No matter how we are going to deal with resolution, we will ultimately
Re: [Patch, libstdc++.exp]Update the usage of cached result, rebuild nlocale wrapper for each variant.
On 16/11/18 10:42 +, Renlin Li wrote: Hi all, Please remember that all patches for libstdc++ must be sent to the libstdc++ list, as documented at https://gcc.gnu.org/lists.html Just CCing me is not enough. Tejas noticed that libstdc++.exp currently builds nlocale driver (libstc++.exp:check_v3_target_namedlocale()) once for a test run. This is done irrespective of the number of variants in the site.exp file. For eg. if we have more than one variant for different target profiles i.e. /-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard /-mthumb/-mcpu=cortex-m0 nlocale.cpp is built once and is reused for all the variants. This is incorrect as the same binary may not work on all target profiles - eg. nlocale.x built for arm A-profile may not work on M-profile targets. nlocale needs to be rebuilt for each variant in site.exp. This patch fixes that. Meanwhile, it updates all the usage of cached value with the new method. This is similar to the recent change in gcc/testsuite/lib/target-support.exp A global dictionary is used to store a property for a particular target, instead of the target check and update approach. This factors the common code out of each procedure, reduce the length of libstdc++.exp file. This is great, thanks! Tested on arm-none-eabi with the following variants in site.exp: /-marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp /-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard /-mthumb/-mcpu=cortex-m0 /-mthumb/-mcpu=cortex-m3 /-mthumb/-mcpu=cortex-m4 /-mthumb/-mcpu=cortex-m7 /-mthumb/-mcpu=cortex-m23 /-mthumb/-march=armv8-m.main Tested on native x86_64, make check-target-libstdc++-v3 with default unix variant. There is no change on the result. Okay to commit? OK, thanks.
Re: [PATCH] Support simd function declarations via a pre-include.
On 11/15/18 9:54 PM, Jakub Jelinek wrote:
> On Thu, Nov 15, 2018 at 08:40:13PM +0100, Bernhard Reutner-Fischer wrote:
>> On 14 November 2018 12:35:27 CET, Jakub Jelinek wrote:
>>
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -170,3 +170,6 @@ see the files COPYING3 and COPYING.RUNTIME
>>> respectively. If not, see
LD_STATIC_OPTION " --whole-archive -llsan --no-whole-archive " \
LD_DYNAMIC_OPTION "}}%{!static-liblsan:-llsan}"
#endif
+
+#undef TARGET_F951_NOSTDINC_OPTIONS
+#define TARGET_F951_NOSTDINC_OPTIONS
>>> "%:fortran-header-file(-fpre-include= math-vector-fortran.h)"
>>>
>>> Too long line, use some \s to split it up.
>>>
>>
>> Can we use plain -include like in C?
>
> Wouldn't that be confusing whether it is included in preprocessor only or if
> it is included as a magic fortran include line at the beginning?
>
> Jakub
>
Agree with that, I'm sending updated version of the patch. It's tested on
x86_64-linux-gnu,
where it survives regression tests and bootstraps.
I hope I addressed all notes that Jakub provided.
Thanks,
Martin
>From 958b29507153e923e08f79e754ed3e2e95bbec91 Mon Sep 17 00:00:00 2001
From: marxin
Date: Wed, 7 Nov 2018 12:41:19 +0100
Subject: [PATCH] Support simd function declarations via a pre-include.
gcc/ChangeLog:
2018-11-15 Martin Liska
* config/gnu-user.h (TARGET_F951_OPTIONS): New.
* gcc.c (find_fortran_preinclude_file): New function
to handle Fortran pre-include.
gcc/fortran/ChangeLog:
2018-11-15 Martin Liska
* decl.c (gfc_match_gcc_builtin): New function.
* gfortran.h (struct vect_builtin_tuple): New.
(gfc_adjust_builtins): Likewise.
* lang-specs.h (TARGET_F951_OPTIONS): New.
(F951_OPTIONS): Use it.
* lang.opt: Add new option -fpre-include.
* match.h (gfc_match_gcc_builtin): Declare new function.
* parse.c (decode_gcc_attribute): Handle builtin.
(parse_progunit): Call gfc_adjust_builtins.
* scanner.c (gfc_new_file): Load pre-included header file
when provided.
* trans-intrinsic.c (add_simd_flag_for_built_in): New.
(gfc_adjust_builtins): Likewise.
gcc/testsuite/ChangeLog:
2018-11-15 Martin Liska
* gfortran.dg/simd-builtins-1.f90: New test.
* gfortran.dg/simd-builtins-1.h: New test.
* gfortran.dg/simd-builtins-2.f90: New test.
---
gcc/config/gnu-user.h | 4 ++
gcc/fortran/decl.c| 33
gcc/fortran/gfortran.h| 13 +
gcc/fortran/lang-specs.h | 10 +++-
gcc/fortran/lang.opt | 4 ++
gcc/fortran/match.h | 1 +
gcc/fortran/parse.c | 3 ++
gcc/fortran/scanner.c | 4 ++
gcc/fortran/trans-intrinsic.c | 54 +++
gcc/gcc.c | 19 +++
gcc/testsuite/gfortran.dg/simd-builtins-1.f90 | 19 +++
gcc/testsuite/gfortran.dg/simd-builtins-1.h | 4 ++
gcc/testsuite/gfortran.dg/simd-builtins-2.f90 | 20 +++
13 files changed, 186 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/simd-builtins-1.f90
create mode 100644 gcc/testsuite/gfortran.dg/simd-builtins-1.h
create mode 100644 gcc/testsuite/gfortran.dg/simd-builtins-2.f90
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 5b48fb21514..d0acfed5116 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -170,3 +170,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
LD_STATIC_OPTION " --whole-archive -llsan --no-whole-archive " \
LD_DYNAMIC_OPTION "}}%{!static-liblsan:-llsan}"
#endif
+
+#undef TARGET_F951_OPTIONS
+#define TARGET_F951_OPTIONS "%{!nostdinc:\
+ %:fortran-preinclude-file(-fpre-include= math-vector-fortran.h)}"
diff --git a/gcc/fortran/decl.c b/gcc/fortran/decl.c
index 2b77d950abb..caac9d65b9f 100644
--- a/gcc/fortran/decl.c
+++ b/gcc/fortran/decl.c
@@ -98,6 +98,9 @@ bool gfc_matching_function;
/* Set upon parsing a !GCC$ unroll n directive for use in the next loop. */
int directive_unroll = -1;
+/* List middle-end built-ins that should be vectorized. */
+vec vectorized_builtins;
+
/* If a kind expression of a component of a parameterized derived type is
parameterized, temporarily store the expression here. */
static gfc_expr *saved_kind_expr = NULL;
@@ -11243,3 +11246,33 @@ gfc_match_gcc_unroll (void)
gfc_error ("Syntax error in !GCC$ UNROLL directive at %C");
return MATCH_ERROR;
}
+
+/* Match a !GCC$ builtin (b) attributes simd flags form:
+
+ The parameter b is name of a middle-end built-in.
+ Flags are one of:
+ - (empty)
+ - inbranch
+ - notinbranch
+
+ When we come here, we have already matched the !GCC$ builtin string. */
+match
+gfc_match_gcc_builtin (void)
+{
+ char builtin[GFC_MAX_SYMBOL_LEN + 1];
+
+ if (gfc_match (" (%n) attributes simd", builtin) != MATCH_YES)
+return MATCH_ERROR;
+
+ int builtin_k
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Re: [PATCH 21/25] GCN Back-end (part 2/2).
The guideline I would give to determine if you're vulnerable... Do you have speculation, including the ability to speculate past a memory operation, branch prediction, memory caches and high resolution timer (ie, like a cycle timer). If you've got those, then the processor is likely vulnerable to a spectre V1 style attack. Those are the basic building blocks. We have cycle timers and caches, but I'll have to ask AMD about the other details. There's no speculation or branch prediction, apparently. I'll set it up to use speculation_safe_value_not_needed. Andrew
Re: [PATCH] minor FDO profile related fixes
On 11/16/18 7:08 AM, Indu Bhagat wrote: > > On 11/12/2018 01:48 AM, Martin Liška wrote: >>> make check-gcc on x86_64 shows no new failures. >>> >>> (A related PR washttps://gcc.gnu.org/bugzilla/show_bug.cgi?id=86957 where >>> we added diagnostics for the NO PROFILE case.) >> Hi. >> >> Thanks for the patch. I'm not a maintainer, but the idea of the patch looks >> correct to me. >> One question about adding "(precise)", have you verified that the patch can >> survive regression >> tests? >> >> Thanks, >> Martin >> > > make check-gcc (configured with --enable-languages=c,c++,fortran,go,lto) > shows no new failures. > make -k check also looks ok. Thanks for testing. Honza can you please review that? Martin
[PATCH] Strenghten assumption about function start and end line (PR gcov-profile/88045).
Hi.
As mentioned in the PR, we should guarantee that a function ends before
it starts (from source line perspective).
For gcc-8 branch, a work-around would be needed.
Survives tests and bootstrap on x86_64-linux-gnu.
Ready for trunk and gcc-8 branch?
Thanks,
Martin
gcc/ChangeLog:
2018-11-16 Martin Liska
PR gcov/88045
* coverage.c (coverage_begin_function): Add assert.
gcc/testsuite/ChangeLog:
2018-11-16 Martin Liska
PR gcov/88045
* g++.dg/gcov/pr88045.C: New test.
---
gcc/coverage.c | 4 +-
gcc/testsuite/g++.dg/gcov/pr88045.C | 90 +
2 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/g++.dg/gcov/pr88045.C
diff --git a/gcc/coverage.c b/gcc/coverage.c
index 599a3bb9aeb..f0cbc1e46ef 100644
--- a/gcc/coverage.c
+++ b/gcc/coverage.c
@@ -639,7 +639,9 @@ coverage_begin_function (unsigned lineno_checksum, unsigned cfg_checksum)
expanded_location endloc = expand_location (cfun->function_end_locus);
/* Function can start in a single file and end in another one. */
- gcov_write_unsigned (endloc.file == xloc.file ? endloc.line : xloc.line);
+ int end_line = endloc.file == xloc.file ? endloc.line : xloc.line;
+ gcc_assert (xloc.line <= end_line);
+ gcov_write_unsigned (end_line);
gcov_write_length (offset);
return !gcov_is_error ();
diff --git a/gcc/testsuite/g++.dg/gcov/pr88045.C b/gcc/testsuite/g++.dg/gcov/pr88045.C
new file mode 100644
index 000..1b077a5e61a
--- /dev/null
+++ b/gcc/testsuite/g++.dg/gcov/pr88045.C
@@ -0,0 +1,90 @@
+// PR gcov-profile/88045
+// { dg-options "-fprofile-arcs -ftest-coverage -std=c++11" }
+// { dg-do run { target native } }
+
+#include
+#include
+#include
+
+struct Foo {
+size_t size() const { return n; };
+const size_t n;
+explicit Foo(size_t a_n) : n{a_n} {};
+};
+
+template class C, typename Head, typename... Tail>
+struct make_with_tail {
+using type = C;
+};
+
+template class C, typename T, typename Head, typename... Tail>
+struct make_with_tail_1 {
+using type = C;
+};
+
+template
+struct head {
+using type = Head;
+};
+template
+struct Tree {
+using root_type = typename head::type;
+using branch_type = typename make_with_tail::type;
+Tree(root_type a_root, std::vector a_branches) :
+root{std::move(a_root)},
+branches{std::move(a_branches)}
+{
+}
+
+explicit Tree(root_type a_root) : root{std::move(a_root)}, branches{root.size()}
+{
+}
+
+root_typeroot;
+std::vector branches;
+};
+
+template<>
+struct Tree<> {
+};
+
+template
+size_t size(const Tree& tree)
+{
+return std::accumulate(
+tree.branches.begin(),
+tree.branches.end(),
+0,
+[](const size_t& count, const typename make_with_tail::type& branch) {
+return count + size(branch);
+});
+}
+
+template<>
+inline size_t size(const Tree<>& /* empty tree */)
+{
+return 1;
+}
+
+int main(int argc, char *argv[])
+{
+size(Tree{Foo{4}, {Tree{Foo{2}, {Tree{Foo{205}},
+ Tree{Foo{261,
+ Tree{Foo{4}, {Tree{Foo{875}},
+ Tree{Foo{492}},
+ Tree{Foo{398}},
+ Tree{Foo{302,
+ Tree{Foo{6}, {Tree{Foo{111}},
+ Tree{Foo{436}},
+ Tree{Foo{388}},
+ Tree{Foo{879}},
+ Tree{Foo{783}},
+ Tree{Foo{735,
+ Tree{Foo{3}, {Tree{Foo{791}},
+ Tree{Foo{ 5}},
+ Tree{Foo{841}});
+
+return 0;
+}
+
+// { dg-final { run-gcov pr88045.C } }
>From cf3cf8a56ff576501701b2d830867a350e205b24 Mon Sep 17 00:00:00 2001
From: marxin
Date: Fri, 16 Nov 2018 13:59:09 +0100
Subject: [PATCH] Make a workaround for PR gcov-profile/88045.
gcc/ChangeLog:
2018-11-16 Martin Liska
PR gcov-profile/88045
* coverage.c (coverage_begin_function): One can't relly on the
fact that function ends on the same line it starts or later.
gcc/testsuite/ChangeLog:
2018-11-16 Martin Liska
PR gcov-profile/88045
* g++.dg/gcov/pr88045.C: New test.
---
gcc/coverage.c | 6 +-
gcc/testsuite/g++.dg/gcov/pr88045.C | 90 +
2 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/g++.dg/gcov/pr88045.C
diff --git a/gcc/coverag
Re: [PATCH] Support simd function declarations via a pre-include.
On Fri, Nov 16, 2018 at 02:24:42PM +0100, Martin Liška wrote:
> + if (gfc_match (" (%n) attributes simd", builtin) != MATCH_YES)
> +return MATCH_ERROR;
> +
> + int builtin_kind = 0;
> + if (gfc_match (" (notinbranch)") == MATCH_YES)
I think you need " ( notinbranch )" here.
> +builtin_kind = -1;
> + else if (gfc_match (" (inbranch)") == MATCH_YES)
> +builtin_kind = 1;
And similarly here (+ testsuite coverage for whether you can in free form
insert spaces in all the spots that should be allowed).
!gcc$ builtin ( sinf ) attributes simd ( notinbranch ) ! comment
e.g. should be valid in free form (and fixed form too).
> --- a/gcc/fortran/gfortran.h
> +++ b/gcc/fortran/gfortran.h
> @@ -2764,6 +2764,18 @@ bool gfc_in_match_data (void);
> match gfc_match_char_spec (gfc_typespec *);
> extern int directive_unroll;
>
> +/* Tuple for parsing of vectorized built-ins. */
> +struct vect_builtin_tuple
> +{
> + vect_builtin_tuple (const char *n, int t): name (n), simd_type (t)
gfc_vect_builtin_tuple ?
+ document what the simd_type is (or make it enum or whatever).
One option would be enum omp_clause_code and use OMP_CLAUSE_ERROR for
the case where the argument isn't specified, but I think generally
gfortran.h doesn't depend on tree* stuff and wants to have its own
enums etc.
> +extern vec vectorized_builtins;
gfc_vectorized_builtins ?
> --- a/gcc/fortran/trans-intrinsic.c
> +++ b/gcc/fortran/trans-intrinsic.c
> @@ -597,7 +597,61 @@ define_quad_builtin (const char *name, tree type, bool
> is_const)
>return fndecl;
> }
>
> +/* Add SIMD attribute for FNDECL built-in if the built-in
> + name is in VECTORIZED_BUILTINS. */
> +#include "print-tree.h"
If you need to include a header, include it at the start of the file.
> +static void
> +add_simd_flag_for_built_in (tree fndecl)
> +{
> + if (fndecl == NULL_TREE)
> +return;
> +
> + const char *name = IDENTIFIER_POINTER (DECL_NAME (fndecl));
> + for (unsigned i = 0; i < vectorized_builtins.length (); i++)
> +if (strcmp (vectorized_builtins[i].name, name) == 0)
How many add_simd_flag_for_built_in calls are we expecting and how many
vectorized_builtins.length ()? If it is too much, perhaps e.g. sort
the vector by name and do a binary search. At least if it turns out to be
non-trivial compile time.
> +
> + vectorized_builtins.truncate (0);
That is a memory leak, right? The names are malloced.
And why truncate rather than release?
> + const char *path = find_a_file (&include_prefixes, argv[1], R_OK, true);
> + if (path != NULL)
> + return concat (argv[0], path, NULL);
Formatting.
> --- /dev/null
> +++ b/gcc/testsuite/gfortran.dg/simd-builtins-1.h
> @@ -0,0 +1,4 @@
> +!GCC$ builtin (sinf) attributes simd
> +!GCC$ builtin (sinf) attributes simd (inbranch)
> +!GCC$ builtin (sinf) attributes simd (notinbranch)
> +!GCC$ builtin (cosf) attributes simd (notinbranch)
Are you sure it is a good idea to have the 3 first lines for the same
builtin, rather than different?
It should be testsuite covered what we do in that case, but with the above
you don't cover what happens e.g. with notinbranch alone, or no argument.
Plus, as I said, I think you should have one *.f and one *.f90 test where
you just use many of those !gcc$ builtin lines with spaces in various spots
to verify it is parsed properly.
Jakub
Re: [RFC][PATCH, rs6000] Replace X-form addressing with D-form addressing in new pass for Power9
On Sat, Nov 10, 2018 at 11:36:28AM -0600, Kelvin Nilsen wrote:
> This new pass scans existing rtl expressions and replaces them with rtl
> expressions that favor selection of the D-form instructions in contexts for
> which the D-form instructions are preferred.
(Here would be a good place to say it runs right after the RTL loop opts).
> Both regressions relate to resolution of ifuncs, and I have determined that
> the toc pointer upon entry into the resolver functions are not valid. I have
> not yet determined why this is happening, though I have observed that the
> same problem seems to occur with certain other versions of the compiler prior
> to my trunk with patch. The two failures are:
>
> FAIL: gcc.dg/attr-ifunc-4.c execution test
> FAIL: gcc.dg/ipa/ipa-pta-19.c execution test
It sounds like those are not new failures. Would be good to figure out
what causes it of course.
> * config/rs6000/rs6000-p9indexing.c: New file.
A better name would be good :-)
> +bool
> +rs6000_target_supports_dform_offset_p (bool is_store __attribute__((unused)),
Just say bool /*is_store*/ or completely delete this if it isn't used?
Shorter name wouldn't hurt either ;-)
> +{
> + const int max_16bit_signed = (0x7fff);
> + const int min_16bit_signed = -1 - max_16bit_signed;
Please use HOST_WIDE_INT, not int.
> + /* available d-form instructions with P1 (the original Power architecture):
We don't actually support that anymore. But we do support original PowerPC
still, which matches what you say here (POWER used diffent mnemonics).
> + /* available d-form instructions with PPC (prior to v2.00):
This is the 64-bit instructions (64-bit is not required before ISA 3.0).
Those did not exist before PowerPC either, yup.
> + if ((byte_offset >= min_16bit_signed)
> + && (byte_offset <= max_16bit_signed))
if (IN_RANGE (byte_offset, min_16bit_signed, max_16bit_signed))
> + return true;
> + else
> + break;
Don't say "return else break" please, just say "return; break;"
> + if (rs6000_isa_flags & OPTION_MASK_MODULO)
> +{/* ISA 3.0 */
Don't put the "ISA" comment here please, put it somewhere before the "{".
> + case E_DFmode:
> + case E_SFmode:
> + /* E_DFmode handled by lxsd and stxsd insns. E_SFmode handled
> + by lxssp and stxssp insn. */
These are already handled by {l,st}f[sd] which are base PowerPC, at any
offset (not just multiples of 4)?
> --- gcc/config/rs6000/rs6000-passes.def (revision 263589)
> +++ gcc/config/rs6000/rs6000-passes.def (working copy)
> @@ -25,3 +25,4 @@
> */
>
>INSERT_PASS_BEFORE (pass_cse, 1, pass_analyze_swaps);
> + INSERT_PASS_AFTER (pass_loop2, 1, pass_fix_indexing);
This name is not super.
> \ No newline at end of file
And neither is that :-)
> + /* If this insn is relevant, it belongs to an equivalence class.
> + The equivalence classes are identified by the definitions that
> + define the inputs to this insn.
> + */
No new line for the comment end please.
> + unsigned int is_relevant: 1;
A space before the colon, too.
> +static int count_links (struct df_link *def_link)
> +{
> + if (def_link == NULL) return 0;
> + else return 1 + count_links (def_link->next);
Each return should start a new line.
> +static int
> +help_hash (int count, struct df_link *def_link) {
> + int *ids;
> + int i = 0;
> +
> + if (count > max_use_links)
> +max_use_links = count;
> +
> + ids = (int *) alloca (count * sizeof (int));
sizeof *ids; but can't you use a VLA?
> + while (def_link != NULL) {
{ on a new line, indented.
> + /* bubble sort to put ids in ascending order. */
> + for (int end = count - 1; end > 0; end--) {
> +for (int j = 0; j < end; j++) {
> + if (ids[j] > ids[j+1]) {
> + int swap = ids[j];
> + ids[j] = ids[j+1];
> + ids[j+1] = swap;
std::swap to swap. And just use qsort?
> +static void
> +find_defs (indexing_web_entry *insn_entry, rtx_insn *insn,
> +struct df_link **insn_base, struct df_link **insn_index)
> +{
> + unsigned int uid = INSN_UID (insn);
> + rtx body = PATTERN (insn);
> + rtx mem;
> + if ((GET_CODE (body) == SET) && MEM_P (SET_SRC (body)))
> +mem = XEXP (SET_SRC (body), 0);
> + else if ((GET_CODE (body) == SET) && MEM_P (SET_DEST (body)))
> +mem = XEXP (SET_DEST (body), 0);
> + else
> +mem = NULL;
> + /* else, this insn is neither load nor store. */
Use single_set instead?
> + }
> + }
> + }
> + }
> + }
> + }
> +}
> +}
This means you need some more factoring and/or some early outs.
> +/* Return non-zero if an only if use represents a compile-time constant. */
> +static int
> +represents_constant_p (df_ref use)
You're returning true or false, so please declare this s "bool".
> + /* We're only happy with multiple uses if all but one represent
> + constant values. Below
Re: [PATCH] Reject too large string literals (PR middle-end/87854)
On Fri, Nov 16, 2018 at 07:06:51AM -0500, Nathan Sidwell wrote: > On 11/16/18 3:43 AM, Jakub Jelinek wrote: > > Hi! > > > > Both C and C++ FE diagnose arrays larger than half of the address space: > > /tmp/1.c:1:6: error: size of array ‘a’ is too large > > char a[__SIZE_MAX__ / 2 + 1]; > >^ > > because one can't do pointer arithmetics on them. But we don't have > > anything similar for string literals. As internally we use host int > > as TREE_STRING_LENGTH, this is relevant to targets that have < 32-bit > > size_t only. > > > > The following patch adds that diagnostics and truncates the string literals. > > Ok by me. No objections from me, either. Marek
Re: [Patch, libstdc++.exp]Update the usage of cached result, rebuild nlocale wrapper for each variant.
On 11/16/2018 01:20 PM, Jonathan Wakely wrote: On 16/11/18 10:42 +, Renlin Li wrote: Hi all, Please remember that all patches for libstdc++ must be sent to the libstdc++ list, as documented at https://gcc.gnu.org/lists.html Just CCing me is not enough. Hi Jonathan, I knew I missed something! Thanks, committed. Regards, Renlin
Re: [PATCH, ARM, ping3] PR85434: Prevent spilling of stack protector guard's address on ARM
Ping? Best regards, Thomas On Sat, 10 Nov 2018 at 15:07, Thomas Preudhomme wrote: > > Thanks Kyrill. > > Updated patch in attachment. Best regards, > > Thomas > On Thu, 8 Nov 2018 at 15:53, Kyrill Tkachov > wrote: > > > > Hi Thomas, > > > > On 08/11/18 09:52, Thomas Preudhomme wrote: > > > Ping? > > > > > > Best regards, > > > > > > Thomas > > > > > > On Thu, 1 Nov 2018 at 16:03, Thomas Preudhomme > > > wrote: > > >> Ping? > > >> > > >> Best regards, > > >> > > >> Thomas > > >> On Fri, 26 Oct 2018 at 22:41, Thomas Preudhomme > > >> wrote: > > >>> Hi, > > >>> > > >>> Please find updated patch to fix PR85434: spilling of stack protector > > >>> guard's address on ARM. Quite a few changes have been made to the ARM > > >>> part since last round of review so I think it makes more sense to > > >>> review it anew. Ran bootstrap + regression testsuite + glibc build + > > >>> glibc regression testsuite for Arm and Thumb-2 and bootstrap + > > >>> regression testsuite for Thumb-1. GCC's regression testsuite was run > > >>> in 3 configurations in all those cases: > > >>> > > >>> - default configuration (no RUNTESTFLAGS) > > >>> - with -fstack-protector-all > > >>> - with -fPIC -fstack-protector-all (to exercise both codepath in stack > > >>> protector's split code) > > >>> > > >>> None of this show any regression beyond some new scan fail with > > >>> -fstack-protector-all or -fPIC due to unexpected code sequence for the > > >>> testcases concerned and some guality swing due to less optimization > > >>> with new stack protector on. > > >>> > > >>> Patch description and ChangeLog below. > > >>> > > >>> In case of high register pressure in PIC mode, address of the stack > > >>> protector's guard can be spilled on ARM targets as shown in PR85434, > > >>> thus allowing an attacker to control what the canary would be compared > > >>> against. ARM does lack stack_protect_set and stack_protect_test insn > > >>> patterns, defining them does not help as the address is expanded > > >>> regularly and the patterns only deal with the copy and test of the > > >>> guard with the canary. > > >>> > > >>> This problem does not occur for x86 targets because the PIC access and > > >>> the test can be done in the same instruction. Aarch64 is exempt too > > >>> because PIC access insn pattern are mov of UNSPEC which prevents it from > > >>> the second access in the epilogue being CSEd in cse_local pass with the > > >>> first access in the prologue. > > >>> > > >>> The approach followed here is to create new "combined" set and test > > >>> standard pattern names that take the unexpanded guard and do the set or > > >>> test. This allows the target to use an opaque pattern (eg. using UNSPEC) > > >>> to hide the individual instructions being generated to the compiler and > > >>> split the pattern into generic load, compare and branch instruction > > >>> after register allocator, therefore avoiding any spilling. This is here > > >>> implemented for the ARM targets. For targets not implementing these new > > >>> standard pattern names, the existing stack_protect_set and > > >>> stack_protect_test pattern names are used. > > >>> > > >>> To be able to split PIC access after register allocation, the functions > > >>> had to be augmented to force a new PIC register load and to control > > >>> which register it loads into. This is because sharing the PIC register > > >>> between prologue and epilogue could lead to spilling due to CSE again > > >>> which an attacker could use to control what the canary gets compared > > >>> against. > > >>> > > >>> ChangeLog entries are as follows: > > >>> > > >>> *** gcc/ChangeLog *** > > >>> > > >>> 2018-10-26 Thomas Preud'homme > > >>> > > >>> * target-insns.def (stack_protect_combined_set): Define new standard > > >>> pattern name. > > >>> (stack_protect_combined_test): Likewise. > > >>> * cfgexpand.c (stack_protect_prologue): Try new > > >>> stack_protect_combined_set pattern first. > > >>> * function.c (stack_protect_epilogue): Try new > > >>> stack_protect_combined_test pattern first. > > >>> * config/arm/arm.c (require_pic_register): Add pic_reg and compute_now > > >>> parameters to control which register to use as PIC register and force > > >>> reloading PIC register respectively. Insert in the stream of insns if > > >>> possible. > > >>> (legitimize_pic_address): Expose above new parameters in prototype and > > >>> adapt recursive calls accordingly. Use pic_reg if non null instead of > > >>> cached one. > > >>> (arm_load_pic_register): Add pic_reg parameter and use it if non null. > > >>> (arm_legitimize_address): Adapt to new legitimize_pic_address > > >>> prototype. > > >>> (thumb_legitimize_address): Likewise. > > >>> (arm_emit_call_insn): Adapt to require_pic_register prototype change. > > >>> (arm_expand_prologue): Adapt to arm_load_pic_register prototype change. > > >>> (thumb1_expand_prologue): Likewise. > > >>> * config/arm/arm-protos.h (legitimize_pic_address): Adapt to prototype > > >>
[PR c++/87269] Mark string operator overload in template defn.
This was a case of not marking the overloads of a lookup as immutable,
leading to an assert failure.
Applying to trunk.
nathan
--
Nathan Sidwell
2018-11-16 Nathan Sidwell
PR c++/87269
* parser.c (lookup_literal_operator): Mark overload for keeping
when inside template. Refactor.
* g++.dg/lookup/pr87269.C: New.
Index: cp/parser.c
===
--- cp/parser.c (revision 266204)
+++ cp/parser.c (working copy)
@@ -4259,20 +4259,21 @@ cp_parser_string_literal (cp_parser *par
static tree
lookup_literal_operator (tree name, vec *args)
{
- tree decl;
- decl = lookup_name (name);
+ tree decl = lookup_name (name);
if (!decl || !is_overloaded_fn (decl))
return error_mark_node;
for (lkp_iterator iter (decl); iter; ++iter)
{
- unsigned int ix;
- bool found = true;
tree fn = *iter;
- tree parmtypes = TYPE_ARG_TYPES (TREE_TYPE (fn));
- if (parmtypes != NULL_TREE)
+
+ if (tree parmtypes = TYPE_ARG_TYPES (TREE_TYPE (fn)))
{
- for (ix = 0; ix < vec_safe_length (args) && parmtypes != NULL_TREE;
+ unsigned int ix;
+ bool found = true;
+
+ for (ix = 0;
+ found && ix < vec_safe_length (args) && parmtypes != NULL_TREE;
++ix, parmtypes = TREE_CHAIN (parmtypes))
{
tree tparm = TREE_VALUE (parmtypes);
@@ -4285,6 +4286,7 @@ lookup_literal_operator (tree name, vec<
TREE_TYPE (targ
found = false;
}
+
if (found
&& ix == vec_safe_length (args)
/* May be this should be sufficient_parms_p instead,
@@ -4292,7 +4294,11 @@ lookup_literal_operator (tree name, vec<
work in presence of default arguments on the literal
operator parameters. */
&& parmtypes == void_list_node)
- return decl;
+ {
+ if (processing_template_decl)
+ lookup_keep (decl);
+ return decl;
+ }
}
}
Index: testsuite/g++.dg/lookup/pr87269.C
===
--- testsuite/g++.dg/lookup/pr87269.C (revision 0)
+++ testsuite/g++.dg/lookup/pr87269.C (working copy)
@@ -0,0 +1,15 @@
+// { dg-do compile { target c++11 } }
+// PR c++/87269 ICE failing to keep a lookup
+
+namespace {
+ void operator"" _a (const char *, unsigned long) {}
+}
+
+void operator"" _a (unsigned long long);
+
+template void f () { ""_a; }
+
+void frob ()
+{
+ f ();
+}
Re: [PATCH] Support simd function declarations via a pre-include.
On 11/16/18 2:49 PM, Jakub Jelinek wrote:
> On Fri, Nov 16, 2018 at 02:24:42PM +0100, Martin Liška wrote:
>> + if (gfc_match (" (%n) attributes simd", builtin) != MATCH_YES)
>> +return MATCH_ERROR;
>> +
>> + int builtin_kind = 0;
>> + if (gfc_match (" (notinbranch)") == MATCH_YES)
>
> I think you need " ( notinbranch )" here.
>
>> +builtin_kind = -1;
>> + else if (gfc_match (" (inbranch)") == MATCH_YES)
>> +builtin_kind = 1;
>
> And similarly here (+ testsuite coverage for whether you can in free form
> insert spaces in all the spots that should be allowed).
> !gcc$ builtin ( sinf ) attributes simd ( notinbranch ) ! comment
> e.g. should be valid in free form (and fixed form too).
>
>> --- a/gcc/fortran/gfortran.h
>> +++ b/gcc/fortran/gfortran.h
>> @@ -2764,6 +2764,18 @@ bool gfc_in_match_data (void);
>> match gfc_match_char_spec (gfc_typespec *);
>> extern int directive_unroll;
>>
>> +/* Tuple for parsing of vectorized built-ins. */
>> +struct vect_builtin_tuple
>> +{
>> + vect_builtin_tuple (const char *n, int t): name (n), simd_type (t)
>
> gfc_vect_builtin_tuple ?
> + document what the simd_type is (or make it enum or whatever).
> One option would be enum omp_clause_code and use OMP_CLAUSE_ERROR for
> the case where the argument isn't specified, but I think generally
> gfortran.h doesn't depend on tree* stuff and wants to have its own
> enums etc.
>
>> +extern vec vectorized_builtins;
>
> gfc_vectorized_builtins ?
>
>> --- a/gcc/fortran/trans-intrinsic.c
>> +++ b/gcc/fortran/trans-intrinsic.c
>> @@ -597,7 +597,61 @@ define_quad_builtin (const char *name, tree type, bool
>> is_const)
>>return fndecl;
>> }
>>
>> +/* Add SIMD attribute for FNDECL built-in if the built-in
>> + name is in VECTORIZED_BUILTINS. */
>> +#include "print-tree.h"
>
> If you need to include a header, include it at the start of the file.
>
>> +static void
>> +add_simd_flag_for_built_in (tree fndecl)
>> +{
>> + if (fndecl == NULL_TREE)
>> +return;
>> +
>> + const char *name = IDENTIFIER_POINTER (DECL_NAME (fndecl));
>> + for (unsigned i = 0; i < vectorized_builtins.length (); i++)
>> +if (strcmp (vectorized_builtins[i].name, name) == 0)
>
> How many add_simd_flag_for_built_in calls are we expecting and how many
> vectorized_builtins.length ()? If it is too much, perhaps e.g. sort
> the vector by name and do a binary search. At least if it turns out to be
> non-trivial compile time.
>> +
>> + vectorized_builtins.truncate (0);
>
> That is a memory leak, right? The names are malloced.
> And why truncate rather than release?
>> + const char *path = find_a_file (&include_prefixes, argv[1], R_OK, true);
>> + if (path != NULL)
>> + return concat (argv[0], path, NULL);
>
> Formatting.
>> --- /dev/null
>> +++ b/gcc/testsuite/gfortran.dg/simd-builtins-1.h
>> @@ -0,0 +1,4 @@
>> +!GCC$ builtin (sinf) attributes simd
>> +!GCC$ builtin (sinf) attributes simd (inbranch)
>> +!GCC$ builtin (sinf) attributes simd (notinbranch)
>> +!GCC$ builtin (cosf) attributes simd (notinbranch)
>
> Are you sure it is a good idea to have the 3 first lines for the same
> builtin, rather than different?
>
> It should be testsuite covered what we do in that case, but with the above
> you don't cover what happens e.g. with notinbranch alone, or no argument.
>
> Plus, as I said, I think you should have one *.f and one *.f90 test where
> you just use many of those !gcc$ builtin lines with spaces in various spots
> to verify it is parsed properly.
>
> Jakub
>
Hi.
I'm sending version, I changed the container to hash_map that should provide
faster look up.
I've been testing the patch right now.
Martin
>From bb6061254e8071b0d208c5a2025aeed968dcdefb Mon Sep 17 00:00:00 2001
From: marxin
Date: Wed, 7 Nov 2018 12:41:19 +0100
Subject: [PATCH] Support simd function declarations via a pre-include.
gcc/ChangeLog:
2018-11-15 Martin Liska
* config/gnu-user.h (TARGET_F951_OPTIONS): New.
* gcc.c (find_fortran_preinclude_file): New function
to handle Fortran pre-include.
gcc/fortran/ChangeLog:
2018-11-15 Martin Liska
* decl.c (gfc_match_gcc_builtin): New function.
* gfortran.h (struct vect_builtin_tuple): New.
(gfc_adjust_builtins): Likewise.
* lang-specs.h (TARGET_F951_OPTIONS): New.
(F951_OPTIONS): Use it.
* lang.opt: Add new option -fpre-include.
* match.h (gfc_match_gcc_builtin): Declare new function.
* parse.c (decode_gcc_attribute): Handle builtin.
(parse_progunit): Call gfc_adjust_builtins.
* scanner.c (gfc_new_file): Load pre-included header file
when provided.
* trans-intrinsic.c (add_simd_flag_for_built_in): New.
(gfc_adjust_builtins): Likewise.
gcc/testsuite/ChangeLog:
2018-11-15 Martin Liska
* gfortran.dg/simd-builtins-1.f90: New test.
* gfortran.dg/simd-builtins-1.h: New test.
* gfortran.dg/simd-builtins-2.f90: New test.
* gfortran.dg/simd-builtins-3.f90: New test.
* gfortran.dg/simd-builtins-3.h: New test.
* gfortran.dg/simd-builtins-4.f: New test.
*
Re: [PATCH] diagnose unsupported uses of hardware register variables (PR 88000)
Hi,
On Thu, 15 Nov 2018, Alexander Monakov wrote:
> Reading the documentation certainly does not make that impression to me.
> In any case, can you elaborate a bit further please:
>
> 1. Regarding the comparison to 'volatile' qualifier. Suppose you have an
> automatic variable 'int v;' in a correct program. The variable is only used
> for some arithmetic, never passed to asms, does not have its address taken.
I should have been more precise, I meant volatile and mapped to some
device memory. I.e. a register variable is never automatic in that sense.
Every read can return different values even without intervening changes in
source code.
> 2. Are testcases given in PR 87984 valid? Quoting the latest example:
>
> int f(void)
> {
> int o=0, i;
> for (i=0; i<3; i++) {
> register int a asm("eax");
> a = 1;
> asm("add %1, %0" : "+r"(o) : "r"(a));
> asm("xor %%eax, %%eax" ::: "eax");
> }
> return o;
> }
Which is indeed what happens here.
> This follows both your model
Not really, it ignores the fact that 'a' can change at any time, which is
what happens.
> and the documentation to the letter, and yet will return 1 rather than
> 3.
>
> I disagree that it is practical to implement your model on GIMPLE.
I claim that that is what is implemented right now.
Ciao,
Michael.
Re: [PATCH]Come up with -flive-patching master option.
On 11/16/18 2:36 AM, Qing Zhao wrote:
> Hi,
>
> this is the new version of the patch.
>
> I have bootstrapped it on both aarch64 and x86, no regression.
>
> please take a look.
Thanks for the updated version of the patch.
I have last small nits I see:
- gcc/common.opt: when running --help=common, the line is too long
- gcc/doc/invoke.texi - 2 spaces in between sentences + better gol
- gcc/opts.c - do not mix spaces + tabs
With that I'm fine. But note that I'm not a maintainer :)
Thanks,
Martin
>
> Okay for commit?
>
> thanks.
>
> Qing
>
> ==
>
> gcc/ChangeLog:
>
> 2018-11-15 qing zhao
>
> * cif-code.def (EXTERN_LIVE_ONLY_STATIC): New CIF code.
> * common.opt: Add -flive-patching flag.
> * doc/invoke.texi: Document -flive-patching.
> * flag-types.h (enum live_patching_level): New enum.
> * ipa-inline.c (can_inline_edge_p): Disable external functions from
> inlining when flag_live_patching is LIVE_PATCHING_INLINE_ONLY_STATIC.
> * opts.c (control_optimizations_for_live_patching): New function.
> (finish_options): Make flag_live_patching incompatible with flag_lto.
> (common_handle_option): Handle flive-patching flag.
>
> gcc/testsuite/ChangeLog:
>
> 2018-11-15 qing zhao
>
> * gcc.dg/live-patching-1.c: New test.
> * gcc.dg/live-patching-2.c: New test.
> * gcc.dg/tree-ssa/writeonly-3.c: New test.
> * gcc.target/i386/ipa-stack-alignment-2.c: New test.
>
>From e44d8b88ac5fb712d5b5e7fdf2f2ad7f43b8ea09 Mon Sep 17 00:00:00 2001
From: marxin
Date: Fri, 16 Nov 2018 16:23:44 +0100
Subject: [PATCH] my fixes.
---
gcc/common.opt | 3 +--
gcc/doc/invoke.texi | 8
gcc/opts.c | 2 +-
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/gcc/common.opt b/gcc/common.opt
index 63cd6cc851d..35c24b8e8cf 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -2187,8 +2187,7 @@ Common RejectNegative Alias(flive-patching=,inline-clone) Optimization
flive-patching=
Common Report Joined RejectNegative Enum(live_patching_level) Var(flag_live_patching) Init(LIVE_PATCHING_NONE) Optimization
-flive-patching=[inline-only-static|inline-clone] Control IPA
-optimizations to provide a safe compilation for live-patching. At the same
-time, provides multiple-level control on the enabled IPA optimizations.
+optimizations to provide a safe compilation for live-patching.
Enum
Name(live_patching_level) Type(enum live_patching_level) UnknownError(unknown Live-Patching Level %qs)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0fb67163490..94455fa 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -9288,13 +9288,13 @@ impacted function of the former. If a function is patched, its impacted
functions should be patched too.
The impacted functions are decided by the compiler's interprocedural
-optimizations. For example, inlining a function into its caller, cloning
+optimizations. For example, inlining a function into its caller, cloning
a function and changing its caller to call this new clone, or extracting
a function's pureness/constness information to optimize its direct or
indirect callers, etc.
Usually, the more IPA optimizations enabled, the larger the number of
-impacted functions for each function. In order to control the number of
+impacted functions for each function. In order to control the number of
impacted functions and computed the list of impacted function easily,
we provide control to partially enable IPA optimizations on two different
levels.
@@ -9313,8 +9313,8 @@ callers need to be patched as well.
@option{-flive-patching=inline-clone} disables the following optimization flags:
@gccoptlist{-fwhole-program -fipa-pta -fipa-reference -fipa-ra @gol
-fipa-icf -fipa-icf-functions -fipa-icf-variables @gol
--fipa-bit-cp -fipa-vrp -fipa-pure-const -fipa-reference-addressable @gol
--fipa-stack-alignment}
+-fipa-bit-cp -fipa-vrp -fipa-pure-const @gol
+-fipa-reference-addressable -fipa-stack-alignment}
@item inline-only-static
diff --git a/gcc/opts.c b/gcc/opts.c
index 570155816e3..0b5e89faeee 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -2347,7 +2347,7 @@ common_handle_option (struct gcc_options *opts,
case OPT_flive_patching_:
if (value)
- control_optimizations_for_live_patching (opts, opts_set,
+ control_optimizations_for_live_patching (opts, opts_set,
opts->x_flag_live_patching);
break;
--
2.19.1
Re: [PATCH] Strenghten assumption about function start and end line (PR gcov-profile/88045).
On 11/16/18 6:48 AM, Martin Liška wrote: > Hi. > > As mentioned in the PR, we should guarantee that a function ends before > it starts (from source line perspective). > > For gcc-8 branch, a work-around would be needed. > > Survives tests and bootstrap on x86_64-linux-gnu. > Ready for trunk and gcc-8 branch? > Thanks, > Martin > > gcc/ChangeLog: > > 2018-11-16 Martin Liska > > PR gcov/88045 > * coverage.c (coverage_begin_function): Add assert. > > gcc/testsuite/ChangeLog: > > 2018-11-16 Martin Liska > > PR gcov/88045 > * g++.dg/gcov/pr88045.C: New test. OK for the trunk. And the work-around for gcc-8 branch is OK as well assuming you think it's worth fixing. jeff
Re: [PATCH] Fix expand_binop (PR middle-end/88032)
On 11/16/18 1:49 AM, Jakub Jelinek wrote: > Hi! > > On Wed, Nov 14, 2018 at 09:35:30AM -0700, Jeff Law wrote: >> +* optabs.c (expand_binop): Pass INT_MODE to operand_subword_force >> +iff the operand is a constant. > > This broke gcc.target/i386/pr80173.c testcase. The problem is > that while operand_subword handles VOIDmode last argument just fine > by using GET_MODE (op), so it is only important to use non-VOIDmode if > op has VOIDmode. But, operand_subword_force actually has a different > behavior, if mode is VOIDmode (or BLKmode), it acts just as operand_subword > followed by assertion that it succeeded, rather than by trying to deal with > failed operand_subword by forcing it into a pseudo. > > In the testcase, op is a hard register, on which operand_subword fails, but > if it is forced into pseudo, it succeeds. > > The following patch arranges it by never passing VOIDmode to > operand_subword_force, pass int_mode as previously if opN has VOIDmode, but > instead of passing VOIDmode otherwise pass the actual mode of the opN > operand. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2018-11-16 Jakub Jelinek > > PR middle-end/88032 > * optabs.c (expand_binop): For op0_mode use GET_MODE (op0), unless it > is VOIDmode, in which case use int_mode. Similarly for op1_mode. Yea, that's fine too -- I had this variant in my tree until the last cycle of testing where I changed it to VOIDmode :-) Sorry for the breakage. jeff
[ARM/FDPIC v4 00/20] FDPIC ABI for ARM
From: Christophe Lyon Hello, This patch series implements the GCC contribution of the FDPIC ABI for ARM targets. This ABI enables to run Linux on ARM MMU-less cores and supports shared libraries to reduce the memory footprint. Without MMU, text and data segments relative distances are different from one process to another, hence the need for a dedicated FDPIC register holding the start address of the data segment. One of the side effects is that function pointers require two words to be represented: the address of the code, and the data segment start address. These two words are designated as "Function Descriptor", hence the "FD PIC" name. On ARM, the FDPIC register is r9 [1], and the target name is arm-uclinuxfdpiceabi. Note that arm-uclinux exists, but uses another ABI and the BFLAT file format; it does not support code sharing. The -mfdpic option is enabled by default, and -mno-fdpic should be used to build the Linux kernel. This work was developed some time ago by STMicroelectronics, and was presented during Linaro Connect SFO15 (September 2015). You can watch the discussion and read the slides [2]. This presentation was related to the toolchain published on github [3], which is based on binutils-2.22, gcc-4.7, uclibc-0.9.33.2, gdb-7.5.1 and qemu-2.3.0, and for which pre-built binaries are available [3]. The ABI itself is described in details in [1]. Our Linux kernel patches have been updated and committed by Nicolas Pitre (Linaro) in July 2017. They are required so that the loader is able to handle this new file type. Indeed, the ELF files are tagged with ELFOSABI_ARM_FDPIC. This new tag has been allocated by ARM, as well as the new relocations involved. The binutils, QEMU and uclibc-ng patch series have been merged recently. [4][5][6] This series provides support for architectures that support ARM and/or Thumb-2 and has been tested on arm-linux-gnueabi without regression, as well as arm-uclinuxfdpiceabi, using QEMU. arm-uclinuxfdpiceabi has more failures than arm-linux-gnueabi, but is quite functional. Are the GCC patches OK for inclusion in master? Changes between v3 and v4: - improved documentation (patch 1) - emit an error message (sorry) if the target architecture does not support arm nor thumb-2 modes (patch 4) - handle Richard's comments on patch 4 (comments, unspec) - added .align directive (patch 5) - fixed use of kernel helpers (__kernel_cmpxchg, __kernel_dmb) (patch 6) - code factorization in patch 7 - typos/internal function name in patch 8 - improved patch 12 - dropped patch 16 - patch 20 introduces arm_arch*_thumb_ok effective targets to help skip some tests - I tested patch 2 on xtensa-buildroot-uclinux-uclibc, it adds many new tests, but a few regressions (https://gcc.gnu.org/ml/gcc-patches/2018-11/msg00713.html) - I compiled and executed several LTP tests to exercise pthreads and signals - I wrote and executed a simple testcase to change the interaction with __kernel_cmpxchg (ie. call the kernel helper rather than use an implementation in libgcc as requested by Richard) Changes between v2 and v3: - added doc entry for -mfdpic new option - took Kyrill's comments into account (use "Armv7" instead of "7", code factorization, use preprocessor instead of hard-coding "r9", remove leftover code for thumb1 support, fixed comments) - rebase over recent trunk - patches with changes: 1, 2 (commit message), 3 (rebase), 4, 6, 7, 9, 14 (rebase), 19 (rebase) Changes between v1 and v2: - fix GNU coding style - exit with an error for pre-Armv7 - use ACLE __ARM_ARCH and remove dead code for pre-Armv4 - remove unsupported attempts of pre-Armv7/thumb1 support - add instructions in comments next to opcodes - merge patches 11 and 13 - fixed protected visibility handling in patch 8 - merged legitimize_tls_address_fdpic and legitimize_tls_address_not_fdpic as requested Thanks, Christophe. [1] https://github.com/mickael-guene/fdpic_doc/blob/master/abi.txt [2] http://connect.linaro.org/resource/sfo15/sfo15-406-arm-fdpic-toolset-kernel-libraries-for-cortex-m-cortex-r-mmuless-cores/ [3] https://github.com/mickael-guene/fdpic_manifest [4] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=f1ac0afe481e83c9a33f247b81fa7de789edc4d9 [5] https://git.qemu.org/?p=qemu.git;a=commit;h=e8fa72957419c11984608062c7dcb204a6003a06 [6] https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/commit/?id=13c46fbc1e5a021f2b9ed32d83aecc93ae5e655d Christophe Lyon (20): [ARM] FDPIC: Add -mfdpic option support [ARM] FDPIC: Handle arm*-*-uclinuxfdpiceabi in configure scripts [ARM] FDPIC: Force FDPIC related options unless -mno-fdpic is provided [ARM] FDPIC: Add support for FDPIC for arm architecture [ARM] FDPIC: Fix __do_global_dtors_aux and frame_dummy generation [ARM] FDPIC: Add support for c++ exceptions [ARM] FDPIC: Avoid saving/restoring r9 on stack since it is read-only [ARM] FDPIC: Enforce local/global binding for function descriptors [ARM] FDPIC: Add suppor
[ARM/FDPIC v4 01/20] [ARM] FDPIC: Add -mfdpic option support
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.opt: Add -mfdpic option.
* doc/invoke.texi: Add documentation for -mfdpic.
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index a1286a4..231c1cb 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -302,3 +302,7 @@ When linking for big-endian targets, generate a legacy BE32
format image.
mbranch-cost=
Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1)
Cost to assume for a branch insn.
+
+mfdpic
+Target Report Mask(FDPIC)
+Enable Function Descriptor PIC mode.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 535b258..6b08b09 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -691,7 +691,8 @@ Objective-C and Objective-C++ Dialects}.
-mrestrict-it @gol
-mverbose-cost-dump @gol
-mpure-code @gol
--mcmse}
+-mcmse @gol
+-mfdpic}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -mabsdata -maccumulate-args @gol
@@ -17538,6 +17539,23 @@ MOVT instruction.
Generate secure code as per the "ARMv8-M Security Extensions: Requirements on
Development Tools Engineering Specification", which can be found on
@url{http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf}.
+
+@item -mfdpic
+@itemx -mno-fdpic
+@opindex mfdpic
+@opindex mno-fdpic
+Select the FDPIC ABI, which uses function descriptors to represent
+pointers to functions. When the compiler is configured for
+@code{arm-*-uclinuxfdpiceabi} targets, this option is on by default
+and implies @option{-fPIE} if none of the PIC/PIE-related options is
+provided. On other targets, it only enables the FDPIC-specific code
+generation features, and the user should explicitly provide the
+PIC/PIE-related options as needed.
+
+The opposite @option{-mno-fdpic} option is useful (and required) to
+build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi})
+toolchain as the one used to build the userland programs.
+
@end table
@node AVR Options
--
2.6.3
[ARM/FDPIC v4 03/20] [ARM] FDPIC: Force FDPIC related options unless -mno-fdpic is provided
In FDPIC mode, we set -fPIE unless the user provides -fno-PIE, -fpie,
-fPIC or -fpic: indeed FDPIC code is PIC, but we want to generate code
for executables rather than shared libraries by default.
We also make sure to use the --fdpic assembler option, and select the
appropriate linker emulation.
At link time, we also default to -pie, unless we are generating a
shared library or a relocatable file (-r). Note that even for static
link, we must specify the dynamic linker because the executable still
has to relocate itself at startup.
We also force 'now' binding since lazy binding is not supported.
We should also apply the same behavior for -Wl,-Ur as for -r, but I
couldn't find how to describe that in the specs fragment.
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config.gcc: Handle arm*-*-uclinuxfdpiceabi.
* config/arm/bpabi.h (TARGET_FDPIC_ASM_SPEC): New.
(SUBTARGET_EXTRA_ASM_SPEC): Use TARGET_FDPIC_ASM_SPEC.
* config/arm/linux-eabi.h (FDPIC_CC1_SPEC): New.
(CC1_SPEC): Use FDPIC_CC1_SPEC.
* config/arm/uclinuxfdpiceabi.h: New file.
libsanitizer/
* configure.tgt (arm*-*-uclinuxfdpiceabi): Sanitizers are
unsupported in this configuration.
Change-Id: If369e0a10bb916fd72e38f71498d3c640fa85c4c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6bfa329..975e293 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1175,6 +1175,11 @@ arm*-*-linux-* | arm*-*-uclinuxfdpiceabi)
# ARM GNU/Linux with ELF
esac
tmake_file="${tmake_file} arm/t-arm arm/t-arm-elf arm/t-bpabi
arm/t-linux-eabi"
tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h arm/aout.h arm/arm.h"
+ case $target in
+ arm*-*-uclinuxfdpiceabi)
+ tm_file="$tm_file arm/uclinuxfdpiceabi.h"
+ ;;
+ esac
# Generation of floating-point instructions requires at least ARMv5te.
if [ "$with_float" = "hard" -o "$with_float" = "softfp" ] ; then
target_cpu_cname="arm10e"
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 1e3ecfb..5901154 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -55,6 +55,8 @@
#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\
"|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}"
+#define TARGET_FDPIC_ASM_SPEC ""
+
#define BE8_LINK_SPEC \
"%{!r:%{!mbe32:%:be8_linkopt(%{mlittle-endian:little}" \
" %{mbig-endian:big}" \
@@ -64,7 +66,7 @@
/* Tell the assembler to build BPABI binaries. */
#undef SUBTARGET_EXTRA_ASM_SPEC
#define SUBTARGET_EXTRA_ASM_SPEC \
- "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC
+ "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC
TARGET_FDPIC_ASM_SPEC
#ifndef SUBTARGET_EXTRA_LINK_SPEC
#define SUBTARGET_EXTRA_LINK_SPEC ""
diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
index 4254b19..af4b740 100644
--- a/gcc/config/arm/linux-eabi.h
+++ b/gcc/config/arm/linux-eabi.h
@@ -101,11 +101,14 @@
#undef ASAN_CC1_SPEC
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
+#define FDPIC_CC1_SPEC ""
+
#undef CC1_SPEC
#define CC1_SPEC \
- LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC, \
+ LINUX_OR_ANDROID_CC (GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC " " \
+ FDPIC_CC1_SPEC, \
GNU_USER_TARGET_CC1_SPEC " " ASAN_CC1_SPEC " " \
- ANDROID_CC1_SPEC)
+ ANDROID_CC1_SPEC "" FDPIC_CC1_SPEC)
#define CC1PLUS_SPEC \
LINUX_OR_ANDROID_CC ("", ANDROID_CC1PLUS_SPEC)
diff --git a/gcc/config/arm/uclinuxfdpiceabi.h
b/gcc/config/arm/uclinuxfdpiceabi.h
new file mode 100644
index 000..43a17de
--- /dev/null
+++ b/gcc/config/arm/uclinuxfdpiceabi.h
@@ -0,0 +1,53 @@
+/* Configuration file for ARM GNU/Linux FDPIC EABI targets.
+ Copyright (C) 2018 Free Software Foundation, Inc.
+ Contributed by STMicroelectronics.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+
[ARM/FDPIC v4 02/20] [ARM] FDPIC: Handle arm*-*-uclinuxfdpiceabi in configure scripts
The new arm-uclinuxfdpiceabi target behaves pretty much like
arm-linux-gnueabi. In order the enable the same set of features, we
have to update several configure scripts that generally match targets
like *-*-linux*: in most places, we add *-uclinux* where there is
already *-linux*, or uclinux* when there is already linux*.
In gcc/config.gcc and libgcc/config.host we use *-*-uclinuxfdpiceabi
because there is already a different behaviour for *-*uclinux* target.
In libtool.m4, we use uclinuxfdpiceabi in cases where ELF shared
libraries support is required, as uclinux does not guarantee that.
2018-XX-XX Christophe Lyon
config/
* futex.m4: Handle *-uclinux*.
* tls.m4 (GCC_CHECK_TLS): Likewise.
gcc/
* config.gcc: Handle *-*-uclinuxfdpiceabi.
libatomic/
* configure.tgt: Handle arm*-*-uclinux*.
* configure: Regenerate.
libgcc/
* config.host: Handle *-*-uclinuxfdpiceabi.
libitm/
* configure.tgt: Handle *-*-uclinux*.
* configure: Regenerate.
libstdc++-v3/
* acinclude.m4: Handle uclinux*.
* configure: Regenerate.
* configure.host: Handle uclinux*
* libtool.m4: Handle uclinux*.
Change-Id: I6a1fdcd9847d8a82179a214612a3474c1f492916
diff --git a/config/futex.m4 b/config/futex.m4
index e95144d..4dffe15 100644
--- a/config/futex.m4
+++ b/config/futex.m4
@@ -9,7 +9,7 @@ AC_DEFUN([GCC_LINUX_FUTEX],[dnl
GCC_ENABLE(linux-futex,default, ,[use the Linux futex system call],
permit yes|no|default)
case "$target" in
- *-linux*)
+ *-linux* | *-uclinux*)
case "$enable_linux_futex" in
default)
# If headers don't have gettid/futex syscalls definition, then
diff --git a/config/tls.m4 b/config/tls.m4
index 1a5fc59..a487aa4 100644
--- a/config/tls.m4
+++ b/config/tls.m4
@@ -76,7 +76,7 @@ AC_DEFUN([GCC_CHECK_TLS], [
dnl Shared library options may depend on the host; this check
dnl is only known to be needed for GNU/Linux.
case $host in
- *-*-linux*)
+ *-*-linux* | -*-uclinux*)
LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
;;
esac
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8525cb5..6bfa329 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -780,7 +780,7 @@ case ${target} in
*-*-fuchsia*)
native_system_header_dir=/include
;;
-*-*-linux* | frv-*-*linux* | *-*-kfreebsd*-gnu | *-*-gnu* |
*-*-kopensolaris*-gnu)
+*-*-linux* | frv-*-*linux* | *-*-kfreebsd*-gnu | *-*-gnu* |
*-*-kopensolaris*-gnu | *-*-uclinuxfdpiceabi)
extra_options="$extra_options gnu-user.opt"
gas=yes
gnu_ld=yes
@@ -789,7 +789,7 @@ case ${target} in
esac
tmake_file="t-slibgcc"
case $target in
-*-*-linux* | frv-*-*linux* | *-*-kfreebsd*-gnu | *-*-kopensolaris*-gnu)
+*-*-linux* | frv-*-*linux* | *-*-kfreebsd*-gnu | *-*-kopensolaris*-gnu |
*-*-uclinuxfdpiceabi)
:;;
*-*-gnu*)
native_system_header_dir=/include
@@ -809,7 +809,7 @@ case ${target} in
*-*-*android*)
tm_defines="$tm_defines DEFAULT_LIBC=LIBC_BIONIC"
;;
-*-*-*uclibc*)
+*-*-*uclibc* | *-*-uclinuxfdpiceabi)
tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
;;
*-*-*musl*)
@@ -1165,7 +1165,7 @@ arm*-*-netbsdelf*)
tmake_file="${tmake_file} arm/t-arm"
target_cpu_cname="strongarm"
;;
-arm*-*-linux-*)# ARM GNU/Linux with ELF
+arm*-*-linux-* | arm*-*-uclinuxfdpiceabi) # ARM GNU/Linux
with ELF
tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h
glibc-stdint.h arm/elf.h arm/linux-gas.h arm/linux-elf.h"
extra_options="${extra_options} linux-android.opt"
case $target in
diff --git a/libatomic/configure b/libatomic/configure
index e7076a0..10b0287 100755
--- a/libatomic/configure
+++ b/libatomic/configure
@@ -6055,7 +6055,7 @@ irix5* | irix6* | nonstopux*)
;;
# This must be Linux ELF.
-linux* | k*bsd*-gnu | kopensolaris*-gnu)
+linux* | k*bsd*-gnu | kopensolaris*-gnu | uclinuxfdpiceabi)
lt_cv_deplibs_check_method=pass_all
;;
@@ -8540,7 +8540,7 @@ $as_echo_n "checking for $compiler option to produce
PIC... " >&6; }
lt_prog_compiler_static='-non_shared'
;;
-linux* | k*bsd*-gnu | kopensolaris*-gnu)
+linux* | k*bsd*-gnu | kopensolaris*-gnu | uclinux*)
case $cc_basename in
# old Intel for x86_64 which still supported -KPIC.
ecc*)
@@ -9135,7 +9135,7 @@ _LT_EOF
archive_expsym_cmds='sed "s,^,_," $export_symbols
>$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs
$compiler_flags ${wl}-h,$soname
${wl}--retain-symbols-file,$output_objdir/$soname.expsym
${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
;;
-gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu)
+gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu | uclinuxfdp
[ARM/FDPIC v4 04/20] [ARM] FDPIC: Add support for FDPIC for arm architecture
The FDPIC register is hard-coded to r9, as defined in the ABI.
We have to disable tailcall optimizations if we don't know if the
target function is in the same module. If not, we have to set r9 to
the value associated with the target module.
When generating a symbol address, we have to take into account whether
it is a pointer to data or to a function, because different
relocations are needed.
2018-XX-XX Christophe Lyon
Mickaël Guêné
* config/arm/arm-c.c (__FDPIC__): Define new pre-processor macro
in FDPIC mode.
* config/arm/arm-protos.h (arm_load_function_descriptor): Declare
new function.
* config/arm/arm.c (arm_option_override): Define pic register to
FDPIC_REGNUM.
(arm_function_ok_for_sibcall): Disable sibcall optimization if we
have no decl or go through PLT.
(arm_load_pic_register): Handle TARGET_FDPIC.
(arm_is_segment_info_known): New function.
(arm_pic_static_addr): Add support for FDPIC.
(arm_load_function_descriptor): New function.
(arm_assemble_integer): Add support for FDPIC.
* config/arm/arm.h (PIC_OFFSET_TABLE_REG_CALL_CLOBBERED):
Define. (FDPIC_REGNUM): New define.
* config/arm/arm.md (call): Add support for FDPIC.
(call_value): Likewise.
(*restore_pic_register_after_call): New pattern.
(untyped_call): Disable if FDPIC.
(untyped_return): Likewise.
* config/arm/unspecs.md (UNSPEC_PIC_RESTORE): New.
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 4471f79..90733cc 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -202,6 +202,8 @@ arm_cpu_builtins (struct cpp_reader* pfile)
builtin_define ("__ARM_EABI__");
}
+ def_or_undef_macro (pfile, "__FDPIC__", TARGET_FDPIC);
+
def_or_undef_macro (pfile, "__ARM_ARCH_EXT_IDIV__", TARGET_IDIV);
def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV);
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 8d6d2395..314f710 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -136,6 +136,7 @@ extern int arm_max_const_double_inline_cost (void);
extern int arm_const_double_inline_cost (rtx);
extern bool arm_const_double_by_parts (rtx);
extern bool arm_const_double_by_immediates (rtx);
+extern rtx arm_load_function_descriptor (rtx funcdesc);
extern void arm_emit_call_insn (rtx, rtx, bool);
bool detect_cmse_nonsecure_call (tree);
extern const char *output_call (rtx *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 8393f0b..63c68e5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3475,6 +3475,15 @@ arm_option_override (void)
if (flag_pic && TARGET_VXWORKS_RTP)
arm_pic_register = 9;
+ /* If in FDPIC mode then force arm_pic_register to be r9. */
+ if (TARGET_FDPIC)
+{
+ arm_pic_register = FDPIC_REGNUM;
+ if (! TARGET_ARM && ! TARGET_THUMB2)
+ sorry ("FDPIC mode is supported on architecture versions that "
+ "support ARM or Thumb-2 only.");
+}
+
if (arm_pic_register_string != NULL)
{
int pic_register = decode_reg_name (arm_pic_register_string);
@@ -7259,6 +7268,21 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
if (cfun->machine->sibcall_blocked)
return false;
+ if (TARGET_FDPIC)
+{
+ /* In FDPIC, never tailcall something for which we have no decl:
+the target function could be in a different module, requiring
+a different FDPIC register value. */
+ if (decl == NULL)
+ return false;
+
+ /* Don't tailcall if we go through the PLT since the FDPIC
+register is then corrupted and we don't restore it after
+static function calls. */
+ if (!targetm.binds_local_p (decl))
+ return false;
+}
+
/* Never tailcall something if we are generating code for Thumb-1. */
if (TARGET_THUMB1)
return false;
@@ -7637,7 +7661,9 @@ arm_load_pic_register (unsigned long saved_regs
ATTRIBUTE_UNUSED)
{
rtx l1, labelno, pic_tmp, pic_rtx, pic_reg;
- if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
+ if (crtl->uses_pic_offset_table == 0
+ || TARGET_SINGLE_PIC_BASE
+ || TARGET_FDPIC)
return;
gcc_assert (flag_pic);
@@ -7705,28 +7731,142 @@ arm_load_pic_register (unsigned long saved_regs
ATTRIBUTE_UNUSED)
emit_use (pic_reg);
}
+/* Try to determine whether an object, referenced via ORIG, will be
+ placed in the text or data segment. This is used in FDPIC mode, to
+ decide which relocations to use when accessing ORIG. IS_READONLY
+ is set to true if ORIG is a read-only location, false otherwise.
+ Return true if we could determine the location of ORIG, false
+ otherwise. IS_READONLY is valid only when we return true. */
+static bool
+arm_is_segment_info_known (rtx orig, bool *is_readonly)
+{
+ bool res = false;
+
+ *is_readonly = false;
+
+ if
[ARM/FDPIC v4 05/20] [ARM] FDPIC: Fix __do_global_dtors_aux and frame_dummy generation
In FDPIC, we need to make sure __do_global_dtors_aux and frame_dummy
are referenced by their address, not by pointers to the function
descriptors.
2018-XX-XX Christophe Lyon
Mickaël Guêné
* libgcc/crtstuff.c: Add support for FDPIC.
diff --git a/libgcc/crtstuff.c b/libgcc/crtstuff.c
index d81c527..8d4ce81 100644
--- a/libgcc/crtstuff.c
+++ b/libgcc/crtstuff.c
@@ -429,9 +429,18 @@ __do_global_dtors_aux (void)
#ifdef FINI_SECTION_ASM_OP
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
+#if defined(__FDPIC__)
+__asm__(
+" .section .fini_array\n"
+" .align 2\n"
+" .word __do_global_dtors_aux\n"
+);
+asm (TEXT_SECTION_ASM_OP);
+#else /* defined(__FDPIC__) */
static func_ptr __do_global_dtors_aux_fini_array_entry[]
__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(func_ptr
= { __do_global_dtors_aux };
+#endif /* defined(__FDPIC__) */
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
static void __attribute__((used))
__do_global_dtors_aux_1 (void)
@@ -473,9 +482,18 @@ frame_dummy (void)
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
+#if defined(__FDPIC__)
+__asm__(
+" .section .init_array\n"
+" .align 2\n"
+" .word frame_dummy\n"
+);
+asm (TEXT_SECTION_ASM_OP);
+#else /* defined(__FDPIC__) */
static func_ptr __frame_dummy_init_array_entry[]
__attribute__ ((__used__, section(".init_array"), aligned(sizeof(func_ptr
= { frame_dummy };
+#endif /* defined(__FDPIC__) */
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */
--
2.6.3
[ARM/FDPIC v4 06/20] [ARM] FDPIC: Add support for c++ exceptions
The main difference with existing support is that function addresses
are function descriptor addresses instead. This means that all code
dealing with function pointers now has to cope with function
descriptors instead.
For the same reason, Linux kernel helpers can no longer be called by
dereferencing their address, so we implement wrappers that directly
call the kernel helpers.
When restoring a function address, we also have to restore the FDPIC
register value (r9).
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* ginclude/unwind-arm-common.h (unwinder_cache): Add reserved5
field.
(FDPIC_REGNUM): New define.
libgcc/
* config/arm/linux-atomic.c (__kernel_cmpxchg): Add FDPIC support.
(__kernel_dmb): Likewise.
(__fdpic_cmpxchg): New function.
(__fdpic_dmb): New function.
* config/arm/unwind-arm.h (FDPIC_REGNUM): New define.
(gnu_Unwind_Find_got): New function.
(_Unwind_decode_typeinfo_ptr): Add FDPIC support.
* unwind-arm-common.inc (UCB_PR_GOT): New.
(funcdesc_t): New struct.
(get_eit_entry): Add FDPIC support.
(unwind_phase2): Likewise.
(unwind_phase2_forced): Likewise.
(__gnu_Unwind_RaiseException): Likewise.
(__gnu_Unwind_Resume): Likewise.
(__gnu_Unwind_Backtrace): Likewise.
* unwind-pe.h (read_encoded_value_with_base): Likewise.
libstdc++/
* libsupc++/eh_personality.cc (get_ttype_entry): Add FDPIC
support.
diff --git a/gcc/ginclude/unwind-arm-common.h b/gcc/ginclude/unwind-arm-common.h
index 8a1a919..150bd0f 100644
--- a/gcc/ginclude/unwind-arm-common.h
+++ b/gcc/ginclude/unwind-arm-common.h
@@ -91,7 +91,7 @@ extern "C" {
_uw reserved2; /* Personality routine address */
_uw reserved3; /* Saved callsite address */
_uw reserved4; /* Forced unwind stop arg */
- _uw reserved5;
+ _uw reserved5; /* Personality routine GOT value in FDPIC mode. */
}
unwinder_cache;
/* Propagation barrier cache (valid after phase 1): */
diff --git a/libgcc/config/arm/linux-atomic.c b/libgcc/config/arm/linux-atomic.c
index d334c58..f8836ba 100644
--- a/libgcc/config/arm/linux-atomic.c
+++ b/libgcc/config/arm/linux-atomic.c
@@ -25,11 +25,62 @@ see the files COPYING3 and COPYING.RUNTIME respectively.
If not, see
/* Kernel helper for compare-and-exchange. */
typedef int (__kernel_cmpxchg_t) (int oldval, int newval, int *ptr);
-#define __kernel_cmpxchg (*(__kernel_cmpxchg_t *) 0x0fc0)
+
+#define STR(X) #X
+#define XSTR(X) STR(X)
+
+#define KERNEL_CMPXCHG 0x0fc0
+
+#if __FDPIC__
+/* Non-FDPIC ABIs call __kernel_cmpxchg directly by dereferencing its
+ address, but under FDPIC we would generate a broken call
+ sequence. That's why we have to implement __kernel_cmpxchg and
+ __kernel_dmb here: this way, the FDPIC call sequence works. */
+#define __kernel_cmpxchg __fdpic_cmpxchg
+#else
+#define __kernel_cmpxchg (*(__kernel_cmpxchg_t *) KERNEL_CMPXCHG)
+#endif
/* Kernel helper for memory barrier. */
typedef void (__kernel_dmb_t) (void);
-#define __kernel_dmb (*(__kernel_dmb_t *) 0x0fa0)
+
+#define KERNEL_DMB 0x0fa0
+
+#if __FDPIC__
+#define __kernel_dmb __fdpic_dmb
+#else
+#define __kernel_dmb (*(__kernel_dmb_t *) KERNEL_DMB)
+#endif
+
+#if __FDPIC__
+static int __fdpic_cmpxchg (int oldval, int newval, int *ptr)
+{
+ int result;
+
+ asm volatile (
+ "ldrip, 1f\n\t"
+ "bx ip\n\t"
+ "1:\n\t"
+ ".word " XSTR(KERNEL_CMPXCHG) "\n\t"
+ : "=r" (result)
+ : "r" (oldval) , "r" (newval), "r" (ptr)
+ : "r3", "memory");
+ /* The result is actually returned by the kernel helper, we need
+ this to avoid a warning. */
+ return result;
+}
+
+static void __fdpic_dmb (void)
+{
+ asm volatile (
+ "ldrip, 1f\n\t"
+ "bx ip\n\t"
+ "1:\n\t"
+ ".word " XSTR(KERNEL_DMB) "\n\t"
+ );
+}
+
+#endif
/* Note: we implement byte, short and int versions of atomic operations using
the above kernel helpers; see linux-atomic-64bit.c for "long long" (64-bit)
diff --git a/libgcc/config/arm/unwind-arm.h b/libgcc/config/arm/unwind-arm.h
index 9f7d3f2..9cb6fd8 100644
--- a/libgcc/config/arm/unwind-arm.h
+++ b/libgcc/config/arm/unwind-arm.h
@@ -33,9 +33,33 @@
/* Use IP as a scratch register within the personality routine. */
#define UNWIND_POINTER_REG 12
+#define FDPIC_REGNUM 9
+
+#define STR(x) #x
+#define XSTR(x) STR(x)
+
#ifdef __cplusplus
extern "C" {
#endif
+_Unwind_Ptr __attribute__((weak)) __gnu_Unwind_Find_got (_Unwind_Ptr);
+
+static inline _Unwind_Ptr gnu_Unwind_Find_got (_Unwind_Ptr ptr)
+{
+_Unwind_Ptr res;
+
+if (__gnu_Unwind_Find_got)
+ res = __gnu_Unwind_Find_got (ptr);
+else
+ {
+ asm volatile ("mov %[result], r" XSTR(F
[ARM/FDPIC v4 07/20] [ARM] FDPIC: Avoid saving/restoring r9 on stack since it is read-only
2018-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.h (PIC_REGISTER_MAY_NEED_SAVING): New helper. * config/arm/arm.c (arm_compute_save_reg0_reg12_mask): Handle FDPIC. Change-Id: I0f3b2023ab2a2a0433dfe081dac6bbb194b7a76c diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 63c68e5..7e7f747 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -19480,9 +19480,7 @@ arm_compute_save_reg0_reg12_mask (void) save_reg_mask |= (1 << reg); /* Also save the pic base register if necessary. */ - if (flag_pic - && !TARGET_SINGLE_PIC_BASE - && arm_pic_register != INVALID_REGNUM + if (PIC_REGISTER_MAY_NEED_SAVING && crtl->uses_pic_offset_table) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; } @@ -19514,9 +19512,7 @@ arm_compute_save_reg0_reg12_mask (void) /* If we aren't loading the PIC register, don't stack it even though it may be live. */ - if (flag_pic - && !TARGET_SINGLE_PIC_BASE - && arm_pic_register != INVALID_REGNUM + if (PIC_REGISTER_MAY_NEED_SAVING && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM) || crtl->uses_pic_offset_table)) save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 53c3b0e..35a2bd2 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1949,6 +1949,13 @@ extern unsigned arm_pic_register; || label_mentioned_p (get_pool_constant (X) \ || tls_mentioned_p (X)) +/* We may want to save the PIC register if it is a dedicated one. */ +#define PIC_REGISTER_MAY_NEED_SAVING \ + (flag_pic\ + && !TARGET_SINGLE_PIC_BASE \ + && !TARGET_FDPIC\ + && arm_pic_register != INVALID_REGNUM) + /* We need to know when we are making a constant pool; this determines whether data needs to be in the GOT or can be referenced via a GOT offset. */ -- 2.6.3
[ARM/FDPIC v4 08/20] [ARM] FDPIC: Enforce local/global binding for function descriptors
Use local binding rules to decide whether we can use GOTOFFFUNCDESC to
compute the function address.
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.c (arm_local_funcdesc_p): New function.
(legitimize_pic_address): Enforce binding rules on function
pointers in FDPIC mode.
(arm_assemble_integer): Likewise.
Change-Id: I3fa0b63bc0f672903f405aa72cc46052de1c0feb
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7e7f747..ca53eae 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3777,6 +3777,42 @@ arm_options_perform_arch_sanity_checks (void)
}
}
+/* Test whether a local function descriptor is canonical, i.e.,
+ whether we can use GOTOFFFUNCDESC to compute the address of the
+ function. */
+static bool
+arm_fdpic_local_funcdesc_p (rtx fnx)
+{
+ tree fn;
+ enum symbol_visibility vis;
+ bool ret;
+
+ if (!TARGET_FDPIC)
+return TRUE;
+
+ if (! SYMBOL_REF_LOCAL_P (fnx))
+return FALSE;
+
+ fn = SYMBOL_REF_DECL (fnx);
+
+ if (! fn)
+return FALSE;
+
+ vis = DECL_VISIBILITY (fn);
+
+ if (vis == VISIBILITY_PROTECTED)
+/* Private function descriptors for protected functions are not
+ canonical. Temporarily change the visibility to global so that
+ we can ensure uniqueness of funcdesc pointers. */
+DECL_VISIBILITY (fn) = VISIBILITY_DEFAULT;
+
+ ret = default_binds_local_p_1 (fn, flag_pic);
+
+ DECL_VISIBILITY (fn) = vis;
+
+ return ret;
+}
+
static void
arm_add_gc_roots (void)
{
@@ -7494,7 +7530,9 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx
reg)
|| (GET_CODE (orig) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig)
&& (SYMBOL_REF_DECL (orig)
- ? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1)))
+ ? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1)
+ && (!SYMBOL_REF_FUNCTION_P (orig)
+ || arm_fdpic_local_funcdesc_p (orig
&& NEED_GOT_RELOC
&& arm_pic_data_is_text_relative)
insn = arm_pic_static_addr (orig, reg);
@@ -23060,7 +23098,9 @@ arm_assemble_integer (rtx x, unsigned int size, int
aligned_p)
|| (GET_CODE (x) == SYMBOL_REF
&& (!SYMBOL_REF_LOCAL_P (x)
|| (SYMBOL_REF_DECL (x)
- ? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0
+ ? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0)
+ || (SYMBOL_REF_FUNCTION_P (x)
+ && !arm_fdpic_local_funcdesc_p (x)
{
if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (x))
fputs ("(GOTFUNCDESC)", asm_out_file);
--
2.6.3
[ARM/FDPIC v4 09/20] [ARM] FDPIC: Add support for taking address of nested function
In FDPIC mode, the trampoline generated to support pointers to nested
functions looks like:
.wordtrampoline address
.wordtrampoline GOT address
ldr r12, [pc, #8]
ldr r9, [pc, #8]
ldr pc, [pc, #8]
.wordstatic chain value
.wordGOT address
.wordfunction's address
because in FDPIC function pointers are actually pointers to function
descriptors, we have to actually generate a function descriptor for
the trampoline.
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.c (arm_asm_trampoline_template): Add FDPIC
support.
(arm_trampoline_init): Likewise.
(arm_trampoline_init): Likewise.
* config/arm/arm.h (TRAMPOLINE_SIZE): Likewise.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index ca53eae..8c2b9d0 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3963,13 +3963,50 @@ arm_warn_func_return (tree decl)
.wordstatic chain value
.wordfunction's address
XXX FIXME: When the trampoline returns, r8 will be clobbered. */
+/* In FDPIC mode, the trampoline looks like:
+ .wordtrampoline address
+ .wordtrampoline GOT address
+ ldr r12, [pc, #8] ; #4 for Thumb2
+ ldr r9, [pc, #8] ; #4 for Thumb2
+ ldr pc, [pc, #8] ; #4 for Thumb2
+ .wordstatic chain value
+ .wordGOT address
+ .wordfunction's address
+*/
static void
arm_asm_trampoline_template (FILE *f)
{
fprintf (f, "\t.syntax unified\n");
- if (TARGET_ARM)
+ if (TARGET_FDPIC)
+{
+ /* The first two words are a function descriptor pointing to the
+trampoline code just below. */
+ if (TARGET_ARM)
+ fprintf (f, "\t.arm\n");
+ else if (TARGET_THUMB2)
+ fprintf (f, "\t.thumb\n");
+ else
+ /* Only ARM and Thumb-2 are supported. */
+ gcc_unreachable ();
+
+ assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
+ assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
+ /* Trampoline code which sets the static chain register but also
+PIC register before jumping into real code. */
+ asm_fprintf (f, "\tldr\t%r, [%r, #%d]\n",
+ STATIC_CHAIN_REGNUM, PC_REGNUM,
+ TARGET_THUMB2 ? 8 : 4);
+ asm_fprintf (f, "\tldr\t%r, [%r, #%d]\n",
+ PIC_OFFSET_TABLE_REGNUM, PC_REGNUM,
+ TARGET_THUMB2 ? 8 : 4);
+ asm_fprintf (f, "\tldr\t%r, [%r, #%d]\n",
+ PC_REGNUM, PC_REGNUM,
+ TARGET_THUMB2 ? 8 : 4);
+ assemble_aligned_integer (UNITS_PER_WORD, const0_rtx);
+}
+ else if (TARGET_ARM)
{
fprintf (f, "\t.arm\n");
asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM, PC_REGNUM);
@@ -4010,12 +4047,40 @@ arm_trampoline_init (rtx m_tramp, tree fndecl, rtx
chain_value)
emit_block_move (m_tramp, assemble_trampoline_template (),
GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
- mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 8 : 12);
- emit_move_insn (mem, chain_value);
+ if (TARGET_FDPIC)
+{
+ rtx funcdesc = XEXP (DECL_RTL (fndecl), 0);
+ rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc);
+ rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4));
+ /* The function start address is at offset 8, but in Thumb mode
+we want bit 0 set to 1 to indicate Thumb-ness, hence 9
+below. */
+ rtx trampoline_code_start
+ = plus_constant (Pmode, XEXP (m_tramp, 0), TARGET_THUMB2 ? 9 : 8);
+
+ /* Write initial funcdesc which points to the trampoline. */
+ mem = adjust_address (m_tramp, SImode, 0);
+ emit_move_insn (mem, trampoline_code_start);
+ mem = adjust_address (m_tramp, SImode, 4);
+ emit_move_insn (mem, gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM));
+ /* Setup static chain. */
+ mem = adjust_address (m_tramp, SImode, 20);
+ emit_move_insn (mem, chain_value);
+ /* GOT + real function entry point. */
+ mem = adjust_address (m_tramp, SImode, 24);
+ emit_move_insn (mem, gotaddr);
+ mem = adjust_address (m_tramp, SImode, 28);
+ emit_move_insn (mem, fnaddr);
+}
+ else
+{
+ mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 8 : 12);
+ emit_move_insn (mem, chain_value);
- mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 12 : 16);
- fnaddr = XEXP (DECL_RTL (fndecl), 0);
- emit_move_insn (mem, fnaddr);
+ mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 12 : 16);
+ fnaddr = XEXP (DECL_RTL (fndecl), 0);
+ emit_move_insn (mem, fnaddr);
+}
a_tramp = XEXP (m_tramp, 0);
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),
@@ -4029,7 +4094,
Re: [PATCH]Come up with -flive-patching master option.
> On 11/16/18 2:36 AM, Qing Zhao wrote:
> > Hi,
> >
> > this is the new version of the patch.
> >
> > I have bootstrapped it on both aarch64 and x86, no regression.
> >
> > please take a look.
>
> Thanks for the updated version of the patch.
> I have last small nits I see:
>
> - gcc/common.opt: when running --help=common, the line is too long
> - gcc/doc/invoke.texi - 2 spaces in between sentences + better gol
> - gcc/opts.c - do not mix spaces + tabs
>
> With that I'm fine. But note that I'm not a maintainer :)
I wonder what happens, when I pass like -flive-patching -fwhole-program
compared to -fwhole-program -flive-patching.
It seems to me that in first case we will end up with whole-program
optimization while in the second we won't.
I guess we should behave in a way that we disable the passes when
they are enabled implicitly (such as by -O2) but output an error when
once uses contradicting set of options, lie -flive-patching
-fwhole-program?
Honza
>
> Thanks,
> Martin
>
> >
> > Okay for commit?
> >
> > thanks.
> >
> > Qing
> >
> > ==
> >
> > gcc/ChangeLog:
> >
> > 2018-11-15 qing zhao
> >
> > * cif-code.def (EXTERN_LIVE_ONLY_STATIC): New CIF code.
> > * common.opt: Add -flive-patching flag.
> > * doc/invoke.texi: Document -flive-patching.
> > * flag-types.h (enum live_patching_level): New enum.
> > * ipa-inline.c (can_inline_edge_p): Disable external functions from
> > inlining when flag_live_patching is LIVE_PATCHING_INLINE_ONLY_STATIC.
> > * opts.c (control_optimizations_for_live_patching): New function.
> > (finish_options): Make flag_live_patching incompatible with flag_lto.
> > (common_handle_option): Handle flive-patching flag.
> >
> > gcc/testsuite/ChangeLog:
> >
> > 2018-11-15 qing zhao
> >
> > * gcc.dg/live-patching-1.c: New test.
> > * gcc.dg/live-patching-2.c: New test.
> > * gcc.dg/tree-ssa/writeonly-3.c: New test.
> > * gcc.target/i386/ipa-stack-alignment-2.c: New test.
> >
> From e44d8b88ac5fb712d5b5e7fdf2f2ad7f43b8ea09 Mon Sep 17 00:00:00 2001
> From: marxin
> Date: Fri, 16 Nov 2018 16:23:44 +0100
> Subject: [PATCH] my fixes.
>
> ---
> gcc/common.opt | 3 +--
> gcc/doc/invoke.texi | 8
> gcc/opts.c | 2 +-
> 3 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/common.opt b/gcc/common.opt
> index 63cd6cc851d..35c24b8e8cf 100644
> --- a/gcc/common.opt
> +++ b/gcc/common.opt
> @@ -2187,8 +2187,7 @@ Common RejectNegative
> Alias(flive-patching=,inline-clone) Optimization
> flive-patching=
> Common Report Joined RejectNegative Enum(live_patching_level)
> Var(flag_live_patching) Init(LIVE_PATCHING_NONE) Optimization
> -flive-patching=[inline-only-static|inline-clone]Control IPA
> -optimizations to provide a safe compilation for live-patching. At the same
> -time, provides multiple-level control on the enabled IPA optimizations.
> +optimizations to provide a safe compilation for live-patching.
>
> Enum
> Name(live_patching_level) Type(enum live_patching_level)
> UnknownError(unknown Live-Patching Level %qs)
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 0fb67163490..94455fa 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -9288,13 +9288,13 @@ impacted function of the former. If a function is
> patched, its impacted
> functions should be patched too.
>
> The impacted functions are decided by the compiler's interprocedural
> -optimizations. For example, inlining a function into its caller, cloning
> +optimizations. For example, inlining a function into its caller, cloning
> a function and changing its caller to call this new clone, or extracting
> a function's pureness/constness information to optimize its direct or
> indirect callers, etc.
>
> Usually, the more IPA optimizations enabled, the larger the number of
> -impacted functions for each function. In order to control the number of
> +impacted functions for each function. In order to control the number of
> impacted functions and computed the list of impacted function easily,
> we provide control to partially enable IPA optimizations on two different
> levels.
> @@ -9313,8 +9313,8 @@ callers need to be patched as well.
> @option{-flive-patching=inline-clone} disables the following optimization
> flags:
> @gccoptlist{-fwhole-program -fipa-pta -fipa-reference -fipa-ra @gol
> -fipa-icf -fipa-icf-functions -fipa-icf-variables @gol
> --fipa-bit-cp -fipa-vrp -fipa-pure-const -fipa-reference-addressable @gol
> --fipa-stack-alignment}
> +-fipa-bit-cp -fipa-vrp -fipa-pure-const @gol
> +-fipa-reference-addressable -fipa-stack-alignment}
>
> @item inline-only-static
>
> diff --git a/gcc/opts.c b/gcc/opts.c
> index 570155816e3..0b5e89faeee 100644
> --- a/gcc/opts.c
> +++ b/gcc/opts.c
> @@ -2347,7 +2347,7 @@ common_handle_option (struct gcc_options *opts,
>
> case OPT_flive_patching_:
>if (value)
[ARM/FDPIC v4 10/20] [ARM] FDPIC: Implement TLS support.
Support additional relocations: TLS_GD32_FDPIC, TLS_LDM32_FDPIC, and
TLS_IE32_FDPIC.
We do not support the GNU2 TLS dialect.
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.c (tls_reloc): Add TLS_GD32_FDPIC,
TLS_LDM32_FDPIC and TLS_IE32_FDPIC.
(arm_call_tls_get_addr): Add FDPIC support.
(legitimize_tls_address): Likewise.
(arm_emit_tls_decoration): Likewise.
Change-Id: I4ea5034ff654540c4658d0a79fb92f70550cdf4a
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 8c2b9d0..47e8203 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2373,9 +2373,12 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
enum tls_reloc {
TLS_GD32,
+ TLS_GD32_FDPIC,
TLS_LDM32,
+ TLS_LDM32_FDPIC,
TLS_LDO32,
TLS_IE32,
+ TLS_IE32_FDPIC,
TLS_LE32,
TLS_DESCSEQ /* GNU scheme */
};
@@ -8685,20 +8688,34 @@ arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int
reloc)
gcc_assert (reloc != TLS_DESCSEQ);
start_sequence ();
- labelno = GEN_INT (pic_labelno++);
- label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
- label = gen_rtx_CONST (VOIDmode, label);
+ if (TARGET_FDPIC)
+{
+ sum = gen_rtx_UNSPEC (Pmode,
+ gen_rtvec (2, x, GEN_INT (reloc)),
+ UNSPEC_TLS);
+}
+ else
+{
+ labelno = GEN_INT (pic_labelno++);
+ label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
+ label = gen_rtx_CONST (VOIDmode, label);
- sum = gen_rtx_UNSPEC (Pmode,
- gen_rtvec (4, x, GEN_INT (reloc), label,
- GEN_INT (TARGET_ARM ? 8 : 4)),
- UNSPEC_TLS);
+ sum = gen_rtx_UNSPEC (Pmode,
+ gen_rtvec (4, x, GEN_INT (reloc), label,
+ GEN_INT (TARGET_ARM ? 8 : 4)),
+ UNSPEC_TLS);
+}
reg = load_tls_operand (sum, reg);
- if (TARGET_ARM)
-emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
+ if (TARGET_FDPIC)
+{
+ emit_insn (gen_addsi3 (reg, reg, gen_rtx_REG (Pmode, FDPIC_REGNUM)));
+}
else
-emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
+if (TARGET_ARM)
+ emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
+else
+ emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
*valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX,
LCT_PURE, /* LCT_CONST? */
@@ -8733,6 +8750,7 @@ arm_tls_descseq_addr (rtx x, rtx reg)
return reg;
}
+
rtx
legitimize_tls_address (rtx x, rtx reg)
{
@@ -8745,6 +8763,9 @@ legitimize_tls_address (rtx x, rtx reg)
case TLS_MODEL_GLOBAL_DYNAMIC:
if (TARGET_GNU2_TLS)
{
+ if (TARGET_FDPIC)
+ gcc_unreachable();
+
reg = arm_tls_descseq_addr (x, reg);
tp = arm_load_tp (NULL_RTX);
@@ -8754,7 +8775,10 @@ legitimize_tls_address (rtx x, rtx reg)
else
{
/* Original scheme */
- insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
+ if (TARGET_FDPIC)
+ insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32_FDPIC);
+ else
+ insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
dest = gen_reg_rtx (Pmode);
emit_libcall_block (insns, dest, ret, x);
}
@@ -8763,6 +8787,9 @@ legitimize_tls_address (rtx x, rtx reg)
case TLS_MODEL_LOCAL_DYNAMIC:
if (TARGET_GNU2_TLS)
{
+ if (TARGET_FDPIC)
+ gcc_unreachable();
+
reg = arm_tls_descseq_addr (x, reg);
tp = arm_load_tp (NULL_RTX);
@@ -8771,7 +8798,10 @@ legitimize_tls_address (rtx x, rtx reg)
}
else
{
- insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
+ if (TARGET_FDPIC)
+ insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32_FDPIC);
+ else
+ insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
/* Attach a unique REG_EQUIV, to allow the RTL optimizers to
share the LDM result with other LD model accesses. */
@@ -8790,23 +8820,35 @@ legitimize_tls_address (rtx x, rtx reg)
return dest;
case TLS_MODEL_INITIAL_EXEC:
- labelno = GEN_INT (pic_labelno++);
- label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
- label = gen_rtx_CONST (VOIDmode, label);
- sum = gen_rtx_UNSPEC (Pmode,
- gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
- GEN_INT (TARGET_ARM ? 8 : 4)),
- UNSPEC_TLS);
- reg = load_tls_operand (sum, reg);
-
- if (TARGET_ARM)
- emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
- else if (TARGET_THUMB2)
- emit_insn (gen_tls_load_dot_plus_four (reg, NULL, reg, labelno));
[ARM/FDPIC v4 12/20] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp
We call __aeabi_read_tp() to get the thread pointer. Since this is a
function call, we have to restore the FDPIC register afterwards.
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/
* config/arm/arm.c (arm_load_tp): Add FDPIC support.
* config/arm/arm.md (load_tp_soft_fdpic): New pattern.
(load_tp_soft): Disable in FDPIC mode.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 47e8203..f2df815 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8657,7 +8657,25 @@ arm_load_tp (rtx target)
rtx tmp;
- emit_insn (gen_load_tp_soft ());
+ if (TARGET_FDPIC)
+ {
+ rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3));
+ rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM);
+ rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode,
FDPIC_REGNUM);
+
+ emit_insn (gen_load_tp_soft_fdpic ());
+
+ /* Restore r9. */
+ XVECEXP (par, 0, 0) = gen_rtx_UNSPEC (VOIDmode,
+ gen_rtvec (2, fdpic_reg,
+ initial_fdpic_reg),
+ UNSPEC_PIC_RESTORE);
+ XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, initial_fdpic_reg);
+ XVECEXP (par, 0, 2) = gen_rtx_CLOBBER (VOIDmode, fdpic_reg);
+ emit_insn (par);
+ }
+ else
+ emit_insn (gen_load_tp_soft ());
tmp = gen_rtx_REG (SImode, R0_REGNUM);
emit_move_insn (target, tmp);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 1200886..c6b4461 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11485,12 +11485,25 @@
)
;; Doesn't clobber R1-R3. Must use r0 for the first operand.
+(define_insn "load_tp_soft_fdpic"
+ [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
+ (clobber (reg:SI 9))
+ (clobber (reg:SI LR_REGNUM))
+ (clobber (reg:SI IP_REGNUM))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_SOFT_TP && TARGET_FDPIC"
+ "bl\\t__aeabi_read_tp\\t@ load_tp_soft"
+ [(set_attr "conds" "clob")
+ (set_attr "type" "branch")]
+)
+
+;; Doesn't clobber R1-R3. Must use r0 for the first operand.
(define_insn "load_tp_soft"
[(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS))
(clobber (reg:SI LR_REGNUM))
(clobber (reg:SI IP_REGNUM))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_SOFT_TP"
+ "TARGET_SOFT_TP && !TARGET_FDPIC"
"bl\\t__aeabi_read_tp\\t@ load_tp_soft"
[(set_attr "conds" "clob")
(set_attr "type" "branch")]
--
2.6.3
[ARM/FDPIC v4 11/20] [ARM] FDPIC: Add support to unwind FDPIC signal frame
2018-XX-XX Christophe Lyon
Mickaël Guêné
libgcc/
* unwind-arm-common.inc (ARM_SET_R7_RT_SIGRETURN)
(THUMB2_SET_R7_RT_SIGRETURN, FDPIC_LDR_R12_WITH_FUNCDESC)
(FDPIC_LDR_R9_WITH_GOT, FDPIC_LDR_PC_WITH_RESTORER)
(FDPIC_FUNCDESC_OFFSET, ARM_NEW_RT_SIGFRAME_UCONTEXT)
(ARM_UCONTEXT_SIGCONTEXT, ARM_SIGCONTEXT_R0,
FDPIC_T2_LDR_R12_WITH_FUNCDESC)
(FDPIC_T2_LDR_R9_WITH_GOT, FDPIC_T2_LDR_PC_WITH_RESTORER): New.
(__gnu_personality_sigframe_fdpic): New.
(get_eit_entry): Add FDPIC signal frame support.
Change-Id: I7f9527cc50665dd1a731b7badf71c319fb38bf57
diff --git a/libgcc/unwind-arm-common.inc b/libgcc/unwind-arm-common.inc
index 0d2ec0b..3151957 100644
--- a/libgcc/unwind-arm-common.inc
+++ b/libgcc/unwind-arm-common.inc
@@ -30,6 +30,26 @@
#include
#endif
+#if __FDPIC__
+/* Load r7 with rt_sigreturn value. */
+#define ARM_SET_R7_RT_SIGRETURN0xe3a070ad /* mov r7,
#0xad */
+#define THUMB2_SET_R7_RT_SIGRETURN 0x07adf04f /* mov.w r7, #0xad */
+
+/* FDPIC jump to restorer sequence. */
+#define FDPIC_LDR_R12_WITH_FUNCDESC0xe59fc004 /* ldr r12, [pc, #4]
*/
+#define FDPIC_LDR_R9_WITH_GOT 0xe59c9004 /* ldr r9, [r12, #4]
*/
+#define FDPIC_LDR_PC_WITH_RESTORER 0xe59cf000 /* ldr pc, [r12] */
+#define FDPIC_T2_LDR_R12_WITH_FUNCDESC 0xc008f8df /* ldr.w r12, [pc, #8]
*/
+#define FDPIC_T2_LDR_R9_WITH_GOT 0x9004f8dc /* ldr.w r9, [r12, #4]
*/
+#define FDPIC_T2_LDR_PC_WITH_RESTORER 0xf000f8dc /* ldr.w pc, [r12] */
+#define FDPIC_FUNCDESC_OFFSET 12
+
+/* Signal frame offsets. */
+#define ARM_NEW_RT_SIGFRAME_UCONTEXT 0x80
+#define ARM_UCONTEXT_SIGCONTEXT0x14
+#define ARM_SIGCONTEXT_R0 0xc
+#endif
+
/* We add a prototype for abort here to avoid creating a dependency on
target headers. */
extern void abort (void);
@@ -199,6 +219,45 @@ search_EIT_table (const __EIT_entry * table, int nrec, _uw
return_address)
}
}
+#if __FDPIC__
+/* VFP is not restored, but this is sufficient to allow unwinding. */
+static _Unwind_Reason_Code
+__gnu_personality_sigframe_fdpic (_Unwind_State state,
+ _Unwind_Control_Block *ucbp,
+ _Unwind_Context *context)
+{
+unsigned int sp;
+unsigned int pc;
+unsigned int funcdesc;
+unsigned int handler;
+unsigned int first_handler_instruction;
+int i;
+
+_Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &sp);
+_Unwind_VRS_Get (context, _UVRSC_CORE, R_PC, _UVRSD_UINT32, &pc);
+
+funcdesc = *(unsigned int *)((pc & ~1) + FDPIC_FUNCDESC_OFFSET);
+handler = *(unsigned int *)(funcdesc);
+first_handler_instruction = *(unsigned int *)(handler & ~1);
+
+/* Adjust SP to point to the start of registers according to
+ signal type. */
+if (first_handler_instruction == ARM_SET_R7_RT_SIGRETURN
+ || first_handler_instruction == THUMB2_SET_R7_RT_SIGRETURN)
+ sp += ARM_NEW_RT_SIGFRAME_UCONTEXT
+ + ARM_UCONTEXT_SIGCONTEXT
+ + ARM_SIGCONTEXT_R0;
+else
+ sp += ARM_UCONTEXT_SIGCONTEXT
+ + ARM_SIGCONTEXT_R0;
+/* Restore regs saved on stack by the kernel. */
+for (i = 0; i < 16; i++)
+ _Unwind_VRS_Set (context, _UVRSC_CORE, i, _UVRSD_UINT32, sp + 4 * i);
+
+return _URC_CONTINUE_UNWIND;
+}
+#endif
+
/* Find the exception index table eintry for the given address.
Fill in the relevant fields of the UCB.
Returns _URC_FAILURE if an error occurred, _URC_OK on success. */
@@ -222,6 +281,27 @@ get_eit_entry (_Unwind_Control_Block *ucbp, _uw
return_address)
&nrec);
if (!eitp)
{
+#if __FDPIC__
+ /* If we are unwinding a signal handler then perhaps we have
+reached a trampoline. Try to detect jump to restorer
+sequence. */
+ _uw *pc = (_uw *)((return_address+2) & ~1);
+ if ((pc[0] == FDPIC_LDR_R12_WITH_FUNCDESC
+ && pc[1] == FDPIC_LDR_R9_WITH_GOT
+ && pc[2] == FDPIC_LDR_PC_WITH_RESTORER)
+ || (pc[0] == FDPIC_T2_LDR_R12_WITH_FUNCDESC
+ && pc[1] == FDPIC_T2_LDR_R9_WITH_GOT
+ && pc[2] == FDPIC_T2_LDR_PC_WITH_RESTORER))
+ {
+ struct funcdesc_t *funcdesc
+ = (struct funcdesc_t *) &__gnu_personality_sigframe_fdpic;
+
+ UCB_PR_ADDR (ucbp) = funcdesc->ptr;
+ UCB_PR_GOT (ucbp) = funcdesc->got;
+
+ return _URC_OK;
+ }
+#endif
UCB_PR_ADDR (ucbp) = 0;
return _URC_FAILURE;
}
@@ -236,6 +316,27 @@ get_eit_entry (_Unwind_Control_Block *ucbp, _uw
return_address)
if (!eitp)
{
+#if __FDPIC__
+ /* If we are unwinding a signal handler then perhaps we have
+reached a trampoline. Try to detect jump to res
[ARM/FDPIC v4 13/20] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture
Without this, when we are unwinding across a signal frame we can jump to an even address which leads to an exception. This is needed in __gnu_persnality_sigframe_fdpic() when restoring the PC from the signal frame since the PC saved by the kernel has the LSB bit set to zero. 2018-XX-XX Christophe Lyon Mickaël Guêné libgcc/ * config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle v7m architecture. Change-Id: Ie84de548226bcf1751e19a09e8f091fb3013ccea diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c index 564e4f13..6da6e3d 100644 --- a/libgcc/config/arm/unwind-arm.c +++ b/libgcc/config/arm/unwind-arm.c @@ -198,6 +198,11 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context, return _UVRSR_FAILED; vrs->core.r[regno] = *(_uw *) valuep; +#if defined(__ARM_ARCH_7M__) + /* Force LSB bit since we always run thumb code. */ + if (regno == 15) + vrs->core.r[regno] |= 1; +#endif return _UVRSR_OK; case _UVRSC_VFP: -- 2.6.3
[ARM/FDPIC v4 15/20] [ARM][testsuite] FDPIC: Adjust scan-assembler patterns.
In FDPIC mode, r9 is saved in addition to other registers, so update
the expected patterns accordingly.
2018-XX-XX Christophe Lyon
Mickaël Guêné
* gcc/testsuite/
* gcc.target/arm/interrupt-1.c: Add scan-assembler pattern for
arm*-*-uclinuxfdpiceabi.
* gcc.target/arm/interrupt-2.c: Likewise.
* gcc.target/arm/pr70830.c: Likewise.
Change-Id: Id946b79bacc32be585c31e60a355191f104cc29e
diff --git a/gcc/testsuite/gcc.target/arm/interrupt-1.c
b/gcc/testsuite/gcc.target/arm/interrupt-1.c
index fe94877..493763d 100644
--- a/gcc/testsuite/gcc.target/arm/interrupt-1.c
+++ b/gcc/testsuite/gcc.target/arm/interrupt-1.c
@@ -13,5 +13,7 @@ void foo ()
bar (0);
}
-/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, fp, ip, lr}" } } */
-/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip,
pc}\\^" } } */
+/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, fp, ip, lr}" {
target { ! arm*-*-uclinuxfdpiceabi } } } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip,
pc}\\^" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
+/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, r5, r9, fp, ip,
lr}" { target arm*-*-uclinuxfdpiceabi } } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, r9, fp,
ip, pc}\\^" { target arm*-*-uclinuxfdpiceabi } } } */
diff --git a/gcc/testsuite/gcc.target/arm/interrupt-2.c
b/gcc/testsuite/gcc.target/arm/interrupt-2.c
index 289eca0..5be1f16 100644
--- a/gcc/testsuite/gcc.target/arm/interrupt-2.c
+++ b/gcc/testsuite/gcc.target/arm/interrupt-2.c
@@ -15,5 +15,7 @@ void test()
foo = 0;
}
-/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, r5, ip, lr}" } } */
-/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip,
pc}\\^" } } */
+/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, r5, ip, lr}" {
target { ! arm*-*-uclinuxfdpiceabi } } } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip,
pc}\\^" { target { ! arm*-*-uclinuxfdpiceabi } } } } */
+/* { dg-final { scan-assembler "push\t{r0, r1, r2, r3, r4, r5, r6, r9, ip,
lr}" { target arm*-*-uclinuxfdpiceabi } } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, r6, r9,
ip, pc}\\^" { target arm*-*-uclinuxfdpiceabi } } } */
diff --git a/gcc/testsuite/gcc.target/arm/pr70830.c
b/gcc/testsuite/gcc.target/arm/pr70830.c
index cad903b..cd84c42 100644
--- a/gcc/testsuite/gcc.target/arm/pr70830.c
+++ b/gcc/testsuite/gcc.target/arm/pr70830.c
@@ -11,4 +11,5 @@ void __attribute__ ((interrupt ("IRQ")))
dm3730_IRQHandler(void)
{
prints("IRQ" );
}
-/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, ip, pc}\\^" } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, ip, pc}\\^" {
target { ! arm*-*-uclinuxfdpiceabi } } } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r9, ip,
pc}\\^" { target arm*-*-uclinuxfdpiceabi } } } */
--
2.6.3
[ARM/FDPIC v4 16/20] [ARM][testsuite] FDPIC: Skip tests that don't work in PIC mode
Some tests fail on arm*-*-uclinuxfdpiceabi because it generates PIC
code and they don't support it: skip them. They also fail on
arm*-linux* when forcing -fPIC.
2018-XX-XX Christophe Lyon
gcc/testsuite/
* gcc.target/arm/eliminate.c: Accept only nonpic targets.
* g++.dg/other/anon5.C: Likewise.
Change-Id: I8efb8d356ce25b020c44a84b07f79a996dca0358
diff --git a/gcc/testsuite/g++.dg/other/anon5.C
b/gcc/testsuite/g++.dg/other/anon5.C
index ee4601e..dadd92e 100644
--- a/gcc/testsuite/g++.dg/other/anon5.C
+++ b/gcc/testsuite/g++.dg/other/anon5.C
@@ -1,5 +1,6 @@
// PR c++/34094
// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* } } } }
+// { dg-require-effective-target nonpic }
// { dg-options "-gdwarf-2" }
// Ignore additional message on powerpc-ibm-aix
// { dg-prune-output "obtain more information" } */
diff --git a/gcc/testsuite/gcc.target/arm/eliminate.c
b/gcc/testsuite/gcc.target/arm/eliminate.c
index f254dd8..299d4df 100644
--- a/gcc/testsuite/gcc.target/arm/eliminate.c
+++ b/gcc/testsuite/gcc.target/arm/eliminate.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { nonpic } } } */
/* { dg-options "-O2" } */
struct X
--
2.6.3
[ARM/FDPIC v4 14/20] [ARM][testsuite] FDPIC: Skip unsupported tests
Several tests cannot work on ARM-FDPIC for various reasons: skip them,
or skip some directives.
gcc.dg/20020312-2.c: Skip since it forces -fno-pic.
gcc.target/arm/:
* Skip since r9 is clobbered by assembly code:
20051215-1.c
mmx-1.c
pr61948.c
pr77933-1.c
pr77933-2.c
* Skip since the test forces armv5te which is not supported by FDPIC:
pr40887.c
pr19599.c
* Skip since FDPIC disables sibcall to external functions:
sibcall-1.c
tail-long-call
vfp-longcall-apcs
* Skip size check since it's different for FDPIC:
ivopts-2.c
ivopts-3.c
ivopts-4.c
ivopts-5.c
pr43597.c
pr43920-2.c
* Disable assembler scanning invalid for FDPIC:
pr45701-1.c
pr45701-2.c
stack-red-zone.c
* gnu2 TLS dialect is not supported by FDPIC:
tlscall.c
* Test relies on symbols not generated in FDPIC:
data-rel-2.c
data-rel-3.c
2018-XX-XX Christophe Lyon
Mickaël Guêné
gcc/testsuite/
* gcc.dg/20020312-2.c: Skip on arm*-*-uclinuxfdpiceabi.
* gcc.target/arm/20051215-1.c: Likewise.
* gcc.target/arm/mmx-1.c: Likewise.
* gcc.target/arm/pr19599.c: Likewise.
* gcc.target/arm/pr40887.c: Likewise.
* gcc.target/arm/pr61948.c: Likewise.
* gcc.target/arm/pr77933-1.c: Likewise.
* gcc.target/arm/pr77933-2.c: Likewise.
* gcc.target/arm/sibcall-1.c: Likewise.
* gcc.target/arm/data-rel-2.c: Likewise.
* gcc.target/arm/data-rel-3.c: Likewise.
* gcc.target/arm/tail-long-call: Likewise.
* gcc.target/arm/tlscall.c: Likewise.
* gcc.target/arm/vfp-longcall-apcs: Likewise.
* gcc.target/arm/ivopts-2.c: Skip object-size test on
arm*-*-uclinuxfdpiceabi.
* gcc.target/arm/ivopts-3.c: Likewise.
* gcc.target/arm/ivopts-4.c: Likewise.
* gcc.target/arm/ivopts-5.c: Likewise.
* gcc.target/arm/pr43597.c: Likewise.
* gcc.target/arm/pr43920-2.c: Likewise.
* gcc.target/arm/pr45701-1.c: Skip scan-assembler on
arm*-*-uclinuxfdpiceabi.
* gcc.target/arm/pr45701-2.c: Likewise.
* gcc.target/arm/stack-red-zone.c: Likewise.
Change-Id: Icada7ce52537901fdac10403e7997571b7e2c509
diff --git a/gcc/testsuite/gcc.dg/20020312-2.c
b/gcc/testsuite/gcc.dg/20020312-2.c
index e72a5b2..f1197ff 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -9,6 +9,7 @@
/* { dg-options "-O -fno-pic" } */
/* { dg-additional-options "-no-pie" { target pie_enabled } } */
/* { dg-require-effective-target nonlocal_goto } */
+/* { dg-skip-if "" { arm*-*-uclinuxfdpiceabi } "*" "" } */
extern void abort (void);
diff --git a/gcc/testsuite/gcc.target/arm/20051215-1.c
b/gcc/testsuite/gcc.target/arm/20051215-1.c
index 0519dc7..cc07693 100644
--- a/gcc/testsuite/gcc.target/arm/20051215-1.c
+++ b/gcc/testsuite/gcc.target/arm/20051215-1.c
@@ -3,6 +3,7 @@
the call would need an output reload. */
/* { dg-do run } */
/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+/* { dg-skip-if "r9 is reserved in FDPIC" { arm*-*-uclinuxfdpiceabi } "*" "" }
*/
extern void abort (void);
typedef void (*callback) (void);
diff --git a/gcc/testsuite/gcc.target/arm/data-rel-2.c
b/gcc/testsuite/gcc.target/arm/data-rel-2.c
index 6ba47d6..7d37a8c 100644
--- a/gcc/testsuite/gcc.target/arm/data-rel-2.c
+++ b/gcc/testsuite/gcc.target/arm/data-rel-2.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "Not supported in FDPIC" { arm*-*-uclinuxfdpiceabi } "*" "" }
*/
/* { dg-options "-fPIC -mno-pic-data-is-text-relative -mno-single-pic-base" }
*/
/* { dg-final { scan-assembler-not "j-\\(.LPIC" } } */
/* { dg-final { scan-assembler "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
diff --git a/gcc/testsuite/gcc.target/arm/data-rel-3.c
b/gcc/testsuite/gcc.target/arm/data-rel-3.c
index 2ce1e66..534c6c4 100644
--- a/gcc/testsuite/gcc.target/arm/data-rel-3.c
+++ b/gcc/testsuite/gcc.target/arm/data-rel-3.c
@@ -1,3 +1,4 @@
+/* { dg-skip-if "Not supported in FDPIC" { arm*-*-uclinuxfdpiceabi } "*" "" }
*/
/* { dg-options "-fPIC -mpic-data-is-text-relative" } */
/* { dg-final { scan-assembler "j-\\(.LPIC" } } */
/* { dg-final { scan-assembler-not "_GLOBAL_OFFSET_TABLE_-\\(.LPIC" } } */
diff --git a/gcc/testsuite/gcc.target/arm/ivopts-2.c
b/gcc/testsuite/gcc.target/arm/ivopts-2.c
index afe91aa..f1d5edb 100644
--- a/gcc/testsuite/gcc.target/arm/ivopts-2.c
+++ b/gcc/testsuite/gcc.target/arm/ivopts-2.c
@@ -14,4 +14,4 @@ tr4 (short array[], int n)
/* { dg-final { scan-tree-dump-times "PHI
[ARM/FDPIC v4 17/20] [ARM][testsuite] FDPIC: Handle *-*-uclinux*
Add *-*-uclinux* to tests that work on this target.
2018-XX-XX Christophe Lyon
gcc/testsuite/
* g++.dg/abi/forced.C: Add *-*-uclinux*.
* g++.dg/abi/guard2.C: Likewise.
* g++.dg/ext/cleanup-10.C: Likewise.
* g++.dg/ext/cleanup-11.C: Likewise.
* g++.dg/ext/cleanup-8.C: Likewise.
* g++.dg/ext/cleanup-9.C: Likewise.
* g++.dg/ext/sync-4.C: Likewise.
* g++.dg/ipa/comdat.C: Likewise.
* gcc.dg/20041106-1.c: Likewise.
* gcc.dg/cleanup-10.c: Likewise.
* gcc.dg/cleanup-11.c: Likewise.
* gcc.dg/cleanup-8.c: Likewise.
* gcc.dg/cleanup-9.c: Likewise.
* gcc.dg/fdata-sections-1.c: Likewise.
* gcc.dg/fdata-sections-2.c: Likewise.
* gcc.dg/pr39323-1.c: Likewise.
* gcc.dg/pr39323-2.c: Likewise.
* gcc.dg/pr39323-3.c: Likewise.
* gcc.dg/pr65780-1.c: Likewise.
* gcc.dg/pr65780-2.c: Likewise.
* gcc.dg/pr67338.c: Likewise.
* gcc.dg/pr78185.c: Likewise.
* gcc.dg/pr83100-1.c: Likewise.
* gcc.dg/pr83100-4.c: Likewise.
* gcc.dg/strlenopt-12g.c: Likewise.
* gcc.dg/strlenopt-14g.c: Likewise.
* gcc.dg/strlenopt-14gf.c: Likewise.
* gcc.dg/strlenopt-16g.c: Likewise.
* gcc.dg/strlenopt-17g.c: Likewise.
* gcc.dg/strlenopt-18g.c: Likewise.
* gcc.dg/strlenopt-1f.c: Likewise.
* gcc.dg/strlenopt-22g.c: Likewise.
* gcc.dg/strlenopt-2f.c: Likewise.
* gcc.dg/strlenopt-31g.c: Likewise.
* gcc.dg/strlenopt-33g.c: Likewise.
* gcc.dg/strlenopt-4g.c: Likewise.
* gcc.dg/strlenopt-4gf.c: Likewise.
* gcc.dg/strncmp-2.c: Likewise.
* gcc.dg/struct-ret-3.c: Likewise.
* gcc.dg/torture/pr69760.c: Likewise.
* gcc.target/arm/div64-unwinding.c: Likewise.
* gcc.target/arm/stack-checking.c: Likewise.
* gcc.target/arm/synchronize.c: Likewise.
* gcc.target/arm/pr66912.c: Add arm*-*-uclinuxfdpiceabi.
* lib/target-supports.exp (check_effective_target_pie): Likewise.
(check_effective_target_sync_long_long_runtime): Likewise.
(check_effective_target_sync_int_long): Likewise.
(check_effective_target_sync_char_short): Likewise.
Change-Id: I89bfea79d4490c5df0b6470def5a31d7f31ac2cc
diff --git a/gcc/testsuite/g++.dg/abi/forced.C
b/gcc/testsuite/g++.dg/abi/forced.C
index 0e6be28..2d1ec53 100644
--- a/gcc/testsuite/g++.dg/abi/forced.C
+++ b/gcc/testsuite/g++.dg/abi/forced.C
@@ -1,4 +1,4 @@
-// { dg-do run { target *-*-linux* *-*-gnu* } }
+// { dg-do run { target *-*-linux* *-*-gnu* *-*-uclinux* } }
// { dg-options "-pthread" }
#include
diff --git a/gcc/testsuite/g++.dg/abi/guard2.C
b/gcc/testsuite/g++.dg/abi/guard2.C
index c35fa7e..74139a8 100644
--- a/gcc/testsuite/g++.dg/abi/guard2.C
+++ b/gcc/testsuite/g++.dg/abi/guard2.C
@@ -1,6 +1,6 @@
// PR c++/41611
// Test that the guard gets its own COMDAT group.
-// { dg-final { scan-assembler "_ZGVZN1A1fEvE1i,comdat" { target *-*-linux*
*-*-gnu* } } }
+// { dg-final { scan-assembler "_ZGVZN1A1fEvE1i,comdat" { target *-*-linux*
*-*-gnu* *-*-uclinux* } } }
struct A {
static int f()
diff --git a/gcc/testsuite/g++.dg/ext/cleanup-10.C
b/gcc/testsuite/g++.dg/ext/cleanup-10.C
index 66c7b76..56aeb66 100644
--- a/gcc/testsuite/g++.dg/ext/cleanup-10.C
+++ b/gcc/testsuite/g++.dg/ext/cleanup-10.C
@@ -1,4 +1,4 @@
-/* { dg-do run { target hppa*-*-hpux* *-*-linux* *-*-gnu* powerpc*-*-darwin*
*-*-darwin[912]* } } */
+/* { dg-do run { target hppa*-*-hpux* *-*-linux* *-*-gnu* powerpc*-*-darwin*
*-*-darwin[912]* *-*-uclinux* } } */
/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */
/* Verify that cleanups work with exception handling through signal frames
on alternate stack. */
diff --git a/gcc/testsuite/g++.dg/ext/cleanup-11.C
b/gcc/testsuite/g++.dg/ext/cleanup-11.C
index 6e96521..c6d3560 100644
--- a/gcc/testsuite/g++.dg/ext/cleanup-11.C
+++ b/gcc/testsuite/g++.dg/ext/cleanup-11.C
@@ -1,4 +1,4 @@
-/* { dg-do run { target hppa*-*-hpux* *-*-linux* *-*-gnu* powerpc*-*-darwin*
*-*-darwin[912]* } } */
+/* { dg-do run { target hppa*-*-hpux* *-*-linux* *-*-gnu* powerpc*-*-darwin*
*-*-darwin[912]* *-*-uclinux* } } */
/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */
/* Verify that cleanups work with exception handling through realtime signal
frames on alternate stack. */
diff --git a/gcc/testsuite/g++.dg/ext/cleanup-8.C
b/gcc/testsuite/g++.dg/ext/cleanup-8.C
index ccf9bef..e99508d 100644
--- a/gcc/testsuite/g++.dg/ext/cleanup-8.C
+++ b/gcc/testsuite/g++.dg/ext/cleanup-8.C
@@ -1,4 +1,4 @@
-/* { dg-do run { target hppa*-*-hpux* *-*-linux* *-*-gnu* powerpc*-*-darwin*
*-*-darwin[912]* } } */
+/* { dg-do run { target hppa*-*-hpux* *-*-linux* *-*-gnu* powerpc*-*-darwin*
*-*-darwin[912]* *-*-uclinux* } } */
/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */
/* Verify that cleanups work with exception
[ARM/FDPIC v4 19/20] [ARM][testsuite] FDPIC: Adjust pr43698.c to avoid clash with uclibc.
uclibc defines bswap_32, so use a different name in this test.
2018-XX-XX Christophe Lyon
gcc/testsuite/
* gcc.target/arm/pr43698.c (bswap_32): Rename as my_bswap_32.
Change-Id: I2591bd911030814331cabf97ee5cf6cf8124b4f3
diff --git a/gcc/testsuite/gcc.target/arm/pr43698.c
b/gcc/testsuite/gcc.target/arm/pr43698.c
index 1fc497c..3b5dad0 100644
--- a/gcc/testsuite/gcc.target/arm/pr43698.c
+++ b/gcc/testsuite/gcc.target/arm/pr43698.c
@@ -6,7 +6,7 @@
char do_reverse_endian = 0;
-# define bswap_32(x) \
+# define my_bswap_32(x) \
x) & 0xff00) >> 24) | \
(((x) & 0x00ff) >> 8) | \
(((x) & 0xff00) << 8) | \
@@ -16,7 +16,7 @@ char do_reverse_endian = 0;
(__extension__ ({ \
uint64_t __res; \
if (!do_reverse_endian) {__res = (X); \
- } else if (sizeof(X) == 4) { __res = bswap_32((X)); \
+ } else if (sizeof(X) == 4) { __res = my_bswap_32((X)); \
} \
__res; \
}))
--
2.6.3
[ARM/FDPIC v4 18/20] [ARM][testsuite] FDPIC: Enable tests on pie_enabled targets
Some tests have the "nonpic" guard, but pass on
arm*-*-uclinuxfdpiceabi because it is in PIE mode by default. Rather
than adding this target to all these tests, add the "pie_enabled"
effective target.
2018-XX-XX Christophe Lyon
gcc/testsuite/
* g++.dg/cpp0x/noexcept03.C: Add pie_enabled.
* g++.dg/ipa/devirt-c-7.C: Likewise.
* g++.dg/ipa/ivinline-1.C: Likewise.
* g++.dg/ipa/ivinline-2.C: Likewise.
* g++.dg/ipa/ivinline-3.C: Likewise.
* g++.dg/ipa/ivinline-4.C: Likewise.
* g++.dg/ipa/ivinline-5.C: Likewise.
* g++.dg/ipa/ivinline-7.C: Likewise.
* g++.dg/ipa/ivinline-8.C: Likewise.
* g++.dg/ipa/ivinline-9.C: Likewise.
* g++.dg/tls/pr79288.C: Likewise.
* gcc.dg/addr_equal-1.c: Likewise.
* gcc.dg/const-1.c: Likewise.
* gcc.dg/ipa/pure-const-1.c: Likewise.
* gcc.dg/noreturn-8.c: Likewise.
* gcc.dg/pr33826.c: Likewise.
* gcc.dg/torture/ipa-pta-1.c: Likewise.
* gcc.dg/tree-ssa/alias-2.c: Likewise.
* gcc.dg/tree-ssa/ipa-split-5.c: Likewise.
* gcc.dg/tree-ssa/loadpre6.c: Likewise.
* gcc.dg/uninit-19.c: Likewise.
Change-Id: I1a0d836b892c23891f739fccdc467d0f354ab82c
diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept03.C
b/gcc/testsuite/g++.dg/cpp0x/noexcept03.C
index 2d37867..906a44d 100644
--- a/gcc/testsuite/g++.dg/cpp0x/noexcept03.C
+++ b/gcc/testsuite/g++.dg/cpp0x/noexcept03.C
@@ -1,6 +1,6 @@
// Runtime test for noexcept-specification.
// { dg-options "-Wnoexcept" }
-// { dg-do run { target nonpic } }
+// { dg-do run { target { nonpic || pie_enabled } } }
// { dg-require-effective-target c++11 }
#include
diff --git a/gcc/testsuite/g++.dg/ipa/devirt-c-7.C
b/gcc/testsuite/g++.dg/ipa/devirt-c-7.C
index 2e76cbe..efb65c2 100644
--- a/gcc/testsuite/g++.dg/ipa/devirt-c-7.C
+++ b/gcc/testsuite/g++.dg/ipa/devirt-c-7.C
@@ -1,7 +1,6 @@
/* Verify that ipa-cp will not get confused by placement new constructing an
object within another one when looking for dynamic type change . */
-/* { dg-do run } */
-/* { dg-require-effective-target nonpic } */
+/* { dg-do run { target { nonpic || pie_enabled } } } */
/* { dg-options "-O3 -Wno-attributes" } */
extern "C" void abort (void);
diff --git a/gcc/testsuite/g++.dg/ipa/ivinline-1.C
b/gcc/testsuite/g++.dg/ipa/ivinline-1.C
index 9b10d20..2d988bc 100644
--- a/gcc/testsuite/g++.dg/ipa/ivinline-1.C
+++ b/gcc/testsuite/g++.dg/ipa/ivinline-1.C
@@ -1,6 +1,6 @@
/* Verify that simple virtual calls are inlined even without early
inlining. */
-/* { dg-do run { target nonpic } } */
+/* { dg-do run { target { nonpic || pie_enabled } } } */
/* { dg-options "-O3 -fdump-ipa-inline -fno-early-inlining -fno-ipa-cp" } */
extern "C" void abort (void);
diff --git a/gcc/testsuite/g++.dg/ipa/ivinline-2.C
b/gcc/testsuite/g++.dg/ipa/ivinline-2.C
index 21cd46f..d978638 100644
--- a/gcc/testsuite/g++.dg/ipa/ivinline-2.C
+++ b/gcc/testsuite/g++.dg/ipa/ivinline-2.C
@@ -1,6 +1,6 @@
/* Verify that simple virtual calls using this pointer are inlined
even without early inlining.. */
-/* { dg-do run { target nonpic } } */
+/* { dg-do run { target { nonpic || pie_enabled } } } */
/* { dg-options "-O3 -fdump-ipa-inline -fno-early-inlining -fno-ipa-cp" } */
extern "C" void abort (void);
diff --git a/gcc/testsuite/g++.dg/ipa/ivinline-3.C
b/gcc/testsuite/g++.dg/ipa/ivinline-3.C
index 1e24644..f756a16 100644
--- a/gcc/testsuite/g++.dg/ipa/ivinline-3.C
+++ b/gcc/testsuite/g++.dg/ipa/ivinline-3.C
@@ -1,6 +1,6 @@
/* Verify that simple virtual calls on an object refrence are inlined
even without early inlining. */
-/* { dg-do run { target nonpic } } */
+/* { dg-do run { target { nonpic || pie_enabled } } } */
/* { dg-options "-O3 -fdump-ipa-inline -fno-early-inlining -fno-ipa-cp" } */
extern "C" void abort (void);
diff --git a/gcc/testsuite/g++.dg/ipa/ivinline-4.C
b/gcc/testsuite/g++.dg/ipa/ivinline-4.C
index cf0d980..5fbd3ef 100644
--- a/gcc/testsuite/g++.dg/ipa/ivinline-4.C
+++ b/gcc/testsuite/g++.dg/ipa/ivinline-4.C
@@ -1,7 +1,7 @@
/* Verify that simple virtual calls are inlined even without early
inlining, even when a typecast to an ancestor is involved along the
way. */
-/* { dg-do run { target nonpic } } */
+/* { dg-do run { target { nonpic || pie_enabled } } } */
/* { dg-options "-O3 -fdump-ipa-inline -fno-early-inlining -fno-ipa-cp" } */
extern "C" void abort (void);
diff --git a/gcc/testsuite/g++.dg/ipa/ivinline-5.C
b/gcc/testsuite/g++.dg/ipa/ivinline-5.C
index f15ebf2..6c19907 100644
--- a/gcc/testsuite/g++.dg/ipa/ivinline-5.C
+++ b/gcc/testsuite/g++.dg/ipa/ivinline-5.C
@@ -1,6 +1,6 @@
/* Verify that virtual call inlining does not pick a wrong method when
there is a user defined ancestor in an object. */
-/* { dg-do run { target nonpic } } */
+/* { dg-do run { target { nonpic || pie_enabled } } } */
/* { dg-options "-O3 -fdump-ipa-inline -fno-early-inlining -fno-i
[ARM/FDPIC v4 20/20] [ARM][testsuite] FDPIC: Skip tests using architectures unsupported by FDPIC
Since FDPIC currently supports arm and thumb-2 modes only, these tests
fail because they enforce an architecture version that doesn't match
these restrictions.
This patch introduces new values for the arm_arch effective-target
(v4t_thumb, v5t_thumb, v5te_thumb, v6_thumb, v6k_thumb, v6z_thumb) as
needed, and adds them to the relevant tests. It also adds the
corresponding non-thumb effective-target to the tests that were
missing it.
2018-07-13 Christophe Lyon
* lib/target-supports.exp
(check_effective_target_arm_arch_FUNC_ok): Add v4t_thumb,
v5t_thumb, v5te_thumb, v6_thumb, v6k_thumb, v6z_thumb.
* gcc.target/arm/armv6-unaligned-load-ice.c: Add arm_arch
effective-target.
* gcc.target/arm/attr-unaligned-load-ice.c: Likewise.
* gcc.target/arm/attr_arm-err.c: Likewise.
* gcc.target/arm/ftest-armv4-arm.c: Likewise.
* gcc.target/arm/ftest-armv4t-arm.c: Likewise.
* gcc.target/arm/ftest-armv4t-thumb.c: Likewise.
* gcc.target/arm/ftest-armv5t-arm.c: Likewise.
* gcc.target/arm/ftest-armv5t-thumb.c: Likewise.
* gcc.target/arm/ftest-armv5te-arm.c: Likewise.
* gcc.target/arm/ftest-armv5te-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6-arm.c: Likewise.
* gcc.target/arm/ftest-armv6-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6k-arm.c: Likewise.
* gcc.target/arm/ftest-armv6k-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6m-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6t2-arm.c: Likewise.
* gcc.target/arm/ftest-armv6t2-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6z-arm.c: Likewise.
* gcc.target/arm/ftest-armv6z-thumb.c: Likewise.
* gcc.target/arm/g2.c: Likewise.
* gcc.target/arm/macro_defs1.c: Likewise.
* gcc.target/arm/pr59858.c: Likewise.
* gcc.target/arm/pr65647-2.c: Likewise.
* gcc.target/arm/pr79058.c: Likewise.
* gcc.target/arm/pr83712.c: Likewise.
* gcc.target/arm/pragma_arch_switch_2.c: Likewise.
* gcc.target/arm/scd42-1.c: Likewise.
* gcc.target/arm/scd42-2.c: Likewise.
* gcc.target/arm/scd42-3.c: Likewise.
* gcc.c-torture/compile/pr82096.c: Fix arm_arch effective-target.
Change-Id: I0845b262b241026561cc52a19ff8bb1659675e49
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr82096.c
b/gcc/testsuite/gcc.c-torture/compile/pr82096.c
index d144b70..4e695cd 100644
--- a/gcc/testsuite/gcc.c-torture/compile/pr82096.c
+++ b/gcc/testsuite/gcc.c-torture/compile/pr82096.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target arm_arch_v5t_ok { target arm*-*-* } } */
+/* { dg-require-effective-target arm_arch_v5t_thumb_ok { target arm*-*-* } } */
/* { dg-skip-if "Do not combine float-abi values" { arm*-*-* } {
"-mfloat-abi=*" } { "-mfloat-abi=soft" } } */
/* { dg-additional-options "-march=armv5t -mthumb -mfloat-abi=soft" { target
arm*-*-* } } */
diff --git a/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
b/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
index 88528f1..886a012 100644
--- a/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
+++ b/gcc/testsuite/gcc.target/arm/armv6-unaligned-load-ice.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv6k" } } */
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } {
"" } } */
+/* { dg-require-effective-target arm_arch_v6k_thumb_ok } */
/* { dg-options "-mthumb -Os -mfloat-abi=softfp" } */
/* { dg-add-options arm_arch_v6k } */
diff --git a/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
b/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
index e1ed1c1..2eeb522 100644
--- a/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
+++ b/gcc/testsuite/gcc.target/arm/attr-unaligned-load-ice.c
@@ -2,6 +2,7 @@
Verify that unaligned_access is correctly with attribute target. */
/* { dg-do compile } */
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv6" } } */
+/* { dg-require-effective-target arm_arch_v6_ok } */
/* { dg-options "-Os -mfloat-abi=softfp -mtp=soft" } */
/* { dg-add-options arm_arch_v6 } */
diff --git a/gcc/testsuite/gcc.target/arm/attr_arm-err.c
b/gcc/testsuite/gcc.target/arm/attr_arm-err.c
index 630c06a..d410056 100644
--- a/gcc/testsuite/gcc.target/arm/attr_arm-err.c
+++ b/gcc/testsuite/gcc.target/arm/attr_arm-err.c
@@ -2,6 +2,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_arm_ok } */
/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" }
{ "-march=armv6-m" } } */
+/* { dg-require-effective-target arm_arch_v6m_ok } */
/* { dg-add-options arm_arch_v6m } */
int __attribute__((target("arm")))
diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
index 4b48ef8..447a8ec 100644
--- a/gcc/test
Re: [PATCH] avoid -Wnonnull for printf format in dead code (PR 87041)
On 11/15/18 12:06 PM, Martin Sebor wrote:
> On 11/15/2018 02:39 AM, Matthew Malcomson wrote:
>> On 02/11/18 09:54, Christophe Lyon wrote:
>>> Hi,
>>>
>>> I've noticed failure on targets using newlib (aarch64-elf and arm-eabi):
>>> FAIL: gcc.c-torture/execute/printf-2.c
>>> FAIL: gcc.c-torture/execute/user-printf.c
>>>
>>> my gcc.log contains:
>>> gcc.c-torture/execute/user-printf.c -O0 execution test (reason: TCL
>>> LOOKUP CHANNEL exp5)
>>> which is not very helpful
>>>
>>
>> @Christophe
>> Can I ask if your DejaGNU board setup has "needs_status_wrapper 1" for
>> both of these boards?
>>
>> I believe this problem is caused by an interaction with the DejaGNU
>> status wrapper.
>>
>> When the status wrapper is needed, DejaGNU looks at stdout for a line
>> saying "*** EXIT code " indicating what the status code was.
>> When it doesn't find that line it assumes an exit code of 2.
>> Without the status wrapper DejaGNU takes the return code from the
>> program executed.
>>
>> Because these tests use "freopen ()" on stdout, the status wrapper fails
>> to print to the IO channel DejaGNU is listening on, hence DejaGNU fails
>> to find it's line, uses an exit code of 2, and fails the test.
>>
>>
>> @Martin
>> Would these tests still be valid having run freopen on stderr and using
>> fprintf instead of printf?
>> That makes the testcases pass for me.
>
> The printf-2.c test specifically exercises the printf built-in,
> i.e., not fprintf, so changing it to use fprintf would defeat
> its purpose.
>
> user-printf.c does something similar but for a user-defined
> function with attribute format (printf).
>
> The purpose of the tests is to verify that what they read from
> the temporary file matches what they wrote (i.e,, that none of
> the printf() or user_print() calls was incorrectly eliminated).
>
>> If not we could add an
>> { dg-require-effective-target unwrapped }
>> directive in the testcases to stop the failure complaints.
>
> I'm not familiar with this directive or really know what
> a status wrapper is but as long as it doesn't change the I/O
> the test does I think it should be fine.
Wrapping in this context refers to the dejagnu harness wrapping to
facilitate testing of remote and embedded targets where getting the real
exit status of an execution test is painful.
We wrap main, exit and abort. The wrappers print info to stdout to
indicate exit status which can reliably be read by the harness.
At least that's my recollection of the wrapper bits.
jeff
Re: PING [PATCH] add simple attribute introspection
On 11/15/18 8:06 PM, Martin Sebor wrote:
> Ping: https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01473.html
> (Still looking for an approval.)
>
> On 11/09/2018 04:43 PM, Martin Sebor wrote:
>> On 11/09/2018 12:59 PM, Jeff Law wrote:
>>> On 10/31/18 10:27 AM, Martin Sebor wrote:
Ping: https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01473.html
With the C++ bits approved I'm still looking for a review/approval
of the remaining changes: the C front end and the shared c-family
handling of the new built-in.
>>> I thought I acked those with just a couple minor doc nits:
>>
>> I don't see a formal approval for the rest in my Inbox or in
>> the archive.
>>
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 8ffb0cd..dcf4747 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2649,8 +2649,9 @@ explicit @code{externally_visible} attributes
>>> are still necessary.
@cindex @code{flatten} function attribute
Generally, inlining into a function is limited. For a function
>>> marked with
this attribute, every call inside this function is inlined, if
possible.
-Whether the function itself is considered for inlining depends on its
>>> size and
-the current inlining parameters.
+Functions declared with attribute @code{noinline} and similar are not
+inlined. Whether the function itself is considered for inlining
depends
+on its size and the current inlining parameters.
>>> Guessing this was from another doc patch that I think has already been
>>> approved
>>
>> Yes. It shouldn't be in the latest patch at the link above.
>>
@@ -11726,6 +11728,33 @@ check its compatibility with @var{size}.
@end deftypefn
+@deftypefn {Built-in Function} bool __builtin_has_attribute
>>> (@var{type-or-expression}, @var{attribute})
+The @code{__builtin_has_attribute} function evaluates to an integer
>>> constant
+expression equal to @code{true} if the symbol or type referenced by
+the @var{type-or-expression} argument has been declared with
+the @var{attribute} referenced by the second argument. Neither
argument
+is valuated. The @var{type-or-expression} argument is subject to the
>>> same
>>> s/valuated/evaluated/ ?
>>
>> This should also be fixed in the latest patch at the link above.
>>
>>> Did the implementation change significantly requiring another review
>>> iteration?
>>
>> I don't think it changed too significantly between the last two
>> revisions but I don't have a record of anyone having approved
>> the C FE and the middle-end bits. (Sorry if I missed it.) Other
>> than this response from you all I see in the archive is this:
>>
>> https://gcc.gnu.org/ml/gcc-patches/2018-10/msg00606.html
>>
>> Please let me if the last revision is okay to commit.
Yes. It's fine to commit.
jeff
Re: [PATCH 21/25] GCN Back-end (part 2/2).
On Mon, Nov 12, 2018 at 11:54:58AM -0700, Jeff Law wrote: > On 11/12/18 10:52 AM, Andrew Stubbs wrote: > > If there are two instructions that both have an UNSPEC_VOLATILE, will > > combine coalesce them into one in the combined pattern? > I think you can put a different constant on each. combine (like everything else) will not remove an unspec_volatile. Two identical ones can be merged, in theory anyway, but the resulting program will always still execute the same number of them, in the same order. unspec_volatile's have unknown side effects, and those have to happen. If you really need to prevent merging them, then sure, using different unspec numbers will work, sure. Segher
[Patch][gcc][testsuite] Skip testcases using freopen when on wrapped board
On 16/11/18 16:04, Jeff Law wrote:
> On 11/15/18 12:06 PM, Martin Sebor wrote:
>> On 11/15/2018 02:39 AM, Matthew Malcomson wrote:
>>> If not we could add an
>>> { dg-require-effective-target unwrapped }
>>> directive in the testcases to stop the failure complaints.
>> I'm not familiar with this directive or really know what
>> a status wrapper is but as long as it doesn't change the I/O
>> the test does I think it should be fine.
> Wrapping in this context refers to the dejagnu harness wrapping to
> facilitate testing of remote and embedded targets where getting the real
> exit status of an execution test is painful.
>
> We wrap main, exit and abort. The wrappers print info to stdout to
> indicate exit status which can reliably be read by the harness.
>
> At least that's my recollection of the wrapper bits.
>
> jeff
That's my understanding too -- since the wrappers print to stdout they
are affected by the freopen call the test made and hence the exit status
is not printed where DejaGNU is looking.
Hence DejaGNU can't read the exit status and defaults to a status of 2,
FAILing the test.
This directive just skips the testcase completely when the status
wrapper is being used, so we get an UNSUPPORTED instead of FAIL test result.
Suggested change below.
===
When running the testsuite on boards that can't report an error status
DejaGNU uses a special wrapper to print the exit code on stdout and
parses stdout to find whether an execution failed or passed.
In testcases that use "freopen (..., ..., stdout)" this special line is
printed to the alternate location described in the freopen call and
DejaGNU can't find the error code.
This results in DejaGNU using a default return status of 2 and the test
failing.
This patch skips the two testcases that use freopen on stdout when
testing a board that requires the status wrapper.
Testing done by running these two tests on arm-none-eabi cross build and
observing that they are now unsupported.
gcc/testsuite/ChangeLog:
2018-11-16 Matthew Malcomson
* gcc.c-torture/execute/printf-2.c: Skip on wrapped boards.
* gcc.c-torture/execute/user-printf.c: Likewise.
### Attachment also inlined for ease of reply
###
diff --git a/gcc/testsuite/gcc.c-torture/execute/printf-2.c
b/gcc/testsuite/gcc.c-torture/execute/printf-2.c
index
50741101bbd64fb301e3069b01d423b4d007f575..2e9f2a2bb755221ec49baad0737e51f579bf
100644
--- a/gcc/testsuite/gcc.c-torture/execute/printf-2.c
+++ b/gcc/testsuite/gcc.c-torture/execute/printf-2.c
@@ -1,6 +1,7 @@
/* Verify that calls to printf don't get eliminated even if their
result on success can be computed at compile time (they can fail).
The calls can still be transformed into those of other functions.
+ { dg-require-effective-target unwrapped }
{ dg-skip-if "requires io" { freestanding } } */
#include
diff --git a/gcc/testsuite/gcc.c-torture/execute/user-printf.c
b/gcc/testsuite/gcc.c-torture/execute/user-printf.c
index
e5784ed8e961e87c8f2d8ba85bbee6bb1b432155..11c61fa3949e962595ca7142bbcecb774fb8231f
100644
--- a/gcc/testsuite/gcc.c-torture/execute/user-printf.c
+++ b/gcc/testsuite/gcc.c-torture/execute/user-printf.c
@@ -1,6 +1,7 @@
/* Verify that calls to a function declared wiith attribute format
(printf)
don't get eliminated even if their result on success can be computed at
compile time (they can fail).
+ { dg-require-effective-target unwrapped }
{ dg-skip-if "requires io" { freestanding } } */
#include
diff --git a/gcc/testsuite/gcc.c-torture/execute/printf-2.c b/gcc/testsuite/gcc.c-torture/execute/printf-2.c
index 50741101bbd64fb301e3069b01d423b4d007f575..2e9f2a2bb755221ec49baad0737e51f579bf 100644
--- a/gcc/testsuite/gcc.c-torture/execute/printf-2.c
+++ b/gcc/testsuite/gcc.c-torture/execute/printf-2.c
@@ -1,6 +1,7 @@
/* Verify that calls to printf don't get eliminated even if their
result on success can be computed at compile time (they can fail).
The calls can still be transformed into those of other functions.
+ { dg-require-effective-target unwrapped }
{ dg-skip-if "requires io" { freestanding } } */
#include
diff --git a/gcc/testsuite/gcc.c-torture/execute/user-printf.c b/gcc/testsuite/gcc.c-torture/execute/user-printf.c
index e5784ed8e961e87c8f2d8ba85bbee6bb1b432155..11c61fa3949e962595ca7142bbcecb774fb8231f 100644
--- a/gcc/testsuite/gcc.c-torture/execute/user-printf.c
+++ b/gcc/testsuite/gcc.c-torture/execute/user-printf.c
@@ -1,6 +1,7 @@
/* Verify that calls to a function declared wiith attribute format (printf)
don't get eliminated even if their result on success can be computed at
compile time (they can fail).
+ { dg-require-effective-target unwrapped }
{ dg-skip-if "requires io" { freestanding } } */
#include
Re: [Patch][gcc][testsuite] Skip testcases using freopen when on wrapped board
On 11/16/18 9:16 AM, Matthew Malcomson wrote:
> On 16/11/18 16:04, Jeff Law wrote:
>> On 11/15/18 12:06 PM, Martin Sebor wrote:
>>> On 11/15/2018 02:39 AM, Matthew Malcomson wrote:
If not we could add an
{ dg-require-effective-target unwrapped }
directive in the testcases to stop the failure complaints.
>>> I'm not familiar with this directive or really know what
>>> a status wrapper is but as long as it doesn't change the I/O
>>> the test does I think it should be fine.
>> Wrapping in this context refers to the dejagnu harness wrapping to
>> facilitate testing of remote and embedded targets where getting the real
>> exit status of an execution test is painful.
>>
>> We wrap main, exit and abort. The wrappers print info to stdout to
>> indicate exit status which can reliably be read by the harness.
>>
>> At least that's my recollection of the wrapper bits.
>>
>> jeff
>
> That's my understanding too -- since the wrappers print to stdout they
> are affected by the freopen call the test made and hence the exit status
> is not printed where DejaGNU is looking.
> Hence DejaGNU can't read the exit status and defaults to a status of 2,
> FAILing the test.
>
> This directive just skips the testcase completely when the status
> wrapper is being used, so we get an UNSUPPORTED instead of FAIL test result.
>
>
> Suggested change below.
> ===
>
> When running the testsuite on boards that can't report an error status
> DejaGNU uses a special wrapper to print the exit code on stdout and
> parses stdout to find whether an execution failed or passed.
>
> In testcases that use "freopen (..., ..., stdout)" this special line is
> printed to the alternate location described in the freopen call and
> DejaGNU can't find the error code.
>
> This results in DejaGNU using a default return status of 2 and the test
> failing.
>
> This patch skips the two testcases that use freopen on stdout when
> testing a board that requires the status wrapper.
>
> Testing done by running these two tests on arm-none-eabi cross build and
> observing that they are now unsupported.
>
> gcc/testsuite/ChangeLog:
>
> 2018-11-16 Matthew Malcomson
>
> * gcc.c-torture/execute/printf-2.c: Skip on wrapped boards.
> * gcc.c-torture/execute/user-printf.c: Likewise.
OK
jeff
[C++ PATCH] OVL_USED not needed
My earlier patch for 87269 got me thinking and I realized that now we
don't order the non-hidden overload members, we can no longer get into
the situation of needing to mutate non-hidden overload members. We only
prepend. So all the lookup keeping & ovl marking machinery can go away.
It is unreachable.
Applying to trunk.
nathan
--
Nathan Sidwell
2018-11-16 Nathan Sidwell
Remove ovl_used, it is no longer needed
* cp-tree.h (OVL_USED_P): Delete.
(lookup_keep): Delete.
* friend.c (add_friend): Don't call it.
* parser.c (lookup_literal_operator): Likewise.
(cp_parser_primary_expression): Likewise.
* semantics.c (perform_koenig_lookup): Likewise.
* pt.c (tsubst_copy ): Don't assert OVL_USED_P.
* tree.c (ovl_copy): Delete.
(ovl_insert): Remove OVL_USED_P checks.
(ovl_iterator::reveal_node): Likewise.
(ovl_iterator::remove__node): Likewise.
(ovl_used, lookup_keep): Delete.
Index: gcc/cp/cp-tree.h
===
--- gcc/cp/cp-tree.h (revision 266210)
+++ gcc/cp/cp-tree.h (working copy)
@@ -706,8 +706,6 @@ typedef struct ptrmem_cst * ptrmem_cst_t
#define OVL_NESTED_P(NODE) TREE_LANG_FLAG_3 (OVERLOAD_CHECK (NODE))
/* If set, this overload was constructed during lookup. */
#define OVL_LOOKUP_P(NODE) TREE_LANG_FLAG_4 (OVERLOAD_CHECK (NODE))
-/* If set, this is a persistant lookup. */
-#define OVL_USED_P(NODE) TREE_USED (OVERLOAD_CHECK (NODE))
/* The first decl of an overload. */
#define OVL_FIRST(NODE) ovl_first (NODE)
@@ -7222,7 +7220,6 @@ extern void lookup_mark(tree lookup,
extern tree lookup_add(tree fns, tree lookup);
extern tree lookup_maybe_add (tree fns, tree lookup,
bool deduping);
-extern void lookup_keep(tree lookup);
extern int is_overloaded_fn (tree) ATTRIBUTE_PURE;
extern bool really_overloaded_fn (tree) ATTRIBUTE_PURE;
extern tree dependent_name (tree);
Index: gcc/cp/friend.c
===
--- gcc/cp/friend.c (revision 266210)
+++ gcc/cp/friend.c (working copy)
@@ -173,12 +173,6 @@ add_friend (tree type, tree decl, bool c
if (decl == error_mark_node)
return;
- if (TREE_CODE (decl) == FUNCTION_DECL
- && DECL_TEMPLATE_INSTANTIATION (decl))
-/* We'll have parsed this as a declaration, and therefore not
- marked the lookup set for keeping. Do that now. */
-lookup_keep (DECL_TI_TEMPLATE (decl));
-
typedecl = TYPE_MAIN_DECL (type);
list = DECL_FRIENDLIST (typedecl);
name = DECL_NAME (decl);
Index: gcc/cp/parser.c
===
--- gcc/cp/parser.c (revision 266210)
+++ gcc/cp/parser.c (working copy)
@@ -4294,11 +4294,7 @@ lookup_literal_operator (tree name, vec<
work in presence of default arguments on the literal
operator parameters. */
&& parmtypes == void_list_node)
- {
- if (processing_template_decl)
- lookup_keep (decl);
- return decl;
- }
+ return decl;
}
}
@@ -5684,14 +5680,6 @@ cp_parser_primary_expression (cp_parser
}
}
- if (processing_template_decl)
- if (tree fns = maybe_get_fns (decl))
- /* It's too difficult to mark ths in all the places where
- we know for sure we need to keep the lookup, so do it
- now. The cost is extra GC to recycle the lookups
- resolved at parse time. */
- lookup_keep (fns);
-
decl = (finish_id_expression
(id_expression, decl, parser->scope,
idk,
Index: gcc/cp/pt.c
===
--- gcc/cp/pt.c (revision 266210)
+++ gcc/cp/pt.c (working copy)
@@ -15541,8 +15541,6 @@ tsubst_copy (tree t, tree args, tsubst_f
return t;
case OVERLOAD:
- /* We must have marked any lookups as persistent. */
- gcc_assert (!OVL_LOOKUP_P (t) || OVL_USED_P (t));
return t;
case BASELINK:
Index: gcc/cp/semantics.c
===
--- gcc/cp/semantics.c (revision 266210)
+++ gcc/cp/semantics.c (working copy)
@@ -2345,11 +2345,6 @@ perform_koenig_lookup (cp_expr fn, vecf",
"c.f", "C::f", and "f" will all be considered possibly
Re: [PATCH] Fix PR87927, implement TARGET_ASM_{,UN}ALIGNED_P{S,D,T}I_OP
On 11/14/18 4:05 AM, Jozef Lawrynowicz wrote:
> Use of the patchable_function_entry attribute when the pointer mode is a
> partial int mode can cause a segfault.
> The handler for this attribute tries to write out the assembler directive
> for an integer with bytesize POINTER_SIZE_UNITS, so if this is not 2, 4, 8 or
>
> 16 NULL is returned, resulting in a segfault.
>
> This was observed on msp430-elf with the large memory model, where
> POINTER_SIZE
>
> is 20, and so POINTER_SIZE_UNITS is 3.
>
> Fixed by implementing TARGET_ASM_{,UN}ALIGNED_PSI_OP, and extending "struct
> asm_int_op".
>
> For completeness I added the hooks for PDImode (used by bfin) and PTImode
> (used
>
> by rs6000). However, these aren't tied to any real types as they are used
> for register modes, so I can't see this patch having any effect for these
> targets. Since there's no way to represent these modes in memory, the compiler
>
> will never need to write out an assembler directive for them.
>
> Successfully bootstrapped and regtested current trunk for x86_64-pc-linux-gnu
>
> and regtested msp430-elf with -mlarge.
>
> Ok for trunk?
>
>
> 0001-Implement-TARGET_ASM_-UN-ALIGNED_P-S-D-T-I_OP.patch
>
> From 48890bd01668f68bafbd94556c9754bf2406 Mon Sep 17 00:00:00 2001
> From: Jozef Lawrynowicz
> Date: Thu, 8 Nov 2018 13:42:27 +
> Subject: [PATCH] Implement TARGET_ASM_{,UN}ALIGNED_P{S,D,T}I_OP
>
> 2018-11-14 Jozef Lawrynowicz
>
> PR target/87927
>
> gcc/ChangeLog:
>
> * target-def.h: Initialize TARGET_ASM_{,UN}ALIGNED_P{S,D,T}I_OP.
> Add them to the TARGET_ASM_{,UN}ALIGNED_INT_OP structs.
> * target.def: Enumerate TARGET_ASM_{,UN}ALIGNED_P{S,D,T}I_OP in
> the byte_op hook.
> * target.h: Add psi, pdi, pti to struct asm_int_op definition.
> * targhooks.c (default_print_patchable_function_entry): Assert
> asm_int_op does not return a NULL string.
> * varasm.c (integer_asm_op): Return the op for a partial int type
> when the requested size does not correspond to an integer type.
> * config/msp430/msp430.c: Initialize TARGET_ASM_{,UN}ALIGNED_PSI_OP.
OK
jeff
Re: [Patch][gcc][testsuite] Skip testcases using freopen when on wrapped board
On Fri, 16 Nov 2018 at 17:16, Matthew Malcomson
wrote:
>
> On 16/11/18 16:04, Jeff Law wrote:
> > On 11/15/18 12:06 PM, Martin Sebor wrote:
> >> On 11/15/2018 02:39 AM, Matthew Malcomson wrote:
> >>> If not we could add an
> >>> { dg-require-effective-target unwrapped }
> >>> directive in the testcases to stop the failure complaints.
> >> I'm not familiar with this directive or really know what
> >> a status wrapper is but as long as it doesn't change the I/O
> >> the test does I think it should be fine.
> > Wrapping in this context refers to the dejagnu harness wrapping to
> > facilitate testing of remote and embedded targets where getting the real
> > exit status of an execution test is painful.
> >
> > We wrap main, exit and abort. The wrappers print info to stdout to
> > indicate exit status which can reliably be read by the harness.
> >
> > At least that's my recollection of the wrapper bits.
> >
> > jeff
>
> That's my understanding too -- since the wrappers print to stdout they
> are affected by the freopen call the test made and hence the exit status
> is not printed where DejaGNU is looking.
> Hence DejaGNU can't read the exit status and defaults to a status of 2,
> FAILing the test.
>
> This directive just skips the testcase completely when the status
> wrapper is being used, so we get an UNSUPPORTED instead of FAIL test result.
>
>
> Suggested change below.
> ===
>
> When running the testsuite on boards that can't report an error status
> DejaGNU uses a special wrapper to print the exit code on stdout and
> parses stdout to find whether an execution failed or passed.
>
> In testcases that use "freopen (..., ..., stdout)" this special line is
> printed to the alternate location described in the freopen call and
> DejaGNU can't find the error code.
>
> This results in DejaGNU using a default return status of 2 and the test
> failing.
>
> This patch skips the two testcases that use freopen on stdout when
> testing a board that requires the status wrapper.
>
> Testing done by running these two tests on arm-none-eabi cross build and
> observing that they are now unsupported.
>
> gcc/testsuite/ChangeLog:
>
> 2018-11-16 Matthew Malcomson
>
> * gcc.c-torture/execute/printf-2.c: Skip on wrapped boards.
> * gcc.c-torture/execute/user-printf.c: Likewise.
>
Looks OK for me.
Thanks for the analysis, which I guess was a bit painful :)
>
>
> ### Attachment also inlined for ease of reply
> ###
>
>
> diff --git a/gcc/testsuite/gcc.c-torture/execute/printf-2.c
> b/gcc/testsuite/gcc.c-torture/execute/printf-2.c
> index
> 50741101bbd64fb301e3069b01d423b4d007f575..2e9f2a2bb755221ec49baad0737e51f579bf
> 100644
> --- a/gcc/testsuite/gcc.c-torture/execute/printf-2.c
> +++ b/gcc/testsuite/gcc.c-torture/execute/printf-2.c
> @@ -1,6 +1,7 @@
> /* Verify that calls to printf don't get eliminated even if their
> result on success can be computed at compile time (they can fail).
> The calls can still be transformed into those of other functions.
> + { dg-require-effective-target unwrapped }
> { dg-skip-if "requires io" { freestanding } } */
>
> #include
> diff --git a/gcc/testsuite/gcc.c-torture/execute/user-printf.c
> b/gcc/testsuite/gcc.c-torture/execute/user-printf.c
> index
> e5784ed8e961e87c8f2d8ba85bbee6bb1b432155..11c61fa3949e962595ca7142bbcecb774fb8231f
> 100644
> --- a/gcc/testsuite/gcc.c-torture/execute/user-printf.c
> +++ b/gcc/testsuite/gcc.c-torture/execute/user-printf.c
> @@ -1,6 +1,7 @@
> /* Verify that calls to a function declared wiith attribute format
> (printf)
> don't get eliminated even if their result on success can be computed at
> compile time (they can fail).
> + { dg-require-effective-target unwrapped }
> { dg-skip-if "requires io" { freestanding } } */
>
> #include
>
Re: [PATCH]Come up with -flive-patching master option.
> On Nov 16, 2018, at 9:51 AM, Jan Hubicka wrote: > >> On 11/16/18 2:36 AM, Qing Zhao wrote: >>> Hi, >>> >>> this is the new version of the patch. >>> >>> I have bootstrapped it on both aarch64 and x86, no regression. >>> >>> please take a look. >> >> Thanks for the updated version of the patch. >> I have last small nits I see: >> >> - gcc/common.opt: when running --help=common, the line is too long >> - gcc/doc/invoke.texi - 2 spaces in between sentences + better gol >> - gcc/opts.c - do not mix spaces + tabs >> >> With that I'm fine. But note that I'm not a maintainer :) > > I wonder what happens, when I pass like -flive-patching -fwhole-program > compared to -fwhole-program -flive-patching. > It seems to me that in first case we will end up with whole-program > optimization while in the second we won't. > > I guess we should behave in a way that we disable the passes when > they are enabled implicitly (such as by -O2) but output an error when > once uses contradicting set of options, lie -flive-patching > -fwhole-program? I have thought of this during the implementation, but finally I decided to provide the user an opportunity to explicitly enable an ipa optimization if they really want to, even though the -flive-patching disables that ipa optimization. But I am Okay to change to the behavior you described in the above, I think it’s reasonable too. Qing > > Honza >> >> Thanks, >> Martin >>
[PATCH 00/10] AMD GCN Port v2
This is a reworked version of the remaining parts of the patch series I posted on September 5th. As before, the series contains the non-OpenACC/OpenMP portions of a port to AMD GCN3 and GCN5 GPU processors. It's sufficient to build single-threaded programs, with vectorization in the usual way. C and Fortran are supported, C++ is not supported, and the other front-ends have not been tested. The OpenACC/OpenMP/libgomp portion will follow, once this is committed, eventually. Of the original 25 patches, 11 have been committed and 3 have been dropped (no longer necessary or fixed another way). There were also 3 patches that needed more work, but don't prevent the toolchain from building so I've postponed them to be revisited later (name mangling, vector size switching, elementwise loading). There will be some additional test failures until these issues are fixed. Of the remaining 8 patches, 3 are already approved and are included here for completeness only. I've split the back-end patch into three parts to avoid the mailing list size limit, so now there are 10 patches in this series. Patch 01/10 is now the only target independent patch remaining. Without this the toolchain will not build libgfortran successfully. The rest are all the various parts of the GCN back-end. I still haven't got around to writing the documentation, but that can still be done in time for the release. -- Andrew Mentor Graphics / CodeSourcery
[PATCH 03/10] GCN libgcc.
This patch contains the GCN port of libgcc.
Since the previous posting, I've removed gomp_print.c and reduction.c,
as well as addressing some other feedback.
2018-11-16 Andrew Stubbs
Kwok Cheung Yeung
Julian Brown
Tom de Vries
libgcc/
* config.host: Recognize amdgcn*-*-amdhsa.
* config/gcn/crt0.c: New file.
* config/gcn/lib2-divmod-hi.c: New file.
* config/gcn/lib2-divmod.c: New file.
* config/gcn/lib2-gcn.h: New file.
* config/gcn/sfp-machine.h: New file.
* config/gcn/t-amdgcn: New file.
---
libgcc/config.host | 8 +++
libgcc/config/gcn/crt0.c | 23
libgcc/config/gcn/lib2-divmod-hi.c | 117 +
libgcc/config/gcn/lib2-divmod.c| 117 +
libgcc/config/gcn/lib2-gcn.h | 49
libgcc/config/gcn/sfp-machine.h| 51
libgcc/config/gcn/t-amdgcn | 16 +
7 files changed, 381 insertions(+)
create mode 100644 libgcc/config/gcn/crt0.c
create mode 100644 libgcc/config/gcn/lib2-divmod-hi.c
create mode 100644 libgcc/config/gcn/lib2-divmod.c
create mode 100644 libgcc/config/gcn/lib2-gcn.h
create mode 100644 libgcc/config/gcn/sfp-machine.h
create mode 100644 libgcc/config/gcn/t-amdgcn
diff --git a/libgcc/config.host b/libgcc/config.host
index 1cbc8ac..a854ede 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -91,6 +91,10 @@ alpha*-*-*)
am33_2.0-*-linux*)
cpu_type=mn10300
;;
+amdgcn*-*-*)
+ cpu_type=gcn
+ tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
+ ;;
arc*-*-*)
cpu_type=arc
;;
@@ -387,6 +391,10 @@ alpha*-dec-*vms*)
extra_parts="$extra_parts vms-dwarf2.o vms-dwarf2eh.o"
md_unwind_header=alpha/vms-unwind.h
;;
+amdgcn*-*-amdhsa)
+ tmake_file="$tmake_file gcn/t-amdgcn"
+ extra_parts="crt0.o"
+ ;;
arc*-*-elf*)
tmake_file="arc/t-arc"
extra_parts="crti.o crtn.o crtend.o crtbegin.o crtendS.o crtbeginS.o"
diff --git a/libgcc/config/gcn/crt0.c b/libgcc/config/gcn/crt0.c
new file mode 100644
index 000..00a3f42
--- /dev/null
+++ b/libgcc/config/gcn/crt0.c
@@ -0,0 +1,23 @@
+/* Copyright (C) 2017-2018 Free Software Foundation, Inc.
+
+ This file is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the
+ Free Software Foundation; either version 3, or (at your option) any
+ later version.
+
+ This file is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+
[PATCH 01/10] Fix IRA ICE.
This patch is unchanged from that which was posted before. Discussion
fizzled out there and I was too busy with other patches to restart it
then. This issue needs to be resolved before libgfortran can be
compiled for GCN.
The IRA pass makes an assumption that any pseudos created after the pass begins
were created explicitly by the pass itself and therefore will have
corresponding entries in its other tables.
The GCN back-end, however, often creates additional pseudos, in expand
patterns, to represent the necessary EXEC value, and these break IRA's
assumption and cause ICEs:
/libgfortran/generated/matmul_r8.c: In function 'matmul_r8':
/libgfortran/generated/matmul_r8.c:3002:1: internal compiler error: in
setup_preferred_alternate_classes_for_new_pseudos, at ira.c:2772
This patch simply has IRA skip unknown pseudos, and the problem goes away.
Presumably, it's not ideal that these registers have not been processed by IRA,
but it does not appear to do any real harm.
2018-11-16 Andrew Stubbs
gcc/
* ira.c (setup_preferred_alternate_classes_for_new_pseudos): Skip
pseudos not created by this pass.
(move_unallocated_pseudos): Likewise.
---
gcc/ira.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/gcc/ira.c b/gcc/ira.c
index def194a..e0c293c 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -2769,7 +2769,12 @@ setup_preferred_alternate_classes_for_new_pseudos (int start)
for (i = start; i < max_regno; i++)
{
old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]);
- ira_assert (i != old_regno);
+
+ /* Skip any new pseudos not created directly by this pass.
+ gen_move_insn can do this on AMD GCN, for example. */
+ if (i == old_regno)
+ continue;
+
setup_reg_classes (i, reg_preferred_class (old_regno),
reg_alternate_class (old_regno),
reg_allocno_class (old_regno));
@@ -5054,6 +5059,12 @@ move_unallocated_pseudos (void)
{
int idx = i - first_moveable_pseudo;
rtx other_reg = pseudo_replaced_reg[idx];
+
+ /* Skip any new pseudos not created directly by find_moveable_pseudos.
+ gen_move_insn can do this on AMD GCN, for example. */
+ if (!other_reg)
+ continue;
+
rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i));
/* The use must follow all definitions of OTHER_REG, so we can
insert the new definition immediately after any of them. */
[PATCH 02/10] GCN libgfortran.
[Already approved by Janne Blomqvist and Jeff Law. Included here for
completeness.]
This patch contains the GCN port of libgfortran. We use the minimal
configuration created for NVPTX. That's all that's required, besides the
target-independent bug fixes posted already.
2018-11-16 Andrew Stubbs
Kwok Cheung Yeung
Julian Brown
Tom de Vries
libgfortran/
* configure.ac: Use minimal mode for amdgcn.
* configure: Regenerate.
---
libgfortran/configure| 7 ---
libgfortran/configure.ac | 3 ++-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/libgfortran/configure b/libgfortran/configure
index 45085d6..8696c9a 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -6164,7 +6164,8 @@ fi
# * C library support for other features such as signal, environment
# variables, time functions
- if test "x${target_cpu}" = xnvptx; then
+ if test "x${target_cpu}" = xnvptx \
+ || test "x${target_cpu}" = xamdgcn; then
LIBGFOR_MINIMAL_TRUE=
LIBGFOR_MINIMAL_FALSE='#'
else
@@ -12684,7 +12685,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12687 "configure"
+#line 12688 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -12790,7 +12791,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 12793 "configure"
+#line 12794 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
index 76007d3..7a1dfc3 100644
--- a/libgfortran/configure.ac
+++ b/libgfortran/configure.ac
@@ -205,7 +205,8 @@ AM_CONDITIONAL(LIBGFOR_USE_SYMVER_SUN, [test "x$gfortran_use_symver" = xsun])
# * C library support for other features such as signal, environment
# variables, time functions
-AM_CONDITIONAL(LIBGFOR_MINIMAL, [test "x${target_cpu}" = xnvptx])
+AM_CONDITIONAL(LIBGFOR_MINIMAL, [test "x${target_cpu}" = xnvptx \
+ || test "x${target_cpu}" = xamdgcn])
# Figure out whether the compiler supports "-ffunction-sections -fdata-sections",
# similarly to how libstdc++ does it
Re: [PATCH] diagnose unsupported uses of hardware register variables (PR 88000)
On Fri, 16 Nov 2018, Michael Matz wrote: > > This follows both your model > > Not really, it ignores the fact that 'a' can change at any time, which is > what happens. Are you saying that local register variables, in your model, are essentially unfit for passing operands to inline asm on specific registers (i.e. their primary purpose)? Alexander
[PATCH 06/10] GCN back-end config
This patch contains the configuration adjustments needed to enable the GCN
back-end.
The new configure check for dlopen is required to allow building the new
gcn-run tool. This tool uses libdl to load the HSA runtime libraries, which
are required to run programs on the GPU. The tool is disabled if libdl is not
available.
2018-11-16 Andrew Stubbs
Kwok Cheung Yeung
Julian Brown
Tom de Vries
Jan Hubicka
Martin Jambor
* config.sub: Recognize amdgcn*-*-amdhsa.
* configure.ac: Likewise.
* configure: Regenerate.
* contrib/config-list.mk: Add amdgcn-amdhsa.
gcc/
* config.gcc: Add amdgcn*-*-amdhsa configuration.
* configure.ac: Check for dlopen.
* configure: Regenerate.
---
config.sub | 9 +++
configure | 2 ++
configure.ac | 2 ++
contrib/config-list.mk | 1 +
gcc/config.gcc | 41 ++
gcc/configure | 68 --
gcc/configure.ac | 8 ++
7 files changed, 129 insertions(+), 2 deletions(-)
diff --git a/config.sub b/config.sub
index c95acc6..33115a5 100755
--- a/config.sub
+++ b/config.sub
@@ -572,6 +572,7 @@ case $basic_machine in
| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \
| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \
| am33_2.0 \
+ | amdgcn \
| arc | arceb \
| arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv6m | armv[78][arm] \
| avr | avr32 \
@@ -909,6 +910,9 @@ case $basic_machine in
fx2800)
basic_machine=i860-alliant
;;
+ amdgcn)
+ basic_machine=amdgcn-unknown
+ ;;
genix)
basic_machine=ns32k-ns
;;
@@ -1524,6 +1528,8 @@ case $os in
;;
*-eabi)
;;
+ amdhsa)
+ ;;
*)
echo Invalid configuration \`"$1"\': system \`"$os"\' not recognized 1>&2
exit 1
@@ -1548,6 +1554,9 @@ case $basic_machine in
spu-*)
os=elf
;;
+ amdgcn-*)
+ os=-amdhsa
+ ;;
*-acorn)
os=riscix1.2
;;
diff --git a/configure b/configure
index 480f4ae..e8a52a7 100755
--- a/configure
+++ b/configure
@@ -3645,6 +3645,8 @@ case "${target}" in
noconfigdirs="$noconfigdirs ld gas gdb gprof"
noconfigdirs="$noconfigdirs sim target-rda"
;;
+ amdgcn*-*-*)
+;;
arm-*-darwin*)
noconfigdirs="$noconfigdirs ld gas gdb gprof"
noconfigdirs="$noconfigdirs sim target-rda"
diff --git a/configure.ac b/configure.ac
index b841c99..87e0bbd 100644
--- a/configure.ac
+++ b/configure.ac
@@ -934,6 +934,8 @@ case "${target}" in
noconfigdirs="$noconfigdirs ld gas gdb gprof"
noconfigdirs="$noconfigdirs sim target-rda"
;;
+ amdgcn*-*-*)
+;;
arm-*-darwin*)
noconfigdirs="$noconfigdirs ld gas gdb gprof"
noconfigdirs="$noconfigdirs sim target-rda"
diff --git a/contrib/config-list.mk b/contrib/config-list.mk
index cbb9e28b..de0226b 100644
--- a/contrib/config-list.mk
+++ b/contrib/config-list.mk
@@ -33,6 +33,7 @@ GCC_SRC_DIR=../../gcc
LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \
alpha-linux-gnu alpha-netbsd alpha-openbsd \
alpha64-dec-vms alpha-dec-vms \
+ amdgcn-amdhsa \
arc-elf32OPT-with-cpu=arc600 arc-elf32OPT-with-cpu=arc700 \
arc-linux-uclibcOPT-with-cpu=arc700 arceb-linux-uclibcOPT-with-cpu=arc700 \
arm-wrs-vxworks arm-netbsdelf \
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8525cb5..62a9915 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -325,6 +325,10 @@ alpha*-*-*)
cpu_type=alpha
extra_options="${extra_options} g.opt"
;;
+amdgcn*)
+ cpu_type=gcn
+ use_gcc_stdint=wrap
+ ;;
am33_2.0-*-linux*)
cpu_type=mn10300
;;
@@ -1406,6 +1410,25 @@ ft32-*-elf)
tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
tmake_file="${tmake_file} ft32/t-ft32"
;;
+amdgcn-*-amdhsa)
+ tm_file="elfos.h gcn/gcn-hsa.h gcn/gcn.h newlib-stdint.h"
+ tmake_file="gcn/t-gcn-hsa"
+ native_system_header_dir=/include
+ extra_modes=gcn/gcn-modes.def
+ extra_objs="${extra_objs} gcn-tree.o"
+ extra_gcc_objs="driver-gcn.o"
+ case "$host" in
+ x86_64*-*-linux-gnu )
+ if test "$ac_cv_search_dlopen" != no; then
+ extra_programs="${extra_programs} gcn-run\$(exeext)"
+ fi
+ ;;
+ esac
+ if test x$enable_as_accelerator = xyes; then
+ extra_programs="${extra_programs} mkoffload\$(exeext)"
+ tm_file="${tm_file} gcn/offload.h"
+ fi
+ ;;
moxie-*-elf)
gas=yes
gnu_ld=yes
@@ -4127,6 +4150,24 @@ case "${target}" in
esac
;;
+ amdgcn-*-*)
+ supported_defaults="arch tune"
+
+ for which in arch tune; do
+ eval "val=\$with_$which"
+ case ${val} in
+ "" | carrizo | fiji | gfx900 )
+# OK
+;;
+ *)
+echo "Unknown cpu used in --with-$which=$val." 1>&2
+exit 1
+;;
+ esac
+ done
+ [ "x$with_arch" = x ] && with_arch=fiji
+ ;;
+
hppa*-*-*)
supported_defaults="arch schedule"
diff --git a/gcc/configure b/gcc/configure
index 8957362..e0eef63 100755
--- a/gcc/configure
+++
[PATCH 08/10] Testsuite: GCN is always PIE.
[Already approved by Jeff Law. Included here for completeness.]
The GCN/HSA loader ignores the load address and uses a random location, so we
build all GCN binaries as PIE, by default.
This patch makes the necessary testsuite adjustments to make this work
correctly.
2018-11-16 Andrew Stubbs
gcc/testsuite/
* gcc.dg/graphite/scop-19.c: Check pie_enabled.
* gcc.dg/pic-1.c: Disable on amdgcn.
* gcc.dg/pic-2.c: Disable on amdgcn.
* gcc.dg/pic-3.c: Disable on amdgcn.
* gcc.dg/pic-4.c: Disable on amdgcn.
* gcc.dg/pie-3.c: Disable on amdgcn.
* gcc.dg/pie-4.c: Disable on amdgcn.
* gcc.dg/uninit-19.c: Check pie_enabled.
* lib/target-supports.exp (check_effective_target_pie): Add amdgcn.
---
gcc/testsuite/gcc.dg/graphite/scop-19.c | 4 ++--
gcc/testsuite/gcc.dg/pic-1.c| 2 +-
gcc/testsuite/gcc.dg/pic-2.c| 1 +
gcc/testsuite/gcc.dg/pic-3.c| 2 +-
gcc/testsuite/gcc.dg/pic-4.c| 2 +-
gcc/testsuite/gcc.dg/pie-3.c| 2 +-
gcc/testsuite/gcc.dg/pie-4.c| 2 +-
gcc/testsuite/lib/target-supports.exp | 3 ++-
8 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/graphite/scop-19.c b/gcc/testsuite/gcc.dg/graphite/scop-19.c
index c89717b..6028132 100644
--- a/gcc/testsuite/gcc.dg/graphite/scop-19.c
+++ b/gcc/testsuite/gcc.dg/graphite/scop-19.c
@@ -31,6 +31,6 @@ d_growable_string_append_buffer (struct d_growable_string *dgs,
if (need > dgs->alc)
d_growable_string_resize (dgs, need);
}
-/* { dg-final { scan-tree-dump-times "number of SCoPs: 0" 2 "graphite" { target nonpic } } } */
-/* { dg-final { scan-tree-dump-times "number of SCoPs: 0" 1 "graphite" { target { ! nonpic } } } } */
+/* { dg-final { scan-tree-dump-times "number of SCoPs: 0" 2 "graphite" { target { nonpic || pie_enabled } } } } */
+/* { dg-final { scan-tree-dump-times "number of SCoPs: 0" 1 "graphite" { target { ! { nonpic || pie_enabled } } } } } */
diff --git a/gcc/testsuite/gcc.dg/pic-1.c b/gcc/testsuite/gcc.dg/pic-1.c
index 82ba43d..4bb332e 100644
--- a/gcc/testsuite/gcc.dg/pic-1.c
+++ b/gcc/testsuite/gcc.dg/pic-1.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*-*-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*-*-* amdgcn*-*-* } } } } */
/* { dg-require-effective-target fpic } */
/* { dg-options "-fpic" } */
diff --git a/gcc/testsuite/gcc.dg/pic-2.c b/gcc/testsuite/gcc.dg/pic-2.c
index bccec13..3846ec4 100644
--- a/gcc/testsuite/gcc.dg/pic-2.c
+++ b/gcc/testsuite/gcc.dg/pic-2.c
@@ -2,6 +2,7 @@
/* { dg-require-effective-target fpic } */
/* { dg-options "-fPIC" } */
/* { dg-skip-if "__PIC__ is always 1 for MIPS" { mips*-*-* } } */
+/* { dg-skip-if "__PIE__ is always defined for GCN" { amdgcn*-*-* } } */
#if __PIC__ != 2
# error __PIC__ is not 2!
diff --git a/gcc/testsuite/gcc.dg/pic-3.c b/gcc/testsuite/gcc.dg/pic-3.c
index c56f06f..1397977 100644
--- a/gcc/testsuite/gcc.dg/pic-3.c
+++ b/gcc/testsuite/gcc.dg/pic-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* amdgcn*-*-* } } } } */
/* { dg-options "-fno-pic" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/gcc.dg/pic-4.c b/gcc/testsuite/gcc.dg/pic-4.c
index 2afdd99..d6d9dc9 100644
--- a/gcc/testsuite/gcc.dg/pic-4.c
+++ b/gcc/testsuite/gcc.dg/pic-4.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* amdgcn*-*-* } } } } */
/* { dg-options "-fno-PIC" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/gcc.dg/pie-3.c b/gcc/testsuite/gcc.dg/pie-3.c
index 5577437..fd4a48d 100644
--- a/gcc/testsuite/gcc.dg/pie-3.c
+++ b/gcc/testsuite/gcc.dg/pie-3.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* amdgcn*-*-* } } } } */
/* { dg-options "-fno-pie" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/gcc.dg/pie-4.c b/gcc/testsuite/gcc.dg/pie-4.c
index 4134676..5523602 100644
--- a/gcc/testsuite/gcc.dg/pie-4.c
+++ b/gcc/testsuite/gcc.dg/pie-4.c
@@ -1,4 +1,4 @@
-/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* } } } } */
+/* { dg-do compile { target { ! { *-*-darwin* hppa*64*-*-* mips*-*-linux-* amdgcn*-*-* } } } } */
/* { dg-options "-fno-PIE" } */
#ifdef __PIC__
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 00b8138..2894401 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1168,7 +1168,8 @@ proc check_effective_target_pie { } {
|| [istarget *-*-dragonfly*]
|| [istarget *-*-freebsd*]
|| [istarget *-*-linux*]
- || [istarget *-*-gnu*] } {
+ || [istarget *
[PATCH 09/10] Ignore LLVM's blank lines.
[Already approved by Jeff Law. Included here for completeness.]
The GCN toolchain must use the LLVM assembler and linker because there's no
binutils port. The LLVM tools do not have the same diagnostic style as
binutils, so the "blank line(s) in output" tests are inappropriate (and very
noisy).
The LLVM tools also have different command line options, so it's not possible
to autodetect object formats in the same way.
This patch addresses both issues.
2018-11-16 Andrew Stubbs
gcc/testsuite/
* lib/file-format.exp (gcc_target_object_format): Handle AMD GCN.
* lib/gcc-dg.exp (gcc-dg-prune): Ignore blank lines from the LLVM
linker.
* lib/target-supports.exp (check_effective_target_llvm_binutils): New.
---
gcc/testsuite/lib/file-format.exp | 3 +++
gcc/testsuite/lib/gcc-dg.exp | 2 +-
gcc/testsuite/lib/target-supports.exp | 15 +++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/lib/file-format.exp b/gcc/testsuite/lib/file-format.exp
index 5c47246..c595fe2 100644
--- a/gcc/testsuite/lib/file-format.exp
+++ b/gcc/testsuite/lib/file-format.exp
@@ -41,6 +41,9 @@ proc gcc_target_object_format { } {
} elseif { [istarget *-*-aix*] } {
# AIX doesn't necessarily have objdump, so hand-code it.
set gcc_target_object_format_saved coff
+} elseif { [istarget *-*-amdhsa*] } {
+ # AMD GCN uses LLVM objdump which is not CLI-compatible
+ set gcc_target_object_format_saved elf
} else {
set objdump_name [find_binutils_prog objdump]
set open_file [open objfmtst.c w]
diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp
index 305dd3c..a5d505d 100644
--- a/gcc/testsuite/lib/gcc-dg.exp
+++ b/gcc/testsuite/lib/gcc-dg.exp
@@ -363,7 +363,7 @@ proc gcc-dg-prune { system text } {
# Complain about blank lines in the output (PR other/69006)
global allow_blank_lines
-if { !$allow_blank_lines } {
+if { !$allow_blank_lines && ![check_effective_target_llvm_binutils]} {
set num_blank_lines [llength [regexp -all -inline "\n\n" $text]]
if { $num_blank_lines } {
global testname_with_flags
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 2894401..f15e679 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8702,6 +8702,14 @@ proc check_effective_target_offload_hsa { } {
} "-foffload=hsa" ]
}
+# Return 1 if the compiler has been configured with hsa offloading.
+
+proc check_effective_target_offload_gcn { } {
+return [check_no_compiler_messages offload_gcn assembly {
+ int main () {return 0;}
+} "-foffload=amdgcn-unknown-amdhsa" ]
+}
+
# Return 1 if the target support -fprofile-update=atomic
proc check_effective_target_profile_update_atomic {} {
return [check_no_compiler_messages profile_update_atomic assembly {
@@ -8992,9 +9000,16 @@ proc check_effective_target_cet { } {
} "-O2" ]
}
+
# Return 1 if target supports floating point "infinite"
proc check_effective_target_inf { } {
return [check_no_compiler_messages supports_inf assembly {
const double pinf = __builtin_inf ();
}]
}
+
+# Return 1 if this target uses an LLVM assembler and/or linker
+proc check_effective_target_llvm_binutils { } {
+return [expr { [istarget amdgcn*-*-*]
+ || [check_effective_target_offload_gcn] } ]
+}
[PATCH 07/10] Add dg-require-effective-target exceptions
[This patch was previously approved by Richard Sandiford (with added
documentation I've still not done), but objected to by Mike Stump. I
need to figure out who's right.]
There are a number of tests that fail because they assume that exceptions are
available, but GCN does not support them, yet.
This patch adds "dg-require-effective-target exceptions" in all the affected
tests. There's probably an automatic way to test for exceptions, but the
current implementation simply says that AMD GCN does not support them. This
should ensure that no other targets are affected by the change.
2018-11-16 Andrew Stubbs
Kwok Cheung Yeung
Julian Brown
Tom de Vries
gcc/testsuite/
* c-c++-common/ubsan/pr71512-1.c: Require exceptions.
* c-c++-common/ubsan/pr71512-2.c: Require exceptions.
* gcc.c-torture/compile/pr34648.c: Require exceptions.
* gcc.c-torture/compile/pr41469.c: Require exceptions.
* gcc.dg/20111216-1.c: Require exceptions.
* gcc.dg/cleanup-10.c: Require exceptions.
* gcc.dg/cleanup-11.c: Require exceptions.
* gcc.dg/cleanup-12.c: Require exceptions.
* gcc.dg/cleanup-13.c: Require exceptions.
* gcc.dg/cleanup-5.c: Require exceptions.
* gcc.dg/cleanup-8.c: Require exceptions.
* gcc.dg/cleanup-9.c: Require exceptions.
* gcc.dg/gomp/pr29955.c: Require exceptions.
* gcc.dg/lto/pr52097_0.c: Require exceptions.
* gcc.dg/nested-func-5.c: Require exceptions.
* gcc.dg/pch/except-1.c: Require exceptions.
* gcc.dg/pch/valid-2.c: Require exceptions.
* gcc.dg/pr41470.c: Require exceptions.
* gcc.dg/pr42427.c: Require exceptions.
* gcc.dg/pr44545.c: Require exceptions.
* gcc.dg/pr47086.c: Require exceptions.
* gcc.dg/pr51481.c: Require exceptions.
* gcc.dg/pr51644.c: Require exceptions.
* gcc.dg/pr52046.c: Require exceptions.
* gcc.dg/pr54669.c: Require exceptions.
* gcc.dg/pr56424.c: Require exceptions.
* gcc.dg/pr64465.c: Require exceptions.
* gcc.dg/pr65802.c: Require exceptions.
* gcc.dg/pr67563.c: Require exceptions.
* gcc.dg/tree-ssa/pr41469-1.c: Require exceptions.
* gcc.dg/tree-ssa/ssa-dse-28.c: Require exceptions.
* gcc.dg/vect/pr46663.c: Require exceptions.
* lib/target-supports.exp (check_effective_target_exceptions): New.
---
gcc/testsuite/c-c++-common/ubsan/pr71512-1.c | 1 +
gcc/testsuite/c-c++-common/ubsan/pr71512-2.c | 1 +
gcc/testsuite/gcc.c-torture/compile/pr34648.c | 1 +
gcc/testsuite/gcc.c-torture/compile/pr41469.c | 1 +
gcc/testsuite/gcc.dg/20111216-1.c | 1 +
gcc/testsuite/gcc.dg/cleanup-10.c | 1 +
gcc/testsuite/gcc.dg/cleanup-11.c | 1 +
gcc/testsuite/gcc.dg/cleanup-12.c | 1 +
gcc/testsuite/gcc.dg/cleanup-13.c | 1 +
gcc/testsuite/gcc.dg/cleanup-5.c | 1 +
gcc/testsuite/gcc.dg/cleanup-8.c | 1 +
gcc/testsuite/gcc.dg/cleanup-9.c | 1 +
gcc/testsuite/gcc.dg/gomp/pr29955.c | 1 +
gcc/testsuite/gcc.dg/lto/pr52097_0.c | 1 +
gcc/testsuite/gcc.dg/nested-func-5.c | 1 +
gcc/testsuite/gcc.dg/pch/except-1.c | 1 +
gcc/testsuite/gcc.dg/pch/valid-2.c| 2 +-
gcc/testsuite/gcc.dg/pr41470.c| 1 +
gcc/testsuite/gcc.dg/pr42427.c| 1 +
gcc/testsuite/gcc.dg/pr44545.c| 1 +
gcc/testsuite/gcc.dg/pr47086.c| 1 +
gcc/testsuite/gcc.dg/pr51481.c| 1 +
gcc/testsuite/gcc.dg/pr51644.c| 1 +
gcc/testsuite/gcc.dg/pr52046.c| 1 +
gcc/testsuite/gcc.dg/pr54669.c| 1 +
gcc/testsuite/gcc.dg/pr56424.c| 1 +
gcc/testsuite/gcc.dg/pr64465.c| 1 +
gcc/testsuite/gcc.dg/pr65802.c| 1 +
gcc/testsuite/gcc.dg/pr67563.c| 1 +
gcc/testsuite/gcc.dg/tree-ssa/pr41469-1.c | 1 +
gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-28.c| 1 +
gcc/testsuite/gcc.dg/vect/pr46663.c | 1 +
gcc/testsuite/lib/target-supports.exp | 10 ++
33 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/c-c++-common/ubsan/pr71512-1.c b/gcc/testsuite/c-c++-common/ubsan/pr71512-1.c
index 2a90ab1..8af9365 100644
--- a/gcc/testsuite/c-c++-common/ubsan/pr71512-1.c
+++ b/gcc/testsuite/c-c++-common/ubsan/pr71512-1.c
@@ -1,5 +1,6 @@
/* PR c/71512 */
/* { dg-do compile } */
/* { dg-options "-O2 -fnon-call-exceptions -ftrapv -fexceptions -fsanitize=undefined" } */
+/* { dg-require-effective-target exceptions } */
#include "../../gcc.dg/pr44545.c"
diff --git a/gcc/testsuite/c-c++-common/ubsan/pr71512-2.c b/gcc/testsuite/c-c++-common/ubsan/pr71512-2.c
index 1c95593..0c16934 100644
--- a/gcc/testsuite/c-c++-common/ubsan/pr71512-2.c
+++ b/gcc/tests
[PATCH 10/10] Port testsuite to GCN
This collection of miscellaneous patches configures the testsuite to run on AMD GCN in a standalone (i.e. not offloading) configuration. It assumes you have your Dejagnu set up to run binaries via the gcn-run tool. 2018-11-16 Andrew Stubbs Kwok Cheung Yeung Julian Brown Tom de Vries gcc/testsuite/ * gcc.dg/20020312-2.c: Add amdgcn support. * gcc.dg/Wno-frame-address.c: Disable on amdgcn. * gcc.dg/builtin-apply2.c: Likewise. * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise. * gcc.dg/gimplefe-28.c: Force -ffast-math. * gcc.dg/intermod-1.c: Add -mlocal-symbol-id on amdgcn. * gcc.dg/memcmp-1.c: Increase timeout factor. * gcc.dg/pr59605-2.c: Addd -DMAX_COPY=1025 on amdgcn. * gcc.dg/sibcall-10.c: xfail on amdgcn. * gcc.dg/sibcall-9.c: Likewise. * gcc.dg/tree-ssa/gen-vect-11c.c: Likewise. * gcc.dg/tree-ssa/pr84512.c: Likewise. * gcc.dg/tree-ssa/loop-1.c: Adjust expectations for amdgcn. * gfortran.dg/bind_c_array_params_2.f90: Likewise. * gcc.dg/vect/tree-vect.h: Avoid signal on amdgcn. * lib/target-supports.exp (check_effective_target_trampolines): Configure amdgcn. (check_profiling_available): Likewise. (check_effective_target_global_constructor): Likewise. (check_effective_target_return_address): Likewise. (check_effective_target_fopenacc): Likewise. (check_effective_target_fopenmp): Likewise. (check_effective_target_vect_int): Likewise. (check_effective_target_vect_intfloat_cvt): Likewise. (check_effective_target_vect_uintfloat_cvt): Likewise. (check_effective_target_vect_floatint_cvt): Likewise. (check_effective_target_vect_floatuint_cvt): Likewise. (check_effective_target_vect_simd_clones): Likewise. (check_effective_target_vect_shift): Likewise. (check_effective_target_whole_vector_shift): Likewise. (check_effective_target_vect_bswap): Likewise. (check_effective_target_vect_shift_char): Likewise. (check_effective_target_vect_long): Likewise. (check_effective_target_vect_float): Likewise. (check_effective_target_vect_double): Likewise. (check_effective_target_vect_perm): Likewise. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. (check_effective_target_vect_widen_mult_hi_to_si): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise. (check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise. (check_effective_target_vect_natural_alignment): Likewise. (check_effective_target_vect_fully_masked): Likewise. (check_effective_target_vect_element_align): Likewise. (check_effective_target_vect_masked_store): Likewise. (check_effective_target_vect_scatter_store): Likewise. (check_effective_target_vect_condition): Likewise. (check_effective_target_vect_cond_mixed): Likewise. (check_effective_target_vect_char_mult): Likewise. (check_effective_target_vect_short_mult): Likewise. (check_effective_target_vect_int_mult): Likewise. (check_effective_target_sqrt_insn): Likewise. (check_effective_target_vect_call_sqrtf): Likewise. (check_effective_target_vect_call_btrunc): Likewise. (check_effective_target_vect_call_btruncf): Likewise. (check_effective_target_vect_call_ceil): Likewise. (check_effective_target_vect_call_floorf): Likewise. (check_effective_target_lto): Likewise. (check_vect_support_and_set_flags): Likewise. (check_effective_target_vect_stridedN): Enable when fully masked is available. --- gcc/testsuite/gcc.dg/20020312-2.c | 2 + gcc/testsuite/gcc.dg/Wno-frame-address.c | 2 +- gcc/testsuite/gcc.dg/builtin-apply2.c | 2 +- gcc/testsuite/gcc.dg/gimplefe-28.c | 2 +- gcc/testsuite/gcc.dg/intermod-1.c | 1 + gcc/testsuite/gcc.dg/memcmp-1.c| 1 + gcc/testsuite/gcc.dg/pr59605-2.c | 2 +- gcc/testsuite/gcc.dg/sibcall-10.c | 2 +- gcc/testsuite/gcc.dg/sibcall-9.c | 2 +- .../gcc.dg/torture/stackalign/builtin-apply-2.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/loop-1.c | 6 +- gcc/testsuite/gcc.dg/tree-ssa/pr84512.c| 2 +- gcc/testsuite/gcc.dg/vect/tree-vect.h | 4 + .../gfortran.dg/bind_c_array_params_2.f90 | 3 +- gcc/testsuite/lib/target-supports.exp | 129 +++-- 16 files changed, 115 insertions(+), 49 deletions(-) diff
[PATCH, i386]: Fix PR88051, internal compiler error: in add_clobbers
Hello!
There are actually two problems discovered:
a) The insn condition of floatunsdidf2 is incorrect, it allows 32bit
AVX512F targets, but these are not necessarily
KEEP_VECTOR_ALIGNED_STACK targets.
b) movdi_to_sse is defined with extra parallel encapsulation.
Instructions in this form don't get registered to add_clobbers, so we
trigger assert for unknown insn ID there.
Attached patch fixes both problems. However, with the fixed pattern,
RA for some reason insists on spilling DImode register to memory, so I
rewrote the whole pattern as UNSPEC.
2018-11-16 Uros Bizjak
PR target/88051
* config/i386/i386.md (floatunsdidf2): Allow only 64bit AVX512F targets.
* config/i386/sse.md (UNSPEC_MOVDI_TO_SSE): New UNSPEC.
(movdi_to_sse): Rewrite using UNSPEC_MOVDI_TO_SSE unspec.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN. The fix for pattern will be backported to
other release branches.
Uros.
Index: config/i386/i386.md
===
--- config/i386/i386.md (revision 266208)
+++ config/i386/i386.md (working copy)
@@ -5194,7 +5194,8 @@
[(set (match_operand:DF 0 "register_operand")
(unsigned_float:DF
(match_operand:DI 1 "nonimmediate_operand")))]
- "(TARGET_KEEPS_VECTOR_ALIGNED_STACK || TARGET_AVX512F)
+ "((TARGET_64BIT && TARGET_AVX512F)
+|| TARGET_KEEPS_VECTOR_ALIGNED_STACK)
&& TARGET_SSE2 && TARGET_SSE_MATH"
{
if (!TARGET_64BIT)
Index: config/i386/sse.md
===
--- config/i386/sse.md (revision 266208)
+++ config/i386/sse.md (working copy)
@@ -21,6 +21,9 @@
;; SSE
UNSPEC_MOVNT
+ ;; SSE2
+ UNSPEC_MOVDI_TO_SSE
+
;; SSE3
UNSPEC_LDDQU
@@ -1235,10 +1238,10 @@
;; from there.
(define_insn_and_split "movdi_to_sse"
- [(parallel
-[(set (match_operand:V4SI 0 "register_operand" "=?x,x")
- (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
- (clobber (match_scratch:V4SI 2 "=&x,X"))])]
+ [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
+ (unspec:V4SI [(match_operand:DI 1 "nonimmediate_operand" "r,m")]
+UNSPEC_MOVDI_TO_SSE))
+ (clobber (match_scratch:V4SI 2 "=&x,X"))]
"!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC"
"#"
"&& reload_completed"
Re: [PATCH] diagnose unsupported uses of hardware register variables (PR 88000)
Hi, On Fri, 16 Nov 2018, Alexander Monakov wrote: > > Not really, it ignores the fact that 'a' can change at any time, which > > is what happens. > > Are you saying that local register variables, in your model, are > essentially unfit for passing operands to inline asm on specific > registers (i.e. their primary purpose)? It seems so, yes. Obviously we _want_ them to be used for this purpose, so something is wrong with my mental model :) I think I'm starting to lean towards your model, hmm. Ciao, Michael.
Re: [PATCH] Come up with gcc/testsuite/g++.target/i386/i386.dg and move there some tests.
Hi Martin, Seems the change is not checked in yet? Thanks, Renlin On 10/22/2018 01:22 PM, Martin Liška wrote: On 10/22/18 12:09 PM, Jakub Jelinek wrote: On Mon, Oct 22, 2018 at 12:04:23PM +0200, Martin Liška wrote: I noticed that before the tests were run with all of -std=(c|gnu)++(98|11|14), now with no explict -std option. I wonder if this is an issue. Rainer Hello. I guess that should not be a problem. If we want that, it is a matter of (untested): --- gcc/testsuite/g++.target/i386/i386.exp.jj 2018-10-10 10:50:48.352235231 +0200 +++ gcc/testsuite/g++.target/i386/i386.exp 2018-10-22 12:08:56.546807996 +0200 @@ -35,8 +35,8 @@ dg-init clearcap-init # Main loop. -dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \ -"" $DEFAULT_CXXFLAGS +g++-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \ + "" $DEFAULT_CXXFLAGS # All done. clearcap-finish Jakub Thank you Jakub, works for me for: $ make check -k RUNTESTFLAGS="i386.exp" I can confirm that: grep '^PASS' ./gcc/testsuite/g++/g++.log | wc -l changed from 61 to 183. I'm going to install the patch. Martin
Re: [PATCH][RS6000] Fix PR87870: ppc64 generates poor code when loading constants into TImode vars
On Tue, Nov 13, 2018 at 11:29:20AM -0600, Peter Bergner wrote: > PR87870 shows a problem loading simple constant values into TImode variables. > This is a regression ever since VSX was added and we started using the > vsx_mov_64bit pattern. We still get the correct code on trunk if we > compile with -mno-vsx, since we fall back to using the older mov_ppc64 > move pattern, which has an alternative "r" <- "n". > > Our current vsx_mov_64bit pattern currently has two alternatives for > loading constants into GPRs, one using "*r" <- "jwM" and "??r" <- "W". > These look redundant to me, since "W" contains support for both all-zero > constants (ie, "j") and all-one constants (ie, wM) as well as a few more. > My patch below consolidates them both and uses a new mode iterator that > uses "W" for the vector modes and "n" for TImode like mov_ppc64 > used. Why does the "r" have a "*"? Should it have been just a "?"? "W" is easy_vector_constant, which requires const_vector always; is that okay here? > I'll note I didn't change the vsx_mov_32bit pattern, since TImode > isn't supported with -m32. However, if you want, I could remove the > redundant "*r" <- "jwM" alternative there too? Yeah, please keep the patterns in synch. Segher
Re: Tweak ALAP calculation in SCHED_PRESSURE_MODEL
On 11/16/18 5:35 AM, Kyrill Tkachov wrote: > >> But more importantly, it seems like blindly ignoring anti dependencies >> is just a hack that happens to work. I wonder if we could somehow mark >> the fake dependencies we add, and avoid bumping the ALAP when we >> encounter those fake dependencies. > > I did experiment with this. I added a new property to dep_t > to mark it as "artificial", that is created in the parts of sched-deps.c > that add dependencies when MAX_PENDING_LIST_LENGTH is exceeded. > > Then ALAP is bumped only when the dependency is not artificial in this way. > This didn't help much on the testcase we were looking at (the hot > function in cactus from SPEC2006). > > The code size increase and number of spills decreased by only 6 (out of > ~800) whereas with Richards' > patch it improved much more (~140 decrease, with a corresponding > improvement in stack usage and code size). > > Richard did suggest that anti-dependencies are already taken into > account in the INSN_PRIORITY tie-breaker, > so perhaps that is a better scheme indeed? ISTM that your experiment indicates that it's not the artificial dependencies that are the problem. It's the real anti-dependencies that are mucking things up. That's fine, it just means I don't think we want/need to do anything special for the artificial dependencies. We certainly use INSN_PRIORITY as one of the (many) tie breakers in the rank_for_schedule routine. BUt I don't know if that's a better place or not. I trust Richard, so if he thinks the patch is the best approach, then let's go with it after that trivial comment fix I mentioned in my previous message. > >> >> It probably wouldn't be a bad idea to look at the default for >> MAX_PENDING_LIST_LENGTH. Based on the current default value and the >> comments in the code that value could well have been tuned 25 or more >> years ago! > > Probably. I see that s390 and spu increase that param in their backends > to much larger values than the default > I played around with increasing it on aarch64. It improved things > somewhat, but Richard's patch still gave superior results. ACK. Thanks for testing. If you want to adjust, that would seem fine as a follow-up. jeff
[PATCH, libstdc++] Implement P0415 More constexpr for std::complex.
Greetings,
This is late but I wanted to put it out there just to finish a thing.
It's fairly straightforward constexpr of operators and some simple
functions for std::complex.
The only thing that jumped out was the norm function. We had this:
struct _Norm_helper
{
template
static inline _Tp _S_do_it(const complex<_Tp>& __z)
{
_Tp __res = std::abs(__z);
return __res * __res;
}
};
Since abs can't be made constexpr for complex since it involves sqrt (It
probably could but that's another story) I had to fall back to the x^2 +
y^2. I don't know who that will bother. This version should be faster
and I can't think of any useful trustworthy difference numerically
either in terms of accuracy of stability.
Barring any feedback on that I'll clean it up and maybe rename my tests
from constexpr_all_the_things.cc to more_constexpr.cc ;-)
It builds and tests cleanly on x86_64-linux.
Ed
2018-11-16 Edward Smith-Rowland <3dw...@verizon.net>
Implement P0415 More constexpr for std::complex.
* include/std/complex (proj(), norm(), conj(), arg()): Constexpr.
(real(Tp), imag(Tp)): Constexpr.
(operator@=(Tp), operator@=(complex)): Constexpr.
(operator@(Tp,complex), operator@(complex,Tp)
operator@(complex,complex)): Constexpr.
* testsuite/26_numerics/complex/comparison_operators/
constexpr_all_the_things.cc: New test.
* testsuite/26_numerics/complex/operators/
constexpr_all_the_things.cc: New test.
* testsuite/26_numerics/complex/requirements/
constexpr_all_the_things.cc: New test.
* testsuite/26_numerics/complex/value_operations/
constexpr_all_the_things.cc: New test.
* testsuite/26_numerics/headers/complex/synopsis.cc:
Add _GLIBCXX20_CONSTEXPR to applicable operators; Add missing proj().
Index: include/std/complex
===
--- include/std/complex (revision 266189)
+++ include/std/complex (working copy)
@@ -68,12 +68,13 @@
/// Return magnitude of @a z.
template _Tp abs(const complex<_Tp>&);
/// Return phase angle of @a z.
- template _Tp arg(const complex<_Tp>&);
+ template _Tp _GLIBCXX20_CONSTEXPR arg(const complex<_Tp>&);
/// Return @a z magnitude squared.
- template _Tp norm(const complex<_Tp>&);
+ template _Tp _GLIBCXX20_CONSTEXPR norm(const complex<_Tp>&);
/// Return complex conjugate of @a z.
- template complex<_Tp> conj(const complex<_Tp>&);
+ template
+_GLIBCXX20_CONSTEXPR complex<_Tp> conj(const complex<_Tp>&);
/// Return complex with magnitude @a rho and angle @a theta.
template complex<_Tp> polar(const _Tp&, const _Tp& = 0);
@@ -169,18 +170,18 @@
// _GLIBCXX_RESOLVE_LIB_DEFECTS
// DR 387. std::complex over-encapsulated.
- void
+ _GLIBCXX20_CONSTEXPR void
real(_Tp __val) { _M_real = __val; }
- void
+ _GLIBCXX20_CONSTEXPR void
imag(_Tp __val) { _M_imag = __val; }
/// Assign a scalar to this complex number.
- complex<_Tp>& operator=(const _Tp&);
+ _GLIBCXX20_CONSTEXPR complex<_Tp>& operator=(const _Tp&);
/// Add a scalar to this complex number.
// 26.2.5/1
- complex<_Tp>&
+ _GLIBCXX20_CONSTEXPR complex<_Tp>&
operator+=(const _Tp& __t)
{
_M_real += __t;
@@ -189,7 +190,7 @@
/// Subtract a scalar from this complex number.
// 26.2.5/3
- complex<_Tp>&
+ _GLIBCXX20_CONSTEXPR complex<_Tp>&
operator-=(const _Tp& __t)
{
_M_real -= __t;
@@ -197,30 +198,30 @@
}
/// Multiply this complex number by a scalar.
- complex<_Tp>& operator*=(const _Tp&);
+ _GLIBCXX20_CONSTEXPR complex<_Tp>& operator*=(const _Tp&);
/// Divide this complex number by a scalar.
- complex<_Tp>& operator/=(const _Tp&);
+ _GLIBCXX20_CONSTEXPR complex<_Tp>& operator/=(const _Tp&);
// Let the compiler synthesize the copy assignment operator
#if __cplusplus >= 201103L
- complex& operator=(const complex&) = default;
+ _GLIBCXX20_CONSTEXPR complex& operator=(const complex&) = default;
#endif
/// Assign another complex number to this one.
template
-complex<_Tp>& operator=(const complex<_Up>&);
+_GLIBCXX20_CONSTEXPR complex<_Tp>& operator=(const complex<_Up>&);
/// Add another complex number to this one.
template
-complex<_Tp>& operator+=(const complex<_Up>&);
+_GLIBCXX20_CONSTEXPR complex<_Tp>& operator+=(const complex<_Up>&);
/// Subtract another complex number from this one.
template
-complex<_Tp>& operator-=(const complex<_Up>&);
+_GLIBCXX20_CONSTEXPR complex<_Tp>& operator-=(const complex<_Up>&);
/// Multiply this complex number by another.
template
-complex<_Tp>& operator*=(const complex<_Up>&);
+_GLIBCXX20_CO
Re: Tweak ALAP calculation in SCHED_PRESSURE_MODEL
Hi Jeff, On 16/11/18 17:08, Jeff Law wrote: On 11/16/18 5:35 AM, Kyrill Tkachov wrote: But more importantly, it seems like blindly ignoring anti dependencies is just a hack that happens to work. I wonder if we could somehow mark the fake dependencies we add, and avoid bumping the ALAP when we encounter those fake dependencies. I did experiment with this. I added a new property to dep_t to mark it as "artificial", that is created in the parts of sched-deps.c that add dependencies when MAX_PENDING_LIST_LENGTH is exceeded. Then ALAP is bumped only when the dependency is not artificial in this way. This didn't help much on the testcase we were looking at (the hot function in cactus from SPEC2006). The code size increase and number of spills decreased by only 6 (out of ~800) whereas with Richards' patch it improved much more (~140 decrease, with a corresponding improvement in stack usage and code size). Richard did suggest that anti-dependencies are already taken into account in the INSN_PRIORITY tie-breaker, so perhaps that is a better scheme indeed? ISTM that your experiment indicates that it's not the artificial dependencies that are the problem. It's the real anti-dependencies that are mucking things up. That's fine, it just means I don't think we want/need to do anything special for the artificial dependencies. I must apologise. Since I sent this out earlier I found a bug in my implementation of the above experiment which meant I wasn't marking the dependencies properly in all cases :( With that fixed, the approach removes ~100 spills which is much better than what I reported initially however still not as good as Richards' patch (removed ~140 spills). I've kicked off a SPEC2006 benchmarking run to see if it has any any effect. We certainly use INSN_PRIORITY as one of the (many) tie breakers in the rank_for_schedule routine. BUt I don't know if that's a better place or not. I trust Richard, so if he thinks the patch is the best approach, then let's go with it after that trivial comment fix I mentioned in my previous message. I'll respin Richard's patch with the comment updates and resend that, unless the benchmark run above shows something interesting. It probably wouldn't be a bad idea to look at the default for MAX_PENDING_LIST_LENGTH. Based on the current default value and the comments in the code that value could well have been tuned 25 or more years ago! Probably. I see that s390 and spu increase that param in their backends to much larger values than the default I played around with increasing it on aarch64. It improved things somewhat, but Richard's patch still gave superior results. ACK. Thanks for testing. If you want to adjust, that would seem fine as a follow-up. I'd need to benchmark such a change, but thanks. MAX_PENDING_LIST_LENGTH only exists to limit compile-time, right? Thanks, and sorry for the confusion. Kyrill jeff
[PATCH, PR libstdc++/83566] - cyl_bessel_j returns wrong result for x>1000
All,
This patch has been in my queue for a while.
I believe it is waiting on Copyright assignment for Michele. Is this
still true?
Ed
2018-11-16 Michele Pezzutti
Edward Smith-Rowland <3dw...@verizon.net>
PR libstdc++/83566 - cyl_bessel_j returns wrong result for x>1000
for high orders.
* include/tr1/bessel_function.tcc: Perform no fewer than nu/2 iterations
of the asymptotic series (nu is the Bessel order).
* testsuite/tr1/5_numerical_facilities/special_functions/
09_cyl_bessel_j/check_value.cc: Add tests at nu=100, 1000<=x<=2000.
* testsuite/tr1/5_numerical_facilities/special_functions/
11_cyl_neumann/check_value.cc: Ditto.
* testsuite/special_functions/08_cyl_bessel_j/check_value.cc: Ditto.
* testsuite/special_functions/10_cyl_neumann/check_value.cc: Ditto.
Index: include/tr1/bessel_function.tcc
===
--- include/tr1/bessel_function.tcc (revision 266189)
+++ include/tr1/bessel_function.tcc (working copy)
@@ -27,6 +27,10 @@
* Do not attempt to use it directly. @headername{tr1/cmath}
*/
+/* __cyl_bessel_jn_asymp adapted from GNU GSL version 2.4 specfunc/bessel_j.c
+ * Copyright (C) 1996-2003 Gerard Jungman
+ */
+
//
// ISO C++ 14882 TR1: 5.2 Special functions
//
@@ -358,24 +362,51 @@
void
__cyl_bessel_jn_asymp(_Tp __nu, _Tp __x, _Tp & __Jnu, _Tp & __Nnu)
{
- const _Tp __mu = _Tp(4) * __nu * __nu;
- const _Tp __mum1 = __mu - _Tp(1);
- const _Tp __mum9 = __mu - _Tp(9);
- const _Tp __mum25 = __mu - _Tp(25);
- const _Tp __mum49 = __mu - _Tp(49);
- const _Tp __xx = _Tp(64) * __x * __x;
- const _Tp __P = _Tp(1) - __mum1 * __mum9 / (_Tp(2) * __xx)
-* (_Tp(1) - __mum25 * __mum49 / (_Tp(12) * __xx));
- const _Tp __Q = __mum1 / (_Tp(8) * __x)
-* (_Tp(1) - __mum9 * __mum25 / (_Tp(6) * __xx));
+ const _Tp __mu = _Tp(4) * __nu * __nu;
+ const _Tp __8x = _Tp(8) * __x;
+ _Tp __P = _Tp(0);
+ _Tp __Q = _Tp(0);
+
+ _Tp __k = _Tp(0);
+ _Tp __term = _Tp(1);
+
+ int __epsP = 0;
+ int __epsQ = 0;
+
+ _Tp __eps = std::numeric_limits<_Tp>::epsilon();
+
+ do
+{
+ __term *= (__k == 0
+ ? _Tp(1)
+ : -(__mu - (2 * __k - 1) * (2 * __k - 1)) / (__k * __8x));
+
+ __epsP = std::abs(__term) < __eps * std::abs(__P);
+ __P += __term;
+
+ __k++;
+
+ __term *= (__mu - (2 * __k - 1) * (2 * __k - 1)) / (__k * __8x);
+ __epsQ = std::abs(__term) < __eps * std::abs(__Q);
+ __Q += __term;
+
+ if (__epsP && __epsQ && __k > (__nu / 2.))
+break;
+
+ __k++;
+}
+ while (__k < 1000);
+
const _Tp __chi = __x - (__nu + _Tp(0.5L))
-* __numeric_constants<_Tp>::__pi_2();
+ * __numeric_constants<_Tp>::__pi_2();
+
const _Tp __c = std::cos(__chi);
const _Tp __s = std::sin(__chi);
const _Tp __coef = std::sqrt(_Tp(2)
/ (__numeric_constants<_Tp>::__pi() * __x));
+
__Jnu = __coef * (__c * __P - __s * __Q);
__Nnu = __coef * (__s * __P + __c * __Q);
Index:
testsuite/tr1/5_numerical_facilities/special_functions/09_cyl_bessel_j/check_value.cc
===
---
testsuite/tr1/5_numerical_facilities/special_functions/09_cyl_bessel_j/check_value.cc
(revision 266189)
+++
testsuite/tr1/5_numerical_facilities/special_functions/09_cyl_bessel_j/check_value.cc
(working copy)
@@ -698,6 +698,39 @@
};
const double toler026 = 1.0006e-11;
+// Test data for nu=100.
+// max(|f - f_GSL|): 3.9438938226332709e-14 at index 19
+// max(|f - f_GSL| / |f_GSL|): 2.0193411077170867e-11
+// mean(f - f_GSL): 1.6682360684660055e-15
+// variance(f - f_GSL): 5.3274331668346898e-28
+// stddev(f - f_GSL): 2.3081232997469372e-14
+const testcase_cyl_bessel_j
+data027[21] =
+{
+ { 1.1676135007789573e-02, 100., 1000., 0.0
},
+ { -1.1699854778025796e-02, 100., 1100., 0.0
},
+ { -2.2801483405083697e-02, 100., 1200., 0.0
},
+ { -1.6973500787373915e-02, 100., 1300., 0.0
},
+ { -1.4154528803481308e-03, 100., 1400., 0.0
},
+ { 1.726584495232e-02, 100., 1500., 0.0
},
+ { 1.9802562020148559e-02, 100., 1600., 0.0
},
+ { 1.6129771279838816e-02, 100., 1700., 0.0
},
+ { 5.3753369281536031e-03, 100., 1800., 0.0
},
+ { -6.9238868725645785e-03, 100., 1900., 0.0
}
Re: [PATCH] Make strlen range computations more conservative
Just a reminder: those are the two parts of this patch, which have been posted already a while ago when we were still in stage 1: https://gcc.gnu.org/ml/gcc-patches/2018-09/msg00805.html https://gcc.gnu.org/ml/gcc-patches/2018-10/msg01237.html Bernd. On 10/20/18 11:16 AM, Bernd Edlinger wrote: > On 10/17/18 11:56 PM, Jeff Law wrote: >> On 10/12/18 9:34 PM, Bernd Edlinger wrote: >>> On 10/12/18 16:55, Jeff Law wrote: On 9/15/18 2:43 AM, Bernd Edlinger wrote: > Hi, > > this is an update on my strlen range patch (V7). Again re-based and > retested to current trunk. > > I am aware that Martin wants to re-factor the interface of > get_range_strlen > and have no objections against, but I'd suggest that to be a follow-up > patch. > > I might suggest to rename one of the two get_range_strlen functions at the > same time as it is rather confusing to have to count the parameters in > order > to tell which function is meant. > > Bootstrapped and reg-tested on x86_64-pc-linux-gnu. > Is it OK for trunk? > > > Thanks > Bernd. > > > changelog-range-strlen-v7.txt > > gcc: > 2018-08-26 Bernd Edlinger > > * gimple-fold.c (looks_like_a_char_array_without_typecast_p): New > helper function for strlen range estimations. > (get_range_strlen): Use looks_like_a_char_array_without_typecast_p > for warnings, but use GIMPLE semantics otherwise. > * tree-ssa-strlen.c (maybe_set_strlen_range): Use GIMPLE semantics. > (get_min_string_length): Avoid not NUL terminated string literals. The introduction of looks_like_a_char_array_without_typecast_p is probably a good thing. Too much code is already implemented inline within get_range_strlen. It looks like you added handling of ARRAY_RANGE_REF. I don't know how often they come up in practice, but handling it seems like a reasonable extension to what we're doing. Bonus points if it's triggering with any kind of consistency. >>> >>> I did only want to be consistent with get_inner_reference here, >>> but did not have encountered these, probably only an Ada thing? >> Trying to be consistent with get_inner_reference is fine :-) GCC >> supports case ranges as an extension for C/C++. No clue if they're >> natively supported by Ada or any other langauge. >> >> >> >>> I actually prefer Martin's unification of type/fuzzy into a single enumeration to describe the desired behavior. Doing it with two args where some values are mutually exclusive is just asking for trouble. Though I like that you called out the values that are mutually exclusive. I definitely want to look at how your patch and Martin's differ on the handling of flexible array members -- clearly we must avoid setting a range in that case. I'm surprised this didn't trigger a failure in the testsuite though. Martin's work in this space did. The bugfix in get_min_string_length looks like it probably stands on its own. I'm still evaluating the two approaches... >>> >>> One thing I should mention is, that there is still one place where >>> opportunistic >>> range info influence conde gen. I mean at least with my patch. >> ACK. That's soemthing Martin's patch does address. AT least it's >> supposed to. > > Okay, based on my previous patch I can of course do the same. > > See attached. This was bootstrapped and reg-tested together with my > previous patch. The only "regression" was pr79376.c, which is xfailed > because the test case is expecting the return value to be in the limits given > by in the opportunistic range info. > > While I think the strlen return optimization will be safe with this patch, > I have however still a philosophical problem with it, because s[n]printf > is a highly complex piece of software, and we take it away the right > to return a failure code, when it has to because of an implementation bug. > >>> >>> That is the return value from sprintf is using the range info from the >>> warning, and uses that to set the range info of the result. >>> In try_substitute_return_value, which uses the range info that was >>> from the warnings and feeds that into set_range_info. >> Right. In Martin's work we have enough range info to distinguish >> between the range info for warnings and the true range info and only use >> the latter in the call to set_range_info. >> >> > > Well I have tried the test cases from Martins patch, and all except one > work fine for me, and pass with my patch-set as well. > > The problematic one is strlenopt-59.c (in his patch, my patch has picked > the same name, unfortunately). > > The difference is how object declarations are handled. While my patch > does not try to solve that problem at all, his patch does probably look > at the declaration size to improve the strict limits. > > I
Re: Tweak ALAP calculation in SCHED_PRESSURE_MODEL
On 11/16/18 10:21 AM, Kyrill Tkachov wrote: > It probably wouldn't be a bad idea to look at the default for MAX_PENDING_LIST_LENGTH. Based on the current default value and the comments in the code that value could well have been tuned 25 or more years ago! >>> Probably. I see that s390 and spu increase that param in their backends >>> to much larger values than the default >>> I played around with increasing it on aarch64. It improved things >>> somewhat, but Richard's patch still gave superior results. >> ACK. Thanks for testing. If you want to adjust, that would seem fine >> as a follow-up. > > I'd need to benchmark such a change, but thanks. > > MAX_PENDING_LIST_LENGTH only exists to limit compile-time, right? I believe so. jeff
Re: [PATCH] Reject too large string literals (PR middle-end/87854)
On Fri, 16 Nov 2018, Jakub Jelinek wrote: > Hi! > > Both C and C++ FE diagnose arrays larger than half of the address space: > /tmp/1.c:1:6: error: size of array ‘a’ is too large > char a[__SIZE_MAX__ / 2 + 1]; > ^ > because one can't do pointer arithmetics on them. But we don't have > anything similar for string literals. As internally we use host int > as TREE_STRING_LENGTH, this is relevant to targets that have < 32-bit > size_t only. > > The following patch adds that diagnostics and truncates the string literals. > > Bootstrapped/regtested on x86_64-linux and i686-linux and tested with > a cross to avr. I'll defer adjusting testcases to the maintainers of 16-bit > ports. From the PR it seems gcc.dg/concat2.c, g++.dg/parse/concat1.C and > pr46534.c tests are affected. > > Ok for trunk? OK with me. I'd hope at least one test (existing or new) would actually test the new diagnostic on 16-bit systems, rather than just those tests being disabled for affected platforms. -- Joseph S. Myers jos...@codesourcery.com
Re: [PATCH, libstdc++] Implement P0415 More constexpr for std::complex.
Am Fr., 16. Nov. 2018 um 18:13 Uhr schrieb Ed Smith-Rowland
<3dw...@verizon.net>:
>
> Greetings,
>
> This is late but I wanted to put it out there just to finish a thing.
>
> It's fairly straightforward constexpr of operators and some simple
> functions for std::complex.
>
> The only thing that jumped out was the norm function. We had this:
>
> struct _Norm_helper
> {
>template
> static inline _Tp _S_do_it(const complex<_Tp>& __z)
> {
>_Tp __res = std::abs(__z);
>return __res * __res;
> }
> };
>
> Since abs can't be made constexpr for complex since it involves sqrt (It
> probably could but that's another story) I had to fall back to the x^2 +
> y^2. I don't know who that will bother. This version should be faster
> and I can't think of any useful trustworthy difference numerically
> either in terms of accuracy of stability.
>
> Barring any feedback on that I'll clean it up and maybe rename my tests
> from constexpr_all_the_things.cc to more_constexpr.cc ;-)
>
> It builds and tests cleanly on x86_64-linux.
Hmmh, according to the recent working draft the following complex
functions are *not* constexpr:
arg, proj
So, shouldn't their new C++20-constexpr specifiers be added
conditionally (In the sense of gcc extensions)?
- Daniel
Re: [PATCH 06/10] GCN back-end config
On Fri, 16 Nov 2018, Andrew Stubbs wrote: > * config.sub: Recognize amdgcn*-*-amdhsa. config.sub should be copied from upstream config.git (along with config.guess at the same time), once the support has been added there; it shouldn't be patched locally in GCC. -- Joseph S. Myers jos...@codesourcery.com
[PATCH] Disable unrolling for loops vectorised with non-constant VF (was: [PATCH][cunroll] Add unroll-known-loop-iterations-only param and use it in aarch64)
Hi all,
This is an alternative to
https://gcc.gnu.org/ml/gcc-patches/2018-11/msg00694.html
As richi suggested, this disables unrolling of loops vectorised with
variable-length SVE
in the vectoriser itself through the loop->unroll member.
It took me a few tries to get it right, as it needs to be set to '1' to disable
unrolling,
the rationale for that mechanism is described in the comment in cfgloop.h.
Bootstrapped and tested on aarch64-none-linux-gnu.
Is this ok for trunk?
Thanks,
Kyrill
2018-11-15 Kyrylo Tkachov
* tree-vect-loop.c (vect_transform_loop): Disable further unrolling
of the loop if vf is non-constant.
2018-11-15 Kyrylo Tkachov
* gcc.target/aarch64/sve/unroll-1.c: New test.
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unroll-1.c b/gcc/testsuite/gcc.target/aarch64/sve/unroll-1.c
new file mode 100644
index ..d4353009e2145ec59b3ac74a8fc0a4a16e441581
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/unroll-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+/* Check that simple loop is not fully unrolled. */
+
+void
+fully_peel_me (double *x)
+{
+ for (int i = 0; i < 5; i++)
+x[i] = x[i] * 2;
+}
+
+/* { dg-final { scan-assembler-times {b..\t\.L.\n} 1 } } */
diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c
index f2d9d8ac2bc44398f955650591eea20dc7fca8a5..40d9584a00ba8d0b3fda58b3ee8df17f24432d5e 100644
--- a/gcc/tree-vect-loop.c
+++ b/gcc/tree-vect-loop.c
@@ -8515,6 +8515,15 @@ vect_transform_loop (loop_vec_info loop_vinfo)
}
}
+ /* Loops vectorized with a variable factor won't benefit from
+ unrolling/peeling. */
+ if (!vf.is_constant ())
+{
+ loop->unroll = 1;
+ if (dump_enabled_p ())
+ dump_printf_loc (MSG_NOTE, vect_location, "Disabling unrolling due to"
+ " variable-length vectorization factor\n");
+}
/* Free SLP instances here because otherwise stmt reference counting
won't work. */
slp_instance instance;
Re: [PATCH] v2: C/C++: add fix-it hints for missing '&' and '*' (PR c++/87850)
On Thu, Nov 15, 2018 at 4:48 PM David Malcolm wrote:
> On Tue, 2018-11-13 at 16:34 -0500, Jason Merrill wrote:
> > On Mon, Nov 12, 2018 at 4:32 PM Martin Sebor
> > wrote:
> > > On 11/11/2018 02:02 PM, David Malcolm wrote:
> > > > On Sun, 2018-11-11 at 11:01 -0700, Martin Sebor wrote:
> > > > > On 11/10/2018 12:01 AM, Eric Gallager wrote:
> > > > > > On 11/9/18, David Malcolm wrote:
> > > > > > > This patch adds a fix-it hint to various pointer-vs-non-
> > > > > > > pointer
> > > > > > > diagnostics, suggesting the addition of a leading '&' or
> > > > > > > '*'.
> > > > > > >
> > > > > > > For example, note the ampersand fix-it hint in the
> > > > > > > following:
> > > > > > >
> > > > > > > demo.c:5:22: error: invalid conversion from 'pthread_key_t'
> > > > > > > {aka
> > > > > > > 'unsigned
> > > > > > > int'}
> > > > > > >to 'pthread_key_t*' {aka 'unsigned int*'} [-fpermissive]
> > > > > > > 5 | pthread_key_create(key, NULL);
> > > > > > > | ^~~
> > > > > > > | |
> > > > > > > | pthread_key_t {aka unsigned
> > > > > > > int}
> > > > > > > | &
> > > > > >
> > > > > > Having both the type and the fixit underneath the caret looks
> > > > > > kind
> > > > > > of confusing
> > > > >
> > > > > I agree it's rather subtle. Keeping the diagnostics separate
> > > > > from
> > > > > the suggested fix should avoid the confusion.
> > > >
> > > > FWIW, the fix-it hint is in a different color (assuming that gcc
> > > > is
> > > > invoked in an environment that prints that...)
> > >
> > > I figured it would be, but I'm still not sure it's good design
> > > to be relying on color alone to distinguish between the problem
> > > and the suggested fix. Especially when they are so close to one
> > > another and the fix is just a single character with no obvious
> > > relationship to the rest of the text on the screen. In other
> > > warnings there's at least the "did you forget the '@'?" part
> > > to give a clue, even though even there the connection between
> > > the "did you forget" and the & several lines down wouldn't
> > > necessarily be immediately apparent.
> >
> > Agreed, something along those lines would help to understand why the
> > compiler is throwing a random & into the diagnostic.
> >
> > Jason
>
> Here's an updated version which adds a note, putting the fix-it hint
> on that instead (I attempted adding the text to the initial error,
> but there was something of a combinatorial explosion of messages).
>
> The above example becomes:
>
> demo.c: In function 'int main()':
> demo.c:5:22: error: invalid conversion from 'pthread_key_t' {aka 'unsigned
> int'}
>to 'pthread_key_t*' {aka 'unsigned int*'} [-fpermissive]
> 5 | pthread_key_create(key, NULL);
> | ^~~
> | |
> | pthread_key_t {aka unsigned int}
> demo.c:5:22: note: possible fix: take the address with '&'
> 5 | pthread_key_create(key, NULL);
> | ^~~
> | &
> In file included from demo.c:1:
> /usr/include/pthread.h:1122:47: note: initializing argument 1 of
>'int pthread_key_create(pthread_key_t*, void (*)(void*))'
> 1122 | extern int pthread_key_create (pthread_key_t *__key,
> |~~~^
>
> Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
>
> OK for trunk?
>
> gcc/c-family/ChangeLog:
> PR c++/87850
> * c-common.c: Include "gcc-rich-location.h".
> (maybe_emit_indirection_note): New function.
> * c-common.h (maybe_emit_indirection_note): New decl.
>
> gcc/c/ChangeLog:
> PR c++/87850
> * c-typeck.c (convert_for_assignment): Call
> maybe_emit_indirection_note for pointer vs non-pointer
> diagnostics.
>
> gcc/cp/ChangeLog:
> PR c++/87850
> * call.c (convert_like_real): Call
> maybe_emit_indirection_note for "invalid conversion" diagnostic.
>
> gcc/testsuite/ChangeLog:
> PR c++/87850
> * c-c++-common/indirection-fixits.c: New test.
> ---
> gcc/c-family/c-common.c | 33 +++
> gcc/c-family/c-common.h | 2 +
> gcc/c/c-typeck.c| 10 +-
> gcc/cp/call.c | 2 +
> gcc/testsuite/c-c++-common/indirection-fixits.c | 270
>
> 5 files changed, 315 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/c-c++-common/indirection-fixits.c
>
> diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c
> index cd88f3a..d5c7c7f 100644
> --- a/gcc/c-family/c-common.c
> +++ b/gcc/c-family/c-common.c
> @@ -48,6 +48,7 @@ along with GCC; see the file COPYING3. If not see
> #include "gimplify.h"
> #include "substring-locations.h"
> #include "spellcheck.h"
> +#include "gcc-rich-location.h"
Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses
On Fri, Nov 16, 2018 at 12:23:42PM +0530, Umesh Kalappa wrote:
> Thank you Marek,Appreciate your valuable feedback on the patch .
>
> Attached the latest ,please do let us know your thoughts.
Thanks, this version looks good! Just some small nits:
--- gcc/cp/parser.c (revision 266026)
+++ gcc/cp/parser.c (working copy)
@@ -24620,6 +24620,12 @@ cp_parser_noexcept_specification_opt (cp_parser* p
{
matching_parens parens;
parens.consume_open (parser);
+
+ tree save_ccp = current_class_ptr;
+ tree save_ccr = current_class_ref;
+
+ if (current_class_type)
+ inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
This is indented a bit too much: the inject_this_parameter call should be two
spaces to the right of the if. I.e.:
if (current_class_type)
inject_this_parameter (current_class_type, TYPE_UNQUALIFIED);
+2018-11-16 Kamlesh Kumar
+
+ PR c++/52869
+ * g++.dg//DRs/dr1207-1.C: New.
+ * g++.dg//DRs/dr1207-2.C: New.
Just one / instead of two.
--- gcc/testsuite/g++.dg/DRs/dr1207-1.C (nonexistent)
+++ gcc/testsuite/g++.dg/DRs/dr1207-1.C (working copy)
@@ -0,0 +1,25 @@
+// DR 1207
+// PR c++/52869
+// { dg-do compile { target c++11 } }
+
+struct S {
+void f() { }
+void g() noexcept(noexcept(f())) { }
+void h() noexcept(noexcept(this->f())) { }
+};
+
+struct Nyan {
+ Nyan &operator++() noexcept { return *this; }
+ void omg() noexcept(noexcept(++*this)) {}
+};
+
+template
+class Test{
+T count;
+Test (T arg) {count=arg;}
+void fetch() { }
+T inc () noexcept(noexcept(this->fetch())) {return ++count;}
+T dec () noexcept(noexcept(fetch())) { return --count;}
+};
+
+
There are two extra newlines you can remove but otherwise the tests look fine
now.
I'll let Jason review the last version. Thanks for contributing to GCC.
Marek
Re: Tweak ALAP calculation in SCHED_PRESSURE_MODEL
On 11/8/18 6:10 AM, Kyrill Tkachov wrote: > The attached patch avoids that by making the alap calculation only > look at true dependencies. This shouldn't be too bad, since we use > INSN_PRIORITY as the final tie-breaker than that does take > anti-dependencies into account. > > This reduces the number of spills in the hot function from 436.cactusADM > by 14% on aarch64 at -O3 (and the number of instructions in general). > SPEC2017 shows a minor improvement on Cortex-A72 (about 0.1% overall). > Thanks to Wilco for the benchmarking. I tried the patch on PowerPC since it also uses SCHED_PRESSURE_MODEL algorithm. For CPU2006 only cactusADM had a noticeable difference, but I'm seeing a 5% degradation. Looking at the generated asm for function bench_staggeredleapfrog2_(), I see about a 1% increase in number of loads and stores generated and an extra 100 bytes allocated on the stack. -Pat
Re: Tweak ALAP calculation in SCHED_PRESSURE_MODEL
On 16/11/18 18:19, Pat Haugen wrote: On 11/8/18 6:10 AM, Kyrill Tkachov wrote: > The attached patch avoids that by making the alap calculation only > look at true dependencies. This shouldn't be too bad, since we use > INSN_PRIORITY as the final tie-breaker than that does take > anti-dependencies into account. > > This reduces the number of spills in the hot function from 436.cactusADM > by 14% on aarch64 at -O3 (and the number of instructions in general). > SPEC2017 shows a minor improvement on Cortex-A72 (about 0.1% overall). > Thanks to Wilco for the benchmarking. I tried the patch on PowerPC since it also uses SCHED_PRESSURE_MODEL algorithm. For CPU2006 only cactusADM had a noticeable difference, but I'm seeing a 5% degradation. Looking at the generated asm for function bench_staggeredleapfrog2_(), I see about a 1% increase in number of loads and stores generated and an extra 100 bytes allocated on the stack. Thanks for trying it out! Given that, I'll try to polish up the more targeted approach that filters out only the fake dependencies, which should give a more targeted approach. Thanks, Kyrill -Pat
Re: [PATCH] Reject too large string literals (PR middle-end/87854)
On 11/16/2018 01:43 AM, Jakub Jelinek wrote:
Hi!
Both C and C++ FE diagnose arrays larger than half of the address space:
/tmp/1.c:1:6: error: size of array ‘a’ is too large
char a[__SIZE_MAX__ / 2 + 1];
^
because one can't do pointer arithmetics on them. But we don't have
anything similar for string literals. As internally we use host int
as TREE_STRING_LENGTH, this is relevant to targets that have < 32-bit
size_t only.
The following patch adds that diagnostics and truncates the string literals.
Bootstrapped/regtested on x86_64-linux and i686-linux and tested with
a cross to avr. I'll defer adjusting testcases to the maintainers of 16-bit
ports. From the PR it seems gcc.dg/concat2.c, g++.dg/parse/concat1.C and
pr46534.c tests are affected.
Ok for trunk?
2018-11-16 Jakub Jelinek
PR middle-end/87854
* c-common.c (fix_string_type): Reject string literals larger than
TYPE_MAX_VALUE (ssizetype) bytes.
--- gcc/c-family/c-common.c.jj 2018-11-14 13:37:46.921050615 +0100
+++ gcc/c-family/c-common.c 2018-11-15 15:20:31.138056115 +0100
@@ -737,31 +737,44 @@ tree
fix_string_type (tree value)
{
int length = TREE_STRING_LENGTH (value);
- int nchars;
+ int nchars, charsz;
tree e_type, i_type, a_type;
/* Compute the number of elements, for the array type. */
if (TREE_TYPE (value) == char_array_type_node || !TREE_TYPE (value))
{
- nchars = length;
+ charsz = 1;
e_type = char_type_node;
}
else if (TREE_TYPE (value) == char16_array_type_node)
{
- nchars = length / (TYPE_PRECISION (char16_type_node) / BITS_PER_UNIT);
+ charsz = TYPE_PRECISION (char16_type_node) / BITS_PER_UNIT;
e_type = char16_type_node;
}
else if (TREE_TYPE (value) == char32_array_type_node)
{
- nchars = length / (TYPE_PRECISION (char32_type_node) / BITS_PER_UNIT);
+ charsz = TYPE_PRECISION (char32_type_node) / BITS_PER_UNIT;
e_type = char32_type_node;
}
else
{
- nchars = length / (TYPE_PRECISION (wchar_type_node) / BITS_PER_UNIT);
+ charsz = TYPE_PRECISION (wchar_type_node) / BITS_PER_UNIT;
e_type = wchar_type_node;
}
+ /* This matters only for targets where ssizetype has smaller precision
+ than 32 bits. */
+ if (wi::lts_p (wi::to_wide (TYPE_MAX_VALUE (ssizetype)), length))
+{
+ error ("size of string literal is too large");
It would be helpful to mention the size of the literal and the limit
so users who do run into the error don't wonder how to fix it.
Martin
Re: [PATCH] Reject too large string literals (PR middle-end/87854)
On Fri, Nov 16, 2018 at 11:25:15AM -0700, Martin Sebor wrote:
> On 11/16/2018 01:43 AM, Jakub Jelinek wrote:
> >
> > + /* This matters only for targets where ssizetype has smaller precision
> > + than 32 bits. */
> > + if (wi::lts_p (wi::to_wide (TYPE_MAX_VALUE (ssizetype)), length))
> > +{
> > + error ("size of string literal is too large");
>
> It would be helpful to mention the size of the literal and the limit
> so users who do run into the error don't wonder how to fix it.
It is consistent with what we emit for the arrays.
So, if the size and limit info is helpful to users, we should provide that
for those too. I mean the:
if (name)
error_at (loc, "size of array %qE is too large",
else
error_at (loc, "size of unnamed array is too large");
name);
calls in the C FE and similar stuff in C++ FE.
Feel free to add that to all of those.
Jakub
