This patch is unchanged from that which was posted before. Discussion
fizzled out there and I was too busy with other patches to restart it
then. This issue needs to be resolved before libgfortran can be
compiled for GCN.
The IRA pass makes an assumption that any pseudos created after the pass begins
were created explicitly by the pass itself and therefore will have
corresponding entries in its other tables.
The GCN back-end, however, often creates additional pseudos, in expand
patterns, to represent the necessary EXEC value, and these break IRA's
assumption and cause ICEs:
..../libgfortran/generated/matmul_r8.c: In function 'matmul_r8':
..../libgfortran/generated/matmul_r8.c:3002:1: internal compiler error: in
setup_preferred_alternate_classes_for_new_pseudos, at ira.c:2772
This patch simply has IRA skip unknown pseudos, and the problem goes away.
Presumably, it's not ideal that these registers have not been processed by IRA,
but it does not appear to do any real harm.
2018-11-16 Andrew Stubbs <a...@codesourcery.com>
gcc/
* ira.c (setup_preferred_alternate_classes_for_new_pseudos): Skip
pseudos not created by this pass.
(move_unallocated_pseudos): Likewise.
---
gcc/ira.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/gcc/ira.c b/gcc/ira.c
index def194a..e0c293c 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -2769,7 +2769,12 @@ setup_preferred_alternate_classes_for_new_pseudos (int start)
for (i = start; i < max_regno; i++)
{
old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]);
- ira_assert (i != old_regno);
+
+ /* Skip any new pseudos not created directly by this pass.
+ gen_move_insn can do this on AMD GCN, for example. */
+ if (i == old_regno)
+ continue;
+
setup_reg_classes (i, reg_preferred_class (old_regno),
reg_alternate_class (old_regno),
reg_allocno_class (old_regno));
@@ -5054,6 +5059,12 @@ move_unallocated_pseudos (void)
{
int idx = i - first_moveable_pseudo;
rtx other_reg = pseudo_replaced_reg[idx];
+
+ /* Skip any new pseudos not created directly by find_moveable_pseudos.
+ gen_move_insn can do this on AMD GCN, for example. */
+ if (!other_reg)
+ continue;
+
rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i));
/* The use must follow all definitions of OTHER_REG, so we can
insert the new definition immediately after any of them. */
