Hello!
There are actually two problems discovered:
a) The insn condition of floatunsdidf2 is incorrect, it allows 32bit
AVX512F targets, but these are not necessarily
KEEP_VECTOR_ALIGNED_STACK targets.
b) movdi_to_sse is defined with extra parallel encapsulation.
Instructions in this form don't get registered to add_clobbers, so we
trigger assert for unknown insn ID there.
Attached patch fixes both problems. However, with the fixed pattern,
RA for some reason insists on spilling DImode register to memory, so I
rewrote the whole pattern as UNSPEC.
2018-11-16 Uros Bizjak <[email protected]>
PR target/88051
* config/i386/i386.md (floatunsdidf2): Allow only 64bit AVX512F targets.
* config/i386/sse.md (UNSPEC_MOVDI_TO_SSE): New UNSPEC.
(movdi_to_sse): Rewrite using UNSPEC_MOVDI_TO_SSE unspec.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN. The fix for pattern will be backported to
other release branches.
Uros.
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 266208)
+++ config/i386/i386.md (working copy)
@@ -5194,7 +5194,8 @@
[(set (match_operand:DF 0 "register_operand")
(unsigned_float:DF
(match_operand:DI 1 "nonimmediate_operand")))]
- "(TARGET_KEEPS_VECTOR_ALIGNED_STACK || TARGET_AVX512F)
+ "((TARGET_64BIT && TARGET_AVX512F)
+ || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
&& TARGET_SSE2 && TARGET_SSE_MATH"
{
if (!TARGET_64BIT)
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 266208)
+++ config/i386/sse.md (working copy)
@@ -21,6 +21,9 @@
;; SSE
UNSPEC_MOVNT
+ ;; SSE2
+ UNSPEC_MOVDI_TO_SSE
+
;; SSE3
UNSPEC_LDDQU
@@ -1235,10 +1238,10 @@
;; from there.
(define_insn_and_split "movdi_to_sse"
- [(parallel
- [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
- (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
- (clobber (match_scratch:V4SI 2 "=&x,X"))])]
+ [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
+ (unspec:V4SI [(match_operand:DI 1 "nonimmediate_operand" "r,m")]
+ UNSPEC_MOVDI_TO_SSE))
+ (clobber (match_scratch:V4SI 2 "=&x,X"))]
"!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC"
"#"
"&& reload_completed"
