Re: Fix PR57268
> I'd guess you don't want to flush on DEBUG_INSN_Ps, because then you'd flush
> differently between -g and -g0. So perhaps something like:
yes, If I skipped to flush all DEBUG_INSN_Ps, then dependence lists
are the same under -g0 and -g. I bootstrapped Jakub's change on
x86_64-linux with no errors.
thanks, Dinar.
On Sat, Jun 1, 2013 at 4:55 PM, Jakub Jelinek wrote:
> On Sat, Jun 01, 2013 at 10:11:24AM +0200, Jakub Jelinek wrote:
>> On Sat, Jun 01, 2013 at 08:39:58AM +0400, Dinar Temirbulatov wrote:
>> > I am investigating the problem.
>>
>> I'd guess you don't want to flush on DEBUG_INSN_Ps, because then you'd flush
>> differently between -g and -g0. So perhaps something like:
>
> Now bootstrapped/regtested on x86_64-linux and i686-linux. I see you've
> already reverted in the mean time, so ok for trunk this way?
>
> 2013-06-01 Jakub Jelinek
>
> PR rtl-optimization/57268
> * sched-deps.c (sched_analyze_2): Don't flush_pedning_lists
> if DEBUG_INSN_P (insn).
>
> Reapply
> 2013-05-31 Dinar Temirbulatov
>
> PR rtl-optimization/57268
> * sched-deps.c (sched_analyze_2): Flush dependence lists if
> the sum of the read and write lists exceeds MAX_PENDING_LIST_LENGTH.
>
> --- gcc/sched-deps.c(revision 199576)
> +++ gcc/sched-deps.c(revision 199575)
> @@ -2690,8 +2690,15 @@
>
> /* Always add these dependencies to pending_reads, since
>this insn may be followed by a write. */
> -if (!deps->readonly)
> - add_insn_mem_dependence (deps, true, insn, x);
> + if (!deps->readonly)
> + {
> + if ((deps->pending_read_list_length
> ++ deps->pending_write_list_length)
> + > MAX_PENDING_LIST_LENGTH
> + && !DEBUG_INSN_P (insn))
> + flush_pending_lists (deps, insn, true, true);
> + add_insn_mem_dependence (deps, true, insn, x);
> + }
>
> sched_analyze_2 (deps, XEXP (x, 0), insn);
>
>
> Jakub
Re: PR57073 - Optimize __builtin_powif (-1.0, k) to k & 1 ? -1.0 : 1.0
On Fri, May 31, 2013 at 5:02 PM, Tobias Burnus wrote:
> Am 31.05.2013 10:24, schrieb Richard Biener:
>>
>> On Thu, May 30, 2013 at 10:54 PM, Jeff Law wrote:
>>>
>>> Don't worry about it. The patch is good as-is.
>>
>> Why sink the !host_integerp check? Please keep it where it is now.
>>
>
> Answer: Because it doesn't work. And if I had a cup of coffee and didn't
> mess up my regtesting (by excluding the newly added test case), I had also
> seen that.
>
> The very old code had (assume: powi(x,n)):
> if (n is not a constant)
> break;
> expand powi to "n" multiplications.
>
> The original patch changed it to:
>
> if (n is a not constant and x == -1)
> result = n & 1 ? -1.0 : 1.0
> else
> {
> if (n is not a constant)
> break;
> expand powi to "n" multiplications.
> }
>
> Thus, if one moves up the condition
> if (n is not a constant)
> break;
> the newly added code becomes unreachable.
>
> However, I think the code is more readable if one simply removes the "&&
> !host_integerp (arg1,0)" from the x==1 case. Due to fold_builtin_powi having
> x==-1 and n == const should not happen - and if, the "n & 1 ? -1.0 : 1.0" is
> also not worse than an expanded multiplication (if n is large).
> [Alternatively, one can also keep (re-add) the "&& !host_integerp
> (arg1,0)".]
>
> OK? (After successful bootstrap and regtesting.)
Ok.
Thanks,
Richard.
> Tobias
Re: [PATCH] Reduce -fopt-info verbosity
On Fri, 31 May 2013, Teresa Johnson wrote:
> This patch changes the -fopt-info default to optimized instead of all,
> since the latter is extremely verbose. This reduced the -fopt-info output by
> over 75% in at least one case, since the vectorizer has many messages under
> MSG_NOTE (and that should grow as more passes are converted to the new dump
> infrastructure). The default now emits high-level optimization success info
> (currently for unrolling, inlining and vectorization).
>
> Also changed which vectorization summary messages are emitted under
> -fopt-info(=optimized), to be more consistent with the format of the
> optimization summary messages emitted by the unroller and inliner,
> and fixed the loop vectorization summary message to use dump_printf_loc
> instead of manually emitting the location info.
>
> Bootstrapped and tested on x86-64-unknown-linux-gnu. Ok for trunk?
>
> 2013-05-31 Teresa Johnson
>
> * dumpfile.c (opt_info_switch_p): Change -fopt-info
> default to -fopt-info=optimized instead of all.
> * doc/invoke.texi: Ditto.
> * tree-vectorizer.c (vectorize_loops): Emit loop vectorization
> success under MSG_ALL, and use dump_printf_loc.
> (execute_vect_slp): Emit BB vectorization success under
> MSG_OPTIMIZED_LOCATIONS.
> * tree-vect-slp.c (vect_make_slp_decision): Ditto.
> (vect_slp_transform_bb): Change MSG_OPTIMIZED_LOCATIONS
> to MSG_NOTE.
> * tree-vect-loop.c (vect_transform_loop): Ditto.
>
> Index: tree-vect-loop.c
> ===
> --- tree-vect-loop.c (revision 199423)
> +++ tree-vect-loop.c (working copy)
> @@ -5801,7 +5801,7 @@ vect_transform_loop (loop_vec_info loop_vinfo)
>
>if (dump_enabled_p ())
> {
> - dump_printf_loc (MSG_OPTIMIZED_LOCATIONS, vect_location,
> + dump_printf_loc (MSG_NOTE, vect_location,
> "LOOP VECTORIZED\n");
>if (loop->inner)
> dump_printf_loc (MSG_NOTE, vect_location,
> Index: dumpfile.c
> ===
> --- dumpfile.c(revision 199423)
> +++ dumpfile.c(working copy)
> @@ -866,7 +866,7 @@ opt_info_switch_p (const char *arg)
>
>file_seen = xstrdup (filename);
>if (!flags)
> -flags = MSG_ALL;
> +flags = MSG_OPTIMIZED_LOCATIONS;
>if (!optgroup_flags)
> optgroup_flags = OPTGROUP_ALL;
>
> Index: tree-vectorizer.c
> ===
> --- tree-vectorizer.c (revision 199423)
> +++ tree-vectorizer.c (working copy)
> @@ -118,8 +118,7 @@ vectorize_loops (void)
>
> if (LOCATION_LOCUS (vect_location) != UNKNOWN_LOC
> && dump_enabled_p ())
> - dump_printf (MSG_NOTE, "\n\nVectorizing loop at %s:%d\n",
> - LOC_FILE (vect_location), LOC_LINE (vect_location));
> + dump_printf_loc (MSG_ALL, vect_location, "Vectorized loop\n");
MSG_ALL looks wrong if we are looking for unoptimized locations
only, no? I think you want MSG_OPTIMIZED_LOCATIONS here.
> vect_transform_loop (loop_vinfo);
> num_vectorized_loops++;
>}
> @@ -179,7 +178,7 @@ execute_vect_slp (void)
> {
>vect_slp_transform_bb (bb);
>if (dump_enabled_p ())
> -dump_printf_loc (MSG_NOTE, vect_location,
> +dump_printf_loc (MSG_OPTIMIZED_LOCATIONS, vect_location,
>"basic block vectorized using SLP\n");
Please make the message consistent with the loop one. The loop one
says "Vectorized loop" (I think the caps 'V' is not according to
our diagnostic policies, it should be lower-case), the basic-block
one "basic block vectorized using SLP" which shouldn't confuse the
user about "SLP" and say "vectorized basic-block" instead.
Yes, that may require you to fiddle with testcases that scan for
these ...
> }
> }
> Index: doc/invoke.texi
> ===
> --- doc/invoke.texi (revision 199423)
> +++ doc/invoke.texi (working copy)
> @@ -6172,7 +6172,7 @@ Controls optimization dumps from various optimizat
> @samp{-@var{options}} form is used, @var{options} is a list of
> @samp{-} separated options to select the dump details and
> optimizations. If @var{options} is not specified, it defaults to
> -@option{all} for details and @option{optall} for optimization
> +@option{optimized} for details and @option{optall} for optimization
> groups. If the @var{filename} is not specified, it defaults to
> @file{stderr}. Note that the output @var{filename} will be overwritten
> in case of multiple translation units. If a combined output from
> Index: tree-vect-slp.c
> ===
> --- tree-vect-slp.c (revision 199423)
> +++ tree-vect-slp.c (working copy)
> @@ -1698,8 +1698,8 @@ vect_make_slp_decision (lo
Re: [PATCH] Improve folding of bitwise ops on booleans
On Fri, May 31, 2013 at 10:18 PM, Jeff Law wrote:
>
> This is an implementation to fix a missed optimization pointed out to me by
> Kai.
>
> In all these examples, assume a & b are single bit types.
>
> ~a && b --> a < b
For a signed 1-bit type you'll have values -1, 0 and clearly
0 < -1
is false while ~0 & -1 is non-zero.
So I believe you have to restrict these transforms to signed 1-bit values
or adjust the folding appropriately. Besides that, ...
> a && ~b --> b < a
> ~a || b --> a <= b
> a && ~b --> b <= a
I wonder if these are really a simplification if the result is not used
exclusively in a conditional jump. Because for setting a register
to a < b you'll likely get worse code than using ~a & b (given that
many ISAs have a and-not instruction). Of course you may argue
that's a bug in the RTL / target piece (getting different code for
a < b vs. ~a & b) and a < b is shorter on the tree level.
More comments in-line.
> This happens with some regularity in GCC itself, though it's not as
> pervasive as some of the other missed optimizations I've run into.
>
> This could have gone into fold-const.c or tree-forwprop. fold-const.c
> isn't as useful as would need to see the entire expression as a single tree
> node. tree-forwprop.c can follow the use-def links and discover more
> opportunities even when the expressions span two source statements or are
> exposed by other optimizations.
>
> Bootstrapped and regression tested on x86_64-unknown-linux-gnu.
>
> OK for the trunk?
>
>
> commit 2b61de6f70576105fe6ada31618db23857f9c902
> Author: Jeff Law
> Date: Fri May 31 14:16:27 2013 -0600
>
> * tree-ssa-forwprop.c (simplify_bitwise_binary_boolean): New
> * function.
> (simplify_bitwise_binary): Use it to simpify certain binary ops
> on
> booleans.
>
> * gcc.dg/tree-ssa/forwprop-27.c: New test.
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 396111e..7f027b0 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,9 @@
> +2013-05-31 Jeff Law
> +
> + * tree-ssa-forwprop.c (simplify_bitwise_binary_boolean): New
> function.
> + (simplify_bitwise_binary): Use it to simpify certain binary ops on
> + booleans.
> +
> 2013-05-28 Steve Ellcey
>
> * config/mips/mips-cpus.def (mips32r2): Change processor type.
> diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
> index 869371a..6f80afb 100644
> --- a/gcc/testsuite/ChangeLog
> +++ b/gcc/testsuite/ChangeLog
> @@ -1,3 +1,7 @@
> +2013-05-31 Jeff Law
> +
> + * gcc.dg/tree-ssa/forwprop-27.c: New test.
> +
> 2013-05-28 Balaji V. Iyer
>
> * c-c++-common/cilk-plus/AN/array_test1.c: New test.
> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-27.c
> b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-27.c
> new file mode 100644
> index 000..75e935d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-27.c
> @@ -0,0 +1,78 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fdump-tree-forwprop1" } */
> +
> +extern char * frob (void);
> +extern _Bool testit(void);
> +
> +test (int code)
> +{
> + char * temp = frob();;
> + int rotate = (code == 22);
> + if (temp == 0 && !rotate)
> + oof();
> +}
> +
> +test_2 (int code)
> +{
> + char * temp = frob();
> + int rotate = (code == 22);
> + if (!rotate && temp == 0)
> + oof();
> +}
> +
> +
> +test_3 (int code)
> +{
> + char * temp = frob();
> + int rotate = (code == 22);
> + if (!rotate || temp == 0)
> + oof();
> +}
> +
> +
> +test_4 (int code)
> +{
> + char * temp = frob();
> + int rotate = (code == 22);
> + if (temp == 0 || !rotate)
> + oof();
> +}
> +
> +
> +test_5 (int code)
> +{
> + _Bool temp = testit();;
> + _Bool rotate = (code == 22);
> + if (temp == 0 && !rotate)
> + oof();
> +}
> +
> +test_6 (int code)
> +{
> + _Bool temp = testit();
> + _Bool rotate = (code == 22);
> + if (!rotate && temp == 0)
> + oof();
> +}
> +
> +
> +test_7 (int code)
> +{
> + _Bool temp = testit();
> + _Bool rotate = (code == 22);
> + if (!rotate || temp == 0)
> + oof();
> +}
> +
> +
> +test_8 (int code)
> +{
> + _Bool temp = testit();
> + _Bool rotate = (code == 22);
> + if (temp == 0 || !rotate)
> + oof();
> +}
> +
> +/* { dg-final { scan-tree-dump-times "Replaced" 8 "forwprop1"} } */
> +
> +
> diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c
> index 6043d31..8c3f08b 100644
> --- a/gcc/tree-ssa-forwprop.c
> +++ b/gcc/tree-ssa-forwprop.c
> @@ -1870,6 +1870,45 @@ hoist_conversion_for_bitop_p (tree to, tree from)
>return false;
> }
>
> +/* GSI points to a statement of the form
> +
> + result = OP0 CODE OP1
> +
> + Where OP0 and OP1 are single bit SSA_NAMEs and CODE is either
> + BIT_AND_EXPR or BIT_IOR_EXPR.
> +
> + If OP0 is fed by a bitwise negation of another single bit SSA_NAME,
> + then we can simplify the two statements into a single LT_EXPR or LE_EXPR
> + when code is BIT_AND_EXPR and BIT_IOR_EXPR
Re: default_no_named_section bad default
On Sat, Jun 1, 2013 at 12:28 AM, Mike Stump wrote:
> On May 31, 2013, at 2:56 PM, Andrew Pinski wrote:
>> This will only fix the GCC source but not other sources which does:
>> void f(void)
>> {
>> __builtin_unreachable();
>> }
>
> Yes. Speaking of which, so how should this be handled? Imagine we have
> asm("# no bytes") before the unreachable. The compiler can't know the size
> (though, the linker can), and yet, a good solution handles this as well.
> Hopefully a dwarf person can weigh in, as engineering a bad solution is worse
> than leaving it broken in my book.
Let the assembler compute it as difference of two labels?
Richard.
Re: PR middle-end/57366
Jan Hubicka writes: > In any case this is quite self contained fix that is backportable to 4.8 if > needed. It should be since it also fixes PR target/47333, a 4.8 regression. Rainer -- - Rainer Orth, Center for Biotechnology, Bielefeld University
Re: [Patch, Fortran] PR57496 use finiteq etc. for __float in write_float.def
Janne has approved the patch on IRC, hence, I committed it as Rev. 199598. Thus, the REAL(16) issue is now solved. However, REAL(10) still fails - and has still to be debugged. See PR. Tobias
Re: Updated MAINTAINERS
2013/6/1 Dinar Temirbulatov : > Hi, > I updated MAINTAINERS list with following change(patch attached). > thanks, Dinar. Hi, Dinar, You forgot to add an entry in ChangeLog like this: Index: ChangeLog === --- ChangeLog (revision 199596) +++ ChangeLog (working copy) @@ -1,3 +1,7 @@ +2013-06-01 Dinar Temirbulatov + + * MAINTAINERS (Write After Approval): Add myself. + 2013-05-17 David Malcolm * MAINTAINERS (Write After Approval): Add myself. Best regards, jasonwucj
Minor formatting tweaks in output_constant
Tested on x86_64-suse-linux, applied on the mainline as obvious.
2013-06-03 Eric Botcazou
* varasm.c (output_constant) : Minor formatting tweak.
: Likewise.
: Likewise.
--
Eric BotcazouIndex: varasm.c
===
--- varasm.c (revision 199590)
+++ varasm.c (working copy)
@@ -4612,28 +4612,21 @@ output_constant (tree exp, unsigned HOST
switch (TREE_CODE (exp))
{
case CONSTRUCTOR:
- output_constructor (exp, size, align, NULL);
+ output_constructor (exp, size, align, NULL);
return;
case STRING_CST:
- thissize = MIN ((unsigned HOST_WIDE_INT)TREE_STRING_LENGTH (exp),
- size);
+ thissize
+ = MIN ((unsigned HOST_WIDE_INT)TREE_STRING_LENGTH (exp), size);
assemble_string (TREE_STRING_POINTER (exp), thissize);
break;
-
case VECTOR_CST:
{
- int elt_size;
- unsigned int i, nalign;
- enum machine_mode inner;
-
- inner = TYPE_MODE (TREE_TYPE (TREE_TYPE (exp)));
- nalign = MIN (align, GET_MODE_ALIGNMENT (inner));
-
- elt_size = GET_MODE_SIZE (inner);
-
+ enum machine_mode inner = TYPE_MODE (TREE_TYPE (TREE_TYPE (exp)));
+ unsigned int nalign = MIN (align, GET_MODE_ALIGNMENT (inner));
+ int elt_size = GET_MODE_SIZE (inner);
output_constant (VECTOR_CST_ELT (exp, 0), elt_size, align);
thissize = elt_size;
- for (i = 1; i < VECTOR_CST_NELTS (exp); ++i)
+ for (unsigned int i = 1; i < VECTOR_CST_NELTS (exp); i++)
{
output_constant (VECTOR_CST_ELT (exp, i), elt_size, nalign);
thissize += elt_size;
[PATCH,ARM] Fix PR57329 - backport to gcc 4.8
Hello, This patch (trunk r197155) http://gcc.gnu.org/ml/gcc-cvs/2013-03/msg00784.html fixes an ICE in gcc 4.8: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57329 OK to backport to 4.8 branch? Tested with 4.8 regression test on QEMU, no new regression. BR, Terry
Re: [PATCH] Fix linking with -findirect-dispatch
Jakub Jelinek writes: > Both libraries are actually intended to be installed, not just one. > Does your patch achieve that? The patch makes sure that the standalone libgcj_bc library is correctly built, instead of trying to install the dummy libgcj_bc library that should only be used for testing. Other than that nothing is changed. Andreas. -- Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."
RE: [PATCH][gensupport] Add optional attributes field to define_cond_exec
> Any comments/suggestions on my implementation of the idea are very > welcome. > http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01093.html > > Otherwise, OK for trunk? Ping? Thanks, Kyrill
RE: [PATCH RX] Added target specific macros for macros for RX100, RX200, and RX600
Hi Gerald, Below is the update to mention under changes link on GCC website. RX The port now allows to specify the RX100, RX200, and RX600 processors with the command line options -mcpu=rx100, -mcpu=rx200 and -mcpu=rx600 This update will go into: "New Targets and Target Specific Improvements" heading Help to guide me for updating this on GCC website would be highly appreciated. Regards, Sandeep Kumar Singh, KPIT Cummins InfoSystems Ltd. Pune, India > -Original Message- > From: Gerald Pfeifer [mailto:ger...@pfeifer.com] > Sent: Sunday, June 02, 2013 11:50 PM > To: Sandeep Kumar Singh > Cc: gcc-patches@gcc.gnu.org; Kaushik Phatak > Subject: Re: [PATCH RX] Added target specific macros for macros for RX100, > RX200, and RX600 > > On Thu, 2 May 2013, Sandeep Kumar Singh wrote: > > 2013-05-02 Sandeep Kumar Singh > > > > * rx/rx.h (TARGET_CPU_CPP_BUILTINS): Add macros for RX100, RX200, > and RX600. > > * rx/rx.opt: Add macro for rx100 with string rx100 and value RX100. > > * rx/rx-opts.h (rx_cpu_types): Add new cpu type rx100. > > * rx/t-rx: Add rx100 under multi library matches option for nofpu > > option. > > Mind also documenting this on http://gcc.gnu.org/gcc-4.9/changes.html ? > > Let me know if you need help with the web pages. > > Gerald
Re: [x86, PATCH 2/2] Enabling of the new Intel microarchitecture Silvermont
Hi, Jakub!
Thanks a lot for you remarks!
Attached is the patch which fixes all of them.
Ok to install if all testing passes?
Changelog:
gcc/
2013-06-03 Yuri Rumyantsev
* config/i386/i386.c (ix86_lea_outperforms): Fix formatting.
(ix86_avoid_lea_for_addr): Likewise.
(exact_dependency_1): Likewise.
(ix86_adjust_cost): Likewise.
(swap_top_of_ready_list): Fix formatting and !reload_completed check
removed.
(do_reorder_for_imul): Fix typo, formatting and
!reload_completed check removed.
(ix86_sched_reorder): Fix typo and formatting.
(fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types
list.
libgcc/
2013-06-03 Yuri Rumyantsev
* config/i386/cpuinfo.c (INTEL_SLM): New enum value.
2013/6/1 Jakub Jelinek :
> On Sat, Jun 01, 2013 at 03:52:55PM +0200, Jakub Jelinek wrote:
>> On Fri, May 31, 2013 at 04:56:35PM +0400, Igor Zamyatin wrote:
>> > Like this?
>>
>> Sorry for nitpicking, but there are various formatting issues.
>
> Also:
> if (clock1 == clock2)
> {
> /* Determine winner - load must win. */
> enum attr_memory memory1, memory2;
> memory1 = get_attr_memory (top);
> memory2 = get_attr_memory (next);
> if (memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD)
> return true;
> }
> should indent { by 2 columns (i.e. use tab) from if, the body
> shouldbe moved 2 extra columns to the right and } as well.
>
> And there is i>= 0 in the patch (missing space after i).
>
> No idea why you do if (!reload_completed) return something;
> in swap_top_of_ready_list and do_reoder_for_imul, when those
> functions are only ever called from ix86_sched_reorder which bails
> out early if !reload_completed.
>
> Jakub
gcc_slm_patch3_2_review.patch
Description: Binary data
Re: [x86, PATCH 2/2] Enabling of the new Intel microarchitecture Silvermont
On Mon, Jun 03, 2013 at 05:00:38PM +0400, Yuri Rumyantsev wrote: > Thanks a lot for you remarks! > > Attached is the patch which fixes all of them. > > Ok to install if all testing passes? > > Changelog: > > gcc/ > > 2013-06-03 Yuri Rumyantsev Two spaces before name, not just one. > * config/i386/i386.c (ix86_lea_outperforms): Fix formatting. Just one space after *, and tab indented CL lines. Other than that it looks good to me, but I'll let Uros chime in. Thanks. Jakub
Re: [Patch libsanitizer] merge rev 182922 (helps running under qemu)
Hi, Just committed as r199606. Thanks Christophe. On 31 May 2013 16:53, Konstantin Serebryany wrote: > On Fri, May 31, 2013 at 6:49 PM, Jack Howarth > wrote: >> On Fri, May 31, 2013 at 04:42:21PM +0200, Christophe Lyon wrote: >>> Hi, >>> >>> I'd like to backport libsanitizer commit #182922: >>> Index: sanitizer_common/sanitizer_linux.cc >>> === >>> --- sanitizer_common/sanitizer_linux.cc(revision 199453) >>> +++ sanitizer_common/sanitizer_linux.cc(working copy) >>> @@ -410,7 +410,9 @@ bool MemoryMappingLayout::Next(uptr *sta >>>CHECK_EQ(*current_++, ' '); >>>while (IsDecimal(*current_)) >>> current_++; >>> - CHECK_EQ(*current_++, ' '); >>> + // Qemu may lack the trailing space. >>> + // http://code.google.com/p/address-sanitizer/issues/detail?id=160 >>> + // CHECK_EQ(*current_++, ' '); >>>// Skip spaces. >>>while (current_ < next_line && *current_ == ' ') >>> current_++; >>> >>> It helps handling qemu's output for /proc/self/maps until the >>> corresponding patch in qemu is available to developers (it has been >>> accepted, but not part of a release yet). >>> >>> OK to commit in trunk? >> >> Christophe, >>I believe that changes from upstream are generally brought into FSF gcc >> with a >> complete merge of libsanitizer rather than just specific patches. We do seem >> to be long past due for remerge with upstream though. >> Jack > > That's correct, however I specifically asked to commit this patch > directly to gcc. > The same patch is already in upstream repo. > Unless anyone objects, this patch is OK to commit. > > I am not planing any new merge from upstream to GCC in the nearest > couple of months, unless someone has a good reason to do that. > Most likely, the next merge will go when we have LeakSanitizer (leak > detector) in stable shape. > > --kcc > > > >> >>> >>> Thanks, >>> >>> Christophe
[Patch, Fortran] PR57508 - Fix ICE/Reject-valid issue with get_temp_from_expr (intrinsic assignment with defined assignment)
Dear all,
Due to copying the attributes, the temporary variable could get marked
as function (attr.function, attr.flavor == FL_PROCEDURE). This either
lead to leaking those attributes into the assembler file - or to cause
an error due to the call to gfc_add_flavor. With this patch, I now
explicitly unset those attribues. (Fund when building ForTrilinos.)
Build and
OK for the trunk and GCC 4.8?
Tobias
2013-06-03 Tobias Burnus
PR fortran/57508
* resolve.c (get_temp_from_expr): Don't copy function
result attributes to temporary.
2013-06-03 Tobias Burnus
PR fortran/57508
* gfortran.dg/defined_assignment_7.f90: New.
diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c
index b2e8fdc..655d3c1 100644
--- a/gcc/fortran/resolve.c
+++ b/gcc/fortran/resolve.c
@@ -9293,8 +9293,12 @@ get_temp_from_expr (gfc_expr *e, gfc_namespace *ns)
}
}
/* Add the attributes and the arrayspec to the temporary. */
/* Add the attributes and the arrayspec to the temporary. */
tmp->n.sym->attr = gfc_expr_attr (e);
+ tmp->n.sym->attr.function = 0;
+ tmp->n.sym->attr.result = 0;
+ tmp->n.sym->attr.flavor = FL_VARIABLE;
+
if (as)
{
tmp->n.sym->as = gfc_copy_array_spec (as);
@@ -9307,7 +9311,6 @@ get_temp_from_expr (gfc_expr *e, gfc_namespace *ns)
tmp->n.sym->attr.dimension = 0;
gfc_set_sym_referenced (tmp->n.sym);
- gfc_add_flavor (&tmp->n.sym->attr, FL_VARIABLE, name, NULL);
gfc_commit_symbol (tmp->n.sym);
e = gfc_lval_expr_from_sym (tmp->n.sym);
--- /dev/null 2013-06-03 08:35:13.011105509 +0200
+++ gcc/gcc/testsuite/gfortran.dg/defined_assignment_7.f90 2013-06-03 15:58:17.227408173 +0200
@@ -0,0 +1,29 @@
+! { dg-compile }
+!
+! PR fortran/57508
+!
+module ForTrilinos_ref_counter
+ type ref_counter
+ contains
+ procedure :: assign
+ generic :: assignment(=) => assign
+ end type
+contains
+ subroutine assign (lhs, rhs)
+class (ref_counter), intent(inout) :: lhs
+class (ref_counter), intent(in) :: rhs
+ end subroutine
+end module
+module FEpetra_BlockMap
+ use ForTrilinos_ref_counter, only : ref_counter
+ type :: Epetra_BlockMap
+type(ref_counter) :: counter
+ end type
+contains
+ function from_struct() result(new_Epetra_BlockMap)
+type(Epetra_BlockMap) :: new_Epetra_BlockMap
+ end function
+ type(Epetra_BlockMap) function create_arbitrary()
+create_arbitrary = from_struct()
+ end function
+end module
symtab cleanups 3/17: fix alias visibility logic
Hi,
GCC's alias support follows how C level alias attributes work: function
bodies/variable initializers are associated with particular symbols and other
aliases are separate symbol referring to the one they are aliasing.
In ELF implementation and by my understanding of BFD also everywher else
the aliases are just symbols pointing to the same place as the symbol they
are aliasing.
This has different semanting WRT interposing. In GCC vision, when you interpose
the alias target, the alias itself is retargetted to new destination. In ELF
implementation this does not happen and it is used common for the internal
aliases within shared libraries.
This patch makes GCC to follow ELF semantic in the visibility code and inlining.
Other IPA passes needs further updating and so does the lto-symtab code where
interposition is implemented in the wrong way.
Bootstrapped/regtested x86_64-linux and ppc64-linux, will commit it shortly.
Honza
* gcc.dg/tree-ssa/attr-alias.c: New testcase.
* ipa-inline.c (update_caller_keys): Fix availability test.
(update_callee_keys): Likewise.
* symtab.c (symtab_alias_ultimate_target): Make availaiblity logic
to follow ELF standard.
Index: testsuite/gcc.dg/tree-ssa/attr-alias.c
===
*** testsuite/gcc.dg/tree-ssa/attr-alias.c (revision 0)
--- testsuite/gcc.dg/tree-ssa/attr-alias.c (revision 0)
***
*** 0
--- 1,29
+ /* { dg-do compile } */
+ /* { dg-require-alias "" } */
+ /* { dg-options "-O2 -fdump-tree-optimized" } */
+ void abort (void);
+ __attribute__ ((weak))
+ int test()
+ {
+return 0;
+ }
+ static int test2() __attribute__ ((alias("test")));
+ static int test3() __attribute__ ((weakref)) __attribute__ ((alias("test2")));
+ static int test4() __attribute__ ((weakref)) __attribute__ ((alias("test")));
+ main()
+ {
+ test();
+ test2();
+ test3();
+ test4();
+ }
+
+ /* calls to test1 and test2 can be inlined and optmized away. Calls
+to test and test4 are overwritable. */
+
+ /* { dg-final { scan-tree-dump-times "test (" 2 "optimized" } } */
+ /* { dg-final { scan-tree-dump-times "test4 (" 1 "optimized" } } */
+ /* { dg-final { scan-tree-dump-not "test1 (" "optimized" } } */
+ /* { dg-final { scan-tree-dump-not "test2 (" "optimized" } } */
+ /* { dg-final { cleanup-tree-dump "optimized" } } */
+
Index: ipa-inline.c
===
*** ipa-inline.c(revision 199591)
--- ipa-inline.c(working copy)
*** update_caller_keys (fibheap_t heap, stru
*** 1101,1107
struct ipa_ref *ref;
if ((!node->symbol.alias && !inline_summary (node)->inlinable)
- || cgraph_function_body_availability (node) <= AVAIL_OVERWRITABLE
|| node->global.inlined_to)
return;
if (!bitmap_set_bit (updated_nodes, node->uid))
--- 1101,1106
*** update_callee_keys (fibheap_t heap, stru
*** 1162,1168
if (e->inline_failed
&& (callee = cgraph_function_or_thunk_node (e->callee, &avail))
&& inline_summary (callee)->inlinable
! && cgraph_function_body_availability (callee) >= AVAIL_AVAILABLE
&& !bitmap_bit_p (updated_nodes, callee->uid))
{
if (can_inline_edge_p (e, false)
--- 1161,1167
if (e->inline_failed
&& (callee = cgraph_function_or_thunk_node (e->callee, &avail))
&& inline_summary (callee)->inlinable
! && avail >= AVAIL_AVAILABLE
&& !bitmap_bit_p (updated_nodes, callee->uid))
{
if (can_inline_edge_p (e, false)
Index: symtab.c
===
*** symtab.c(revision 199591)
--- symtab.c(working copy)
*** symtab_node_availability (symtab_node no
*** 834,852
symtab_node
symtab_alias_ultimate_target (symtab_node node, enum availability
*availability)
{
if (availability)
! *availability = symtab_node_availability (node);
while (node)
{
if (node->symbol.alias && node->symbol.analyzed)
node = symtab_alias_target (node);
else
! return node;
! if (node && availability)
{
enum availability a = symtab_node_availability (node);
if (a < *availability)
*availability = a;
}
}
if (availability)
--- 834,897
symtab_node
symtab_alias_ultimate_target (symtab_node node, enum availability
*availability)
{
+ bool weakref_p = false;
+
+ if (!node->symbol.alias)
+ {
+ if (availability)
+ *availability = symtab_node_availability (node);
+ return node;
+ }
+
+ /* To determine visibility of the target, we follow ELF semantic of aliases.
+ Here alias is an alternative assembler name of a given definition. Its
+ availablity prevails the availablity of its targe
[gomp4] Array section C++ parsing
Hi!
This patch parses array sections in map/to/from/depend clauses and provides
diagnostics (+ testcases for that) for it. Depend clause right now is just
ignored during omp lowering, and for map/to/from clause we would ICE during
omp expansion, which isn't done yet, but as the testcases test errorneous
code we don't go that far right now and bail out earlier.
For depend clause with array sections it just affects what address is
kept in the clause afterwards, for map/to/from there is OMP_CLAUSE_SIZE
which says how many bytes are to be allocated and sometimes also copied.
Does this look reasonable?
2013-06-03 Jakub Jelinek
* gimplify.c (gimplify_scan_omp_clauses): Handle array
sections on OMP_CLAUSE_{MAP,TO,FROM} clauses, handle
OMP_CLAUSE_DEPEND clause.
(gimplify_adjust_omp_clauses): Handle array sections on
OMP_CLAUSE_MAP, handle OMP_CLAUSE_DEPEND clause.
* tree.c (omp_clause_num_ops): OMP_CLAUSE_{MAP,TO,FROM}
now have 2 arguments, move OMP_CLAUSE_UNIFORM before these
3.
(omp_clause_code_name): Adjust for OMP_CLAUSE_UNIFORM movement.
(walk_tree_1): Adjust to handle 2 arguments of
OMP_CLAUSE_{MAP,TO,FROM}.
* tree-pretty-print.c (dump_omp_clause): For OMP_CLAUSE_{MAP,TO,FROM}
print OMP_CLAUSE_SIZE, and for OMP_CLAUSE_MAP handle
OMP_CLAUSE_MAP_POINTER.
* tree.h (enum omp_clause_code): Move OMP_CLAUSE_UNIFORM before
OMP_CLAUSE_{MAP,TO,FROM}.
(OMP_CLAUSE_SIZE): Define.
(enum omp_clause_map_kind): Add OMP_CLAUSE_MAP_POINTER.
* omp-low.c (scan_sharing_clauses): Handle OMP_CLAUSE_DEPEND.
cp/
* semantics.c (handle_omp_array_sections_1, handle_omp_array_sections):
New functions.
(finish_omp_clauses): Handle array sections on
OMP_CLAUSE_{MAP,TO,FROM,DEPEND}. If not array sections, mark the decl
addressable.
* parser.c (cp_parser_omp_var_list_no_open): Parse array sections
on OMP_CLAUSE_{MAP,TO,FROM,DEPEND} clauses.
testsuite/
* g++.dg/gomp/depend-1.C: New test.
* g++.dg/gomp/depend-2.C: New test.
* c-c++-common/gomp/depend-1.c: New test.
* c-c++-common/gomp/depend-2.c: New test.
* c-c++-common/gomp/map-1.c: New test.
--- gcc/gimplify.c.jj 2013-05-29 10:05:42.0 +0200
+++ gcc/gimplify.c 2013-06-03 15:37:14.653703574 +0200
@@ -6258,19 +6258,78 @@ gimplify_scan_omp_clauses (tree *list_p,
}
flags = GOVD_LINEAR | GOVD_EXPLICIT;
goto do_add;
+
case OMP_CLAUSE_MAP:
+ if (OMP_CLAUSE_SIZE (c)
+ && gimplify_expr (&OMP_CLAUSE_SIZE (c), pre_p,
+ NULL, is_gimple_val, fb_rvalue) == GS_ERROR)
+ {
+ remove = true;
+ break;
+ }
+ decl = OMP_CLAUSE_DECL (c);
+ if (!DECL_P (decl))
+ {
+ if (gimplify_expr (&OMP_CLAUSE_DECL (c), pre_p,
+NULL, is_gimple_lvalue, fb_lvalue)
+ == GS_ERROR)
+ {
+ remove = true;
+ break;
+ }
+ break;
+ }
flags = GOVD_MAP | GOVD_EXPLICIT;
notice_outer = false;
goto do_add;
+ case OMP_CLAUSE_DEPEND:
+ if (TREE_CODE (OMP_CLAUSE_DECL (c)) == COMPOUND_EXPR)
+ {
+ gimplify_expr (&TREE_OPERAND (OMP_CLAUSE_DECL (c), 0), pre_p,
+NULL, is_gimple_val, fb_rvalue);
+ OMP_CLAUSE_DECL (c) = TREE_OPERAND (OMP_CLAUSE_DECL (c), 1);
+ }
+ if (error_operand_p (OMP_CLAUSE_DECL (c)))
+ {
+ remove = true;
+ break;
+ }
+ OMP_CLAUSE_DECL (c) = build_fold_addr_expr (OMP_CLAUSE_DECL (c));
+ if (gimplify_expr (&OMP_CLAUSE_DECL (c), pre_p, NULL,
+is_gimple_val, fb_rvalue) == GS_ERROR)
+ {
+ remove = true;
+ break;
+ }
+ break;
+
case OMP_CLAUSE_TO:
case OMP_CLAUSE_FROM:
+ if (OMP_CLAUSE_SIZE (c)
+ && gimplify_expr (&OMP_CLAUSE_SIZE (c), pre_p,
+ NULL, is_gimple_val, fb_rvalue) == GS_ERROR)
+ {
+ remove = true;
+ break;
+ }
decl = OMP_CLAUSE_DECL (c);
if (error_operand_p (decl))
{
remove = true;
break;
}
+ if (!DECL_P (decl))
+ {
+ if (gimplify_expr (&OMP_CLAUSE_DECL (c), pre_p,
+NULL, is_gimple_lvalue, fb_lvalue)
+ == GS_ERROR)
+ {
+ remove = true;
+ break;
+ }
+ break;
+ }
goto do_notice;
do_add:
@@ -6621,8 +6680,9 @@ gimplify_adjust_omp_clauses (tree *list_
Re: [PATCH] Improve folding of bitwise ops on booleans
Hmm, it isn't necessary to restrict this optimization AFAICS. We have just two cases. (~X & Y) -> X < Y (X & ~Y) -> Y < X (~X | Y) -> X <= Y (X | ~Y) -> Y <= X is true for unsigned 1-bit types. For signed 1-bit types we need to invert logic here as following: (~X & Y) -> X > Y (X & ~Y) -> Y > X (~X | Y) -> X >= Y (X | ~Y) -> Y >= X Btw there is one optimization in this context which might be something worth here too. -X -> X for 1-bit typed X (signed doesn't matter here). Kai
Re: [PATCH, libcpp] Do not decrease highest_location if the included file has be included twice.
Hello Dehao, Dehao Chen a écrit: > This patch fixes the bug that when include a header file, if the > header file is already included (with #define _HEADER_H_), libcpp > should not decrease its highest_location, otherwise it'll cause > incorrect source location when source location numbers are large > enough to omit columns. Just for my education, could you please explain why decreasing pfile->line_table->highest_location here would incur incorrect source location *when* location numbers are so large that we emit column numbers? As the patch lacks a test case, I cannot e.g, run this in a debugger to understand precisely what you mean. Thus it'd be helpful for me to understand what code spots are involved exactly under the conditions you are seeing. I am CC-ing Tom for this as well. Thanks. [...] > 2013-05-31 Dehao Chen > > * files.c (_cpp_stack_include): Fix the highest_location when header > file is guarded by #ifndef and is included twice. > > > Index: libcpp/files.c > === > --- libcpp/files.c (revision 199416) > +++ libcpp/files.c (working copy) > @@ -1002,7 +1002,8 @@ _cpp_stack_include (cpp_reader *pfile, const char > linemap_add is not called) or we were included from the > command-line. */ >if (file->pchname == NULL && file->err_no == 0 > - && type != IT_CMDLINE && type != IT_DEFAULT) > + && type != IT_CMDLINE && type != IT_DEFAULT > + && !(file->cmacro && file->cmacro->type == NT_MACRO)) > pfile->line_table->highest_location--; > >return _cpp_stack_file (pfile, file, type == IT_IMPORT); -- Dodji
Re: [PATCH RX] Added target specific macros for macros for RX100, RX200, and RX600
2013/6/3 Sandeep Kumar Singh : > Hi Gerald, > > Below is the update to mention under changes link on GCC website. > > RX > The port now allows to specify the RX100, RX200, and RX600 processors > with the command > line options -mcpu=rx100, -mcpu=rx200 and -mcpu=rx600 > > This update will go into: > "New Targets and Target Specific Improvements" heading > > Help to guide me for updating this on GCC website would be highly appreciated. > > > Regards, > Sandeep Kumar Singh, > KPIT Cummins InfoSystems Ltd. > Pune, India > > Hi, Sandeep, GCC website is available via CVS access: http://gcc.gnu.org/cvs.html I think your patch for wwwdoc can be presented as follows: Index: htdocs/gcc-4.9/changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.9/changes.html,v retrieving revision 1.15 diff -r1.15 changes.html 176d175 < --- > RX > > The port now allows to specify the RX100, RX200, and RX600 processors > with the command line options -mcpu=rx100, -mcpu=rx200 and -mcpu=rx600. > > Best regards, jasonwucj
Re: PING^2 [libitm,PATCH] Fix bootstrap due to __always_inline in libitm
On 06/01/2013 03:44 PM, Gerald Pfeifer wrote: > 2013-05-31 Gerald Pfeifer > > PR bootstrap/56714 > * local_atomic (__always_inline): Always define our version. > (__calculate_memory_order): Mark inline. > (atomic_thread_fence): Ditto. > (atomic_signal_fence): Ditto. > (atomic_bool::atomic_flag_test_and_set_explicit): Ditto. > (atomic_bool::atomic_flag_clear_explicit): Ditto. > (atomic_bool::atomic_flag_test_and_set): Ditto. > (atomic_bool::atomic_flag_clear): Ditto. Ok. r~
Re: [PATCH] Disable no-section-anchors-vect-68.C for aarch64 tiny memory model.
On 31/05/13 12:52, Marcus Shawcroft wrote:
The vect/no-section-anchors-vect-68.C test case results in a binary that
is tool large for the aarch64 tiny memory model. This patch disables
the test case for that memory model.
/Marcus
2013-05-31 Marcus Shawcroft
* gcc.dg/vect/no-section-anchors-vect-68.c:
Add dg-skip-if aarch64_tiny.
gcc-disable-tiny-test-1.diff
diff --git a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c
b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c
index 4b61305..7a77651 100644
--- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c
+++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c
@@ -1,4 +1,6 @@
-/* { dg-require-effective-target vect_int } */
+/* { dg-require-effective-target vect_int }
+ { dg-skip-if "AArch64 tiny code model does not support programs larger than 1MiB"
{aarch64_tiny} {"*"} {""} }
+ */
#include
#include "tree-vect.h"
OK.
R.
Re: [x86, PATCH 2/2] Enabling of the new Intel microarchitecture Silvermont
Thanks, Jakub! Updated Changelog: gcc/ 2013-06-03 Yuri Rumyantsev * config/i386/i386.c (ix86_lea_outperforms): Fix formatting. (ix86_avoid_lea_for_addr): Likewise. (exact_dependency_1): Likewise. (ix86_adjust_cost): Likewise. (swap_top_of_ready_list): Fix formatting and !reload_completed check removed. (do_reorder_for_imul): Fix typo, formatting and !reload_completed check removed. (ix86_sched_reorder): Fix typo and formatting. (fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types list. libgcc/ 2013-06-03 Yuri Rumyantsev * config/i386/cpuinfo.c (INTEL_SLM): New enum value. All testing is ok. Uros, is it ok for trunk? 2013/6/3 Jakub Jelinek : > On Mon, Jun 03, 2013 at 05:00:38PM +0400, Yuri Rumyantsev wrote: >> Thanks a lot for you remarks! >> >> Attached is the patch which fixes all of them. >> >> Ok to install if all testing passes? >> >> Changelog: >> >> gcc/ >> >> 2013-06-03 Yuri Rumyantsev > > Two spaces before name, not just one. > >> * config/i386/i386.c (ix86_lea_outperforms): Fix formatting. > > Just one space after *, and tab indented CL lines. > Other than that it looks good to me, but I'll let Uros chime in. > > Thanks. > > Jakub
[C++ Patch] PR 57419
Hi,
in this SFINAE issue, finish_qualified_id_expr is called with complain
== 0 and calls mark_used, which has naked error calls. The
straightforward fix works well. I'm also taking the occasion to change
an error to inform (then some testcases must be adjusted).
Tested x86_64-linux.
Thanks,
Paolo.
/gcc/cp
2013-06-03 Paolo Carlini
PR c++/57419
* decl2.c (mark_used_sfinae): Add.
* semantics.c (finish_qualified_id_expr): Use it.
* cp-tree.h: Update.
/gcc/testsuite
2013-06-03 Paolo Carlini
PR c++/57419
* g++.dg/cpp0x/sfinae46.C: New.
* g++.dg/cpp0x/defaulted13.C: Adjust.
* g++.dg/cpp0x/defaulted2.C: Likewise.
* g++.dg/cpp0x/defaulted26.C: Likewise.
* g++.dg/cpp0x/defaulted3.C: Likewise.
* g++.dg/cpp0x/error1.C: Likewise.
* g++.dg/cpp0x/implicit1.C: Likewise.
* g++.dg/cpp0x/implicit11.C: Likewise.
* g++.dg/cpp0x/inh-ctor13.C: Likewise.
* g++.dg/cpp0x/initlist47.C: Likewise.
* g++.dg/cpp0x/initlist9.C: Likewise.
* g++.dg/cpp0x/lambda/lambda-errloc.C: Likewise.
* g++.dg/cpp0x/lambda/lambda-errloc2.C: Likewise.
* g++.dg/cpp0x/nsdmi-local.C: Likewise.
* g++.dg/cpp0x/union4.C: Likewise.
* g++.dg/template/crash108.C: Likewise.
* g++.dg/template/crash41.C: Likewise.
* g++.old-deja/g++.jason/local.C: Likewise.
* g++.old-deja/g++.law/visibility3.C: Likewise.
/libstdc++-v3
2013-06-03 Paolo Carlini
PR c++/57419
* testsuite/20_util/default_delete/48631_neg.cc: Adjust.
Index: gcc/cp/cp-tree.h
===
--- gcc/cp/cp-tree.h(revision 199607)
+++ gcc/cp/cp-tree.h(working copy)
@@ -5278,6 +5278,7 @@ extern bool decl_constant_var_p (tree);
extern bool decl_maybe_constant_var_p (tree);
extern void check_default_args (tree);
extern bool mark_used (tree);
+extern bool mark_used_sfinae (tree, tsubst_flags_t);
extern void finish_static_data_member_decl (tree, tree, bool, tree, int);
extern tree cp_build_parm_decl (tree, tree);
extern tree get_guard (tree);
Index: gcc/cp/decl2.c
===
--- gcc/cp/decl2.c (revision 199607)
+++ gcc/cp/decl2.c (working copy)
@@ -4499,7 +4499,7 @@ possibly_inlined_p (tree decl)
wrong, true otherwise. */
bool
-mark_used (tree decl)
+mark_used_sfinae (tree decl, tsubst_flags_t complain)
{
/* If DECL is a BASELINK for a single function, then treat it just
like the DECL for the function. Otherwise, if the BASELINK is
@@ -4537,9 +4537,12 @@ bool
return false;
}
}
- error ("use of deleted function %qD", decl);
- if (!maybe_explain_implicit_delete (decl))
- error_at (DECL_SOURCE_LOCATION (decl), "declared here");
+ if (complain & tf_error)
+ {
+ error ("use of deleted function %qD", decl);
+ if (!maybe_explain_implicit_delete (decl))
+ inform (DECL_SOURCE_LOCATION (decl), "declared here");
+ }
return false;
}
@@ -4552,7 +4555,8 @@ bool
{
if (!processing_template_decl && type_uses_auto (TREE_TYPE (decl)))
{
- error ("use of %qD before deduction of %", decl);
+ if (complain & tf_error)
+ error ("use of %qD before deduction of %", decl);
return false;
}
return true;
@@ -4701,4 +4705,10 @@ bool
return true;
}
+bool
+mark_used (tree decl)
+{
+ return mark_used_sfinae (decl, tf_warning_or_error);
+}
+
#include "gt-cp-decl2.h"
Index: gcc/cp/semantics.c
===
--- gcc/cp/semantics.c (revision 199607)
+++ gcc/cp/semantics.c (working copy)
@@ -1778,8 +1778,9 @@ finish_qualified_id_expr (tree qualifying_class,
if (error_operand_p (expr))
return error_mark_node;
- if (DECL_P (expr) || BASELINK_P (expr))
-mark_used (expr);
+ if ((DECL_P (expr) || BASELINK_P (expr))
+ && !mark_used_sfinae (expr, complain))
+return error_mark_node;
if (template_p)
check_template_keyword (expr);
Index: gcc/testsuite/g++.dg/cpp0x/defaulted13.C
===
--- gcc/testsuite/g++.dg/cpp0x/defaulted13.C(revision 199598)
+++ gcc/testsuite/g++.dg/cpp0x/defaulted13.C(working copy)
@@ -7,13 +7,13 @@ struct NonCopyable {
};
template<>
-NonCopyable::NonCopyable(NonCopyable const&) = delete; // { dg-error
"declared" }
+NonCopyable::NonCopyable(NonCopyable const&) = delete; // {
dg-message "declared" }
template
NonCopyable::NonCopyable(NonCopyable const&) = default;
template<>
-NonCopyable::NonCopyable(NonCopyable const&) = delete; // {
dg-error "declared" }
+NonCopy
RE: [AArch64] Fix printf format warning in aarch64_print_operand
> > --- > > gcc/ > > > > 2013-04-22 James Greenhalgh > > > > * config/aarch64/aarch64.c (aarch64_print_operand): Fix > asm_fprintf > > format specifier in 'X' case. > > > > OK. > > R. Hi, This warning also occurs on gcc-4_8-branch, can I also backport the fix to there now that 4.8 is open again? I've run a regression run for aarch64-none-elf with no regressions. Thanks, James
Re: [AArch64] Fix printf format warning in aarch64_print_operand
On 03/06/13 16:17, James Greenhalgh wrote: --- gcc/ 2013-04-22 James Greenhalgh * config/aarch64/aarch64.c (aarch64_print_operand): Fix asm_fprintf format specifier in 'X' case. OK. R. Hi, This warning also occurs on gcc-4_8-branch, can I also backport the fix to there now that 4.8 is open again? I've run a regression run for aarch64-none-elf with no regressions. OK /Marcus
Re: [x86, PATCH 2/2] Enabling of the new Intel microarchitecture Silvermont
On Mon, Jun 3, 2013 at 4:43 PM, Yuri Rumyantsev wrote: > Updated Changelog: > > gcc/ > > 2013-06-03 Yuri Rumyantsev > > * config/i386/i386.c (ix86_lea_outperforms): Fix formatting. > (ix86_avoid_lea_for_addr): Likewise. > (exact_dependency_1): Likewise. > (ix86_adjust_cost): Likewise. > (swap_top_of_ready_list): Fix formatting and !reload_completed check > removed. > (do_reorder_for_imul): Fix typo, formatting and > !reload_completed check removed. > (ix86_sched_reorder): Fix typo and formatting. > (fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types > list. > > libgcc/ > > 2013-06-03 Yuri Rumyantsev > > * config/i386/cpuinfo.c (INTEL_SLM): New enum value. > > > All testing is ok. > > Uros, is it ok for trunk? Looks OK. Sorry for not noticing ABI breakage earlier. Thanks, Uros.
Re: [GOOGLE] Unrestrict early inline restrictions for AutoFDO
The performance testing is ok. But it does not solve the problem: for
some recursive function calls, the size growth is calculated as 0. So
I think we may want to just fall back to the 4.7 to limit the
iterations to 10 for AutoFDO enabled build?
Dehao
On Sun, Jun 2, 2013 at 9:36 PM, Xinliang David Li wrote:
> The patch is ok if performance test passes. For a complete fix, Is it
> better to tune down PARAM_EARLY_INLINE_INSNS from 11 to a small value
> for autoFDO or use a different parameter?
>
> David
>
> On Sun, Jun 2, 2013 at 9:19 PM, Dehao Chen wrote:
>> I've updated the patch to check it at ipa-inline:
>>
>> Index: gcc/ipa-inline.c
>> ===
>> --- gcc/ipa-inline.c (revision 199593)
>> +++ gcc/ipa-inline.c (working copy)
>> @@ -434,6 +434,16 @@ want_early_inline_function_p (struct cgraph_edge *
>>
>>if (growth <= PARAM_VALUE (PARAM_EARLY_INLINING_INSNS_ANY))
>> ;
>> + else if (flag_auto_profile)
>> + {
>> + if (dump_file)
>> +fprintf (dump_file, " will not early inline: %s/%i->%s/%i, "
>> + "call is cold in profiling and code would grow by %i\n",
>> + xstrdup (cgraph_node_name (e->caller)), e->caller->uid,
>> + xstrdup (cgraph_node_name (callee)), callee->uid,
>> + growth);
>> +want_inline = false;
>> + }
>>else if (!cgraph_maybe_hot_edge_p (e))
>> {
>>if (dump_file)
>>
>> Thanks,
>> Dehao
>>
>> On Sun, Jun 2, 2013 at 9:08 PM, Xinliang David Li wrote:
>>> If the purpose of the fix is to filter early inlinings with code
>>> growth in autoFDO, the proposed fix is the wrong way to do -- it
>>> changes the meaning of cgraph_maybe_hot_edge_p.
>>>
>>> David
>>>
>>> On Sun, Jun 2, 2013 at 7:25 PM, Dehao Chen wrote:
On Sun, Jun 2, 2013 at 7:14 PM, Xinliang David Li
wrote:
>
> auto profile info is not available yet in early inlining, why would
> this change make any difference?
Because the check of PARAM_EARLY_INLINING_INSNS is after the check of
cgraph_maybe_hot_edge_p in early inline. If
cgraph_maybe_hot_edge_p fails, the early inline will not happen even
if growth is less than PARAM_EARLY_INLINING_INSNS.
>
> Can you just reset the max_iters to a
> higher value for autoFDO?
We could do that, but it could still lead to some code bloat because
recursive inlines can happen for at most, say 10, iterations.
Dehao
>
> David
>
> On Sun, Jun 2, 2013 at 6:21 PM, Dehao Chen wrote:
> > The patch was committed to google-4_8, but it causes problem because
> > einline sets PARAM_EARLY_INLINING_INSNS = 11. This will cause
> > recursive inlining at einline stage (e.g. main->foo, foo->bar,
> > bar->foo) when autofdo is enabled.
> >
> > The following patch can fix the problem by doing more targetted early
> > inlining:
> >
> > Index: gcc/predict.c
> > ===
> > --- gcc/predict.c (revision 199593)
> > +++ gcc/predict.c (working copy)
> > @@ -175,6 +175,8 @@ cgraph_maybe_hot_edge_p (struct cgraph_edge *edge)
> >&& !maybe_hot_count_p (NULL,
> > edge->count))
> > return false;
> > + if (flag_auto_profile)
> > +return false;
> >if (edge->caller->frequency == NODE_FREQUENCY_UNLIKELY_EXECUTED
> >|| (edge->callee
> >&& edge->callee->frequency == NODE_FREQUENCY_UNLIKELY_EXECUTED))
> >
> > Performance testing on-going...
> >
> > Dehao
> >
> > On Wed, May 29, 2013 at 3:44 PM, Dehao Chen wrote:
> >> OK, I'll commit the early inline part.
> >>
> >> Dehao
> >>
> >> On Wed, May 29, 2013 at 10:00 AM, Xinliang David Li
> >> wrote:
> >>> The early inlining part is ok. The tracer optimization should be
> >>> revisited -- we should have more fine grain control on it (for
> >>> instance, based on FDO summary -- but that should be common to
> >>> FDO/LIPO).
> >>>
> >>> David
> >>>
> >>> On Wed, May 29, 2013 at 9:39 AM, Dehao Chen wrote:
> In gcc4-8, the max einline iterations are restricted to 1. For
> AutoFDO, this is bad because early inline is not size restricted.
> This
> patch allows einline to do multiple iterations in AutoFDO. It also
> enables tracer optimization in AutoFDO.
>
> Bootstrapped and passed regression test.
>
> OK for googel-4_8?
>
> Thanks,
> Dehao
>
> Index: gcc/ipa-inline.c
> ===
> --- gcc/ipa-inline.c (revision 199416)
> +++ gcc/ipa-inline.c (working copy)
> @@ -2161,7 +2161,8 @@ early_inliner (void)
> {
> /* We iterate incremental inlining to get triv
[PATCH v2 1/6] rs6000: Introducing define_dot_insn
This adds a program (mdm.pl) that does some processing on machine
description files. It is careful to keep formatting and comments
intact as much as possible, so that its output is well readable.
The only transform it does so far is convert a "define_dot_insn"
construct to three "define_insn"s and two "define_split"s, that
together handle a PowerPC GPR instruction and its record-form
("dot") variant. The syntax of define_dot_insn is just like that
of define_insn, with an extra condition string added after the
normal one; the condition used for the record form variant is the
conjunction of both those condition strings.
The mdm.pl program is only used if the input file (*.mdm) has been
touched, so users do not need Perl installed to build GCC unless
they have changed the input file. The output file (*.md) is checked
into SVN.
This needs Perl 5.14, which is two years old. If that won't do
I can rework some of it so it needs only 5.10, which is five years
old.
As an example this patch moves lshrdi3 over. This causes a minor
regression that further patches will fix: no longer a different
instruction type attribute is used for the dot form; instead, the
"dot" attribute is set to "yes". Hopefully, with many fewer (and
more descriptive) possible values for "type" the scheduling
descriptions will be clearer and contain fewer silly bugs.
Bootstrapped and tested on powerpc64-linux --enable-languages=c,c++,fortran
--disable-libsanitizer, -m64,-m32,-m32/-mpowerpc64, no regressions.
Comments, questions, flames? I'm still wearing my asbestos suit...
Segher
2013-06-03 Segher Boessenkool
gcc/
* config/rs6000/rs6000.md (dot): New.
(include "integer.md"): New.
(lshrdi3_internal1, lshrdi3_internal2, lshrdi3_internal3): Delete.
* config/rs6000/integer.mdm: New file.
* config/rs6000/integer.md: New file, autogenerated.
* config/rs6000/mdm.pl: New file.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add integer.md.
(MDM): New.
(%.md: %.mdm): New.
contrib/
* gcc_update (files_and_dependencies): Add rs6000 integer.md.
---
contrib/gcc_update| 1 +
gcc/config/rs6000/integer.md | 145 +
gcc/config/rs6000/integer.mdm | 66 ++
gcc/config/rs6000/mdm.pl | 470 ++
gcc/config/rs6000/rs6000.md | 82 +---
gcc/config/rs6000/t-rs6000| 6 +
6 files changed, 693 insertions(+), 77 deletions(-)
create mode 100644 gcc/config/rs6000/integer.md
create mode 100644 gcc/config/rs6000/integer.mdm
create mode 100755 gcc/config/rs6000/mdm.pl
diff --git a/contrib/gcc_update b/contrib/gcc_update
index 10a5970..5fd2f2e 100755
--- a/contrib/gcc_update
+++ b/contrib/gcc_update
@@ -89,6 +89,7 @@ gcc/config/c6x/c6x-mult.md: gcc/config/c6x/c6x-mult.md.in
gcc/config/c6x/genmult
gcc/config/m68k/m68k-tables.opt: gcc/config/m68k/m68k-devices.def
gcc/config/m68k/m68k-isas.def gcc/config/m68k/m68k-microarchs.def
gcc/config/m68k/genopt.sh
gcc/config/mips/mips-tables.opt: gcc/config/mips/mips-cpus.def
gcc/config/mips/genopt.sh
gcc/config/rs6000/rs6000-tables.opt: gcc/config/rs6000/rs6000-cpus.def
gcc/config/rs6000/genopt.sh
+gcc/config/rs6000/integer.md: gcc/config/rs6000/integer.mdm
gcc/config/rs6000/mdm.pl
gcc/config/tilegx/mul-tables.c: gcc/config/tilepro/gen-mul-tables.cc
gcc/config/tilepro/mul-tables.c: gcc/config/tilepro/gen-mul-tables.cc
# And then, language-specific files
diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md
new file mode 100644
index 000..780e418
--- /dev/null
+++ b/gcc/config/rs6000/integer.md
@@ -0,0 +1,145 @@
+; Generated by mdm.pl; do not edit (edit the .mdm instead).
+; vi:ro
+
+
+; Copyright (C) 1990-2013 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published
+; by the Free Software Foundation; either version 3, or (at your
+; option) any later version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT
+; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+; License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+;
[PATCH v2 2/6] rs6000: dot for lshrsi3
This moves lshrsi3 over and merges it with lshrdi3. The immediate version is split off since it needs a different condition (and is a separate instruction anyway). Tested as per usual; okay? 2013-06-03 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (lshrsi3): Delete. * config/rs6000/integer.mdm: (lshrdi3): Delete. (lshr3, lshr3_imm): New. * config/rs6000/integer.md: Regenerate. --- gcc/config/rs6000/integer.md | 178 ++ gcc/config/rs6000/integer.mdm | 28 --- gcc/config/rs6000/rs6000.md | 75 -- 3 files changed, 144 insertions(+), 137 deletions(-) diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md index 780e418..2ffe991 100644 --- a/gcc/config/rs6000/integer.md +++ b/gcc/config/rs6000/integer.md @@ -32,87 +32,161 @@ ; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.] -(define_insn "lshrdi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") -(match_operand:SI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" +(define_insn "lshr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "sr %0,%1,%2" + [(set_attr "type" "var_shift_rotate")]) + +(define_insn "*lshr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - srd %0,%1,%2 - srdi %0,%1,%H2" - [(set_attr "type" "var_shift_rotate,shift")]) + sr. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "(mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshr3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" + "@ + sr. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (lshiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (lshiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshr3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "sri %0,%1,%2" + [(set_attr "type" "shift")]) -(define_insn "*lshrdi3_dot" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") +(define_insn "*lshr3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC - (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") -(match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (const_int 0))) - (clobber (match_scratch:DI 0 "=r,r,r,r"))] - "(TARGET_POWERPC64) - && (DImode == Pmode && rs6000_gen_cell_microcode)" + (clobber (match_scratch:GPR 0 "=r,r"))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || (mode == SImode && UINTVAL (operands[2]))) + && rs6000_gen_cell_microcode)" "@ - srd. %0,%1,%2 - srdi. %0,%1,
[PATCH v2 0/6] define_dot_insn
David alerted me to the proper way to ensure generated files will not be regenerated for end-users. I also cleaned up some whitespace/comment churn; and there was an embarrassing bug in the dot condition for sri, for -m32 -mpowerpc64. So, v2. Bootstrapped and tested these six together, no regressions. I also checked that gcc_update change does in fact work (and it indeed does). Segher contrib/gcc_update| 1 + gcc/config/rs6000/40x.md | 12 +- gcc/config/rs6000/440.md | 6 +- gcc/config/rs6000/476.md | 10 +- gcc/config/rs6000/601.md | 11 +- gcc/config/rs6000/603.md | 12 +- gcc/config/rs6000/6xx.md | 12 +- gcc/config/rs6000/7450.md | 12 +- gcc/config/rs6000/7xx.md | 12 +- gcc/config/rs6000/cell.md | 25 +- gcc/config/rs6000/e500mc64.md | 2 +- gcc/config/rs6000/integer.md | 531 ++ gcc/config/rs6000/integer.mdm | 110 + gcc/config/rs6000/mdm.pl | 470 + gcc/config/rs6000/mpc.md | 12 +- gcc/config/rs6000/power4.md | 9 +- gcc/config/rs6000/power5.md | 9 +- gcc/config/rs6000/power6.md | 10 +- gcc/config/rs6000/power7.md | 10 +- gcc/config/rs6000/rs6000.c| 8 + gcc/config/rs6000/rs6000.md | 505 +-- gcc/config/rs6000/rs64.md | 12 +- gcc/config/rs6000/t-rs6000| 6 + gcc/config/rs6000/titan.md| 4 +- 24 files changed, 1251 insertions(+), 560 deletions(-) create mode 100644 gcc/config/rs6000/integer.md create mode 100644 gcc/config/rs6000/integer.mdm create mode 100755 gcc/config/rs6000/mdm.pl -- 1.8.1.4
[PATCH v2 4/6] rs6000: dot for var_shift_rotate/var_delayed_compare
This changes all scheduling descriptions to treat insn type var_shift_rotate with dot=yes the same as var_delayed_compare is treated, and to require dot=no for var_shift_rotate that already was handled. 2013-06-03 Segher Boessenkool gcc/ * config/rs6000/40x.md: Require dot=no for type=var_shift_rotate; where type=var_delayed_compare, also handle type=var_shift_rotate dot=yes. * config/rs6000/440.md: Ditto. * config/rs6000/476.md: Ditto. * config/rs6000/601.md: Ditto. * config/rs6000/603.md: Ditto. * config/rs6000/6xx.md: Ditto. * config/rs6000/7450.md: Ditto. * config/rs6000/7xx.md: Ditto. * config/rs6000/cell.md: Ditto. * config/rs6000/mpc.md: Ditto. * config/rs6000/power4.md: Ditto. * config/rs6000/power5.md: Ditto. * config/rs6000/power6.md: Ditto. * config/rs6000/power7.md: Ditto. * config/rs6000/rs64.md: Ditto. * config/rs6000/titan.md: Ditto. * config/rs6000/rs6000.c (is_cracked_insn): Add missing TYPE_VAR_DELAYED_COMPARE case. Also handle TYPE_VAR_SHIFT_ROTATE. (insn_must_be_first_in_group): Add missing TYPE_VAR_DELAYED_COMPARE case. (insn_must_be_last_in_group): Ditto. --- gcc/config/rs6000/40x.md| 12 gcc/config/rs6000/440.md| 6 -- gcc/config/rs6000/476.md| 10 +++--- gcc/config/rs6000/601.md| 11 +++ gcc/config/rs6000/603.md| 12 gcc/config/rs6000/6xx.md| 12 gcc/config/rs6000/7450.md | 12 gcc/config/rs6000/7xx.md| 12 gcc/config/rs6000/cell.md | 25 +++-- gcc/config/rs6000/mpc.md| 12 gcc/config/rs6000/power4.md | 9 ++--- gcc/config/rs6000/power5.md | 10 +++--- gcc/config/rs6000/power6.md | 5 - gcc/config/rs6000/power7.md | 10 +++--- gcc/config/rs6000/rs6000.c | 5 + gcc/config/rs6000/rs64.md | 12 gcc/config/rs6000/titan.md | 4 +++- 17 files changed, 121 insertions(+), 58 deletions(-) diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index ab0cf06..2054e65 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -37,8 +37,10 @@ (define_insn_reservation "ppc403-store" 2 "iu_40x") (define_insn_reservation "ppc403-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ -var_shift_rotate,cntlz,exts,isel") + (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + cntlz,exts,isel") +(and (eq_attr "type" "var_shift_rotate") + (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc403,ppc405")) "iu_40x") @@ -53,8 +55,10 @@ (define_insn_reservation "ppc403-three" 1 "iu_40x,iu_40x,iu_40x") (define_insn_reservation "ppc403-compare" 3 - (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ -var_delayed_compare") + (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ + var_delayed_compare") +(and (eq_attr "type" "var_shift_rotate") + (eq_attr "dot" "yes"))) (eq_attr "cpu" "ppc403,ppc405")) "iu_40x,nothing,bpu_40x") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index fe70be0..b4abab5 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -54,8 +54,10 @@ (define_insn_reservation "ppc440-fpstore" 3 "ppc440_issue,ppc440_l_pipe") (define_insn_reservation "ppc440-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ -trap,var_shift_rotate,cntlz,exts,isel") + (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\ + trap,cntlz,exts,isel") +(and (eq_attr "type" "var_shift_rotate") + (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 4254659..5448ab2 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -64,7 +64,9 @@ (define_insn_reservation "ppc476-fpstore" 4 ppc476_lj_pipe") (define_insn_reservation "ppc476-simple-integer" 1 - (and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift") + (and (ior (eq_attr "type" "integer,insert_word,exts,shift") +(and (eq_attr "type" "var_shift_rotate") + (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc476")) "ppc476_issue,\ ppc476_i_pipe|ppc476_lj_pipe") @@ -76,8 +78,10 @@ (define_insn_reservation "ppc476-complex-integer" 1 ppc476_i_pipe") (define_insn_reservation "ppc476-compare" 4 - (and (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\ -mtcr,mfjmpr,mtjmpr,var_delayed_compare") + (and (ior (eq_attr "typ
[PATCH v2 3/6] dot for ashl3
Similar to lshr, for ashl. Okay? 2013-06-03 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (ashlsi3, ashldi3_internal1, ashldi3_internal2, ashldi3_internal3): Delete. * config/rs6000/integer.mdm (ashl3, ashl3_imm): New. * config/rs6000/integer.md: Regenerate. --- gcc/config/rs6000/integer.md | 156 ++ gcc/config/rs6000/integer.mdm | 18 + gcc/config/rs6000/rs6000.md | 147 --- 3 files changed, 174 insertions(+), 147 deletions(-) diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md index 2ffe991..b075166 100644 --- a/gcc/config/rs6000/integer.md +++ b/gcc/config/rs6000/integer.md @@ -32,6 +32,162 @@ ; slw[.], srw[.], srawi[.], sraw[.], sld[.], srd[.], sradi[.], srad[.] +(define_insn "ashl3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "sl %0,%1,%2" + [(set_attr "type" "var_shift_rotate")]) + +(define_insn "*ashl3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" + "@ + sl. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "(mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (ashift:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashl3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (ashift:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" + "@ + sl. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashift:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (ashift:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashl3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "sli %0,%1,%2" + [(set_attr "type" "shift")]) + +(define_insn "*ashl3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && (mode == Pmode && rs6000_gen_cell_microcode)" + "@ + sli. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && (mode == Pmode && rs6000_gen_cell_microcode)) + && (reload_completed)" + [(set (match_dup 0) + (ashift:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashl3_imm_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") +
[PATCH v2 5/6] rs6000: dot for shift/delayed_compare
Similar, but now for shift and delayed_compare. 2013-06-03 Segher Boessenkool gcc/ * config/rs6000/40x.md: Require dot=no for type=shift; where type=delayed_compare, also handle type=shift dot=yes. * config/rs6000/440.md: Ditto. * config/rs6000/476.md: Ditto. * config/rs6000/601.md: Ditto. * config/rs6000/603.md: Ditto. * config/rs6000/6xx.md: Ditto. * config/rs6000/7450.md: Ditto. * config/rs6000/7xx.md: Ditto. * config/rs6000/cell.md: Ditto. * config/rs6000/mpc.md: Ditto. * config/rs6000/power4.md: Ditto. * config/rs6000/power5.md: Ditto. * config/rs6000/power6.md: Ditto. * config/rs6000/power7.md: Ditto. * config/rs6000/rs64.md: Ditto. * config/rs6000/titan.md: Ditto. * config/rs6000/rs6000.c (rs6000_adjust_cost): Add missing TYPE_DELAYED_COMPARE case, twice. (is_cracked_insn): Handle TYPE_SHIFT. --- gcc/config/rs6000/40x.md | 6 +++--- gcc/config/rs6000/440.md | 4 ++-- gcc/config/rs6000/476.md | 6 +++--- gcc/config/rs6000/601.md | 6 +++--- gcc/config/rs6000/603.md | 6 +++--- gcc/config/rs6000/6xx.md | 6 +++--- gcc/config/rs6000/7450.md | 6 +++--- gcc/config/rs6000/7xx.md | 6 +++--- gcc/config/rs6000/cell.md | 8 gcc/config/rs6000/e500mc64.md | 2 +- gcc/config/rs6000/mpc.md | 6 +++--- gcc/config/rs6000/power4.md | 6 +++--- gcc/config/rs6000/power5.md | 7 +++ gcc/config/rs6000/power6.md | 5 - gcc/config/rs6000/power7.md | 6 +++--- gcc/config/rs6000/rs6000.c| 5 - gcc/config/rs6000/rs64.md | 8 gcc/config/rs6000/titan.md| 4 ++-- 18 files changed, 54 insertions(+), 49 deletions(-) diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index 2054e65..ddd0c21 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -37,9 +37,9 @@ (define_insn_reservation "ppc403-store" 2 "iu_40x") (define_insn_reservation "ppc403-integer" 1 - (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (ior (eq_attr "type" "integer,insert_word,insert_dword,trap,\ cntlz,exts,isel") -(and (eq_attr "type" "var_shift_rotate") +(and (eq_attr "type" "shift,var_shift_rotate") (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc403,ppc405")) "iu_40x") @@ -57,7 +57,7 @@ (define_insn_reservation "ppc403-three" 1 (define_insn_reservation "ppc403-compare" 3 (and (ior (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ var_delayed_compare") -(and (eq_attr "type" "var_shift_rotate") +(and (eq_attr "type" "shift,var_shift_rotate") (eq_attr "dot" "yes"))) (eq_attr "cpu" "ppc403,ppc405")) "iu_40x,nothing,bpu_40x") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index b4abab5..8c18cde 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -54,9 +54,9 @@ (define_insn_reservation "ppc440-fpstore" 3 "ppc440_issue,ppc440_l_pipe") (define_insn_reservation "ppc440-integer" 1 - (and (ior (eq_attr "type" "integer,insert_word,insert_dword,shift,\ + (and (ior (eq_attr "type" "integer,insert_word,insert_dword,\ trap,cntlz,exts,isel") -(and (eq_attr "type" "var_shift_rotate") +(and (eq_attr "type" "shift,var_shift_rotate") (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 5448ab2..d68f1a4 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -64,8 +64,8 @@ (define_insn_reservation "ppc476-fpstore" 4 ppc476_lj_pipe") (define_insn_reservation "ppc476-simple-integer" 1 - (and (ior (eq_attr "type" "integer,insert_word,exts,shift") -(and (eq_attr "type" "var_shift_rotate") + (and (ior (eq_attr "type" "integer,insert_word,exts") +(and (eq_attr "type" "shift,var_shift_rotate") (eq_attr "dot" "no"))) (eq_attr "cpu" "ppc476")) "ppc476_issue,\ @@ -80,7 +80,7 @@ (define_insn_reservation "ppc476-complex-integer" 1 (define_insn_reservation "ppc476-compare" 4 (and (ior (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\ mtcr,mfjmpr,mtjmpr,var_delayed_compare") -(and (eq_attr "type" "var_shift_rotate") +(and (eq_attr "type" "shift,var_shift_rotate") (eq_attr "dot" "yes"))) (eq_attr "cpu" "ppc476")) "ppc476_issue,\ diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index 4a7dc3f..06b060f 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -46,9 +46,9 @@ (define_insn_reservation "ppc601-fpstore" 3 "iu_ppc601+fpu_ppc601") (defin
[PATCH v2 6/6] rs6000: dot for ashiftrt
Last for now: move ashiftrt to integer.mdm. 2013-06-03 Segher Boessenkool gcc/ * config/rs6000/rs6000.md (ashrsi3, ashrdi3_no_power, ashrdisi3_noppc64be, ashrdi3, ashrdi3_internal1, ashrdi3_internal2, ashrdi3_internal3): Delete. (ashr3, ashr3_imm): New. * config/rs6000/integer.md: Regenerate. --- gcc/config/rs6000/integer.md | 156 gcc/config/rs6000/integer.mdm | 18 gcc/config/rs6000/rs6000.md | 201 -- 3 files changed, 174 insertions(+), 201 deletions(-) diff --git a/gcc/config/rs6000/integer.md b/gcc/config/rs6000/integer.md index b075166..90c6632 100644 --- a/gcc/config/rs6000/integer.md +++ b/gcc/config/rs6000/integer.md @@ -348,6 +348,162 @@ (define_split (const_int 0)))] "") +(define_insn "ashr3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")))] + "" + "sra %0,%1,%2" + [(set_attr "type" "var_shift_rotate")]) + +(define_insn "*ashr3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "(mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode" + "@ + sra. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashr3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode" + "@ + sra. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "var_shift_rotate")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:GPR 0 "gpc_reg_operand" "") + (ashiftrt:GPR (match_dup 1) + (match_dup 2)))] + "((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*ashr3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")))] + "UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)" + "srai %0,%1,%2" + [(set_attr "type" "shift")]) + +(define_insn "*ashr3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) + (const_int 0))) + (clobber (match_scratch:GPR 0 "=r,r"))] + "(UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode)" + "@ + srai. %0,%1,%2 + #" + [(set_attr "length" "4,8") + (set_attr "dot" "yes,no") + (set_attr "type" "shift")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC + (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) + (const_int 0))) + (clobber (match_scratch:GPR 0 ""))] + "((UINTVAL (operands[2]) < GET_MODE_BITSIZE (mode)) + && ((mode == Pmode || mode == SImode) && rs6000_gen_cell_microcode)) + && (reload_completed)" + [(set (match_dup 0) + (ashiftrt:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))]
[AArch64, PATCH 1/5] Improve MOVI handling (Change interface of aarch64_simd_valid_immediate)
(This patch is the first of five, where the first 4 do some clean-up and the last fixes a bug with scalar MOVI. The bug fix without the clean-up was particularly ugly!) This one is pretty simple - just altering an interface, so we can later remove an unnecessary wrapper function. OK for trunk? Cheers, Ian 13-06-03 Ian Bolton * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Change return type to bool for prototype. (aarch64_legitimate_constant_p): Check for true instead of not -1. (aarch64_simd_valid_immediate): Fix up each return to return a bool. (aarch64_simd_immediate_valid_for_move): Update retval for bool.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 12a7055..05ff5fa 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -103,7 +103,7 @@ static bool aarch64_vfp_is_call_or_return_candidate (enum machine_mode, static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_override_options_after_change (void); -static int aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *, +static bool aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *, int *, unsigned char *, int *, int *); static bool aarch64_vector_mode_supported_p (enum machine_mode); static unsigned bit_count (unsigned HOST_WIDE_INT); @@ -5153,7 +5153,7 @@ aarch64_legitimate_constant_p (enum machine_mode mode, rtx x) we now decompose CONST_INTs according to expand_mov_immediate. */ if ((GET_CODE (x) == CONST_VECTOR && aarch64_simd_valid_immediate (x, mode, false, - NULL, NULL, NULL, NULL, NULL) != -1) + NULL, NULL, NULL, NULL, NULL)) || CONST_INT_P (x) || aarch64_valid_floating_const (mode, x)) return !targetm.cannot_force_const_mem (mode, x); @@ -6144,11 +6144,8 @@ aarch64_vect_float_const_representable_p (rtx x) return aarch64_float_const_representable_p (x0); } -/* TODO: This function returns values similar to those - returned by neon_valid_immediate in gcc/config/arm/arm.c - but the API here is different enough that these magic numbers - are not used. It should be sufficient to return true or false. */ -static int +/* Return true for valid and false for invalid. */ +static bool aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, rtx *modconst, int *elementwidth, unsigned char *elementchar, @@ -6184,24 +6181,21 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, if (!(simd_imm_zero || aarch64_vect_float_const_representable_p (op))) - return -1; + return false; - if (modconst) - *modconst = CONST_VECTOR_ELT (op, 0); + if (modconst) + *modconst = CONST_VECTOR_ELT (op, 0); - if (elementwidth) - *elementwidth = elem_width; + if (elementwidth) + *elementwidth = elem_width; - if (elementchar) - *elementchar = sizetochar (elem_width); + if (elementchar) + *elementchar = sizetochar (elem_width); - if (shift) - *shift = 0; + if (shift) + *shift = 0; - if (simd_imm_zero) - return 19; - else - return 18; + return true; } /* Splat vector constant out into a byte vector. */ @@ -6299,7 +6293,7 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, if (immtype == -1 || (immtype >= 12 && immtype <= 15) || immtype == 18) -return -1; +return false; if (elementwidth) @@ -6351,7 +6345,7 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse, } } - return immtype; + return (immtype >= 0); #undef CHECK } @@ -6369,11 +6363,11 @@ aarch64_simd_immediate_valid_for_move (rtx op, enum machine_mode mode, int tmpwidth; unsigned char tmpwidthc; int tmpmvn = 0, tmpshift = 0; - int retval = aarch64_simd_valid_immediate (op, mode, 0, &tmpconst, + bool retval = aarch64_simd_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth, &tmpwidthc, &tmpmvn, &tmpshift); - if (retval == -1) + if (!retval) return 0; if (modconst)
[AArch64, PATCH 3/5] Improve MOVI handling (Don't update RTX operand in-place)
(This patch is the third of five, where the first 4 do some clean-up and
the last fixes a bug with scalar MOVI. The bug fix without the clean-up
was particularly ugly!)
This one is focused on cleaning up aarch64_simd_valid_immediate, with
better use of arguments and no in-place modification of RTX operands.
Specifically, I've changed the set of pointers that are passed in
(it's now a struct) and the caller prints out the immediate value
directly instead of letting operand[1] get fudged.
OK for trunk?
Cheers,
Ian
2013-06-03 Ian Bolton
* config/aarch64/aarch64.c (simd_immediate_info): Struct to hold
information completed by aarch64_simd_valid_immediate.
(aarch64_legitimate_constant_p): Update arguments.
(aarch64_simd_valid_immediate): Work with struct rather than many
pointers.
(aarch64_simd_scalar_immediate_valid_for_move): Update arguments.
(aarch64_simd_make_constant): Update arguments.
(aarch64_output_simd_mov_immediate): Work with struct rather than
many pointers. Output immediate directly rather than as operand.
* config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate):
Update prototype.
* config/aarch64/constraints.md (Dn): Update arguments.diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index d1de14e..083ce91 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -156,8 +156,8 @@ bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode
mode);
bool aarch64_simd_imm_zero_p (rtx, enum machine_mode);
bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode);
bool aarch64_simd_shift_imm_p (rtx, enum machine_mode, bool);
-bool aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *,
- int *, unsigned char *, int *, int *);
+bool aarch64_simd_valid_immediate (rtx, enum machine_mode, bool,
+ struct simd_immediate_info *);
bool aarch64_symbolic_address_p (rtx);
bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context,
enum aarch64_symbol_type *);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5f97efe..d83e645 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -87,6 +87,14 @@ struct aarch64_address_info {
enum aarch64_symbol_type symbol_type;
};
+struct simd_immediate_info {
+ rtx value;
+ int shift;
+ int element_width;
+ unsigned char element_char;
+ bool mvn;
+};
+
/* The current code model. */
enum aarch64_code_model aarch64_cmodel;
@@ -5150,8 +5158,7 @@ aarch64_legitimate_constant_p (enum machine_mode mode,
rtx x)
/* This could probably go away because
we now decompose CONST_INTs according to expand_mov_immediate. */
if ((GET_CODE (x) == CONST_VECTOR
- && aarch64_simd_valid_immediate (x, mode, false,
- NULL, NULL, NULL, NULL, NULL))
+ && aarch64_simd_valid_immediate (x, mode, false, NULL))
|| CONST_INT_P (x) || aarch64_valid_floating_const (mode, x))
return !targetm.cannot_force_const_mem (mode, x);
@@ -6144,10 +6151,8 @@ aarch64_vect_float_const_representable_p (rtx x)
/* Return true for valid and false for invalid. */
bool
-aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse,
- rtx *modconst, int *elementwidth,
- unsigned char *elementchar,
- int *mvn, int *shift)
+aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse,
+ struct simd_immediate_info *info)
{
#define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
matches = 1; \
@@ -6181,17 +6186,14 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode
mode, int inverse,
|| aarch64_vect_float_const_representable_p (op)))
return false;
- if (modconst)
- *modconst = CONST_VECTOR_ELT (op, 0);
-
- if (elementwidth)
- *elementwidth = elem_width;
-
- if (elementchar)
- *elementchar = sizetochar (elem_width);
-
- if (shift)
- *shift = 0;
+ if (info)
+ {
+ info->value = CONST_VECTOR_ELT (op, 0);
+ info->element_width = elem_width;
+ info->element_char = sizetochar (elem_width);
+ info->mvn = false;
+ info->shift = 0;
+ }
return true;
}
@@ -6293,21 +6295,13 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode
mode, int inverse,
|| immtype == 18)
return false;
-
- if (elementwidth)
-*elementwidth = elsize;
-
- if (elementchar)
-*elementchar = elchar;
-
- if (mvn)
-*mvn = emvn;
-
- if (shift)
-*shift = eshift;
-
- if (modconst)
+ if (info)
{
+ info->element_width = elsize;
+ info-
[AArch64, PATCH 2/5] Improve MOVI handling (Remove wrapper function)
(This patch is the second of five, where the first 4 do some clean-up and
the last fixes a bug with scalar MOVI. The bug fix without the clean-up
was particularly ugly!)
This one is also very simple - removing a wrapper function that was an
unnecessary level of indirection.
OK for trunk?
Cheers,
Ian
13-06-03 Ian Bolton
* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): No
longer static.
(aarch64_simd_immediate_valid_for_move): Remove.
(aarch64_simd_scalar_immediate_valid_for_move): Update call.
(aarch64_simd_make_constant): Update call.
(aarch64_output_simd_mov_immediate): Update call.
* config/aarch64/aarch64-protos.h (aarch64_simd_valid_immediate):
Add prototype.
* config/aarch64/constraints.md (Dn): Update call.diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index 91fcde8..d1de14e 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -156,6 +156,8 @@ bool aarch64_simd_imm_scalar_p (rtx x, enum machine_mode
mode);
bool aarch64_simd_imm_zero_p (rtx, enum machine_mode);
bool aarch64_simd_scalar_immediate_valid_for_move (rtx, enum machine_mode);
bool aarch64_simd_shift_imm_p (rtx, enum machine_mode, bool);
+bool aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *,
+ int *, unsigned char *, int *, int *);
bool aarch64_symbolic_address_p (rtx);
bool aarch64_symbolic_constant_p (rtx, enum aarch64_symbol_context,
enum aarch64_symbol_type *);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 05ff5fa..aec59b0 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -103,8 +103,6 @@ static bool aarch64_vfp_is_call_or_return_candidate (enum
machine_mode,
static void aarch64_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
static void aarch64_override_options_after_change (void);
-static bool aarch64_simd_valid_immediate (rtx, enum machine_mode, int, rtx *,
-int *, unsigned char *, int *, int *);
static bool aarch64_vector_mode_supported_p (enum machine_mode);
static unsigned bit_count (unsigned HOST_WIDE_INT);
static bool aarch64_const_vec_all_same_int_p (rtx,
@@ -6145,7 +6143,7 @@ aarch64_vect_float_const_representable_p (rtx x)
}
/* Return true for valid and false for invalid. */
-static bool
+bool
aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, int inverse,
rtx *modconst, int *elementwidth,
unsigned char *elementchar,
@@ -6349,45 +6347,6 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode
mode, int inverse,
#undef CHECK
}
-/* Return TRUE if rtx X is legal for use as either a AdvSIMD MOVI instruction
- (or, implicitly, MVNI) immediate. Write back width per element
- to *ELEMENTWIDTH, and a modified constant (whatever should be output
- for a MOVI instruction) in *MODCONST. */
-int
-aarch64_simd_immediate_valid_for_move (rtx op, enum machine_mode mode,
- rtx *modconst, int *elementwidth,
- unsigned char *elementchar,
- int *mvn, int *shift)
-{
- rtx tmpconst;
- int tmpwidth;
- unsigned char tmpwidthc;
- int tmpmvn = 0, tmpshift = 0;
- bool retval = aarch64_simd_valid_immediate (op, mode, 0, &tmpconst,
-&tmpwidth, &tmpwidthc,
-&tmpmvn, &tmpshift);
-
- if (!retval)
-return 0;
-
- if (modconst)
-*modconst = tmpconst;
-
- if (elementwidth)
-*elementwidth = tmpwidth;
-
- if (elementchar)
-*elementchar = tmpwidthc;
-
- if (mvn)
-*mvn = tmpmvn;
-
- if (shift)
-*shift = tmpshift;
-
- return 1;
-}
-
static bool
aarch64_const_vec_all_same_int_p (rtx x,
HOST_WIDE_INT minval,
@@ -6492,9 +6451,8 @@ aarch64_simd_scalar_immediate_valid_for_move (rtx op,
enum machine_mode mode)
gcc_assert (!VECTOR_MODE_P (mode));
vmode = aarch64_preferred_simd_mode (mode);
rtx op_v = aarch64_simd_gen_const_vector_dup (vmode, INTVAL (op));
- int retval = aarch64_simd_immediate_valid_for_move (op_v, vmode, 0,
- NULL, NULL, NULL, NULL);
- return retval;
+ return aarch64_simd_valid_immediate (op_v, vmode, 0, NULL,
+ NULL, NULL, NULL, NULL);
}
/* Construct and return a PARALLEL RTX vector. */
@@ -6722,8 +6680,8 @@ aarch64_simd_make_constant (rtx vals)
gcc_unreachable ();
if (const_vec != NULL_RTX
- && aarch64_simd_immediate_valid_for_move (const_vec, mode, NULL, NULL,
- NULL, NULL, NULL))
+ && aarch64
[AArch64, PATCH 4/5] Improve MOVI handling (Other minor clean-up)
(This patch is the fourth of five, where the first 4 do some clean-up and
the last fixes a bug with scalar MOVI. The bug fix without the clean-up
was particularly ugly!)
I think the changelog says it all here. Nothing major, just tidying up.
OK for trunk?
Cheers,
Ian
2013-06-03 Ian Bolton
* config/aarch64/aarch64.c (simd_immediate_info): Remove
element_char member.
(sizetochar): Return signed char.
(aarch64_simd_valid_immediate): Remove elchar and other
unnecessary variables.
(aarch64_output_simd_mov_immediate): Take rtx instead of &rtx.
Calculate element_char as required.
* config/aarch64/aarch64-protos.h: Update and move prototype
for aarch64_output_simd_mov_immediate.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov):
Update arguments.diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index 083ce91..d21a2f5 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -148,6 +148,7 @@ bool aarch64_legitimate_pic_operand_p (rtx);
bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
enum machine_mode);
+char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool);
bool aarch64_regno_ok_for_base_p (int, bool);
@@ -258,6 +259,4 @@ extern void aarch64_split_combinev16qi (rtx operands[3]);
extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
extern bool
aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
-
-char* aarch64_output_simd_mov_immediate (rtx *, enum machine_mode, unsigned);
#endif /* GCC_AARCH64_PROTOS_H */
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index 04fbdbd..e5990d4 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -409,7 +409,7 @@
case 4: return "ins\t%0.d[0], %1";
case 5: return "mov\t%0, %1";
case 6:
- return aarch64_output_simd_mov_immediate (&operands[1],
+ return aarch64_output_simd_mov_immediate (operands[1],
mode, 64);
default: gcc_unreachable ();
}
@@ -440,7 +440,7 @@
case 5:
return "#";
case 6:
- return aarch64_output_simd_mov_immediate (&operands[1], mode,
128);
+ return aarch64_output_simd_mov_immediate (operands[1], mode, 128);
default:
gcc_unreachable ();
}
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index d83e645..001f9c5 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -91,7 +91,6 @@ struct simd_immediate_info {
rtx value;
int shift;
int element_width;
- unsigned char element_char;
bool mvn;
};
@@ -6102,7 +6101,7 @@ aarch64_mangle_type (const_tree type)
}
/* Return the equivalent letter for size. */
-static unsigned char
+static char
sizetochar (int size)
{
switch (size)
@@ -6163,7 +6162,6 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode
mode, bool inverse,
{ \
immtype = (CLASS); \
elsize = (ELSIZE); \
- elchar = sizetochar (elsize);\
eshift = (SHIFT);\
emvn = (NEG);\
break; \
@@ -6172,25 +6170,20 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode
mode, bool inverse,
unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op);
unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
unsigned char bytes[16];
- unsigned char elchar = 0;
int immtype = -1, matches;
unsigned int invmask = inverse ? 0xff : 0;
int eshift, emvn;
if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
{
- bool simd_imm_zero = aarch64_simd_imm_zero_p (op, mode);
- int elem_width = GET_MODE_BITSIZE (GET_MODE (CONST_VECTOR_ELT (op, 0)));
-
- if (!(simd_imm_zero
- || aarch64_vect_float_const_representable_p (op)))
+ if (! (aarch64_simd_imm_zero_p (op, mode)
+|| aarch64_vect_float_const_representable_p (op)))
return false;
if (info)
{
info->value = CONST_VECTOR_ELT (op, 0);
- info->element_width = elem_width;
- info->element_char = sizetochar (elem_width);
+ info->element_width = GET_MODE_BITSIZE (GET_MODE (info->value));
info->mvn = false;
info->shift = 0;
}
@@ -6298,7 +6291,6 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode
mode, bool inverse,
if (info)
{
[AArch64, PATCH 5/5] Improve MOVI handling (Fix invalid assembler bug)
(This patch is the last of five, where the first 4 did some clean-up and
this one fixes a bug with scalar MOVI. The bug fix without the clean-up
was particularly ugly!)
GCC will currently generator invalid assembler for MOVI, if the
value in question needs to be shifted.
For example:
prog.s:270: Error: immediate value out of range -128 to 255
at operand 2 -- `movi v16.4h,1024'
The correct assembler for the example should be:
movi v16.4h, 0x4, lsl 8
The fix involves calling into a function to output the instruction,
rather than just leaving for aarch64_print_operand, as is done for
vector immediates.
Regression runs have passed for Linux and bare-metal.
OK for trunk?
Cheers,
Ian
2013-06-03 Ian Bolton
gcc/
* config/aarch64/aarch64.md (*mov_aarch64): Call
into function to generate MOVI instruction.
* config/aarch64/aarch64.c (aarch64_simd_container_mode):
New function.
(aarch64_preferred_simd_mode): Turn into wrapper.
(aarch64_output_scalar_simd_mov_immediate): New function.
* config/aarch64/aarch64-protos.h: Add prototype for above.
testsuite/
* gcc.target/aarch64/movi_1.c: New test.
diff --git a/gcc/config/aarch64/aarch64-protos.h
b/gcc/config/aarch64/aarch64-protos.h
index d21a2f5..0dface1 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -148,6 +148,7 @@ bool aarch64_legitimate_pic_operand_p (rtx);
bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
enum machine_mode);
+char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode);
char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
bool aarch64_pad_reg_upward (enum machine_mode, const_tree, bool);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 001f9c5..0ea05d8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -5988,32 +5988,57 @@ aarch64_vector_mode_supported_p (enum machine_mode mode)
return false;
}
-/* Return quad mode as the preferred SIMD mode. */
+/* Return appropriate SIMD container
+ for MODE within a vector of WIDTH bits. */
static enum machine_mode
-aarch64_preferred_simd_mode (enum machine_mode mode)
+aarch64_simd_container_mode (enum machine_mode mode, unsigned width)
{
+ gcc_assert (width == 64 || width == 128);
if (TARGET_SIMD)
-switch (mode)
- {
- case DFmode:
-return V2DFmode;
- case SFmode:
-return V4SFmode;
- case SImode:
-return V4SImode;
- case HImode:
-return V8HImode;
- case QImode:
-return V16QImode;
- case DImode:
- return V2DImode;
-break;
-
- default:;
- }
+{
+ if (width == 128)
+ switch (mode)
+ {
+ case DFmode:
+ return V2DFmode;
+ case SFmode:
+ return V4SFmode;
+ case SImode:
+ return V4SImode;
+ case HImode:
+ return V8HImode;
+ case QImode:
+ return V16QImode;
+ case DImode:
+ return V2DImode;
+ default:
+ break;
+ }
+ else
+ switch (mode)
+ {
+ case SFmode:
+ return V2SFmode;
+ case SImode:
+ return V2SImode;
+ case HImode:
+ return V4HImode;
+ case QImode:
+ return V8QImode;
+ default:
+ break;
+ }
+}
return word_mode;
}
+/* Return 128-bit container as the preferred SIMD mode for MODE. */
+static enum machine_mode
+aarch64_preferred_simd_mode (enum machine_mode mode)
+{
+ return aarch64_simd_container_mode (mode, 128);
+}
+
/* Return the bitmask of possible vector sizes for the vectorizer
to iterate over. */
static unsigned int
@@ -7280,6 +7305,18 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
return templ;
}
+char*
+aarch64_output_scalar_simd_mov_immediate (rtx immediate,
+ enum machine_mode mode)
+{
+ enum machine_mode vmode;
+
+ gcc_assert (!VECTOR_MODE_P (mode));
+ vmode = aarch64_simd_container_mode (mode, 64);
+ rtx v_op = aarch64_simd_gen_const_vector_dup (vmode, INTVAL (immediate));
+ return aarch64_output_simd_mov_immediate (v_op, vmode, 64);
+}
+
/* Split operands into moves from op[1] + op[2] into op[0]. */
void
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e1ec48f..458239e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -774,17 +774,34 @@
(match_operand:SHORT 1 "general_operand" " r,M,D,m,
m,rZ,*w,*w, r,*w"))]
"(register_operand (operands[0], mode)
|| aarch64_reg_or_zero (operands[1], mode))"
- "@
- mov\\t%w0, %w1
- mov\\t%w0, %1
- mov
Re: [PATCH] Improve folding of bitwise ops on booleans
2013/6/3 Jeff Law :
> The counter to that argument of leaving it to the backend to recover the
> and-not for is that the backend doesn't typically see these as single bit
> operations which makes turning the relational back into an and-not sequence
> considerably more difficult.
>
> Do we consider this enough of an issue to want to avoid going down this
> path? (in which case we'll file the example code as a missed-opt PR and
> attach the code and pointer to this thread for future reference)
>
Hmm, my tests are showing (for targets with conditional set
instructions) and improvement even for none-conditional-branch code.
Sample code:
_Bool foo (_Bool a, _Bool b)
{
_Bool r = a < b;
return r;
}
_Bool boo (_Bool a, _Bool b)
{
_Bool r = ~a & b;
return r;
}
produces:
.text
.p2align 4,,15
.globl foo
.deffoo;.scl2; .type 32; .endef
.seh_proc foo
foo:
.seh_endprologue
cmpb%cl, %dl
seta%al
ret
.seh_endproc
.p2align 4,,15
.globl boo
.defboo;.scl2; .type 32; .endef
.seh_proc boo
boo:
.seh_endprologue
movl%ecx, %eax
notl%eax
andl%edx, %eax
andl$1, %eax
ret
So it seems to be obvious that code gets much less costy as without
this optimization.
Kai
Re: [PATCH] Improve folding of bitwise ops on booleans
On 06/03/2013 02:24 AM, Richard Biener wrote:
On Fri, May 31, 2013 at 10:18 PM, Jeff Law wrote:
This is an implementation to fix a missed optimization pointed out to me by
Kai.
In all these examples, assume a & b are single bit types.
~a && b --> a < b
For a signed 1-bit type you'll have values -1, 0 and clearly
0 < -1
is false while ~0 & -1 is non-zero.
Sigh. Yes.
So I believe you have to restrict these transforms to signed 1-bit values
or adjust the folding appropriately. Besides that, ...
a && ~b --> b < a
~a || b --> a <= b
a && ~b --> b <= a
I wonder if these are really a simplification if the result is not used
exclusively in a conditional jump. Because for setting a register
to a < b you'll likely get worse code than using ~a & b (given that
many ISAs have a and-not instruction). Of course you may argue
that's a bug in the RTL / target piece (getting different code for
a < b vs. ~a & b) and a < b is shorter on the tree level.
The gimple optimizers should be looking to simplify things to the
fullest extent possible at the gimple level and let the backend make the
determination to use and-not if such an insn is available.
The counter to that argument of leaving it to the backend to recover the
and-not for is that the backend doesn't typically see these as single
bit operations which makes turning the relational back into an and-not
sequence considerably more difficult.
Do we consider this enough of an issue to want to avoid going down this
path? (in which case we'll file the example code as a missed-opt PR and
attach the code and pointer to this thread for future reference)
+static bool
+simplify_bitwise_binary_boolean (gimple_stmt_iterator *gsi,
+enum tree_code code,
+tree op0, tree op1)
+{
+ gimple op0_def_stmt = SSA_NAME_DEF_STMT (op0);
+
+ if (!is_gimple_assign (op0_def_stmt)
+ || (gimple_assign_rhs_code (op0_def_stmt) != BIT_NOT_EXPR))
+return false;
+
+ tree x = gimple_assign_rhs1 (op0_def_stmt);
+ if (TREE_CODE (x) == SSA_NAME
+ && INTEGRAL_TYPE_P (TREE_TYPE (x))
+ && TYPE_PRECISION (TREE_TYPE (x)) == 1)
Do these transforms not work for BOOLEAN_TYPE as well?
Yes. Booleans are integral types with a single bit of precision, right?
So this check should allow boolean types. What am I missing?
+{
+ gimple stmt = gsi_stmt (*gsi);
+ gimple_assign_set_rhs1 (stmt, x);
+ gimple_assign_set_rhs2 (stmt, op1);
+ gimple_assign_set_rhs_code (stmt, code == BIT_AND_EXPR ? LT_EXPR :
LE_EXPR);
+ update_stmt (gsi_stmt (*gsi));
No need to query gsi_stmt again, it cannot change.
I'd have to check on that; I think this was cribbed from another
transformation in tree-ssa-reassoc.
Re: [PATCH v2 0/6] define_dot_insn
On 06/03/2013 09:26 AM, Segher Boessenkool wrote: > David alerted me to the proper way to ensure generated files > will not be regenerated for end-users. I also cleaned up some > whitespace/comment churn; and there was an embarrassing bug in > the dot condition for sri, for -m32 -mpowerpc64. So, v2. Well, my first comment is that this is more or less exactly what we invented define_subst to attempt to handle. Could we have more constructive feedback on that mechanism rather than inventing a new mechanism private to the rs6000 backend? r~
Re: [PATCH, libcpp] Do not decrease highest_location if the included file has be included twice.
Hi, Dodji,
Thanks for looking into this.
The reason a test is missing is that it would need a super large
source file to reproduce the problem. However, if you apply the
attached patch, you can reproduce the problem with attached testcase:
g++ a.cpp -g -S -c -o a.s
in a.s, the linenos are off-by-one.
The root cause is that highest_location-- should not happen when the
header file is not gonna be read. In should_stack file, there is
following check:
/* Skip if the file had a header guard and the macro is defined.
PCH relies on this appearing before the PCH handler below. */
if (file->cmacro && file->cmacro->type == NT_MACRO)
return false;
Thus we should add it back to _cpp_stack_include too.
The problem was hidden when column number is used because
highest_location is updated in linemap_position_for_column. However,
when linemap are too large, it disables columns and do not update the
highest_location.
Dehao
Index: libcpp/line-map.c
===
--- libcpp/line-map.c (revision 199570)
+++ libcpp/line-map.c (working copy)
@@ -536,7 +536,7 @@ linemap_line_start (struct line_maps *set, linenum
if (add_map)
{
int column_bits;
- if (max_column_hint > 10 || highest > 0x6000)
+ if (1 || max_column_hint > 10 || highest > 0x6000)
{
/* If the column number is ridiculous or we've allocated a huge
number of source_locations, give up on column numbers. */
@@ -598,7 +598,7 @@ linemap_position_for_column (struct line_maps *set
if (to_column >= set->max_column_hint)
{
- if (r >= 0xC00 || to_column > 10)
+ if (1 || r >= 0xC00 || to_column > 10)
{
/* Running low on source_locations - disable column numbers. */
return r;
#include "inc_1.h"
#include "inc_2.h"
int main() {
foo();
boo();
return 0;
}
#ifndef _INC_1_H_
#define _INC_1_H_
#include "inc_2.h"
void foo (void);
#endif
#ifndef _INC_2_H_
#define _INC_2_H_
void boo (void);
#endif
Re: [PATCH] Improve folding of bitwise ops on booleans
On 06/03/2013 11:00 AM, Richard Henderson wrote: On 06/03/2013 09:37 AM, Kai Tietz wrote: foo: .seh_endprologue cmpb%cl, %dl seta%al ret .seh_endproc .p2align 4,,15 .globl boo .defboo;.scl2; .type 32; .endef .seh_proc boo boo: .seh_endprologue movl%ecx, %eax notl%eax andl%edx, %eax andl$1, %eax ret Try arm or s390 or ppc for significantly different results. I'm starting to wonder if we could delay make a choice about using a relational or bit ops until gimple->rtl expansion. I haven't seen any secondary benefits, so deferring to a later point where we might be able to query the backend's capabilities might make sense. jeff
Re: [PATCH] Improve folding of bitwise ops on booleans
On 06/03/2013 09:37 AM, Kai Tietz wrote: > foo: > .seh_endprologue > cmpb%cl, %dl > seta%al > ret > .seh_endproc > .p2align 4,,15 > .globl boo > .defboo;.scl2; .type 32; .endef > .seh_proc boo > boo: > .seh_endprologue > movl%ecx, %eax > notl%eax > andl%edx, %eax > andl$1, %eax > ret Try arm or s390 or ppc for significantly different results. r~
[Fortran-Dev] Merge trunk into the branch
I updated the branch to the trunk. Committed as 199612. Tobias
[PATCH] Handle MIPS EVA
Hi Richard, This is the gcc patch to handle the -meva option to gcc. Okay? Thanks, Catherine 2013-06-03 Catherine Moore gcc/ * config/mips/mips.opt (meva): New. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_eva. (ASM_SPEC): Handle -meva. gcc.eva.patch Description: gcc.eva.patch
Re: Fix PR57268
On 06/01/2013 06:55 AM, Jakub Jelinek wrote: On Sat, Jun 01, 2013 at 10:11:24AM +0200, Jakub Jelinek wrote: On Sat, Jun 01, 2013 at 08:39:58AM +0400, Dinar Temirbulatov wrote: I am investigating the problem. I'd guess you don't want to flush on DEBUG_INSN_Ps, because then you'd flush differently between -g and -g0. So perhaps something like: Now bootstrapped/regtested on x86_64-linux and i686-linux. I see you've already reverted in the mean time, so ok for trunk this way? 2013-06-01 Jakub Jelinek PR rtl-optimization/57268 * sched-deps.c (sched_analyze_2): Don't flush_pedning_lists if DEBUG_INSN_P (insn). Reapply 2013-05-31 Dinar Temirbulatov PR rtl-optimization/57268 * sched-deps.c (sched_analyze_2): Flush dependence lists if the sum of the read and write lists exceeds MAX_PENDING_LIST_LENGTH. Yes, this way is fine. jeff
Re: [PATCH] Basic support for MIPS r5900
On 06/02/2013 01:45 PM, "Jürgen Urban" wrote: Hello, after some months I reworked the patch for r5900. It would be nice if this could be accepted. The patch contains only changes to get basic support for MIPS r5900. It can be used to compile a working Linux kernel for the Playstation 2. It is also possible to get Linux programs working with software floating point and ABI o32. Other stuff like hardware floating point and ABI n32 is not fully supported yet. How much other changes will be currently accepted here? There is other stuff which I want to prepare and submit here, e.g.: 1. disable use of dmult and ddiv (ABI n32). 2. use trunc.w.s instead of cvt.w.s (to get single float working for normal range calculations; i.e. calculating without inf or nan). 3. fix use of ll/sc in libgomp, either increase mips ISA level or use syscall (which is broken in Linux 2.6.35.4). 4. fix libgcc to build a real muldi3 function for ABI n32 (not the multi3 function which is stored in muldi3.o file). 5. add support for configure parameters --float=single and --float=double in addition to --float=soft and --float=hard. 6. rework floating point to support single float with ABI n32 (either break the ABI or store floating point values in general purpose registers like soft float). 7. change libgcc or mips.md in way so that the non IEEE 754 compatible FPU of the r5900 gets compatible. I'd like those more regularly working on the MIPS backend to chime in on final approval. However, it looks reasonable to me. jeff
[patch, testsuite, cilk] Fix cilk tests for simulators
A number of the new cilk tests in gcc/testsuite/c-c++-common/cilk-plus/AN
fail for me when run via the gnu simulator on mips. The problem is that
the gnu simulator does not set up argc and argv. After asking in the gdb
mailing list I believe this is an issue for multiple simulators on multiple
platforms. Looking through the GCC testsuite I did not see any other tests
that looked at argc/argv so I would like to change these tests to not use
argc/argv either. In some tests I added a define (IN_GCC_TESTSUITE) that
I set to 1 and then don't check argc if this is set, in others I just used
the constant value 1 instead of using argc and in one (where argc was being
changed) I replaced the use of argc with a local variable.
Tested on mips-mti-elf with the GNU simulator.
OK to checkin?
2013-06-03 Steve Ellcey
* c-c++-common/cilk-plus/AN/array_test2.c: Do not check argc value.
* c-c++-common/cilk-plus/AN/array_test_ND.c: Ditto.
* c-c++-common/cilk-plus/AN/comma_exp.c: Ditto.
* c-c++-common/cilk-plus/AN/if_test.c: Ditto.
* c-c++-common/cilk-plus/AN/conditional.c: Replace argc with const 1.
* c-c++-common/cilk-plus/AN/sec_reduce_return.c: Ditto.
* c-c++-common/cilk-plus/AN/test_builtin_return.c: Ditto.
* c-c++-common/cilk-plus/AN/exec-once2.c: Replace argc with local var.
diff --git a/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test2.c
b/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test2.c
index bd7a4ad..178bba6 100644
--- a/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test2.c
+++ b/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test2.c
@@ -1,12 +1,12 @@
/* { dg-do run } */
-/* { dg-options "-fcilkplus" } */
+/* { dg-options "-fcilkplus -DIN_GCC_TESTSUITE=1" } */
#include
int main2(int argc, char **argv);
int main(int argc, char **argv)
{
int x = 0;
- if (argc == 1)
+ if (argc == 1 || IN_GCC_TESTSUITE)
{
const char *array[] = {"a.out", "5"};
x = main2 (2, (char **)array);
diff --git a/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test_ND.c
b/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test_ND.c
index 1431c22..441342b 100644
--- a/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test_ND.c
+++ b/gcc/testsuite/c-c++-common/cilk-plus/AN/array_test_ND.c
@@ -1,12 +1,12 @@
/* { dg-do run } */
-/* { dg-options "-fcilkplus" } */
+/* { dg-options "-fcilkplus -DIN_GCC_TESTSUITE=1" } */
#include
int main2(int argc, char **argv);
int main(int argc, char **argv)
{
int x = 0;
- if (argc == 1)
+ if (argc == 1 || IN_GCC_TESTSUITE)
{
const char *array[] = {"a.out", "10", "15"};
x = main2 (3, (char **)array);
diff --git a/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
b/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
index bcb3e1b..43138bb 100644
--- a/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
+++ b/gcc/testsuite/c-c++-common/cilk-plus/AN/comma_exp.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-fcilkplus" } */
+/* { dg-options "-fcilkplus -DIN_GCC_TESTSUITE" } */
#include
@@ -7,7 +7,7 @@ int main2 (int argc, char **argv);
int main(int argc, char **argv)
{
int x = 0;
- if (argc == 1)
+ if (argc == 1 || IN_GCC_TESTSUITE)
{
const char *array[] = {"a.out", "5"};
x = main2 (2, (char **)array);
diff --git a/gcc/testsuite/c-c++-common/cilk-plus/AN/conditional.c
b/gcc/testsuite/c-c++-common/cilk-plus/AN/conditional.c
index 0be99b2..4345a26 100644
--- a/gcc/testsuite/c-c++-common/cilk-plus/AN/conditional.c
+++ b/gcc/testsuite/c-c++-common/cilk-plus/AN/conditional.c
@@ -31,7 +31,7 @@ int main(int argc, char **argv)
array[ii] = 3;
}
array3 = (short *) malloc (sizeof (short) * 1000);
- array3[0:1000:argc] = cond[:] ? array[0:(argc * 1000)] : array2[argc-1:1000];
+ array3[0:1000:1] = cond[:] ? array[0:(1 * 1000)] : array2[0:1000];
for (ii = 0; ii < 1000; ii++) {
if ((cond[ii] == 0 && array3[ii] != 5)
diff --git a/gcc/testsuite/c-c++-common/cilk-plus/AN/exec-once2.c
b/gcc/testsuite/c-c++-common/cilk-plus/AN/exec-once2.c
index 8d208b9..6cbfb66 100644
--- a/gcc/testsuite/c-c++-common/cilk-plus/AN/exec-once2.c
+++ b/gcc/testsuite/c-c++-common/cilk-plus/AN/exec-once2.c
@@ -34,23 +34,23 @@ int func4(int x)
}
-/* This program makes an assumption that argc == 1. */
int main (int argc, char **argv)
{
int array[2500];
+ int i = 1;
/* This should set array[0->999] to 5. */
- array[argc-1:func2(++argc):1] = 5;
+ array[i-1:func2(++i):1] = 5;
array[1000:500:1] = 10; /* set all variables in array[1000-->1499] to 10. */
array[1500:500:1] = 15; /* set all variables in array[1500-->1999] to 15. */
array[2000:500:1] = 20; /* set all variables in array[2000-->2499] to 20. */
array[2000:500:1] = 25; /* set all variables in array[2500-->2999] to 25. */
array[2000:500:1] = 30; /* set all variables in array[3000-->3499] to 30. */
- argc = func3 (argc); /* This wi
Re: [C++ Patch] PR 57419
Now that we're using C++, I'm inclined to give the sfinae version the same name. Jason
Re: [PATCH][gensupport] Add optional attributes field to define_cond_exec
On 06/03/2013 04:06 AM, Kyrylo Tkachov wrote: >> Any comments/suggestions on my implementation of the idea are very >> welcome. >> http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01093.html >> >> Otherwise, OK for trunk? > > Ping? Ok. If we ever get serious about re-implementing define_cond_exec with more generic functionality we'll take adding attributes into account then. In the meantime this is a fairly small change. r~
Re: [C++ Patch] PR 57419
On 06/03/2013 07:55 PM, Jason Merrill wrote:
Now that we're using C++, I'm inclined to give the sfinae version the
same name.
Indeed. I'm finishing testing the below, then.
Thanks,
Paolo.
///
/gcc/cp
2013-06-03 Paolo Carlini
PR c++/57419
* decl2.c (mark_used): Add overload taking a tsubst_flags_t too.
* semantics.c (finish_qualified_id_expr): Use it.
* cp-tree.h: Update.
/gcc/testsuite
2013-06-03 Paolo Carlini
PR c++/57419
* g++.dg/cpp0x/sfinae46.C: New.
* g++.dg/cpp0x/defaulted13.C: Adjust.
* g++.dg/cpp0x/defaulted2.C: Likewise.
* g++.dg/cpp0x/defaulted26.C: Likewise.
* g++.dg/cpp0x/defaulted3.C: Likewise.
* g++.dg/cpp0x/error1.C: Likewise.
* g++.dg/cpp0x/implicit1.C: Likewise.
* g++.dg/cpp0x/implicit11.C: Likewise.
* g++.dg/cpp0x/inh-ctor13.C: Likewise.
* g++.dg/cpp0x/initlist47.C: Likewise.
* g++.dg/cpp0x/initlist9.C: Likewise.
* g++.dg/cpp0x/lambda/lambda-errloc.C: Likewise.
* g++.dg/cpp0x/lambda/lambda-errloc2.C: Likewise.
* g++.dg/cpp0x/nsdmi-local.C: Likewise.
* g++.dg/cpp0x/union4.C: Likewise.
* g++.dg/template/crash108.C: Likewise.
* g++.dg/template/crash41.C: Likewise.
* g++.old-deja/g++.jason/local.C: Likewise.
* g++.old-deja/g++.law/visibility3.C: Likewise.
/libstdc++-v3
2013-06-03 Paolo Carlini
PR c++/57419
* testsuite/20_util/default_delete/48631_neg.cc: Adjust.
Index: gcc/cp/cp-tree.h
===
--- gcc/cp/cp-tree.h(revision 199607)
+++ gcc/cp/cp-tree.h(working copy)
@@ -5278,6 +5278,7 @@ extern bool decl_constant_var_p (tree);
extern bool decl_maybe_constant_var_p (tree);
extern void check_default_args (tree);
extern bool mark_used (tree);
+extern bool mark_used (tree, tsubst_flags_t);
extern void finish_static_data_member_decl (tree, tree, bool, tree, int);
extern tree cp_build_parm_decl (tree, tree);
extern tree get_guard (tree);
Index: gcc/cp/decl2.c
===
--- gcc/cp/decl2.c (revision 199607)
+++ gcc/cp/decl2.c (working copy)
@@ -4499,7 +4499,7 @@ possibly_inlined_p (tree decl)
wrong, true otherwise. */
bool
-mark_used (tree decl)
+mark_used (tree decl, tsubst_flags_t complain)
{
/* If DECL is a BASELINK for a single function, then treat it just
like the DECL for the function. Otherwise, if the BASELINK is
@@ -4537,9 +4537,12 @@ bool
return false;
}
}
- error ("use of deleted function %qD", decl);
- if (!maybe_explain_implicit_delete (decl))
- error_at (DECL_SOURCE_LOCATION (decl), "declared here");
+ if (complain & tf_error)
+ {
+ error ("use of deleted function %qD", decl);
+ if (!maybe_explain_implicit_delete (decl))
+ inform (DECL_SOURCE_LOCATION (decl), "declared here");
+ }
return false;
}
@@ -4552,7 +4555,8 @@ bool
{
if (!processing_template_decl && type_uses_auto (TREE_TYPE (decl)))
{
- error ("use of %qD before deduction of %", decl);
+ if (complain & tf_error)
+ error ("use of %qD before deduction of %", decl);
return false;
}
return true;
@@ -4701,4 +4705,10 @@ bool
return true;
}
+bool
+mark_used (tree decl)
+{
+ return mark_used (decl, tf_warning_or_error);
+}
+
#include "gt-cp-decl2.h"
Index: gcc/cp/semantics.c
===
--- gcc/cp/semantics.c (revision 199607)
+++ gcc/cp/semantics.c (working copy)
@@ -1778,8 +1778,9 @@ finish_qualified_id_expr (tree qualifying_class,
if (error_operand_p (expr))
return error_mark_node;
- if (DECL_P (expr) || BASELINK_P (expr))
-mark_used (expr);
+ if ((DECL_P (expr) || BASELINK_P (expr))
+ && !mark_used (expr, complain))
+return error_mark_node;
if (template_p)
check_template_keyword (expr);
Index: gcc/testsuite/g++.dg/cpp0x/defaulted13.C
===
--- gcc/testsuite/g++.dg/cpp0x/defaulted13.C(revision 199598)
+++ gcc/testsuite/g++.dg/cpp0x/defaulted13.C(working copy)
@@ -7,13 +7,13 @@ struct NonCopyable {
};
template<>
-NonCopyable::NonCopyable(NonCopyable const&) = delete; // { dg-error
"declared" }
+NonCopyable::NonCopyable(NonCopyable const&) = delete; // {
dg-message "declared" }
template
NonCopyable::NonCopyable(NonCopyable const&) = default;
template<>
-NonCopyable::NonCopyable(NonCopyable const&) = delete; // {
dg-error "declared" }
+NonCopyable::NonCopyable(NonCopyable const&) = delete; // {
dg-message "declared" }
int main()
Index: gcc/tes
Re: [PATCH] Handle MIPS EVA
"Moore, Catherine" writes:
> Index: config/mips/mips.opt
> ===
> --- config/mips/mips.opt (revision 199610)
> +++ config/mips/mips.opt (working copy)
> @@ -141,6 +141,10 @@ membedded-data
> Target Report Var(TARGET_EMBEDDED_DATA)
> Use ROM instead of RAM
>
> +meva
> +Target Report Var(TARGET_EVA)
> +Use microMIPS32/MIPS32 Enhanced VA instructions
This is likely to get out of date if EVA is ever extended to MIPS64.
It's probably easier just to drop the "microMIPS32/MIPS32" bit.
> Index: config/mips/mips.h
> ===
> --- config/mips/mips.h(revision 199610)
> +++ config/mips/mips.h(working copy)
> @@ -399,6 +399,11 @@ struct mips_cpu_info {
>if (TARGET_MCU)
> \
> builtin_define ("__mips_mcu"); \
> \
> + if (TARGET_EVA)
> \
> + { \
> + builtin_define ("__mips_eva");\
> + } \
> + \
This should be:
if (TARGET_EVA) \
builtin_define ("__mips_eva"); \
You need to document the option too.
Thanks,
Richard
Re: [patch, testsuite, cilk] Fix cilk tests for simulators
On 06/03/2013 11:49 AM, Steve Ellcey wrote:
A number of the new cilk tests in gcc/testsuite/c-c++-common/cilk-plus/AN
fail for me when run via the gnu simulator on mips. The problem is that
the gnu simulator does not set up argc and argv. After asking in the gdb
mailing list I believe this is an issue for multiple simulators on multiple
platforms. Looking through the GCC testsuite I did not see any other tests
that looked at argc/argv so I would like to change these tests to not use
argc/argv either. In some tests I added a define (IN_GCC_TESTSUITE) that
I set to 1 and then don't check argc if this is set, in others I just used
the constant value 1 instead of using argc and in one (where argc was being
changed) I replaced the use of argc with a local variable.
Tested on mips-mti-elf with the GNU simulator.
Yea, this should have been caught earlier. argc/argv aren't set
properly in many simulator environments.
{
int x = 0;
- if (argc == 1)
+ if (argc == 1 || IN_GCC_TESTSUITE)
So why not just eliminate the conditional completely and simplify the
test appropriately? The only reason I can think of to keep it as-is
would be if the test were from another suite and we wanted to minimize
the amount of divergence from that other testsuite.
Balaji, is there a good reason to keep the argc/argv usage in these tests?
jeff
Re: [patch, testsuite, cilk] Fix cilk tests for simulators
On Mon, Jun 03, 2013 at 12:27:15PM -0600, Jeff Law wrote:
> On 06/03/2013 11:49 AM, Steve Ellcey wrote:
> >
> >A number of the new cilk tests in gcc/testsuite/c-c++-common/cilk-plus/AN
> >fail for me when run via the gnu simulator on mips. The problem is that
> >the gnu simulator does not set up argc and argv. After asking in the gdb
> >mailing list I believe this is an issue for multiple simulators on multiple
> >platforms. Looking through the GCC testsuite I did not see any other tests
> >that looked at argc/argv so I would like to change these tests to not use
> >argc/argv either. In some tests I added a define (IN_GCC_TESTSUITE) that
> >I set to 1 and then don't check argc if this is set, in others I just used
> >the constant value 1 instead of using argc and in one (where argc was being
> >changed) I replaced the use of argc with a local variable.
> >
> >Tested on mips-mti-elf with the GNU simulator.
> Yea, this should have been caught earlier. argc/argv aren't set
> properly in many simulator environments.
>
> >> {
> >int x = 0;
> >- if (argc == 1)
> >+ if (argc == 1 || IN_GCC_TESTSUITE)
> So why not just eliminate the conditional completely and simplify
> the test appropriately? The only reason I can think of to keep it
> as-is would be if the test were from another suite and we wanted to
> minimize the amount of divergence from that other testsuite.
Another reason (at least in a couple of tests I think that is the case)
is that argc is used as a variable without known compile time value, but
with expected known runtime value. That can be replaced with something
like:
int var = 1;
__asm volatile ("" : "+r" (var));
or so.
Jakub
Re: [PATCH] Improve folding of bitwise ops on booleans
2013/6/3 Jeff Law : > On 06/03/2013 11:00 AM, Richard Henderson wrote: >> >> On 06/03/2013 09:37 AM, Kai Tietz wrote: >>> >>> foo: >>> .seh_endprologue >>> cmpb%cl, %dl >>> seta%al >>> ret >>> .seh_endproc >>> .p2align 4,,15 >>> .globl boo >>> .defboo;.scl2; .type 32; .endef >>> .seh_proc boo >>> boo: >>> .seh_endprologue >>> movl%ecx, %eax >>> notl%eax >>> andl%edx, %eax >>> andl$1, %eax >>> ret >> >> >> Try arm or s390 or ppc for significantly different results. > > I'm starting to wonder if we could delay make a choice about using a > relational or bit ops until gimple->rtl expansion. I haven't seen any > secondary benefits, so deferring to a later point where we might be able to > query the backend's capabilities might make sense. > jeff Well, a secondary benefit I see in area of BC-optimization. But I agree that this operation should go along gimple->rtl transformation. And at same place BC-optimization should happen. Kai
Re: [PATCH] Reduce -fopt-info verbosity
On Mon, Jun 3, 2013 at 1:05 AM, Richard Biener wrote:
> On Fri, 31 May 2013, Teresa Johnson wrote:
>
>> This patch changes the -fopt-info default to optimized instead of all,
>> since the latter is extremely verbose. This reduced the -fopt-info output by
>> over 75% in at least one case, since the vectorizer has many messages under
>> MSG_NOTE (and that should grow as more passes are converted to the new dump
>> infrastructure). The default now emits high-level optimization success info
>> (currently for unrolling, inlining and vectorization).
>>
>> Also changed which vectorization summary messages are emitted under
>> -fopt-info(=optimized), to be more consistent with the format of the
>> optimization summary messages emitted by the unroller and inliner,
>> and fixed the loop vectorization summary message to use dump_printf_loc
>> instead of manually emitting the location info.
>>
>> Bootstrapped and tested on x86-64-unknown-linux-gnu. Ok for trunk?
>>
>> 2013-05-31 Teresa Johnson
>>
>> * dumpfile.c (opt_info_switch_p): Change -fopt-info
>> default to -fopt-info=optimized instead of all.
>> * doc/invoke.texi: Ditto.
>> * tree-vectorizer.c (vectorize_loops): Emit loop vectorization
>> success under MSG_ALL, and use dump_printf_loc.
>> (execute_vect_slp): Emit BB vectorization success under
>> MSG_OPTIMIZED_LOCATIONS.
>> * tree-vect-slp.c (vect_make_slp_decision): Ditto.
>> (vect_slp_transform_bb): Change MSG_OPTIMIZED_LOCATIONS
>> to MSG_NOTE.
>> * tree-vect-loop.c (vect_transform_loop): Ditto.
>>
>> Index: tree-vect-loop.c
>> ===
>> --- tree-vect-loop.c (revision 199423)
>> +++ tree-vect-loop.c (working copy)
>> @@ -5801,7 +5801,7 @@ vect_transform_loop (loop_vec_info loop_vinfo)
>>
>>if (dump_enabled_p ())
>> {
>> - dump_printf_loc (MSG_OPTIMIZED_LOCATIONS, vect_location,
>> + dump_printf_loc (MSG_NOTE, vect_location,
>> "LOOP VECTORIZED\n");
>>if (loop->inner)
>> dump_printf_loc (MSG_NOTE, vect_location,
>> Index: dumpfile.c
>> ===
>> --- dumpfile.c(revision 199423)
>> +++ dumpfile.c(working copy)
>> @@ -866,7 +866,7 @@ opt_info_switch_p (const char *arg)
>>
>>file_seen = xstrdup (filename);
>>if (!flags)
>> -flags = MSG_ALL;
>> +flags = MSG_OPTIMIZED_LOCATIONS;
>>if (!optgroup_flags)
>> optgroup_flags = OPTGROUP_ALL;
>>
>> Index: tree-vectorizer.c
>> ===
>> --- tree-vectorizer.c (revision 199423)
>> +++ tree-vectorizer.c (working copy)
>> @@ -118,8 +118,7 @@ vectorize_loops (void)
>>
>> if (LOCATION_LOCUS (vect_location) != UNKNOWN_LOC
>> && dump_enabled_p ())
>> - dump_printf (MSG_NOTE, "\n\nVectorizing loop at %s:%d\n",
>> - LOC_FILE (vect_location), LOC_LINE (vect_location));
>> + dump_printf_loc (MSG_ALL, vect_location, "Vectorized loop\n");
>
> MSG_ALL looks wrong if we are looking for unoptimized locations
> only, no? I think you want MSG_OPTIMIZED_LOCATIONS here.
Ok, fixed.
>
>> vect_transform_loop (loop_vinfo);
>> num_vectorized_loops++;
>>}
>> @@ -179,7 +178,7 @@ execute_vect_slp (void)
>> {
>>vect_slp_transform_bb (bb);
>>if (dump_enabled_p ())
>> -dump_printf_loc (MSG_NOTE, vect_location,
>> +dump_printf_loc (MSG_OPTIMIZED_LOCATIONS, vect_location,
>>"basic block vectorized using SLP\n");
>
> Please make the message consistent with the loop one. The loop one
> says "Vectorized loop" (I think the caps 'V' is not according to
> our diagnostic policies, it should be lower-case), the basic-block
> one "basic block vectorized using SLP" which shouldn't confuse the
> user about "SLP" and say "vectorized basic-block" instead.
>
> Yes, that may require you to fiddle with testcases that scan for
> these ...
As suggested, I changed the above to "Vectorized basic-block" (kept
both success notes with leading
capital to be consistent with the loop unroller
MSG_OPTIMIZED_LOCATIONS messages).
Updated test cases with the new message.
>
>> }
>> }
>> Index: doc/invoke.texi
>> ===
>> --- doc/invoke.texi (revision 199423)
>> +++ doc/invoke.texi (working copy)
>> @@ -6172,7 +6172,7 @@ Controls optimization dumps from various optimizat
>> @samp{-@var{options}} form is used, @var{options} is a list of
>> @samp{-} separated options to select the dump details and
>> optimizations. If @var{options} is not specified, it defaults to
>> -@option{all} for details and @option{optall} for optimization
>> +@option{optimized} for details and @option{optall} for optimization
>> groups. If the @var{filename} is n
Re: [PATCH] Improve folding of bitwise ops on booleans
On 06/03/2013 12:32 PM, Kai Tietz wrote: 2013/6/3 Jeff Law : On 06/03/2013 11:00 AM, Richard Henderson wrote: On 06/03/2013 09:37 AM, Kai Tietz wrote: foo: .seh_endprologue cmpb%cl, %dl seta%al ret .seh_endproc .p2align 4,,15 .globl boo .defboo;.scl2; .type 32; .endef .seh_proc boo boo: .seh_endprologue movl%ecx, %eax notl%eax andl%edx, %eax andl$1, %eax ret Try arm or s390 or ppc for significantly different results. I'm starting to wonder if we could delay make a choice about using a relational or bit ops until gimple->rtl expansion. I haven't seen any secondary benefits, so deferring to a later point where we might be able to query the backend's capabilities might make sense. jeff Well, a secondary benefit I see in area of BC-optimization. But I agree that this operation should go along gimple->rtl transformation. And at same place BC-optimization should happen. Let's table it for now then. Ironically I was just looking at moving one of the branch-cost transformations out of fold-const.c. We're going to have to build out some infrastructure to make that happen. I'll withdraw the patch and just submit a missed optimization PR and xfailed testsuite for this issue. jeff
Re: [PATCH, libcpp] Do not decrease highest_location if the included file has be included twice.
Dehao Chen a écrit: > Thanks for looking into this. You are welcome. Libcpp is fun. Is it not? :-) > The reason a test is missing is that it would need a super large > source file to reproduce the problem. I see. It's kind of a pity that we cannot have tests for interesting cases like this, though. I am wondering if with some #line tricks (like setting #line we couldn't simulate that. I haven't tried myself though. > However, if you apply the attached patch, you can reproduce the > problem with attached testcase: > > g++ a.cpp -g -S -c -o a.s > > in a.s, the linenos are off-by-one. Thanks. > The root cause is that highest_location-- should not happen when the > header file is not gonna be read. In should_stack file, there is > following check: > > /* Skip if the file had a header guard and the macro is defined. > PCH relies on this appearing before the PCH handler below. */ > if (file->cmacro && file->cmacro->type == NT_MACRO) > return false; > > Thus we should add it back to _cpp_stack_include too. Yeah, I figured that out. What I didn't get is how the column number disabling thing was interacting with this > The problem was hidden when column number is used because > highest_location is updated in linemap_position_for_column. However, > when linemap are too large, it disables columns and do not update the > highest_location. Gotcha. Thank you for the insight. So, I'd say that in this hunk of your patch: > @@ -1002,7 +1002,8 @@ _cpp_stack_include (cpp_reader *pfile, const char > linemap_add is not called) or we were included from the > command-line. */ >if (file->pchname == NULL && file->err_no == 0 > - && type != IT_CMDLINE && type != IT_DEFAULT) > + && type != IT_CMDLINE && type != IT_DEFAULT > + && !(file->cmacro && file->cmacro->type == NT_MACRO)) Maybe you should test: && should_stack_file (pfile, file, type == IT_IMPORT) rather than testing the last conjunction you added? This is because there are many conditions that could make the header to not be loaded, besides the one you are testing. Would this work in your environment? If that works, maybe add a comment to : /* Compensate for the increment in linemap_add that occurs in _cpp_stack_file. ... */ Saying that the compensation should happen when _cpp_stack_file really stacks the file, that is, when should_stack_file returns true; this does not seem obvious. At least not to me. :-) Cheers. -- Dodji
Re: [PATCH] pr57457
On 05/31/2013 12:01 PM, Iyer, Balaji V wrote: -Original Message- From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- ow...@gcc.gnu.org] On Behalf Of Jeff Law Sent: Friday, May 31, 2013 11:50 AM To: Iyer, Balaji V Cc: gcc-patches@gcc.gnu.org; Steve Ellcey Subject: Re: [PATCH] pr57457 On 05/31/2013 07:54 AM, Iyer, Balaji V wrote: Hello Everyone, This patch will fix a bug reported in PR57457. One of the array notation function was not checking for NULL_TREE before accessing its fields. This patch should fix that issue. A test case is also added. Is this OK for trunk? Here are the ChangeLog Entries: gcc/c/ChangeLog 2013-05-31 Balaji V. Iyer * c-array-notation.c (is_cilkplus_reduce_builtin): Added a check for NULL_TREE parameter input. gcc/testsuite/ChangeLog 2013-05-31 Balaji V. Iyer PR c/57457 * c-c++-common/cilk-plus/AN/pr57457.c: New testcase. So what you need to do is explain how you got into this function with a NULL fndecl and why that's OK. Hi Jeff, I looked into it, and there is another function call called inform_declaration, and that does exactly what I did (i.e. check for NULL fundecl before accessing its fields). From what I can tell, fundecl will be NULL_TREE if a function declaration is a function pointer. The problematical calls are coming from convert_arguments which is a bit inconsistent in how it handles a null FUNDECL. In some places it checks it direction in convert_arguments and avoids certain actions. In other places the callee checks. The code looks like it's screaming to be simplified. Neither flag_cilkplus nor FUNDECL change inside the main loop in convert_arguments, so the first thing I'd ponder is pulling that condition out of the loop. And after doing that we a similar condition being used to suppress warnings just after the loop. I wonder if we could have something like if (flag_enable_cilkplus && fundecl && is_cilkplus_reduction_builtin (fundecl)) return vec_safe_length (values); before the loop, then eliminate the the test inside the loop and just after the loop. That simplifies the code a bit and should fix this problem unless I'm missing something? jeff
Remove redundant target_cpu_default settings
Some (but not all) 64-bit MIPS configurations were setting target_cpu_default
to MASK_64BIT|MASK_FLOAT64. This has been redundant for a long time.
The masks are now derived from the ABI and ISA settings, and also aren't
tested directly in preprocessor conditions (such as those used when setting
up the default multilibs).
This patch removes them. Tested on mips64-elf and applied.
Richard
gcc/
* config.gcc (mipsisa64sr71k-*-elf*, mipsisa64sb1-*-elf*)
(mipsisa64sb1el-*-elf*, mips64-*-elf*, mips64el-*-elf*)
(mips64orion-*-elf*, mips64orionel-*-elf*): Remove
target_cpu_default setting.
Index: gcc/config.gcc
===
--- gcc/config.gcc 2013-06-03 20:11:08.037638775 +0100
+++ gcc/config.gcc 2013-06-03 20:11:09.766655898 +0100
@@ -1928,13 +1928,11 @@ mipsisa64r2-*-elf* | mipsisa64r2el-*-elf
mipsisa64sr71k-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
tmake_file=mips/t-sr71k
- target_cpu_default="MASK_64BIT|MASK_FLOAT64"
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64
MIPS_CPU_STRING_DEFAULT=\\\"sr71000\\\" MIPS_ABI_DEFAULT=ABI_EABI"
;;
mipsisa64sb1-*-elf* | mipsisa64sb1el-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
tmake_file="mips/t-elf mips/t-sb1"
- target_cpu_default="MASK_64BIT|MASK_FLOAT64"
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64
MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64"
;;
mips-*-elf* | mipsel-*-elf*)
@@ -1944,7 +1942,6 @@ mips-*-elf* | mipsel-*-elf*)
mips64-*-elf* | mips64el-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h"
tmake_file="mips/t-elf"
- target_cpu_default="MASK_64BIT|MASK_FLOAT64"
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64"
;;
mips64vr-*-elf* | mips64vrel-*-elf*)
@@ -1955,7 +1952,6 @@ mips64vr-*-elf* | mips64vrel-*-elf*)
mips64orion-*-elf* | mips64orionel-*-elf*)
tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elforion.h mips/elf.h"
tmake_file="mips/t-elf"
- target_cpu_default="MASK_64BIT|MASK_FLOAT64"
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64"
;;
mips*-*-rtems*)
RE: [patch, testsuite, cilk] Fix cilk tests for simulators
> -Original Message-
> From: Jeff Law [mailto:l...@redhat.com]
> Sent: Monday, June 03, 2013 2:27 PM
> To: Steve Ellcey
> Cc: Iyer, Balaji V; gcc-patches@gcc.gnu.org
> Subject: Re: [patch, testsuite, cilk] Fix cilk tests for simulators
>
> On 06/03/2013 11:49 AM, Steve Ellcey wrote:
> >
> > A number of the new cilk tests in
> > gcc/testsuite/c-c++-common/cilk-plus/AN
> > fail for me when run via the gnu simulator on mips. The problem is
> > that the gnu simulator does not set up argc and argv. After asking in
> > the gdb mailing list I believe this is an issue for multiple
> > simulators on multiple platforms. Looking through the GCC testsuite I
> > did not see any other tests that looked at argc/argv so I would like
> > to change these tests to not use argc/argv either. In some tests I
> > added a define (IN_GCC_TESTSUITE) that I set to 1 and then don't check
> > argc if this is set, in others I just used the constant value 1
> > instead of using argc and in one (where argc was being
> > changed) I replaced the use of argc with a local variable.
> >
> > Tested on mips-mti-elf with the GNU simulator.
> Yea, this should have been caught earlier. argc/argv aren't set properly in
> many
> simulator environments.
>
> >> {
> > int x = 0;
> > - if (argc == 1)
> > + if (argc == 1 || IN_GCC_TESTSUITE)
> So why not just eliminate the conditional completely and simplify the test
> appropriately? The only reason I can think of to keep it as-is would be if
> the test
> were from another suite and we wanted to minimize the amount of divergence
> from that other testsuite.
>
> Balaji, is there a good reason to keep the argc/argv usage in these tests?
I am OK with Steve's changes in most cases. In a few cases, I am using it as a
parameter to pass into tests. On a top-level, the main reason why I used argc,
and argv is that, I want to make sure the compiler will never do things like
constant propagation, and it will pass it as a variable.
Thanks,
Balaji V. Iyer.
>
> jeff
>
Re: [PATCH] Improve folding of bitwise ops on booleans
On Mon, Jun 03, 2013 at 10:00:19AM -0700, Richard Henderson wrote:
> On 06/03/2013 09:37 AM, Kai Tietz wrote:
> > foo:
> > .seh_endprologue
> > cmpb%cl, %dl
> > seta%al
> > ret
> > .seh_endproc
> > .p2align 4,,15
> > .globl boo
> > .defboo;.scl2; .type 32; .endef
> > .seh_proc boo
> > boo:
> > .seh_endprologue
> > movl%ecx, %eax
> > notl%eax
> > andl%edx, %eax
> > andl$1, %eax
> > ret
>
> Try arm or s390 or ppc for significantly different results.
Lets see for powerpc:
.L.foo:
cmpw 7,3,4
mfcr 3,1
rlwinm 3,3,29,1
blr
.L.boo:
andc 3,4,3
rldicl 3,3,0,63
blr
So for powerpc, the second is the preferred method.
However, in looking at it, if we rewrite the code to have come from
comparisons:
_Bool foo_cmp (long w, long x, long y, long z)
{
_Bool a = (w < x);
_Bool b = (y < z);
_Bool r = a < b;
return r;
}
_Bool bfoo_cmp (long w, long x, long y, long z)
{
_Bool a = (w < x);
_Bool b = (y < z);
_Bool r = ~a & b;
return r;
}
We get:
.L.foo_cmp:
cmpd 7,5,6
cmpd 6,3,4
mfcr 6
rlwinm 3,6,25,1
rlwinm 6,6,29,1
cmpw 7,3,6
mfcr 3,1
rlwinm 3,3,29,1
blr
.L.bfoo_cmp:
cmpd 6,3,4
cmpd 7,5,6
mfcr 3,2
rlwinm 3,3,25,1
mfcr 6,1
rlwinm 6,6,29,1
andc 3,6,3
blr
And it would have been nice to use the logcal comparison operations in the CR
register unit (i.e. doing a crandc in the CR unit rather than moving the value
from a CR to a GPR -- cmpd/mfcr/rlwinm instructions).
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Re: [patch, testsuite, cilk] Fix cilk tests for simulators
On 06/03/2013 01:27 PM, Iyer, Balaji V wrote: I am OK with Steve's changes in most cases. In a few cases, I am using it as a parameter to pass into tests. On a top-level, the main reason why I used argc, and argv is that, I want to make sure the compiler will never do things like constant propagation, and it will pass it as a variable. So use Jakub's trick, or define non-inlinable functions which return suitable tables. We simply can't use argc/argv in the manner in which those tests do and I'd rather clean up the test to avoid argc/argv than support two paths through the test, one with argc/argv, one without. jeff
Re: [PATCH] fix for pr 57474
On 05/31/2013 06:28 PM, Iyer, Balaji V wrote: Hello Everyone, PR reports that sec_implicit2 and sec_implicit regression tests were failing in darwin. I looked into it and it is due to an uninitialized variable (rhs_length). This patch pasted below should fix that issue. Is this OK for trunk? Here are the ChangeLog entries: 2013-05-31 Balaji V. Iyer PR c/57474 * c-array-notation.c (build_array_notation_expr): Initialized rhs_length array to NULL_TREE if they are unused. Also added a check for the field to be NULL before its fields are used in future. Does lhs_length need similar initialization & checks? If not, why? jeff
Re: default_no_named_section bad default
On Jun 3, 2013, at 1:27 AM, Richard Biener wrote:
>> Yes. Speaking of which, so how should this be handled? Imagine we have
>> asm("# no bytes") before the unreachable. The compiler can't know the size
>> (though, the linker can), and yet, a good solution handles this as well.
>> Hopefully a dwarf person can weigh in, as engineering a bad solution is
>> worse than leaving it broken in my book.
>
> Let the assembler compute it as difference of two labels?
We do use two labels, one for the start, one for the end.
Re: [PATCH] Basic support for MIPS r5900
"Jürgen Urban" writes:
> after some months I reworked the patch for r5900. It would be nice if
> this could be accepted. The patch contains only changes to get basic
> support for MIPS r5900. It can be used to compile a working Linux kernel
> for the Playstation 2. It is also possible to get Linux programs working
> with software floating point and ABI o32. Other stuff like hardware
> floating point and ABI n32 is not fully supported yet.
Thanks, looks good. The comments I have are only minor and seemed easier
to spell out as a revised patch, attached below. The changes are:
* removing the config.sub bit, which looked redundant. We already have
the up-to-date upstream config.sub.
* removing the target_cpu_default setting. I realise this was taken
from mips64-elf, but it was redundant here, there, and elsewhere.
I've just committed a patch to remove the existing cases.
* removing the TUNE_5900 definition. I prefer not to define these
kinds of macro until they're used.
* removing the ISA_HAS_LDC1_SDC1 setting. I realise what you did
describes the reality of the processor, but the problem is that
the patch doesn't provide an alternative for 64-bit loads and
stores when -mfp64 is used. That combination also isn't rejected,
so we're likely to get an internal compiler error instead.
This change shouldn't affect the soft-float case you describe.
It also shouldn't be important for the single-float code.
* tweaking the mips_reorg_process_insns comment slightly
* fixing a few minor formatting issues
Does this version look OK to you? I'll commit it if so.
> How much other changes will be currently accepted here? There is other
> stuff which I want to prepare and submit here, e.g.:
> 1. disable use of dmult and ddiv (ABI n32).
> 2. use trunc.w.s instead of cvt.w.s (to get single float working for
> normal range calculations; i.e. calculating without inf or nan).
> 3. fix use of ll/sc in libgomp, either increase mips ISA level or use
> syscall (which is broken in Linux 2.6.35.4).
> 4. fix libgcc to build a real muldi3 function for ABI n32 (not the
> multi3 function which is stored in muldi3.o file).
> 5. add support for configure parameters --float=single and
> --float=double in addition to --float=soft and --float=hard.
> 6. rework floating point to support single float with ABI n32 (either
> break the ABI or store floating point values in general purpose
> registers like soft float).
> 7. change libgcc or mips.md in way so that the non IEEE 754 compatible
> FPU of the r5900 gets compatible.
Well, I'm afraid that's hard to say in advance. It really depends
on what the changes look like. (1) and (2) sound harmless enough,
although (1) should probably only be done in conjunction with (4).
I'm not sure what (3) involves. (5) sounds like a good idea.
(6) is worth doing, but anything ABI-related gets extra-paranoid
treatment. :-)
I'm not sure about (7) though. I'd imagine trying to get true IEEE
conformance out of the R5900 FPU would be pretty difficult and carry
quite a bit of runtime overhead, especially with the subnormal handling.
Is it really worth it? Do you have any particular use cases in mind?
FWIW, the Cygnus/Red Hat version of the port just stuck with the R5900
behaviour and made GCC understand it (MODE_HAS_* & various other bits).
This code was then updated and extended for the SPU. I'd have expected
the support to be in reasonably good shape because of the SPU.
Thanks,
Richard
gcc/
2013-06-03 Jürgen Urban
* config.gcc (mipsr5900-*-elf*, mipsr5900el-*-elf*, mips64r5900-*-elf*)
(mips64r5900el-*-elf*): New configurations.
* config/mips/mips-cpus.def (r5900): New processor.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.c (mips_rtx_cost_data): Add an R5900 entry.
(mips_issue_rate): Handle PROCESSOR_R5900.
(mips_reorg_process_insns): Force reorder mode for the R5900.
* config/mips/mips.h (TARGET_MIPS5900): Define.
(ISA_HAS_CONDMOVE, ISA_HAS_PREFETCH, ISA_HAS_HILO_INTERLOCKS): Include
TARGET_MIPS5900.
(ISA_HAS_LOAD_DELAY, ISA_HAS_XFER_DELAY, ISA_HAS_FCMP_DELAY): Exclude
TARGET_MIPS5900.
* config/mips/mips.md (processor): Add r5900.
(MOVECC): Disallow CCmode conditions for TARGET_MIPS5900.
libgcc/
2013-06-03 Jürgen Urban
* config.host (mipsr5900-*-elf*, mipsr5900el-*-elf*, mips64r5900-*-elf*)
(mips64r5900el-*-elf*): New configurations.
Index: gcc/config.gcc
===
--- gcc/config.gcc 2013-06-03 20:28:18.959933736 +0100
+++ gcc/config.gcc 2013-06-03 20:30:19.110139050 +0100
@@ -1935,10 +1935,15 @@ mipsisa64sb1-*-elf* | mipsisa64sb1el-*-e
tmake_file="mips/t-elf mips/t-sb1"
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64
MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64"
;;
-mips-*-elf* | mipsel-*-elf*)
+mips-*-elf* |
Re: [C++ Patch] PR 57419
OK. Jason
Re: [PATCH v2 0/6] define_dot_insn
Well, my first comment is that this is more or less exactly what we invented define_subst to attempt to handle. Could we have more constructive feedback on that mechanism rather than inventing a new mechanism private to the rs6000 backend? Hi Richard, I don't think this can be done using define_subst. To start with, we need both define_insns and define_splits. We need to be able to change constraints. We need to be able to change all match_operands in an expression into match_dups. We need to add an extra match_operand. We need to change the output template, and add alternatives to it. We need to edit the set_attrs in various ways. And we need to change the condition of the transformed instruction in a way dependent on the instruction, not the transform. We will have over 100 such define_dot_insns; any construct that is more clumsy, more verbose, more error prone is a lot more clumsy, verbose, and/or error prone. This removes about 6000 lines of rs6000.md (from the current 15000). define_subst is not flexible enough for our purpose by far, as far as I can see. But feel free to prove me wrong :-) I think define_subst will work out okay for the sign/zero- extending variants of the insns. Segher
Re: [PATCH] Expanding array notations inside conditions
On 05/30/2013 10:00 PM, Iyer, Balaji V wrote: Hello Everyone, When I was looking at the erroneous test on PR 57452, I found out that array notations in conditions were not expanded correctly. The rank for the array notation condition must be same (or equal to zero) as the rank of the array notations inside the else-block and then-block (or they could be zero). I found out that GCC was not detecting these errors. I am very sorry for this mishap. The attached patch should fix that issue. I have also enclosed a test-suite code to make sure this gets caught in future. It is tested on x86_64 and seem to work OK. The only test that it is failing is the erronous test called if_test.c, and if patch specified in (http://gcc.gnu.org/ml/gcc-patches/2013-05/msg01815.html) is applied, then that test will pass. Is this OK for trunk? Here are the ChangeLog entries: gcc/c/ChangeLog 2013-05-30 Balaji V. Iyer * c-typeck.c (c_finish_if_stmt): Added a check to see if the rank of the condition of the if-statement matches the rank of else-block and then- block when array notations are used. * c-parser.c (c_parser_declaration_or_fndef): Expanded array notation expression after the entire function body is parsed. (c_parser_expr_no_commas): Delayed creating array notation expressions to the end of function parsing. * c-array-notation.c (fix_conditional_array_notations_1): Expanded the whole if-statement instead of just the condition. (expand_array_notation_exprs): Added MODIFY_EXPR case. gcc/testsuite/ChangeLog 2013-05-30 Balaji V. Iyer * c-c++-common/cilk-plus/AN/if_test_errors.c (main): New testcase. * c-c++-common/cilk-plus/AN/rank_mismatch.c: Added a '-w' option to dg-option and an header comment. OK after fixing the new tests not to rely on argc/argv. jeff
RE: [PATCH] fix for pr 57474
> -Original Message- > From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- > ow...@gcc.gnu.org] On Behalf Of Jeff Law > Sent: Monday, June 03, 2013 3:51 PM > To: Iyer, Balaji V > Cc: gcc-patches@gcc.gnu.org; domi...@lps.ens.fr > Subject: Re: [PATCH] fix for pr 57474 > > On 05/31/2013 06:28 PM, Iyer, Balaji V wrote: > > Hello Everyone, > > PR reports that sec_implicit2 and sec_implicit regression tests were > failing in darwin. I looked into it and it is due to an uninitialized variable > (rhs_length). This patch pasted below should fix that issue. Is this OK for > trunk? > > > > Here are the ChangeLog entries: > > > > 2013-05-31 Balaji V. Iyer > > PR c/57474 > > * c-array-notation.c (build_array_notation_expr): Initialized > > rhs_length > > array to NULL_TREE if they are unused. Also added a check for the > > field to be NULL before its fields are used in future. > Does lhs_length need similar initialization & checks? If not, why? The only reason why we will get to this spot is if we have the following : E.g. X[:] = Z + Y[:] Where Z is an expression with rank 0. The reason why we do not need to check for null length for LHS is because we cannot have such a scenario: (e.g. Z+Y = Q is invalid) Thanks, Balaji V. Iyer. > > jeff
Re: [PATCH] fix for pr 57474
On 06/03/2013 02:34 PM, Iyer, Balaji V wrote: -Original Message- From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches- ow...@gcc.gnu.org] On Behalf Of Jeff Law Sent: Monday, June 03, 2013 3:51 PM To: Iyer, Balaji V Cc: gcc-patches@gcc.gnu.org; domi...@lps.ens.fr Subject: Re: [PATCH] fix for pr 57474 On 05/31/2013 06:28 PM, Iyer, Balaji V wrote: Hello Everyone, PR reports that sec_implicit2 and sec_implicit regression tests were failing in darwin. I looked into it and it is due to an uninitialized variable (rhs_length). This patch pasted below should fix that issue. Is this OK for trunk? Here are the ChangeLog entries: 2013-05-31 Balaji V. Iyer PR c/57474 * c-array-notation.c (build_array_notation_expr): Initialized rhs_length array to NULL_TREE if they are unused. Also added a check for the field to be NULL before its fields are used in future. Does lhs_length need similar initialization & checks? If not, why? The only reason why we will get to this spot is if we have the following : E.g. X[:] = Z + Y[:] Where Z is an expression with rank 0. The reason why we do not need to check for null length for LHS is because we cannot have such a scenario: (e.g. Z+Y = Q is invalid) OK. The patch is fine in that case. Thanks, jeff
Re: [PATCH v2 0/6] define_dot_insn
On Jun 3, 2013, at 1:16 PM, Segher Boessenkool wrote: > define_subst is not flexible enough for our purpose by far I had Kenny review define_subst when it went in, though it is a step in the right direction, it misses out on a lot completeness that a port maintainer might wish it had. For me personally, with the viewpoint of knowing lisp, I see the advantage of a nice general scheme; that said, I know the downside as well. I remain conflicted as to the right balance.
Re: [ada, build] host/target configuration
On Jun 2, 2013, at 21:18 , Alexandre Oliva wrote: >> - Use target_alias explicitly just at the points where >> we know that we need to depart from the canonical name > > I suggest another approach: if there are significant differences between > the run-time systems, they ought to be preserved in the canonical target > names. So, adjust config.sub so that it preserve them, and then we can > decide based on the canonical target name only. Can we do that without adding loads of instances of this canonical names in all the switch/case statements around ? The idea was trying not to go there because this is a maintenance pain, essentially pointless if the only differences are a couple of Ada RTS unit selections.
Re: [PATCH] Handle MIPS EVA
On Mon, 3 Jun 2013, Richard Sandiford wrote: > > Index: config/mips/mips.opt > > === > > --- config/mips/mips.opt(revision 199610) > > +++ config/mips/mips.opt(working copy) > > @@ -141,6 +141,10 @@ membedded-data > > Target Report Var(TARGET_EMBEDDED_DATA) > > Use ROM instead of RAM > > > > +meva > > +Target Report Var(TARGET_EVA) > > +Use microMIPS32/MIPS32 Enhanced VA instructions > > This is likely to get out of date if EVA is ever extended to MIPS64. > It's probably easier just to drop the "microMIPS32/MIPS32" bit. I agree, however may I suggest spelling out EVA in full, that is: "Use Enhanced Virtual Addressing instructions" Maciej
C++ PATCH to avoid false positives with -Wabi-tag
It occurred to me that -Wabi-tag would probably warn about a template
instantiated with a class that has an ABI tag, and indeed it does. This
is unnecessary; since the template argument is part of the signature of
the instantiation, we don't need to worry about the tag being hidden
when the type is used as a base or member.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit fdeabae097d4140dd56345ee9ca81fb9d6df15b9
Author: Jason Merrill
Date: Fri May 31 22:42:48 2013 -0400
* class.c (mark_type_abi_tags): New.
(check_abi_tags): Use it.
diff --git a/gcc/cp/class.c b/gcc/cp/class.c
index 64918c6..286164d 100644
--- a/gcc/cp/class.c
+++ b/gcc/cp/class.c
@@ -1354,39 +1354,55 @@ find_abi_tags_r (tree *tp, int */*walk_subtrees*/, void *data)
return NULL_TREE;
}
+/* Set IDENTIFIER_MARKED on all the ABI tags on T and its (transitively
+ complete) template arguments. */
+
+static void
+mark_type_abi_tags (tree t, bool val)
+{
+ tree attributes = lookup_attribute ("abi_tag", TYPE_ATTRIBUTES (t));
+ if (attributes)
+{
+ for (tree list = TREE_VALUE (attributes); list;
+ list = TREE_CHAIN (list))
+ {
+ tree tag = TREE_VALUE (list);
+ tree id = get_identifier (TREE_STRING_POINTER (tag));
+ IDENTIFIER_MARKED (id) = val;
+ }
+}
+
+ /* Also mark ABI tags from template arguments. */
+ if (CLASSTYPE_TEMPLATE_INFO (t))
+{
+ tree args = CLASSTYPE_TI_ARGS (t);
+ for (int i = 0; i < TMPL_ARGS_DEPTH (args); ++i)
+ {
+ tree level = TMPL_ARGS_LEVEL (args, i+1);
+ for (int j = 0; j < TREE_VEC_LENGTH (level); ++j)
+ {
+ tree arg = TREE_VEC_ELT (level, j);
+ if (CLASS_TYPE_P (arg))
+ mark_type_abi_tags (arg, val);
+ }
+ }
+}
+}
+
/* Check that class T has all the abi tags that subobject SUBOB has, or
warn if not. */
static void
check_abi_tags (tree t, tree subob)
{
- tree attributes = lookup_attribute ("abi_tag", TYPE_ATTRIBUTES (t));
- if (attributes)
-{
- for (tree list = TREE_VALUE (attributes); list;
- list = TREE_CHAIN (list))
- {
- tree tag = TREE_VALUE (list);
- tree id = get_identifier (TREE_STRING_POINTER (tag));
- IDENTIFIER_MARKED (id) = true;
- }
-}
+ mark_type_abi_tags (t, true);
tree subtype = TYPE_P (subob) ? subob : TREE_TYPE (subob);
struct abi_tag_data data = { t, subob };
cp_walk_tree_without_duplicates (&subtype, find_abi_tags_r, &data);
- if (attributes)
-{
- for (tree list = TREE_VALUE (attributes); list;
- list = TREE_CHAIN (list))
- {
- tree tag = TREE_VALUE (list);
- tree id = get_identifier (TREE_STRING_POINTER (tag));
- IDENTIFIER_MARKED (id) = false;
- }
-}
+ mark_type_abi_tags (t, false);
}
/* Run through the base classes of T, updating CANT_HAVE_CONST_CTOR_P,
diff --git a/gcc/testsuite/g++.dg/abi/abi-tag5.C b/gcc/testsuite/g++.dg/abi/abi-tag5.C
new file mode 100644
index 000..de55802
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/abi-tag5.C
@@ -0,0 +1,6 @@
+// { dg-options -Wabi-tag }
+
+struct __attribute__ ((abi_tag ("foo"))) A { };
+template struct B: T { };
+
+B b;
Re: [patch, testsuite, cilk] Fix cilk tests for simulators
On Mon, 2013-06-03 at 13:47 -0600, Jeff Law wrote: > On 06/03/2013 01:27 PM, Iyer, Balaji V wrote: > > > > I am OK with Steve's changes in most cases. In a few cases, I am > > using it as a parameter to pass into tests. On a top-level, the main > > reason why I used argc, and argv is that, I want to make sure the > > compiler will never do things like constant propagation, and it will > > pass it as a variable. > So use Jakub's trick, or define non-inlinable functions which return > suitable tables. > > We simply can't use argc/argv in the manner in which those tests do and > I'd rather clean up the test to avoid argc/argv than support two paths > through the test, one with argc/argv, one without. > > jeff I'll leave fixing the tests to Balaji then instead of doing it myself since that way he can be sure that they are testing what he wants to test. Steve Ellcey sell...@mips.com
RE: [patch, testsuite, cilk] Fix cilk tests for simulators
> -Original Message- > From: Steve Ellcey [mailto:sell...@mips.com] > Sent: Monday, June 03, 2013 6:31 PM > To: Jeff Law > Cc: Iyer, Balaji V; gcc-patches@gcc.gnu.org > Subject: Re: [patch, testsuite, cilk] Fix cilk tests for simulators > > On Mon, 2013-06-03 at 13:47 -0600, Jeff Law wrote: > > On 06/03/2013 01:27 PM, Iyer, Balaji V wrote: > > > > > > I am OK with Steve's changes in most cases. In a few cases, I am > > > using it as a parameter to pass into tests. On a top-level, the main > > > reason why I used argc, and argv is that, I want to make sure the > > > compiler will never do things like constant propagation, and it will > > > pass it as a variable. > > So use Jakub's trick, or define non-inlinable functions which return > > suitable tables. > > > > We simply can't use argc/argv in the manner in which those tests do > > and I'd rather clean up the test to avoid argc/argv than support two > > paths through the test, one with argc/argv, one without. > > > > jeff > > I'll leave fixing the tests to Balaji then instead of doing it myself since > that way > he can be sure that they are testing what he wants to test. OK, I will look into this. -Balaji V. Iyer. > > Steve Ellcey > sell...@mips.com >
Re: [c++-concepts]
On 06/01/2013 10:57 AM, Gabriel Dos Reis wrote: Well, we don't want to check cxx0x one place and cxx11 others. But we still do. I'd rather fix that all together in a separate patch than mess with it in this context. Jason
Re: [PATCH, libcpp] Do not decrease highest_location if the included file has be included twice.
On Mon, Jun 3, 2013 at 11:46 AM, Dodji Seketeli wrote: > Dehao Chen a écrit: > >> Thanks for looking into this. > > You are welcome. Libcpp is fun. Is it not? :-) It truly is ;-) > >> The reason a test is missing is that it would need a super large >> source file to reproduce the problem. > > I see. It's kind of a pity that we cannot have tests for interesting > cases like this, though. I am wondering if with some #line tricks (like > setting #line we couldn't simulate that. I > haven't tried myself though. The problem is it's not about the line number, but number of lines. We need to have no less than 10M lines in one module in order for this problem to show up. (and the parsing itself takes several minutes on a powerful machine) > >> However, if you apply the attached patch, you can reproduce the >> problem with attached testcase: >> >> g++ a.cpp -g -S -c -o a.s >> >> in a.s, the linenos are off-by-one. > > Thanks. > >> The root cause is that highest_location-- should not happen when the >> header file is not gonna be read. In should_stack file, there is >> following check: >> >> /* Skip if the file had a header guard and the macro is defined. >> PCH relies on this appearing before the PCH handler below. */ >> if (file->cmacro && file->cmacro->type == NT_MACRO) >> return false; >> >> Thus we should add it back to _cpp_stack_include too. > > Yeah, I figured that out. What I didn't get is how the column number > disabling thing was interacting with this > >> The problem was hidden when column number is used because >> highest_location is updated in linemap_position_for_column. However, >> when linemap are too large, it disables columns and do not update the >> highest_location. > > Gotcha. Thank you for the insight. > > So, I'd say that in this hunk of your patch: > >> @@ -1002,7 +1002,8 @@ _cpp_stack_include (cpp_reader *pfile, const char >> linemap_add is not called) or we were included from the >> command-line. */ >>if (file->pchname == NULL && file->err_no == 0 >> - && type != IT_CMDLINE && type != IT_DEFAULT) >> + && type != IT_CMDLINE && type != IT_DEFAULT >> + && !(file->cmacro && file->cmacro->type == NT_MACRO)) > > Maybe you should test: > > && should_stack_file (pfile, file, type == IT_IMPORT) > > rather than testing the last conjunction you added? This is because > there are many conditions that could make the header to not be loaded, > besides the one you are testing. Would this work in your environment? I tried to apply this change, but it failed several PCH related regression tests. I still haven't look into why because those tests are hard to reproduce... Dehao > > If that works, maybe add a comment to : > > /* Compensate for the increment in linemap_add that occurs in > _cpp_stack_file. ... */ > > Saying that the compensation should happen when _cpp_stack_file really > stacks the file, that is, when should_stack_file returns true; this does > not seem obvious. At least not to me. :-) > > Cheers. > > -- > Dodji
RE: [PATCH] Handle MIPS EVA
> -Original Message-
> From: Richard Sandiford [mailto:rdsandif...@googlemail.com]
> Sent: Monday, June 03, 2013 2:28 PM
> To: Moore, Catherine
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] Handle MIPS EVA
>
> "Moore, Catherine" writes:
> > Index: config/mips/mips.opt
> >
> ==
> =
> > --- config/mips/mips.opt(revision 199610)
> > +++ config/mips/mips.opt(working copy)
> > @@ -141,6 +141,10 @@ membedded-data
> > Target Report Var(TARGET_EMBEDDED_DATA) Use ROM instead of RAM
> >
> > +meva
> > +Target Report Var(TARGET_EVA)
> > +Use microMIPS32/MIPS32 Enhanced VA instructions
>
> This is likely to get out of date if EVA is ever extended to MIPS64.
> It's probably easier just to drop the "microMIPS32/MIPS32" bit.
Now done, plus incorporated Maciej's suggestion.
>
> > Index: config/mips/mips.h
> >
> ==
> =
> > --- config/mips/mips.h (revision 199610)
> > +++ config/mips/mips.h (working copy)
> > @@ -399,6 +399,11 @@ struct mips_cpu_info {
> >if (TARGET_MCU)
> > \
> > builtin_define ("__mips_mcu");
> \
> > \
> > + if (TARGET_EVA)
> > \
> > + { \
> > + builtin_define ("__mips_eva");\
> > + } \
> > + \
>
> This should be:
>
> if (TARGET_EVA) \
> builtin_define ("__mips_eva"); \
>
> You need to document the option too.
>
Also done.
Okay, now?
2013-06-03 Catherine Moore
gcc/
* config/mips/mips.opt (meva): New.
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS):
Define __mips_eva.
(ASM_SPEC): Handle -meva.
* doc/invoke.texi (meva): Document.
gcc.eva.patch
Description: gcc.eva.patch
Re: [PATCH] Basic support for MIPS r5900
Hello Richard, > Thanks, looks good. The comments I have are only minor and seemed easier > to spell out as a revised patch, attached below. The changes are: > > * removing the config.sub bit, which looked redundant. We already have > the up-to-date upstream config.sub. > > * removing the target_cpu_default setting. I realise this was taken > from mips64-elf, but it was redundant here, there, and elsewhere. > I've just committed a patch to remove the existing cases. > > * removing the TUNE_5900 definition. I prefer not to define these > kinds of macro until they're used. > > * removing the ISA_HAS_LDC1_SDC1 setting. I realise what you did > describes the reality of the processor, but the problem is that > the patch doesn't provide an alternative for 64-bit loads and > stores when -mfp64 is used. That combination also isn't rejected, > so we're likely to get an internal compiler error instead. > > This change shouldn't affect the soft-float case you describe. > It also shouldn't be important for the single-float code. > > * tweaking the mips_reorg_process_insns comment slightly > > * fixing a few minor formatting issues > > Does this version look OK to you? I'll commit it if so. This is OK and the generated code is still working on the PS2 in my test run. > > How much other changes will be currently accepted here? There is other > > stuff which I want to prepare and submit here, e.g.: > > 1. disable use of dmult and ddiv (ABI n32). > > 2. use trunc.w.s instead of cvt.w.s (to get single float working for > > normal range calculations; i.e. calculating without inf or nan). > > 3. fix use of ll/sc in libgomp, either increase mips ISA level or use > > syscall (which is broken in Linux 2.6.35.4). > > 4. fix libgcc to build a real muldi3 function for ABI n32 (not the > > multi3 function which is stored in muldi3.o file). > > 5. add support for configure parameters --float=single and > > --float=double in addition to --float=soft and --float=hard. > > 6. rework floating point to support single float with ABI n32 (either > > break the ABI or store floating point values in general purpose > > registers like soft float). > > 7. change libgcc or mips.md in way so that the non IEEE 754 compatible > > FPU of the r5900 gets compatible. > > Well, I'm afraid that's hard to say in advance. It really depends > on what the changes look like. (1) and (2) sound harmless enough, > although (1) should probably only be done in conjunction with (4). > I'm not sure what (3) involves. (5) sounds like a good idea. > (6) is worth doing, but anything ABI-related gets extra-paranoid > treatment. :-) > > I'm not sure about (7) though. I'd imagine trying to get true IEEE > conformance out of the R5900 FPU would be pretty difficult and carry > quite a bit of runtime overhead, especially with the subnormal handling. > Is it really worth it? Do you have any particular use cases in mind? My target was to get existing C programs working (e.g. all mipsel programs from Debian 5 or 6, all mips64el programs from Fedora 12 or 13). The programs should work like programs on normal mipsel or mips64el Linux. I don't know what in the different programs is used. > FWIW, the Cygnus/Red Hat version of the port just stuck with the R5900 > behaviour and made GCC understand it (MODE_HAS_* & various other bits). > This code was then updated and extended for the SPU. I'd have expected > the support to be in reasonably good shape because of the SPU. I assume that you mean the cell processor of the PS3 and not the Sound Processing Unit of the PS2. The macros MODE_HAS_* in the GCC look promising. Best regards Jürgen
[PATCH] libffi documentation fix
This patch from libffi revision 675c9839224 allows libffi.pdf to be
generated without tex related errors. I tested it on gcc trunk. Please
backport it to gcc. The original patch can be found here:
http://sourceware.org/ml/libffi-discuss/2013/msg00086.html
Cesar
2013-06-03 Andreas Schwab
* doc/libffi.texi (Structures): Fix missing category argument of
@deftp.
Index: libffi/doc/libffi.texi
===
--- libffi/doc/libffi.texi (revision 199458)
+++ libffi/doc/libffi.texi (working copy)
@@ -360,7 +360,7 @@
new @code{ffi_type} object for it.
@tindex ffi_type
-@deftp ffi_type
+@deftp {Data type} ffi_type
The @code{ffi_type} has the following members:
@table @code
@item size_t size
Added build_c_cast to c-family?
Hello Everyone, Is it OK to move build_c_cast prototype into c-common.h? The reason for this is that, I would like to share some of the code between array notation for C and C++ and this function is sort of required for both places. Also, the exact same call is available for both C and C++ with the same parameters at the same locations. The change involves removing the prototype from c-tree.h and cp-tree.h and moving it to c-common.h. Here is the changelogs and the patch to accomplish what I am requesting. Please let me know if it is OK for the trunk. gcc/c-family/ChangeLog 2013-06-03 Balaji V. Iyer * c-common.h (build_c_cast): Added new extern prototype. gcc/c/ChangeLog 2013-06-03 Balaji V. Iyer * c-tree.h (build_c_cast): Remove prototype. gcc/cp/ChangeLog 2013-06-03 Balaji V. Iyer * c-tree.h (build_c_cast): Remove prototype. Index: gcc/c-family/c-common.h === --- gcc/c-family/c-common.h (revision 199630) +++ gcc/c-family/c-common.h (working copy) @@ -538,6 +538,7 @@ extern tree pushdecl (tree); extern tree build_modify_expr (location_t, tree, tree, enum tree_code, location_t, tree, tree); +extern tree build_c_cast (location_t, tree, tree); extern tree build_array_notation_expr (location_t, tree, tree, enum tree_code, location_t, tree, tree); extern tree build_array_notation_ref (location_t, tree, tree, tree, tree, tree); Index: gcc/c/c-tree.h === --- gcc/c/c-tree.h (revision 199630) +++ gcc/c/c-tree.h (working copy) @@ -600,7 +600,6 @@ tree, tree); extern tree build_compound_expr (location_t, tree, tree); extern tree c_cast_expr (location_t, struct c_type_name *, tree); -extern tree build_c_cast (location_t, tree, tree); extern void store_init_value (location_t, tree, tree, tree); extern void error_init (const char *); extern void pedwarn_init (location_t, int opt, const char *); Index: gcc/cp/cp-tree.h === --- gcc/cp/cp-tree.h(revision 199630) +++ gcc/cp/cp-tree.h(working copy) @@ -6000,7 +6000,6 @@ extern tree build_static_cast (tree, tree, tsubst_flags_t); extern tree build_reinterpret_cast (tree, tree, tsubst_flags_t); extern tree build_const_cast (tree, tree, tsubst_flags_t); -extern tree build_c_cast (location_t, tree, tree); extern tree cp_build_c_cast(tree, tree, tsubst_flags_t); extern tree build_x_modify_expr(location_t, tree, enum tree_code, tree, Thanks, Balaji V. Iyer.
Re: [GOOGLE] More strict checking for call args
Hi,
This patch was committed to google branch. But I think it is of
general interest. So is it ok for trunk?
Thanks,
Dehao
gcc/ChangeLog:
2013-06-03 Dehao Chen
*gimple-low.c (gimple_check_call_args): Restrict the call_arg check to
contain same number of args.
Index: gcc/gimple-low.c
===
--- gcc/gimple-low.c (revision 199570)
+++ gcc/gimple-low.c (working copy)
@@ -243,6 +243,8 @@ gimple_check_call_args (gimple stmt, tree fndecl)
&& !fold_convertible_p (DECL_ARG_TYPE (p), arg)))
return false;
}
+ if (p != NULL)
+ return false;
}
else if (parms)
{
Re: [PATCH] Handle MIPS EVA
"Moore, Catherine" writes: > @@ -16376,6 +16377,12 @@ Use (do not use) MT Multithreading instructions. > @opindex mno-mcu > Use (do not use) the MIPS MCU ASE instructions. > > +@item -meva > +@itemx -mno-eva > +@opindex meva > +@opindex mno-eva > +Use (do not use) the MIPS EVA instructions. Please spell it out here too, for consistency: Use (do not use) the MIPS Enhanced Virtual Addressing instructions. OK with that change, thanks. Richard
