[gcc r15-274] tree-optimization/110490 - bitcount for narrow modes

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e1f56c67a82172730c377a96a46e8d75445e6a48

commit r15-274-ge1f56c67a82172730c377a96a46e8d75445e6a48
Author: Stefan Schulze Frielinghaus 
Date:   Tue May 7 14:12:55 2024 +0200

tree-optimization/110490 - bitcount for narrow modes

Bitcount operations popcount, clz, and ctz are emulated for narrow modes
in case an operation is only supported for wider modes.  Beside that ctz
may be emulated via clz in expand_ctz.  Reflect this in
expression_expensive_p.

I considered the emulation of ctz via clz as not expensive since this
basically reduces to ctz (x) = c - (clz (x & ~x)) where c is the mode
precision minus 1 which should be faster than a loop.

gcc/ChangeLog:

PR tree-optimization/110490
* tree-scalar-evolution.cc (expression_expensive_p): Also
consider mode widening for popcount, clz, and ctz.

Diff:
---
 gcc/tree-scalar-evolution.cc | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/gcc/tree-scalar-evolution.cc b/gcc/tree-scalar-evolution.cc
index b0a5e09a77c..622c7246c1b 100644
--- a/gcc/tree-scalar-evolution.cc
+++ b/gcc/tree-scalar-evolution.cc
@@ -3458,6 +3458,28 @@ bitcount_call:
  && (optab_handler (optab, word_mode)
  != CODE_FOR_nothing))
  break;
+ /* If popcount is available for a wider mode, we emulate the
+operation for a narrow mode by first zero-extending the value
+and then computing popcount in the wider mode.  Analogue for
+ctz.  For clz we do the same except that we additionally have
+to subtract the difference of the mode precisions from the
+result.  */
+ if (is_a  (mode, &int_mode))
+   {
+ machine_mode wider_mode_iter;
+ FOR_EACH_WIDER_MODE (wider_mode_iter, mode)
+   if (optab_handler (optab, wider_mode_iter)
+   != CODE_FOR_nothing)
+ goto check_call_args;
+ /* Operation ctz may be emulated via clz in expand_ctz.  */
+ if (optab == ctz_optab)
+   {
+ FOR_EACH_WIDER_MODE_FROM (wider_mode_iter, mode)
+   if (optab_handler (clz_optab, wider_mode_iter)
+   != CODE_FOR_nothing)
+ goto check_call_args;
+   }
+   }
  return true;
}
  break;
@@ -3469,6 +3491,7 @@ bitcount_call:
  break;
}
 
+check_call_args:
   FOR_EACH_CALL_EXPR_ARG (arg, iter, expr)
if (expression_expensive_p (arg, cond_overflow_p, cache, op_cost))
  return true;

[gcc r15-319] tree-ssa-loop-prefetch.cc: Honour -fno-unroll-loops

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e755f478c24c3e99409936af545ac83d35d27ad9

commit r15-319-ge755f478c24c3e99409936af545ac83d35d27ad9
Author: Stefan Schulze Frielinghaus 
Date:   Wed May 8 10:48:45 2024 +0200

tree-ssa-loop-prefetch.cc: Honour -fno-unroll-loops

This fixes a couple of tests (gcc.dg/vect/pr109011-*.c) on s390 where
loops are unrolled although -fno-unroll-loops is specified.

gcc/ChangeLog:

* tree-ssa-loop-prefetch.cc (determine_unroll_factor): Honour
-fno-unroll-loops.

Diff:
---
 gcc/tree-ssa-loop-prefetch.cc | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/tree-ssa-loop-prefetch.cc b/gcc/tree-ssa-loop-prefetch.cc
index 70073cc4fe46..bb5d5dec7795 100644
--- a/gcc/tree-ssa-loop-prefetch.cc
+++ b/gcc/tree-ssa-loop-prefetch.cc
@@ -1401,6 +1401,10 @@ determine_unroll_factor (class loop *loop, struct 
mem_ref_group *refs,
   struct mem_ref_group *agp;
   struct mem_ref *ref;
 
+  /* Bail out early in case we must not unroll loops.  */
+  if (!flag_unroll_loops)
+return 1;
+
   /* First check whether the loop is not too large to unroll.  We ignore
  PARAM_MAX_UNROLL_TIMES, because for small loops, it prevented us
  from unrolling them enough to make exactly one cache line covered by each

[gcc r15-3602] s390: Fix strict_low_part generation

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:9ebc9fbdddfe1ec85355b068354315a4da8e1ca0

commit r15-3602-g9ebc9fbdddfe1ec85355b068354315a4da8e1ca0
Author: Stefan Schulze Frielinghaus 
Date:   Thu Sep 12 13:29:43 2024 +0200

s390: Fix strict_low_part generation

In s390_expand_insv(), if generating code for ICM et al. src is a MEM
and gen_lowpart might force src into a register such that we end up with
patterns which do not match anymore.  Use adjust_address() instead in
order to preserve a MEM.

Furthermore, it is not straight forward to enforce a subreg.  For
example, in case of a paradoxical subreg, gen_lowpart() may return a
register.  In order to compensate this, s390_gen_lowpart_subreg() emits
a reference to a pseudo which does not coincide with its definition
which is wrong.  Additionally, if dest is a paradoxical subreg, then do
not try to emit a strict_low_part since it could mean that dest was not
initialized even though this might be fixed up later by init-regs.

Splitter for insn *get_tp_64, *zero_extendhisi2_31,
*zero_extendqisi2_31, *zero_extendqihi2_31 are applied after reload.
Thus, operands[0] is a hard register and gen_lowpart (m, operands[0])
just returns the hard register for mode m which is fine to use as an
argument for strict_low_part, i.e., we do not need to enforce subregs
here since after reload subregs are supposed to be eliminated anyway.

This fixes gcc.dg/torture/pr111821.c.

gcc/ChangeLog:

* config/s390/s390-protos.h (s390_gen_lowpart_subreg): Remove.
* config/s390/s390.cc (s390_gen_lowpart_subreg): Remove.
(s390_expand_insv): Use adjust_address() and emit a
strict_low_part only in case of a natural subreg.
* config/s390/s390.md: Use gen_lowpart() instead of
s390_gen_lowpart_subreg().

Diff:
---
 gcc/config/s390/s390-protos.h |  1 -
 gcc/config/s390/s390.cc   | 47 +--
 gcc/config/s390/s390.md   | 13 ++--
 3 files changed, 20 insertions(+), 41 deletions(-)

diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index b4646ccb6060..e7ac59d17daa 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -50,7 +50,6 @@ extern void s390_set_has_landing_pad_p (bool);
 extern bool s390_hard_regno_rename_ok (unsigned int, unsigned int);
 extern int s390_class_max_nregs (enum reg_class, machine_mode);
 extern bool s390_return_addr_from_memory(void);
-extern rtx s390_gen_lowpart_subreg (machine_mode, rtx);
 extern bool s390_fma_allowed_p (machine_mode);
 #if S390_USE_TARGET_ATTRIBUTE
 extern tree s390_valid_target_attribute_tree (tree args,
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 47e1d5adfd99..c1649ca49bd1 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -516,31 +516,6 @@ s390_return_addr_from_memory ()
   return cfun_gpr_save_slot(RETURN_REGNUM) == SAVE_SLOT_STACK;
 }
 
-/* Generate a SUBREG for the MODE lowpart of EXPR.
-
-   In contrast to gen_lowpart it will always return a SUBREG
-   expression.  This is useful to generate STRICT_LOW_PART
-   expressions.  */
-rtx
-s390_gen_lowpart_subreg (machine_mode mode, rtx expr)
-{
-  rtx lowpart = gen_lowpart (mode, expr);
-
-  /* There might be no SUBREG in case it could be applied to the hard
- REG rtx or it could be folded with a paradoxical subreg.  Bring
- it back.  */
-  if (!SUBREG_P (lowpart))
-{
-  machine_mode reg_mode = TARGET_ZARCH ? DImode : SImode;
-  gcc_assert (REG_P (lowpart));
-  lowpart = gen_lowpart_SUBREG (mode,
-   gen_rtx_REG (reg_mode,
-REGNO (lowpart)));
-}
-
-  return lowpart;
-}
-
 /* Return nonzero if it's OK to use fused multiply-add for MODE.  */
 bool
 s390_fma_allowed_p (machine_mode mode)
@@ -7112,15 +7087,21 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
   /* Emit a strict_low_part pattern if possible.  */
   if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
{
- rtx low_dest = s390_gen_lowpart_subreg (smode, dest);
- rtx low_src = gen_lowpart (smode, src);
-
- switch (smode)
+ rtx low_dest = gen_lowpart (smode, dest);
+ if (SUBREG_P (low_dest) && !paradoxical_subreg_p (low_dest))
{
-   case E_QImode: emit_insn (gen_movstrictqi (low_dest, low_src)); 
return true;
-   case E_HImode: emit_insn (gen_movstricthi (low_dest, low_src)); 
return true;
-   case E_SImode: emit_insn (gen_movstrictsi (low_dest, low_src)); 
return true;
-   default: break;
+ poly_int64 offset = GET_MODE_SIZE (mode) - GET_MODE_SIZE (smode);
+ rtx low_src = adjust_address (src, smode, offset);
+ switch (smode)
+   {
+   case E_QImode: emit_insn (gen_movst

[gcc r15-3625] s390: Fix AQ and AR constraints

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1a71ff3b89aadc7fa0af0bca269d74bb23c1a957

commit r15-3625-g1a71ff3b89aadc7fa0af0bca269d74bb23c1a957
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 13 15:05:33 2024 +0200

s390: Fix AQ and AR constraints

Ensure for AQ and AR constraints that the resulting displacement after
adding any positive offset less than the size of the object being
referenced is still valid.

gcc/ChangeLog:

* config/s390/s390.cc (s390_mem_constraint): Check displacement
for AQ and AR constraints.

Diff:
---
 gcc/config/s390/s390.cc | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index c1649ca49bd1..926987113dd4 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3689,6 +3689,18 @@ s390_mem_constraint (const char *str, rtx op)
   if ((reload_completed || reload_in_progress)
  ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
return 0;
+  /* offsettable_memref_p ensures only that any positive offset added to
+the address forms a valid general address.  For AQ and AR constraints
+we also have to verify that the resulting displacement after adding
+any positive offset less than the size of the object being referenced
+is still valid.  */
+  if (str[1] == 'Q' || str[1] == 'R')
+   {
+ int o = GET_MODE_SIZE (GET_MODE (op)) - 1;
+ rtx tmp = adjust_address (op, QImode, o);
+ if (!s390_check_qrst_address (str[1], XEXP (tmp, 0), true))
+   return 0;
+   }
   return s390_check_qrst_address (str[1], XEXP (op, 0), true);
 case 'B':
   /* Check for non-literal-pool variants of memory constraints.  */

[gcc r15-3626] s390: Fix TF to FPRX2 conversion [PR115860]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:46c2538435dfc50dd5c67c4e03ce387d1f6ebe9b

commit r15-3626-g46c2538435dfc50dd5c67c4e03ce387d1f6ebe9b
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 13 15:09:55 2024 +0200

s390: Fix TF to FPRX2 conversion [PR115860]

Currently subregs originating from *tf_to_fprx2_0 and *tf_to_fprx2_1
survive register allocation.  This in turn leads to wrong register
renaming.  Keeping the current approach would mean we need two insns for
*tf_to_fprx2_0 and *tf_to_fprx2_1, respectively.  Something along the
lines

(define_insn "*tf_to_fprx2_0"
  [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0)
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "#")

(define_insn "*tf_to_fprx2_0"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "vpdi\t%v0,%v1,%v0,1
  [(set_attr "op_type" "VRR")])

and similar for *tf_to_fprx2_1.  Note, pre register allocation operand 0
has mode FPRX2 and afterwards DF once subregs have been eliminated.

Since we always copy a whole vector register into a floating-point
register pair, another way to fix this is to merge *tf_to_fprx2_0 and
*tf_to_fprx2_1 into a single insn which means we don't have to use
subregs at all.  The downside of this is that the assembler template
contains two instructions, now.  The upside is that we don't have to
come up with some artificial insn before RA which might be more
readable/maintainable.  That is implemented by this patch.

In commit r11-4872-ge627cda5686592, the output operand specifier %V was
introduced which is used in tf_to_fprx2 only, now.  Instead of coming up
with its counterpart %F for floating-point registers, which would also
only be used in tf_to_fprx2, I print the operands directly.  This
renders %V unused which is why it is removed by this patch.

gcc/ChangeLog:

PR target/115860
* config/s390/s390.cc (print_operand): Remove operand specifier
%V.
* config/s390/s390.md (UNSPEC_TF_TO_FPRX2): New.
* config/s390/vector.md (*tf_to_fprx2_0): Remove.
(*tf_to_fprx2_1): Remove.
(tf_to_fprx2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/long-double-asm-abi.c: Adapt
scan-assembler directive.
* gcc.target/s390/vector/long-double-to-i64.c: Adapt
scan-assembler directive.
* gcc.target/s390/pr115860-1.c: New test.

Diff:
---
 gcc/config/s390/s390.cc|  5 +-
 gcc/config/s390/s390.md|  2 +
 gcc/config/s390/vector.md  | 75 --
 gcc/testsuite/gcc.target/s390/pr115860-1.c | 26 
 .../gcc.target/s390/vector/long-double-asm-abi.c   |  2 +-
 .../gcc.target/s390/vector/long-double-to-i64.c|  2 -
 6 files changed, 72 insertions(+), 40 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 926987113dd4..c9172d1153ac 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -8600,7 +8600,6 @@ print_operand_address (FILE *file, rtx addr)
 't': CONST_INT: "start" of contiguous bitmask X in SImode.
 'x': print integer X as if it's an unsigned halfword.
 'v': print register number as vector register (v1 instead of f1).
-'V': print the second word of a TFmode operand as vector register.
 */
 
 void
@@ -8854,13 +8853,13 @@ print_operand (FILE *file, rtx x, int code)
 case REG:
   /* Print FP regs as fx instead of vx when they are accessed
 through non-vector mode.  */
-  if ((code == 'v' || code == 'V')
+  if (code == 'v'
  || VECTOR_NOFP_REG_P (x)
  || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x)))
  || (VECTOR_REG_P (x)
  && (GET_MODE_SIZE (GET_MODE (x)) /
  s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8))
-   fprintf (file, "%%v%s", reg_names[REGNO (x) + (code == 'V')] + 2);
+   fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2);
   else
fprintf (file, "%s", reg_names[REGNO (x)]);
   break;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 592cf62d9623..4a225ae24f33 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -241,6 +241,8 @@
UNSPEC_VEC_VFMIN
UNSPEC_VEC_VFMAX
 
+   UNSPEC_TF_TO_FPRX2
+
UNSPEC_NNPA_VCLFNHS_V8HI
UNSPEC_NNPA_VCLFNLS_V8HI
UNSPEC_NNPA_VCRNFS_V8HI
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index a75b7cb58257..e6f83d07de27 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -907,36 +907,45 @@
   "vmrlg\t%0,%1,%2";
   [

[gcc r15-1695] s390: Check for ADDR_REGS in s390_decompose_addrstyle_without_index

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:187eeb99ec5289538923668de9d61a3138376817

commit r15-1695-g187eeb99ec5289538923668de9d61a3138376817
Author: Stefan Schulze Frielinghaus 
Date:   Thu Jun 27 15:46:24 2024 +0200

s390: Check for ADDR_REGS in s390_decompose_addrstyle_without_index

An explicit check for address registers was not required so far since
during register allocation the processing of address constraints was
sufficient.  However, address constraints themself do not check for
REGNO_OK_FOR_{BASE,INDEX}_P.  Thus, with the newly introduced
late-combine pass in r15-1579-g792f97b44ffc5e we generate new insns with
invalid address registers which aren't fixed up afterwards.

Fixed by explicitly checking for address registers in
s390_decompose_addrstyle_without_index such that those new insns are
rejected.

gcc/ChangeLog:

PR target/115634
* config/s390/s390.cc (s390_decompose_addrstyle_without_index):
Check for ADDR_REGS in s390_decompose_addrstyle_without_index.

Diff:
---
 gcc/config/s390/s390.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index c65421de831..05a0fde7fb0 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3347,7 +3347,9 @@ s390_decompose_addrstyle_without_index (rtx op, rtx *base,
   while (op && GET_CODE (op) == SUBREG)
 op = SUBREG_REG (op);
 
-  if (op && GET_CODE (op) != REG)
+  if (op && (!REG_P (op)
+|| (reload_completed
+&& !REGNO_OK_FOR_BASE_P (REGNO (op)
 return false;
 
   if (offset)

[gcc r15-1999] s390: Align *cjump_64 and *icjump_64

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d

commit r15-1999-g56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jul 12 13:27:08 2024 +0200

s390: Align *cjump_64 and *icjump_64

During machine reorg we optimize backward jumps and transform insns as
e.g.

(jump_insn 118 117 119 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(label_ref 134)
(pc))) "dec_math_1.f90":204:8 discrim 1 2161 {*cjump_64}
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 134)

into

(jump_insn 118 117 432 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(pc)
(label_ref 433))) "dec_math_1.f90":204:8 discrim 1 -1
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 433)

The latter is not recognized anymore since *icjump_64 only matches
CC_REGNUM against zero.  Fixed by aligning *cjump_64 and *icjump_64.

gcc/ChangeLog:

* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
i.e., any constant integer between 0 and 15 for CC comparisons.

Diff:
---
 gcc/config/s390/s390.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 1311a5f01cf3..2555006bb4b9 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -9530,7 +9530,8 @@
 (define_insn "*icjump_64"
   [(set (pc)
 (if_then_else
-  (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+  (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
+  (match_operand 2 
"const_int_operand" "")])
   (pc)
   (label_ref (match_operand 0 "" ""]
   ""

[gcc r15-2001] s390: Fix output template for movv1qi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e6680d3f392f7f7cc2a1515276213e21e9eeab1c

commit r15-2001-ge6680d3f392f7f7cc2a1515276213e21e9eeab1c
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jul 12 13:40:19 2024 +0200

s390: Fix output template for movv1qi

Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.

gcc/ChangeLog:

* config/s390/vector.md (mov): Fix output template for
movv1qi.

Diff:
---
 gcc/config/s390/vector.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 40de0c75a7cf..26fd505f2cd9 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -368,8 +368,8 @@
lr\t%0,%1
mvi\t%0,0
mviy\t%0,0
-   mvi\t%0,-1
-   mviy\t%0,-1
+   mvi\t%0,255
+   mviy\t%0,255
lhi\t%0,0
lhi\t%0,-1
llc\t%0,%1

[gcc r15-2002] s390: Fully exploit vgm, vgbm, vrepi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:61715e9340ab8941d40d62158fe437e9dbe3e068

commit r15-2002-g61715e9340ab8941d40d62158fe437e9dbe3e068
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jul 12 13:42:08 2024 +0200

s390: Fully exploit vgm, vgbm, vrepi

Currently instructions vgm and vrepi are utilized only for constant
vectors where the element mode equals the element mode of the
corresponding instruction.  This patch lifts this restriction by making
use of those instructions for constant vectors even if element modes
do not coincide.  For example, the constant vector

  (v2di){0x7ffe7ffe, 0x7ffe7ffe}

can be loaded via vgmf %v0,1,30.  Similar, the constant vector

  (v4si){0x, 0x, 0x, 0x}

can be loaded via vrepiq %v0,-86.

Analog, if the element mode of a constant vector is smaller than the
element mode of a corresponding instruction, we still may make use of
those instructions.  For example, the constant vector

  (v4si){0x7fff, 0xfffe, 0x7fff, 0xfffe}

can be loaded via vgmg %v0,17,46.  Similar, the constant vector

  (v4si){-1, -16643, -1, -16643}

can be loaded via vrepig %v0,-16643.

Additionally this patch enables vgm, vgbm, vrepi for partial vectors,
i.e., vectors of size less than 16 bytes.  Basically this is done by
treating a vector as a full vector resulting in replicating constants
into the ignored bits whereas vgbm sets those to zero.

Furthermore, there is no restriction to integer vectors anymore, i.e.,
supporting scalars of mode up to and including TI and TF and also
floating-point vectors.

Here are some numbers how often instructions are emitted for SPEC 2017:

w/o patch w/ patch
vgbm  140  365
vgm 1750824452
vrepi1360 2775

I expect most (maybe even all) to save us a load from the literal pool.

gcc/ChangeLog:

* config/s390/2964.md: Remove extended mnemonics for vgm.
* config/s390/3906.md: Remove extended mnemonics for vgm.
* config/s390/3931.md: Remove extended mnemonics for vgm.
* config/s390/8561.md: Remove extended mnemonics for vgm.
* config/s390/constraints.md (jKK): Remove constraint.
(jzz): Add constraint.
* config/s390/s390-protos.h (s390_contiguous_bitmask_vector_p):
Add prototype.
(s390_constant_via_vgm_p): Add prototype.
(s390_constant_via_vrepi_p): Add prototype.
* config/s390/s390.cc (s390_contiguous_bitmask_vector_p): New
function.
(s390_constant_via_vgm_vrepi_helper): New function.
(s390_constant_via_vgm_p): New function.
(s390_constant_via_vgbm_p): For the sake of symmetry rename
s390_bytemask_vector_p into s390_constant_via_vgbm_p.
(s390_bytemask_vector_p): Deal with non-integer and partial
vectors.
(s390_constant_via_vrepi_p): New function.
(s390_legitimate_constant_p): Allow partial vectors.
(legitimate_reload_constant_p): Fix indentation.
(legitimate_reload_vector_constant_p): Restrict to constraints
j00, jm1, jxx, jyy, jzz only, i.e., allow partial vectors.
(s390_expand_vec_init): Also make use of vrepi if possible.
(print_operand): Add q,p,r for vgm,vrepi,vgbm, respectively.
Remove e,s,t for constant vectors.
* config/s390/s390.md (movti): Add variants utilizing
vgbm,vgm,vrepi.
* config/s390/vector.md (mov): Adapt variants
for vgbm,vgm,vrepi for the new scheme.
(mov): Adapt variants for vgbm,vgm for the new
scheme and add vrepi variant for modes V_8,V_16,V_32,V_64.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-copysign.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vec-genmask-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vec-init-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vec-vrepi-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/zvector/autovec-double-quiet-uneq.c: Change to
non-extended mnemonic.
* gcc.target/s390/zvector/autovec-float-quiet-uneq.c: Change to
non-extended mnemonic.
* gcc.target/s390/zvector/vec-genmask-1.c: Change to
non-extended mnemonic.
* gcc.target/s390/zvector/vec-splat-1.c: Change to non-extended
mnemonic.
* gcc.target/s390/zvector/vec-splat-2.c: Change to non-extended
mnemonic.
* gcc.target/s390/vector/vgbm-double-1.c: New test.
* gcc.target/s390/vector/vgbm-

[gcc r14-10415] s390: Align *cjump_64 and *icjump_64

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:cd11413ff7c4353a3e336db415304f788d23a393

commit r14-10415-gcd11413ff7c4353a3e336db415304f788d23a393
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 13 08:01:51 2024 +0200

s390: Align *cjump_64 and *icjump_64

During machine reorg we optimize backward jumps and transform insns as
e.g.

(jump_insn 118 117 119 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(label_ref 134)
(pc))) "dec_math_1.f90":204:8 discrim 1 2161 {*cjump_64}
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 134)

into

(jump_insn 118 117 432 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(pc)
(label_ref 433))) "dec_math_1.f90":204:8 discrim 1 -1
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 433)

The latter is not recognized anymore since *icjump_64 only matches
CC_REGNUM against zero.  Fixed by aligning *cjump_64 and *icjump_64.

gcc/ChangeLog:

* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
i.e., any constant integer between 0 and 15 for CC comparisons.

(cherry picked from commit 56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d)

Diff:
---
 gcc/config/s390/s390.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index c607dce3cf0f..202aeb39d692 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -9526,7 +9526,8 @@
 (define_insn "*icjump_64"
   [(set (pc)
 (if_then_else
-  (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+  (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
+  (match_operand 2 
"const_int_operand" "")])
   (pc)
   (label_ref (match_operand 0 "" ""]
   ""

[gcc r14-10416] s390: Fix output template for movv1qi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:5ade7afdefe7a5179c6a139103885c2cf911d9d0

commit r14-10416-g5ade7afdefe7a5179c6a139103885c2cf911d9d0
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 13 08:01:59 2024 +0200

s390: Fix output template for movv1qi

Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.

gcc/ChangeLog:

* config/s390/vector.md (mov): Fix output template for
movv1qi.

(cherry picked from commit e6680d3f392f7f7cc2a1515276213e21e9eeab1c)

Diff:
---
 gcc/config/s390/vector.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index ed4742d93c91..7577f979243f 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -359,8 +359,8 @@
lr\t%0,%1
mvi\t%0,0
mviy\t%0,0
-   mvi\t%0,-1
-   mviy\t%0,-1
+   mvi\t%0,255
+   mviy\t%0,255
lhi\t%0,0
lhi\t%0,-1
llc\t%0,%1

[gcc r15-2056] s390: Emulate vec_cmp{eq,gt,gtu} for 128-bit integers

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1b575bb24a7a3d2b00197dd5deb4c26b313f442b

commit r15-2056-g1b575bb24a7a3d2b00197dd5deb4c26b313f442b
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 10:41:41 2024 +0200

s390: Emulate vec_cmp{eq,gt,gtu} for 128-bit integers

Mode iterator V_HW enables V1TI for target VXE which means
vec_cmpv1tiv1ti becomes available which leads to an ICE since there is
no corresponding insn.

Fixed by emulating comparisons and enabling mode V1TI unconditionally
for V_HW.  For the sake of symmetry, I also added TI mode to V_HW since
TF mode is already included.  As a consequence the consumers of V_HW
vec_{splat,slb,sld,sldw,sldb,srdb,srab,srb,test_mask_int,test_mask}
also become available for 128-bit integers.

This fixes gcc.c-torture/execute/pr105613.c and gcc.dg/pr106063.c.

gcc/ChangeLog:

* config/s390/vector.md (V_HW): Enable V1TI unconditionally and
add TI.
(vec_cmpu): Add 128-bit integer
variants.
(*vec_cmpeq_nocc_emu): Emulate operation.
(*vec_cmpgt_nocc_emu): Emulate operation.
(*vec_cmpgtu_nocc_emu): Emulate operation.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-cmp-emu-1.c: New test.
* gcc.target/s390/vector/vec-cmp-emu-2.c: New test.
* gcc.target/s390/vector/vec-cmp-emu-3.c: New test.

Diff:
---
 gcc/config/s390/vector.md  | 113 ++---
 .../gcc.target/s390/vector/vec-cmp-emu-1.c |  35 +++
 .../gcc.target/s390/vector/vec-cmp-emu-2.c |  18 
 .../gcc.target/s390/vector/vec-cmp-emu-3.c |  17 
 4 files changed, 171 insertions(+), 12 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 636788596574..756011728938 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -30,7 +30,7 @@
 ; V_HW2 is for having two iterators expanding independently e.g. vcond.
 ; It's similar to V_HW, but not fully identical: V1TI is not included, because
 ; there are no 128-bit compares.
-(define_mode_iterator V_HW  [V16QI V8HI V4SI V2DI (V1TI "TARGET_VXE") V2DF
+(define_mode_iterator V_HW  [V16QI V8HI V4SI V2DI V1TI TI V2DF
 (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")
 (TF "TARGET_VXE")])
 (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")
@@ -50,6 +50,7 @@
 (define_mode_iterator VI_HW_HSDT [V8HI V4SI V2DI V1TI TI])
 (define_mode_iterator VI_HW_HS  [V8HI  V4SI])
 (define_mode_iterator VI_HW_QH  [V16QI V8HI])
+(define_mode_iterator VI_HW_T   [V1TI TI])
 
 ; Directly supported vector modes with a certain number of elements
 (define_mode_iterator V_HW_2   [V2DI V2DF])
@@ -151,7 +152,7 @@
(V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI 
"V8HI")
(V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI")
(V1DI "V1DI") (V2DI "V2DI")
-   (V1TI "V1TI")
+   (V1TI "V1TI") (TI "V1TI")
(V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI")
(V1DF "V1DI") (V2DF "V2DI")
(V1TF "V1TI") (TF "V1TI")])
@@ -160,7 +161,7 @@
(V1HI "v1hi") (V2HI "v2hi") (V4HI "v4hi") (V8HI 
"v8hi")
(V1SI "v1si") (V2SI "v2si") (V4SI "v4si")
(V1DI "v1di") (V2DI "v2di")
-   (V1TI "v1ti")
+   (V1TI "v1ti") (TI "v1ti")
(V1SF "v1si") (V2SF "v2si") (V4SF "v4si")
(V1DF "v1di") (V2DF "v2di")
(V1TF "v1ti") (TF   "v1ti")])
@@ -1960,11 +1961,11 @@
   DONE;
 })
 
-(define_expand "vec_cmpu"
-  [(set (match_operand:VI_HW0 "register_operand" "")
-   (match_operator:VI_HW   1 ""
- [(match_operand:VI_HW 2 "register_operand" "")
-  (match_operand:VI_HW 3 "register_operand" "")]))]
+(define_expand "vec_cmpu"
+  [(set (match_operand:VIT_HW0 "register_operand" "")
+   (match_operator:VIT_HW   1 ""
+ [(match_operand:VIT_HW 2 "register_operand" "")
+  (match_operand:VIT_HW 3 "register_operand" "")]))]
   "TARGET_VX"
 {
   s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], 
operands[3]);
@@ -1979,6 +1980,94 @@
   "vc\t%v2,%v0,%v1"
   [(set_attr "op_type" "VRR")])
 
+(define_insn_and_split "*vec_cmpeq_nocc_emu"
+  [(set (match_operand:VI_HW_T 0 "register_operand" "=v")
+   (eq:VI_HW_T (match_operand:VI_HW_T 1 "register_operand"  "v")
+   (match_operand:VI_HW_T 2 "register_operand"  "v")))]
+  "TARGET_VX"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(set (match_dup 3)
+   (eq:V2DI (match_dup 1) (match_dup 2)))
+   (set (match_dup 4)
+   (vec_select:V2DI (match_dup 3) (parall

[gcc r15-2058] s390: Drop vcond{,u} expanders

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:75c0bf997d2808561451e62aa6b7ae7c8e32b9e9

commit r15-2058-g75c0bf997d2808561451e62aa6b7ae7c8e32b9e9
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 10:41:52 2024 +0200

s390: Drop vcond{,u} expanders

Optabs vcond{,u} will be removed for GCC 15.  Since regtest shows no
fallout, dropping the expanders, now.

gcc/ChangeLog:

PR target/114189
* config/s390/vector.md (V_HW2): Remove.
(vcond): Remove.
(vcondu): Remove.

Diff:
---
 gcc/config/s390/vector.md | 35 ---
 1 file changed, 35 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index c8e8029167d3..69efbbb61acd 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -27,14 +27,9 @@
V2SF V4SF V1DF V2DF V1TF V1TI TI])
 
 ; All modes directly supported by the hardware having full vector reg size
-; V_HW2 is for having two iterators expanding independently e.g. vcond.
-; It's similar to V_HW, but not fully identical: V1TI is not included, because
-; there are no 128-bit compares.
 (define_mode_iterator V_HW  [V16QI V8HI V4SI V2DI V1TI TI V2DF
 (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")
 (TF "TARGET_VXE")])
-(define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")
-(V1TF "TARGET_VXE") (TF "TARGET_VXE")])
 
 (define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF])
 (define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF])
@@ -729,36 +724,6 @@
 }
 })
 
-(define_expand "vcond"
-  [(set (match_operand:V_HW 0 "register_operand" "")
-   (if_then_else:V_HW
-(match_operator 3 "vcond_comparison_operator"
-[(match_operand:V_HW2 4 "register_operand" "")
- (match_operand:V_HW2 5 "nonmemory_operand" "")])
-(match_operand:V_HW 1 "nonmemory_operand" "")
-(match_operand:V_HW 2 "nonmemory_operand" "")))]
-  "TARGET_VX && GET_MODE_NUNITS (mode) == GET_MODE_NUNITS 
(mode)"
-{
-  s390_expand_vcond (operands[0], operands[1], operands[2],
-GET_CODE (operands[3]), operands[4], operands[5]);
-  DONE;
-})
-
-(define_expand "vcondu"
-  [(set (match_operand:V_HW 0 "register_operand" "")
-   (if_then_else:V_HW
-(match_operator 3 "comparison_operator"
-[(match_operand:V_HW2 4 "register_operand" "")
- (match_operand:V_HW2 5 "nonmemory_operand" "")])
-(match_operand:V_HW 1 "nonmemory_operand" "")
-(match_operand:V_HW 2 "nonmemory_operand" "")))]
-  "TARGET_VX && GET_MODE_NUNITS (mode) == GET_MODE_NUNITS 
(mode)"
-{
-  s390_expand_vcond (operands[0], operands[1], operands[2],
-GET_CODE (operands[3]), operands[4], operands[5]);
-  DONE;
-})
-
 (define_expand "vcond_mask_"
   [(set (match_operand:VT 0 "register_operand" "")
(if_then_else:VT

[gcc r15-2057] s390: Enable vcond_mask for 128-bit ops

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:6d1095788e23c27061421c7d180209264ebb32f7

commit r15-2057-g6d1095788e23c27061421c7d180209264ebb32f7
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 10:41:46 2024 +0200

s390: Enable vcond_mask for 128-bit ops

In preparation of dropping vcond{,u,eq} optabs
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/654690.html
enable 128-bit operands for vcond_mask---including integer as well as
floating point.

This fixes partially PR115519 w.r.t. autovec-long-double-signaling-*.c
tests.

gcc/ChangeLog:

* config/s390/vector.md: Enable vcond_mask for 128-bit ops.

Diff:
---
 gcc/config/s390/vector.md | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 756011728938..c8e8029167d3 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -760,12 +760,12 @@
 })
 
 (define_expand "vcond_mask_"
-  [(set (match_operand:V 0 "register_operand" "")
-   (if_then_else:V
+  [(set (match_operand:VT 0 "register_operand" "")
+   (if_then_else:VT
 (eq (match_operand: 3 "register_operand" "")
 (match_dup 4))
-(match_operand:V 2 "register_operand" "")
-(match_operand:V 1 "register_operand" "")))]
+(match_operand:VT 2 "register_operand" "")
+(match_operand:VT 1 "register_operand" "")))]
   "TARGET_VX"
   "operands[4] = CONST0_RTX (mode);")

[gcc r15-2060] s390: Fix unresolved iterators bhfgq and xdee

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:a4abda934aa426137f059934629d3241f008e113

commit r15-2060-ga4abda934aa426137f059934629d3241f008e113
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 11:23:10 2024 +0200

s390: Fix unresolved iterators bhfgq and xdee

Code attribute bhfgq is missing a mapping for TF.  This results in
unresolved iterators in assembler templates for *bswaptf.

With the TF mapping added the base mnemonics vlbr and vstbr are not
"used" anymore but only the extended mnemonics (vlbr was
interpreted as vlbr; likewise for vstbr).  Therefore, remove the base
mnemonics from the scheduling description, otherwise, genattrtab would
error about unknown mnemonics.

Similarly, we end up with unresolved iterators in assembler templates
for mulfprx23 since code attribute xdee is missing a mapping for FPRX2.

gcc/ChangeLog:

* config/s390/3931.md (vlbr, vstbr): Remove.
* config/s390/s390.md (xdee): Add FPRX2 mapping.
* config/s390/vector.md (bhfgq): Add TF mapping.

Diff:
---
 gcc/config/s390/3931.md   | 5 -
 gcc/config/s390/s390.md   | 2 +-
 gcc/config/s390/vector.md | 2 +-
 3 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/gcc/config/s390/3931.md b/gcc/config/s390/3931.md
index 632c2456b6a3..9f7a4c58755c 100644
--- a/gcc/config/s390/3931.md
+++ b/gcc/config/s390/3931.md
@@ -404,7 +404,6 @@ vlvgg,
 vlvgh,
 vlvgp,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -627,7 +626,6 @@ tm,
 tmy,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -661,7 +659,6 @@ vlreph,
 vlrl,
 vlrlr,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -2148,7 +2145,6 @@ vistrfs,
 vistrhs,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -2240,7 +2236,6 @@ tbegin,
 tbeginc,
 tend,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 303026f6af7c..3d5759d62521 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -745,7 +745,7 @@
 ;; In FP templates, a  in "mr" will expand to "mxr" in
 ;; TF/TDmode, "mdr" in DF/DDmode, "meer" in SFmode and "mer in
 ;; SDmode.
-(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD 
"e")])
+(define_mode_attr xdee [(TF "x") (FPRX2 "x") (DF "d") (SF "ee") (TD "x") (DD 
"d") (SD "e")])
 
 ;; The decimal floating point variants of add, sub, div and mul support 3
 ;; fp register operands.  The following attributes allow to merge the bfp and
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 69efbbb61acd..a75b7cb58257 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -132,7 +132,7 @@
(V1TI "q") (TI "q")
(V1SF "f") (V2SF "f") (V4SF "f")
(V1DF "g") (V2DF "g")
-   (V1TF "q")])
+   (V1TF "q") (TF "q")])
 
 ; This is for vmalhw. It gets an 'w' attached to avoid confusion with
 ; multiply and add logical high vmalh.

[gcc r13-8917] s390: Align *cjump_64 and *icjump_64

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:544b65cddf296a63dfb91c6ffa4f474ae9d70052

commit r13-8917-g544b65cddf296a63dfb91c6ffa4f474ae9d70052
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 13:59:06 2024 +0200

s390: Align *cjump_64 and *icjump_64

During machine reorg we optimize backward jumps and transform insns as
e.g.

(jump_insn 118 117 119 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(label_ref 134)
(pc))) "dec_math_1.f90":204:8 discrim 1 2161 {*cjump_64}
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 134)

into

(jump_insn 118 117 432 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(pc)
(label_ref 433))) "dec_math_1.f90":204:8 discrim 1 -1
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 433)

The latter is not recognized anymore since *icjump_64 only matches
CC_REGNUM against zero.  Fixed by aligning *cjump_64 and *icjump_64.

gcc/ChangeLog:

* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
i.e., any constant integer between 0 and 15 for CC comparisons.

(cherry picked from commit 56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d)

Diff:
---
 gcc/config/s390/s390.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 00d39608e1d7..50a828f2bbba 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -9480,7 +9480,8 @@
 (define_insn "*icjump_64"
   [(set (pc)
 (if_then_else
-  (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+  (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
+  (match_operand 2 
"const_int_operand" "")])
   (pc)
   (label_ref (match_operand 0 "" ""]
   ""

[gcc r13-8918] s390: Fix output template for movv1qi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1accf7036570cbb0fef9afa595634be03f8c14e8

commit r13-8918-g1accf7036570cbb0fef9afa595634be03f8c14e8
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 13:59:38 2024 +0200

s390: Fix output template for movv1qi

Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.

gcc/ChangeLog:

* config/s390/vector.md (mov): Fix output template for
movv1qi.

(cherry picked from commit e6680d3f392f7f7cc2a1515276213e21e9eeab1c)

Diff:
---
 gcc/config/s390/vector.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 21bec729efa7..1bae1056951c 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -359,8 +359,8 @@
lr\t%0,%1
mvi\t%0,0
mviy\t%0,0
-   mvi\t%0,-1
-   mviy\t%0,-1
+   mvi\t%0,255
+   mviy\t%0,255
lhi\t%0,0
lhi\t%0,-1
llc\t%0,%1

[gcc r12-10619] s390: Align *cjump_64 and *icjump_64

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:06d825719fd4b71c8e3d34fd9756be7f847b

commit r12-10619-g06d825719fd4b71c8e3d34fd9756be7f847b
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 14:01:50 2024 +0200

s390: Align *cjump_64 and *icjump_64

During machine reorg we optimize backward jumps and transform insns as
e.g.

(jump_insn 118 117 119 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(label_ref 134)
(pc))) "dec_math_1.f90":204:8 discrim 1 2161 {*cjump_64}
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 134)

into

(jump_insn 118 117 432 (set (pc)
(if_then_else (ne (reg:CCRAW 33 %cc)
(const_int 8 [0x8]))
(pc)
(label_ref 433))) "dec_math_1.f90":204:8 discrim 1 -1
 (expr_list:REG_DEAD (reg:CCRAW 33 %cc)
(int_list:REG_BR_PROB 719407028 (nil)))
 -> 433)

The latter is not recognized anymore since *icjump_64 only matches
CC_REGNUM against zero.  Fixed by aligning *cjump_64 and *icjump_64.

gcc/ChangeLog:

* config/s390/s390.md (*icjump_64): Allow raw CC comparisons,
i.e., any constant integer between 0 and 15 for CC comparisons.

(cherry picked from commit 56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d)

Diff:
---
 gcc/config/s390/s390.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index aaa247d7612f..5b174e0d866f 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -9472,7 +9472,8 @@
 (define_insn "*icjump_64"
   [(set (pc)
 (if_then_else
-  (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
+  (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
+  (match_operand 2 
"const_int_operand" "")])
   (pc)
   (label_ref (match_operand 0 "" ""]
   ""

[gcc r12-10620] s390: Fix output template for movv1qi

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:9e00ae3e23eef8bff497981e00853ca092772201

commit r12-10620-g9e00ae3e23eef8bff497981e00853ca092772201
Author: Stefan Schulze Frielinghaus 
Date:   Tue Jul 16 14:01:58 2024 +0200

s390: Fix output template for movv1qi

Although for instructions MVI and MVIY it does not make a difference
whether the immediate is interpreted as signed or unsigned, GAS expects
unsigned immediates for instruction format SI_URD.

gcc/ChangeLog:

* config/s390/vector.md (mov): Fix output template for
movv1qi.

(cherry picked from commit e6680d3f392f7f7cc2a1515276213e21e9eeab1c)

Diff:
---
 gcc/config/s390/vector.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 624729814afd..e795b4ffef7f 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -357,8 +357,8 @@
lr\t%0,%1
mvi\t%0,0
mviy\t%0,0
-   mvi\t%0,-1
-   mviy\t%0,-1
+   mvi\t%0,255
+   mviy\t%0,255
lhi\t%0,0
lhi\t%0,-1
llc\t%0,%1

[gcc r14-10482] s390: Fix unresolved iterators bhfgq and xdee

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:bb34b7eda1fbfcfe108d985fd0ae1421c2fa14c0

commit r14-10482-gbb34b7eda1fbfcfe108d985fd0ae1421c2fa14c0
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 20 16:03:33 2024 +0200

s390: Fix unresolved iterators bhfgq and xdee

Code attribute bhfgq is missing a mapping for TF.  This results in
unresolved iterators in assembler templates for *bswaptf.

With the TF mapping added the base mnemonics vlbr and vstbr are not
"used" anymore but only the extended mnemonics (vlbr was
interpreted as vlbr; likewise for vstbr).  Therefore, remove the base
mnemonics from the scheduling description, otherwise, genattrtab would
error about unknown mnemonics.

Likewise, for movtf_vr only the extended mnemonics for vrepi are used,
now, which means the base mnemonic is "unused" and has to be removed
from the scheduling description.

Similarly, we end up with unresolved iterators in assembler templates
for mulfprx23 since code attribute xdee is missing a mapping for FPRX2.

Note, this is basically a cherry pick of commit r15-2060-ga4abda934aa426
with the addition that vrepi is removed from the scheduling description,
too.

gcc/ChangeLog:

* config/s390/3931.md (vlbr, vstbr, vrepi): Remove.
* config/s390/s390.md (xdee): Add FPRX2 mapping.
* config/s390/vector.md (bhfgq): Add TF mapping.

Diff:
---
 gcc/config/s390/3931.md   | 7 ---
 gcc/config/s390/s390.md   | 2 +-
 gcc/config/s390/vector.md | 2 +-
 3 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/gcc/config/s390/3931.md b/gcc/config/s390/3931.md
index 740e0f3718f9..b8e196cf36ce 100644
--- a/gcc/config/s390/3931.md
+++ b/gcc/config/s390/3931.md
@@ -404,7 +404,6 @@ vlvgg,
 vlvgh,
 vlvgp,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -627,7 +626,6 @@ tm,
 tmy,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -661,7 +659,6 @@ vlreph,
 vlrl,
 vlrlr,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -1077,7 +1074,6 @@ vrepb,
 vrepf,
 vrepg,
 vreph,
-vrepi,
 vrepib,
 vrepif,
 vrepig,
@@ -1930,7 +1926,6 @@ vrepb,
 vrepf,
 vrepg,
 vreph,
-vrepi,
 vrepib,
 vrepif,
 vrepig,
@@ -2156,7 +2151,6 @@ vistrfs,
 vistrhs,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -2248,7 +2242,6 @@ tbegin,
 tbeginc,
 tend,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 202aeb39d692..41715f938b33 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -741,7 +741,7 @@
 ;; In FP templates, a  in "mr" will expand to "mxr" in
 ;; TF/TDmode, "mdr" in DF/DDmode, "meer" in SFmode and "mer in
 ;; SDmode.
-(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD 
"e")])
+(define_mode_attr xdee [(TF "x") (FPRX2 "x") (DF "d") (SF "ee") (TD "x") (DD 
"d") (SD "e")])
 
 ;; The decimal floating point variants of add, sub, div and mul support 3
 ;; fp register operands.  The following attributes allow to merge the bfp and
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 7577f979243f..55dc35a71bf5 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -134,7 +134,7 @@
(V1TI "q") (TI "q")
(V1SF "f") (V2SF "f") (V4SF "f")
(V1DF "g") (V2DF "g")
-   (V1TF "q")])
+   (V1TF "q") (TF "q")])
 
 ; This is for vmalhw. It gets an 'w' attached to avoid confusion with
 ; multiply and add logical high vmalh.

[gcc r13-8927] s390: Fix unresolved iterators bhfgq and xdee

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:130edabae09e18064e0bdcb12656e4f4f9a51ff3

commit r13-8927-g130edabae09e18064e0bdcb12656e4f4f9a51ff3
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 20 16:05:41 2024 +0200

s390: Fix unresolved iterators bhfgq and xdee

Code attribute bhfgq is missing a mapping for TF.  This results in
unresolved iterators in assembler templates for *bswaptf.

With the TF mapping added the base mnemonics vlbr and vstbr are not
"used" anymore but only the extended mnemonics (vlbr was
interpreted as vlbr; likewise for vstbr).  Therefore, remove the base
mnemonics from the scheduling description, otherwise, genattrtab would
error about unknown mnemonics.

Likewise, for movtf_vr only the extended mnemonics for vrepi are used,
now, which means the base mnemonic is "unused" and has to be removed
from the scheduling description.

Similarly, we end up with unresolved iterators in assembler templates
for mulfprx23 since code attribute xdee is missing a mapping for FPRX2.

Note, this is basically a cherry pick of commit r15-2060-ga4abda934aa426
with the addition that vrepi is removed from the scheduling description,
too.

gcc/ChangeLog:

* config/s390/3931.md (vlbr, vstbr, vrepi): Remove.
* config/s390/s390.md (xdee): Add FPRX2 mapping.
* config/s390/vector.md (bhfgq): Add TF mapping.

Diff:
---
 gcc/config/s390/3931.md   | 7 ---
 gcc/config/s390/s390.md   | 2 +-
 gcc/config/s390/vector.md | 2 +-
 3 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/gcc/config/s390/3931.md b/gcc/config/s390/3931.md
index bed1f6c21f1f..9cb11b72bba3 100644
--- a/gcc/config/s390/3931.md
+++ b/gcc/config/s390/3931.md
@@ -404,7 +404,6 @@ vlvgg,
 vlvgh,
 vlvgp,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -627,7 +626,6 @@ tm,
 tmy,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -661,7 +659,6 @@ vlreph,
 vlrl,
 vlrlr,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -1077,7 +1074,6 @@ vrepb,
 vrepf,
 vrepg,
 vreph,
-vrepi,
 vrepib,
 vrepif,
 vrepig,
@@ -1930,7 +1926,6 @@ vrepb,
 vrepf,
 vrepg,
 vreph,
-vrepi,
 vrepib,
 vrepif,
 vrepig,
@@ -2156,7 +2151,6 @@ vistrfs,
 vistrhs,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -2248,7 +2242,6 @@ tbegin,
 tbeginc,
 tend,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 50a828f2bbba..8edc1261c381 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -744,7 +744,7 @@
 ;; In FP templates, a  in "mr" will expand to "mxr" in
 ;; TF/TDmode, "mdr" in DF/DDmode, "meer" in SFmode and "mer in
 ;; SDmode.
-(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD 
"e")])
+(define_mode_attr xdee [(TF "x") (FPRX2 "x") (DF "d") (SF "ee") (TD "x") (DD 
"d") (SD "e")])
 
 ;; The decimal floating point variants of add, sub, div and mul support 3
 ;; fp register operands.  The following attributes allow to merge the bfp and
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 1bae1056951c..f88e8b655fa8 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -134,7 +134,7 @@
(V1TI "q") (TI "q")
(V1SF "f") (V2SF "f") (V4SF "f")
(V1DF "g") (V2DF "g")
-   (V1TF "q")])
+   (V1TF "q") (TF "q")])
 
 ; This is for vmalhw. It gets an 'w' attached to avoid confusion with
 ; multiply and add logical high vmalh.

[gcc r12-10627] s390: Fix unresolved iterators bhfgq and xdee

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:7ad764fe3c3ad0e1167b58cf3785629d788491f4

commit r12-10627-g7ad764fe3c3ad0e1167b58cf3785629d788491f4
Author: Stefan Schulze Frielinghaus 
Date:   Sat Jul 20 17:13:03 2024 +0200

s390: Fix unresolved iterators bhfgq and xdee

Code attribute bhfgq is missing a mapping for TF.  This results in
unresolved iterators in assembler templates for *bswaptf.

With the TF mapping added the base mnemonics vlbr and vstbr are not
"used" anymore but only the extended mnemonics (vlbr was
interpreted as vlbr; likewise for vstbr).  Therefore, remove the base
mnemonics from the scheduling description, otherwise, genattrtab would
error about unknown mnemonics.

Likewise, for movtf_vr only the extended mnemonics for vrepi are used,
now, which means the base mnemonic is "unused" and has to be removed
from the scheduling description.

Similarly, we end up with unresolved iterators in assembler templates
for mulfprx23 since code attribute xdee is missing a mapping for FPRX2.

Note, this is basically a cherry pick of commit r15-2060-ga4abda934aa426
with the addition that vrepi is removed from the scheduling description,
too.

gcc/ChangeLog:

* config/s390/3931.md (vlbr, vstbr, vrepi): Remove.
* config/s390/s390.md (xdee): Add FPRX2 mapping.
* config/s390/vector.md (bhfgq): Add TF mapping.

Diff:
---
 gcc/config/s390/3931.md   | 7 ---
 gcc/config/s390/s390.md   | 2 +-
 gcc/config/s390/vector.md | 2 +-
 3 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/gcc/config/s390/3931.md b/gcc/config/s390/3931.md
index bc97bc50b786..ecd290abc083 100644
--- a/gcc/config/s390/3931.md
+++ b/gcc/config/s390/3931.md
@@ -404,7 +404,6 @@ vlvgg,
 vlvgh,
 vlvgp,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -627,7 +626,6 @@ tm,
 tmy,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -661,7 +659,6 @@ vlreph,
 vlrl,
 vlrlr,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
@@ -1077,7 +1074,6 @@ vrepb,
 vrepf,
 vrepg,
 vreph,
-vrepi,
 vrepib,
 vrepif,
 vrepig,
@@ -1930,7 +1926,6 @@ vrepb,
 vrepf,
 vrepg,
 vreph,
-vrepi,
 vrepib,
 vrepif,
 vrepig,
@@ -2156,7 +2151,6 @@ vistrfs,
 vistrhs,
 vl,
 vlbb,
-vlbr,
 vlbrf,
 vlbrg,
 vlbrh,
@@ -2248,7 +2242,6 @@ tbegin,
 tbeginc,
 tend,
 vst,
-vstbr,
 vstbrf,
 vstbrg,
 vstbrh,
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 5b174e0d866f..b8dcf2bb58a8 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -745,7 +745,7 @@
 ;; In FP templates, a  in "mr" will expand to "mxr" in
 ;; TF/TDmode, "mdr" in DF/DDmode, "meer" in SFmode and "mer in
 ;; SDmode.
-(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD 
"e")])
+(define_mode_attr xdee [(TF "x") (FPRX2 "x") (DF "d") (SF "ee") (TD "x") (DD 
"d") (SD "e")])
 
 ;; The decimal floating point variants of add, sub, div and mul support 3
 ;; fp register operands.  The following attributes allow to merge the bfp and
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index e795b4ffef7f..75912280c23d 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -134,7 +134,7 @@
(V1TI "q") (TI "q")
(V1SF "f") (V2SF "f") (V4SF "f")
(V1DF "g") (V2DF "g")
-   (V1TF "q")])
+   (V1TF "q") (TF "q")])
 
 ; This is for vmalhw. It gets an 'w' attached to avoid confusion with
 ; multiply and add logical high vmalh.

[gcc r14-9448] s390: Deprecate some vector builtins

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:b59f0c9c5a4838658dd2a1db58ac09d9f3be0f51

commit r14-9448-gb59f0c9c5a4838658dd2a1db58ac09d9f3be0f51
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 13 10:59:02 2024 +0100

s390: Deprecate some vector builtins

According to IBM Open XL C/C++ for z/OS version 1.1 builtins

- vec_permi
- vec_ctd
- vec_ctsl
- vec_ctul
- vec_ld2f
- vec_st2f

are deprecated.  Also deprecate helper builtins vec_ctd_s64 and
vec_ctd_u64.

Furthermore, the overloads of vec_insert which make use of a bool vector
are deprecated, too.

gcc/ChangeLog:

* config/s390/s390-builtins.def (vec_permi): Deprecate.
(vec_ctd): Deprecate.
(vec_ctd_s64): Deprecate.
(vec_ctd_u64): Deprecate.
(vec_ctsl): Deprecate.
(vec_ctul): Deprecate.
(vec_ld2f): Deprecate.
(vec_st2f): Deprecate.
(vec_insert): Deprecate overloads with bool vectors.

Diff:
---
 gcc/config/s390/s390-builtins.def | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 680a038fa4b..54f400ceb5a 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -416,16 +416,16 @@ B_DEF  (s390_vec_splat_s64, vec_splatsv2di,   
  0,
 OB_DEF (s390_vec_insert,s390_vec_insert_s8, 
s390_vec_insert_dbl,B_VX,   BT_FN_OV4SI_INT_OV4SI_INT)
 OB_DEF_VAR (s390_vec_insert_s8, s390_vlvgb, 0, 
 O3_ELEM,BT_OV_V16QI_SCHAR_V16QI_INT)
 OB_DEF_VAR (s390_vec_insert_u8, s390_vlvgb, 0, 
 O3_ELEM,BT_OV_UV16QI_UCHAR_UV16QI_INT)
-OB_DEF_VAR (s390_vec_insert_b8, s390_vlvgb, 0, 
 O3_ELEM,BT_OV_UV16QI_UCHAR_BV16QI_INT)
+OB_DEF_VAR (s390_vec_insert_b8, s390_vlvgb, B_DEP, 
 O3_ELEM,BT_OV_UV16QI_UCHAR_BV16QI_INT)
 OB_DEF_VAR (s390_vec_insert_s16,s390_vlvgh, 0, 
 O3_ELEM,BT_OV_V8HI_SHORT_V8HI_INT)
 OB_DEF_VAR (s390_vec_insert_u16,s390_vlvgh, 0, 
 O3_ELEM,BT_OV_UV8HI_USHORT_UV8HI_INT)
-OB_DEF_VAR (s390_vec_insert_b16,s390_vlvgh, 0, 
 O3_ELEM,BT_OV_UV8HI_USHORT_BV8HI_INT)
+OB_DEF_VAR (s390_vec_insert_b16,s390_vlvgh, B_DEP, 
 O3_ELEM,BT_OV_UV8HI_USHORT_BV8HI_INT)
 OB_DEF_VAR (s390_vec_insert_s32,s390_vlvgf, 0, 
 O3_ELEM,BT_OV_V4SI_INT_V4SI_INT)
 OB_DEF_VAR (s390_vec_insert_u32,s390_vlvgf, 0, 
 O3_ELEM,BT_OV_UV4SI_UINT_UV4SI_INT)
-OB_DEF_VAR (s390_vec_insert_b32,s390_vlvgf, 0, 
 O3_ELEM,BT_OV_UV4SI_UINT_BV4SI_INT)
+OB_DEF_VAR (s390_vec_insert_b32,s390_vlvgf, B_DEP, 
 O3_ELEM,BT_OV_UV4SI_UINT_BV4SI_INT)
 OB_DEF_VAR (s390_vec_insert_s64,s390_vlvgg, 0, 
 O3_ELEM,BT_OV_V2DI_LONGLONG_V2DI_INT)
 OB_DEF_VAR (s390_vec_insert_u64,s390_vlvgg, 0, 
 O3_ELEM,BT_OV_UV2DI_ULONGLONG_UV2DI_INT)
-OB_DEF_VAR (s390_vec_insert_b64,s390_vlvgg, 0, 
 O3_ELEM,BT_OV_UV2DI_ULONGLONG_BV2DI_INT)
+OB_DEF_VAR (s390_vec_insert_b64,s390_vlvgg, B_DEP, 
 O3_ELEM,BT_OV_UV2DI_ULONGLONG_BV2DI_INT)
 OB_DEF_VAR (s390_vec_insert_flt,s390_vlvgf_flt, B_VXE, 
 O3_ELEM,BT_OV_V4SF_FLT_V4SF_INT) /* vlvgf */
 OB_DEF_VAR (s390_vec_insert_dbl,s390_vlvgg_dbl, 0, 
 O3_ELEM,BT_OV_V2DF_DBL_V2DF_INT) /* vlvgg */
 
@@ -658,7 +658,7 @@ OB_DEF_VAR (s390_vec_perm_dbl,  s390_vperm, 
0,
 
 B_DEF  (s390_vperm, vec_permv16qi,  0, 
 B_VX,   0,  BT_FN_UV16QI_UV16QI_UV16QI_UV16QI)
 
-OB_DEF (s390_vec_permi, s390_vec_permi_s64, 
s390_vec_permi_dbl, B_VX,   BT_FN_OV4SI_OV4SI_OV4SI_INT)
+OB_DEF (s390_vec_permi, s390_vec_permi_s64, 
s390_vec_permi_dbl, B_DEP | B_VX,   BT_FN_OV4SI_OV4SI_OV4SI_INT)
 OB_DEF_VAR (s390_vec_permi_s64, s390_vpdi,  0, 
 O3_U2,  BT_OV_V2DI_V2DI_V2DI_INT)
 OB_DEF_VAR (s390_vec_permi_b64, s390_vpdi,  0, 
 O3_U2,  BT_OV_BV2DI_BV2DI_BV2DI_INT)
 OB_DEF_VAR (s390_vec_permi_u64, s390_vpdi,  0, 
 O3_U2,  BT_OV_UV2DI_UV2DI_UV2DI_INT)
@@ -2806,7 +2806,7 @@ OB_DEF (s390_vec_any_ngt,   
s390_vec_any_ngt_flt,s390_vec_any_ngt_db
 OB_DEF_VAR (s390_

[gcc r14-9449] s390: Streamline vector builtins with LLVM

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:9f2b16ce1efef0648a6d52c1d744735c46e2eec1

commit r14-9449-g9f2b16ce1efef0648a6d52c1d744735c46e2eec1
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 13 11:03:02 2024 +0100

s390: Streamline vector builtins with LLVM

Similar as to s390_lcbb, s390_vll, s390_vstl, et al. make use of a
signed vector type for vlbb.  Furthermore, a const void pointer seems
more common and an integer for the mask.

For s390_vfi(s,d)b make use of integers for masks, too.

Use unsigned integers for all s390_vlbr/vstbr variants.

Make use of type UV16QI for the length operand of s390_vstrs(,z)(h,f).

Following the Principles of Operation, change from signed to unsigned
type for s390_va(c,cc,ccc)q and s390_vs(,c,bc)biq and s390_vmslg.

Make use of scalar type UINT128 instead of UV16QI for s390_vgfm(,a)g,
and s390_vsumq(f,g).

gcc/ChangeLog:

* config/s390/s390-builtin-types.def: Update to reflect latest
changes.
* config/s390/s390-builtins.def: Streamline vector builtins with
LLVM.

Diff:
---
 gcc/config/s390/s390-builtin-types.def | 23 +---
 gcc/config/s390/s390-builtins.def  | 48 +-
 2 files changed, 37 insertions(+), 34 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 556104e0e23..d70eaade8ea 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -69,6 +69,7 @@ DEF_TYPE (BT_SHORTCONST, short_integer_type_node, 1)
 DEF_TYPE (BT_UCHAR, unsigned_char_type_node, 0)
 DEF_TYPE (BT_UCHARCONST, unsigned_char_type_node, 1)
 DEF_TYPE (BT_UINT, unsigned_type_node, 0)
+DEF_TYPE (BT_UINT128, unsigned_intTI_type_node, 0)
 DEF_TYPE (BT_UINT64, c_uint64_type_node, 0)
 DEF_TYPE (BT_UINTCONST, unsigned_type_node, 1)
 DEF_TYPE (BT_ULONG, long_unsigned_type_node, 0)
@@ -83,7 +84,6 @@ DEF_VECTOR_TYPE (BT_UV2DI, BT_ULONGLONG, 2)
 DEF_VECTOR_TYPE (BT_UV4SI, BT_UINT, 4)
 DEF_VECTOR_TYPE (BT_UV8HI, BT_USHORT, 8)
 DEF_VECTOR_TYPE (BT_V16QI, BT_SCHAR, 16)
-DEF_VECTOR_TYPE (BT_V1TI, BT_INT128, 1)
 DEF_VECTOR_TYPE (BT_V2DF, BT_DBL, 2)
 DEF_VECTOR_TYPE (BT_V2DI, BT_LONGLONG, 2)
 DEF_VECTOR_TYPE (BT_V4SF, BT_FLT, 4)
@@ -114,9 +114,11 @@ DEF_POINTER_TYPE (BT_VOIDCONSTPTR, BT_VOIDCONST)
 DEF_POINTER_TYPE (BT_VOIDPTR, BT_VOID)
 DEF_DISTINCT_TYPE (BT_BCHAR, BT_UCHAR)
 DEF_DISTINCT_TYPE (BT_BINT, BT_UINT)
+DEF_DISTINCT_TYPE (BT_BINT128, BT_UINT128)
 DEF_DISTINCT_TYPE (BT_BLONGLONG, BT_ULONGLONG)
 DEF_DISTINCT_TYPE (BT_BSHORT, BT_USHORT)
 DEF_OPAQUE_VECTOR_TYPE (BT_BV16QI, BT_BCHAR, 16)
+DEF_OPAQUE_VECTOR_TYPE (BT_BV1TI, BT_BINT128, 1)
 DEF_OPAQUE_VECTOR_TYPE (BT_BV2DI, BT_BLONGLONG, 2)
 DEF_OPAQUE_VECTOR_TYPE (BT_BV4SI, BT_BINT, 4)
 DEF_OPAQUE_VECTOR_TYPE (BT_BV8HI, BT_BSHORT, 8)
@@ -131,6 +133,7 @@ DEF_FN_TYPE_1 (BT_FN_INT_VOIDPTR, BT_INT, BT_VOIDPTR)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_INT, BT_OV4SI, BT_INT)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_INTCONSTPTR, BT_OV4SI, BT_INTCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI)
+DEF_FN_TYPE_1 (BT_FN_UINT128_UINT128, BT_UINT128, BT_UINT128)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UCHAR, BT_UV16QI, BT_UCHAR)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UCHARCONSTPTR, BT_UV16QI, BT_UCHARCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_USHORT, BT_UV16QI, BT_USHORT)
@@ -154,7 +157,6 @@ DEF_FN_TYPE_1 (BT_FN_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI)
 DEF_FN_TYPE_1 (BT_FN_V16QI_SCHAR, BT_V16QI, BT_SCHAR)
 DEF_FN_TYPE_1 (BT_FN_V16QI_UCHAR, BT_V16QI, BT_UCHAR)
 DEF_FN_TYPE_1 (BT_FN_V16QI_V16QI, BT_V16QI, BT_V16QI)
-DEF_FN_TYPE_1 (BT_FN_V1TI_V1TI, BT_V1TI, BT_V1TI)
 DEF_FN_TYPE_1 (BT_FN_V2DF_DBL, BT_V2DF, BT_DBL)
 DEF_FN_TYPE_1 (BT_FN_V2DF_DBLCONSTPTR, BT_V2DF, BT_DBLCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_V2DF_FLTCONSTPTR, BT_V2DF, BT_FLTCONSTPTR)
@@ -207,18 +209,18 @@ DEF_FN_TYPE_2 (BT_FN_OV4SI_OV4SI_OV4SI, BT_OV4SI, 
BT_OV4SI, BT_OV4SI)
 DEF_FN_TYPE_2 (BT_FN_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_OV4SI_OV4SI_ULONG, BT_OV4SI, BT_OV4SI, BT_ULONG)
 DEF_FN_TYPE_2 (BT_FN_UCHAR_UV16QI_INT, BT_UCHAR, BT_UV16QI, BT_INT)
+DEF_FN_TYPE_2 (BT_FN_UINT128_UINT128_UINT128, BT_UINT128, BT_UINT128, 
BT_UINT128)
+DEF_FN_TYPE_2 (BT_FN_UINT128_UV2DI_UV2DI, BT_UINT128, BT_UV2DI, BT_UV2DI)
+DEF_FN_TYPE_2 (BT_FN_UINT128_UV4SI_UV4SI, BT_UINT128, BT_UV4SI, BT_UV4SI)
 DEF_FN_TYPE_2 (BT_FN_UINT_UV4SI_INT, BT_UINT, BT_UV4SI, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_UINT_VOIDCONSTPTR_INT, BT_UINT, BT_VOIDCONSTPTR, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_ULONGLONG_UV2DI_INT, BT_ULONGLONG, BT_UV2DI, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_USHORT_UV8HI_INT, BT_USHORT, BT_UV8HI, BT_INT)
-DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHARCONSTPTR_USHORT, BT_UV16QI, BT_UCHARCONSTPTR, 
BT_USHORT)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR_INT, BT_UV16QI, BT_UCHAR, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR_UCHAR, BT_UV16QI, BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_2 

[gcc r14-9450] s390: Fix tests rosbg_si_srl and rxsbg_si_srl

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:a63fb786f8564880c91a30b99fda6d8a44adf81d

commit r14-9450-ga63fb786f8564880c91a30b99fda6d8a44adf81d
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 13 11:05:08 2024 +0100

s390: Fix tests rosbg_si_srl and rxsbg_si_srl

Starting with r14-2047-gd0e891406b16dc two SI mode tests are optimized
into DI mode.  Thus, the scan-assembler directives fail.  For example
RTL expression

(ior:SI (subreg:SI (lshiftrt:DI (reg:DI 69)
(const_int 2 [0x2])) 4)
(subreg:SI (reg:DI 68) 4))

is optimized into

(ior:DI (lshiftrt:DI (reg:DI 69)
(const_int 2 [0x2]))
(reg:DI 68))

Fixed by moving operands into memory in order to enforce SI mode
computation.

Furthermore, in r9-6056-g290dfd9bc7bea2 the starting bit position of the
scan-assembler directive for rosbg was incorrectly set to 32 which
actually should be 32+SHIFT_AMOUNT, i.e., in this particular case 34.

gcc/testsuite/ChangeLog:

* gcc.target/s390/md/rXsbg_mode_sXl.c: Fix tests rosbg_si_srl
and rxsbg_si_srl.

Diff:
---
 gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c 
b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
index ede813818ff..cf454d2783c 100644
--- a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
+++ b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
@@ -22,6 +22,8 @@
 { dg-skip-if "" { *-*-* } { "*" } { "-march=*" } }
 */
 
+unsigned int a, b;
+
 __attribute__ ((noinline)) unsigned int
 si_sll (unsigned int x)
 {
@@ -42,11 +44,11 @@ rosbg_si_sll (unsigned int a, unsigned int b)
 /* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,62,1" 1 } } */
 
 __attribute__ ((noinline)) unsigned int
-rosbg_si_srl (unsigned int a, unsigned int b)
+rosbg_si_srl (void)
 {
   return a | (b >> 2);
 }
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,63,62" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,34,63,62" 1 } } */
 
 __attribute__ ((noinline)) unsigned int
 rxsbg_si_sll (unsigned int a, unsigned int b)
@@ -56,11 +58,11 @@ rxsbg_si_sll (unsigned int a, unsigned int b)
 /* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,62,1" 1 } } */
 
 __attribute__ ((noinline)) unsigned int
-rxsbg_si_srl (unsigned int a, unsigned int b)
+rxsbg_si_srl (void)
 {
   return a ^ (b >> 2);
 }
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,63,62" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,34,63,62" 1 } } */
 
 __attribute__ ((noinline)) unsigned long long
 di_sll (unsigned long long x)
@@ -108,21 +110,21 @@ main (void)
   /* SIMode */
   {
 unsigned int r;
-unsigned int a = 0x12488421u;
-unsigned int b = 0xu;
+a = 0x12488421u;
+b = 0xu;
 unsigned int csll = si_sll (b);
 unsigned int csrl = si_srl (b);
 
 r = rosbg_si_sll (a, b);
 if (r != (a | csll))
   __builtin_abort ();
-r = rosbg_si_srl (a, b);
+r = rosbg_si_srl ();
 if (r != (a | csrl))
   __builtin_abort ();
 r = rxsbg_si_sll (a, b);
 if (r != (a ^ csll))
   __builtin_abort ();
-r = rxsbg_si_srl (a, b);
+r = rxsbg_si_srl ();
 if (r != (a ^ csrl))
   __builtin_abort ();
   }

[gcc r14-9451] s390: Fix TARGET_SECONDARY_RELOAD for non-SYMBOL_REFs

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:4d049fadc25585e336c06e6b60b592f40ddbcc12

commit r14-9451-g4d049fadc25585e336c06e6b60b592f40ddbcc12
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 13 11:07:03 2024 +0100

s390: Fix TARGET_SECONDARY_RELOAD for non-SYMBOL_REFs

RTX X need not necessarily be a SYMBOL_REF and may e.g. be an
UNSPEC_GOTENT for which SYMBOL_FLAG_NOTALIGN2_P fails.

gcc/ChangeLog:

* config/s390/s390.cc (s390_secondary_reload): Guard
SYMBOL_FLAG_NOTALIGN2_P.

Diff:
---
 gcc/config/s390/s390.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index c857b2028f2..e63965578f1 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -4779,7 +4779,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t 
rclass_i,
   if (in_p
  && s390_loadrelative_operand_p (x, &symref, &offset)
  && mode == Pmode
- && !SYMBOL_FLAG_NOTALIGN2_P (symref)
+ && (!SYMBOL_REF_P (symref) || !SYMBOL_FLAG_NOTALIGN2_P (symref))
  && (offset & 1) == 1)
sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
  : CODE_FOR_reloadsi_larl_odd_addend_z10);

[gcc r14-9608] s390: testsuite: Fix abs-4.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:d4ad99b0355bce23524aa0ecb5100b987279de96

commit r14-9608-gd4ad99b0355bce23524aa0ecb5100b987279de96
Author: Stefan Schulze Frielinghaus 
Date:   Fri Mar 22 08:41:39 2024 +0100

s390: testsuite: Fix abs-4.c

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/abs-4.c: On s390 we also have a copysign optab
for long double.  Thus, scan 3 instead of 2 times for it.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/abs-4.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/abs-4.c 
b/gcc/testsuite/gcc.dg/tree-ssa/abs-4.c
index 80fa448df12..4144d1cd954 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/abs-4.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/abs-4.c
@@ -10,8 +10,9 @@ long double abs_ld(long double x) { return 
__builtin_signbit(x) ? x : -x; }
 
 /* __builtin_signbit(x) ? x : -x. Should be convert into - ABS_EXP */
 /* { dg-final { scan-tree-dump-not "signbit" "optimized"} } */
-/* { dg-final { scan-tree-dump-times "= ABS_EXPR" 1 "optimized" { target 
ifn_copysign } } } */
-/* { dg-final { scan-tree-dump-times "= -" 1 "optimized" { target ifn_copysign 
} } } */
-/* { dg-final { scan-tree-dump-times "= \.COPYSIGN" 2 "optimized" { target 
ifn_copysign } } } */
+/* { dg-final { scan-tree-dump-times "= ABS_EXPR" 1 "optimized" { target { 
ifn_copysign && { ! { s390*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times "= -" 1 "optimized" { target { 
ifn_copysign && { ! { s390*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times "= \.COPYSIGN" 2 "optimized" { target { 
ifn_copysign && { ! { s390*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times "= \.COPYSIGN" 3 "optimized" { target { 
ifn_copysign && s390*-*-* } } } } */
 /* { dg-final { scan-tree-dump-times "= ABS_EXPR" 3 "optimized" { target { ! 
ifn_copysign } } } } */
 /* { dg-final { scan-tree-dump-times "= -" 3 "optimized" { target { ! 
ifn_copysign } } } } */

[gcc r14-9615] s390: testsuite: Fix backprop-6.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e0a7233e1d2e617e1913b9873599e7a50bfe1c8f

commit r14-9615-ge0a7233e1d2e617e1913b9873599e7a50bfe1c8f
Author: Stefan Schulze Frielinghaus 
Date:   Fri Mar 22 11:23:24 2024 +0100

s390: testsuite: Fix backprop-6.c

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/backprop-6.c: On s390 we also have a copysign
optab for long double.  Thus, scan 3 instead of 2 times for it.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/backprop-6.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/backprop-6.c 
b/gcc/testsuite/gcc.dg/tree-ssa/backprop-6.c
index 4087ba93018..dbde681e383 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/backprop-6.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/backprop-6.c
@@ -27,8 +27,9 @@ TEST_FUNCTION (float, f)
 TEST_FUNCTION (double, )
 TEST_FUNCTION (long double, l)
 
-/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = -} 4 "backprop" { 
target ifn_copysign } } } */
-/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = \.COPYSIGN} 2 
"backprop" { target ifn_copysign } } } */
-/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = ABS_EXPR <} 1 
"backprop" { target ifn_copysign } } } */
+/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = -} 4 "backprop" { 
target { ifn_copysign && { ! { s390*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = \.COPYSIGN} 2 
"backprop" { target { ifn_copysign && { ! { s390*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = ABS_EXPR <} 1 
"backprop" { target { ifn_copysign && { ! { s390*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times {Deleting[^\n]* = \.COPYSIGN} 3 
"backprop" { target { ifn_copysign && s390*-*-* } } } } */
 /* { dg-final { scan-tree-dump-times {Deleting[^\n]* = -} 6 "backprop" { 
target { ! ifn_copysign } } } } */
 /* { dg-final { scan-tree-dump-times {Deleting[^\n]* = ABS_EXPR <} 3 
"backprop" { target { ! ifn_copysign } } } } */

[gcc r14-9683] testsuite: Fix copy-headers-8.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:291c46a3f0d0355680f94280e955f4faf1cae6f9

commit r14-9683-g291c46a3f0d0355680f94280e955f4faf1cae6f9
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 27 08:50:47 2024 +0100

testsuite: Fix copy-headers-8.c

For targets where LOGICAL_OP_NON_SHORT_CIRCUIT evaluates to false, two
conditional jumps are emitted instead of a combined conditional which
this test is all about.  Thus, set it to true.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/copy-headers-8.c: Set
LOGICAL_OP_NON_SHORT_CIRCUIT to true.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/copy-headers-8.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/copy-headers-8.c 
b/gcc/testsuite/gcc.dg/tree-ssa/copy-headers-8.c
index 8b4b5e7ea81..e35aaf93da8 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/copy-headers-8.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/copy-headers-8.c
@@ -1,5 +1,8 @@
+/* For targets where LOGICAL_OP_NON_SHORT_CIRCUIT evaluates to false, two
+   conditional jumps are emitted instead of a combined conditional which this
+   test is all about.  Thus, set it to true.  */
 /* { dg-do compile } */
-/* { dg-options "-O2 -fdump-tree-ch2-details" } */
+/* { dg-options "-O2 -fdump-tree-ch2-details --param 
logical-op-non-short-circuit=1" } */
 
 int is_sorted(int *a, int n, int m, int k)
 {

[gcc r14-9931] testsuite: Fix loop-interchange-16.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:b6c8259076a336e8082853ed6dda083c25a465d0

commit r14-9931-gb6c8259076a336e8082853ed6dda083c25a465d0
Author: Stefan Schulze Frielinghaus 
Date:   Fri Apr 12 09:20:53 2024 +0200

testsuite: Fix loop-interchange-16.c

Prevent loop unrolling of the innermost loop because otherwise we are
left with no loop interchange for targets like s390 which have a more
aggressive loop unrolling strategy.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/loop-interchange-16.c: Prevent loop unrolling
of the innermost loop.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c 
b/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
index 781555e085d..bbcb14f9c6c 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
@@ -11,6 +11,7 @@ double s231(int iterations)
 //loop with data dependency
 for (int nl = 0; nl < 100*(iterations/LEN_2D); nl++) {
 for (int i = 0; i < LEN_2D; ++i) {
+#pragma GCC unroll 0
 for (int j = 1; j < LEN_2D; j++) {
 aa[j][i] = aa[j - 1][i] + bb[j][i];
 }

[gcc r14-9935] analyzer: Bail out on function pointer for -Wanalyzer-allocation-size

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:67e1433a94f8ca82e2c36b79af44256430c73c38

commit r14-9935-g67e1433a94f8ca82e2c36b79af44256430c73c38
Author: Stefan Schulze Frielinghaus 
Date:   Fri Apr 12 11:06:24 2024 +0200

analyzer: Bail out on function pointer for -Wanalyzer-allocation-size

On s390 pr94688.c is failing due to excess error

pr94688.c:6:5: warning: allocated buffer size is not a multiple of the 
pointee's size [CWE-131] [-Wanalyzer-allocation-size]

This is because on s390 functions are by default aligned to an 8-byte
boundary and during function type construction size is set to function
boundary.  Thus, for the assignment

a.0_1 = (void (*) ()) &a;

we have that the right-hand side is pointing to a 4-byte memory region
whereas the size of the function pointer is 8 byte and a warning is
emitted.

Since -Wanalyzer-allocation-size is not about pointers to code, bail out
early.

gcc/analyzer/ChangeLog:

* region-model.cc (region_model::check_region_size): Bail out
early on function pointers.

Diff:
---
 gcc/analyzer/region-model.cc | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc
index 665873dbe94..bebe2ed3cd6 100644
--- a/gcc/analyzer/region-model.cc
+++ b/gcc/analyzer/region-model.cc
@@ -3514,6 +3514,10 @@ region_model::check_region_size (const region *lhs_reg, 
const svalue *rhs_sval,
   || TYPE_SIZE_UNIT (pointee_type) == NULL_TREE)
 return;
 
+  /* Bail out early on function pointers.  */
+  if (TREE_CODE (pointee_type) == FUNCTION_TYPE)
+return;
+
   /* Bail out early on pointers to structs where we can
  not deduce whether the buffer size is compatible.  */
   bool is_struct = RECORD_OR_UNION_TYPE_P (pointee_type);

[gcc r14-9939] s390: testsuite: Xfail range-sincos.c and vrp-float-abs-1.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:a76f236e084cbd02e4e3711cdfc3191dc7eeb460

commit r14-9939-ga76f236e084cbd02e4e3711cdfc3191dc7eeb460
Author: Stefan Schulze Frielinghaus 
Date:   Fri Apr 12 16:54:38 2024 +0200

s390: testsuite: Xfail range-sincos.c and vrp-float-abs-1.c

As mentioned in PR114678 those failures will be fixed by
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/648303.html
For GCC 14 just xfail them which should be reverted once the patch is
applied.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/range-sincos.c: Xfail for s390.
* gcc.dg/tree-ssa/vrp-float-abs-1.c: Dito.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c| 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c 
b/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
index 337f9cda02f..35b38c3c914 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
@@ -40,4 +40,4 @@ stool (double x)
 link_error ();
 }
 
-// { dg-final { scan-tree-dump-not "link_error" "evrp" { target { { *-*-linux* 
} && { glibc } } } } }
+// { dg-final { scan-tree-dump-not "link_error" "evrp" { target { { *-*-linux* 
} && { glibc } } xfail s390*-*-* } } } xfail: PR114678
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c 
b/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
index 4b7b75833e0..a814a973963 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
@@ -14,4 +14,4 @@ foo (double x, double y)
 }
 }
 
-// { dg-final { scan-tree-dump-not "link_error" "evrp" } }
+// { dg-final { scan-tree-dump-not "link_error" "evrp" { xfail s390*-*-* } } } 
xfail: PR114678

[gcc r14-10066] s390: testsuite: Remove xfail for vpopct{b,h}

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:16aea8c584ea2784a4f5a39352f867506d3441f6

commit r14-10066-g16aea8c584ea2784a4f5a39352f867506d3441f6
Author: Stefan Schulze Frielinghaus 
Date:   Mon Apr 15 15:28:43 2024 +0200

s390: testsuite: Remove xfail for vpopct{b,h}

Starting with r14-9316-g7890836de20912 patterns for vpopct{b,h} are also
detected.  Thus, remove xfails.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vxe/popcount-1.c: Remove xfail.

Diff:
---
 gcc/testsuite/gcc.target/s390/vxe/popcount-1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/s390/vxe/popcount-1.c 
b/gcc/testsuite/gcc.target/s390/vxe/popcount-1.c
index 9ea835a1cf0..25ef354f963 100644
--- a/gcc/testsuite/gcc.target/s390/vxe/popcount-1.c
+++ b/gcc/testsuite/gcc.target/s390/vxe/popcount-1.c
@@ -21,7 +21,7 @@ vpopctb (uv16qi a)
 
   return r;
 }
-/* { dg-final { scan-assembler "vpopctb\t%v24,%v24" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler "vpopctb\t%v24,%v24" } } */
 
 uv8hi __attribute__((noinline))
 vpopcth (uv8hi a)
@@ -34,7 +34,7 @@ vpopcth (uv8hi a)
 
   return r;
 }
-/* { dg-final { scan-assembler "vpopcth\t%v24,%v24" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler "vpopcth\t%v24,%v24" } } */
 
 uv4si __attribute__((noinline))
 vpopctf (uv4si a)

[gcc r14-10090] s390: testsuite: Xfail forwprop-4{0,1}.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:3d5699930fe6cfc595e5a920ab36a1bc065be534

commit r14-10090-g3d5699930fe6cfc595e5a920ab36a1bc065be534
Author: Stefan Schulze Frielinghaus 
Date:   Tue Apr 23 13:29:10 2024 +0200

s390: testsuite: Xfail forwprop-4{0,1}.c

The tests fail on s390 since can_vec_perm_const_p fails and therefore
the bit insert/ref survive which r14-3381-g27de9aa152141e aims for.
Strictly speaking, the tests only fail in case the target supports
vectors, i.e., for targets prior z13 or in case of -mesa the emulated
vector operations are optimized out.

Set to xfail and tracked by PR114802.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/forwprop-40.c: Xfail for s390.
* gcc.dg/tree-ssa/forwprop-41.c: Xfail for s390.
* lib/target-supports.exp: Add target check s390_mvx.

Diff:
---
 gcc/testsuite/gcc.dg/tree-ssa/forwprop-40.c |  4 ++--
 gcc/testsuite/gcc.dg/tree-ssa/forwprop-41.c |  4 ++--
 gcc/testsuite/lib/target-supports.exp   | 14 ++
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-40.c 
b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-40.c
index 7513497f552..0c5233a68f4 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-40.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-40.c
@@ -10,5 +10,5 @@ vector int g(vector int a)
   return a;
 }
 
-/* { dg-final { scan-tree-dump-times "BIT_INSERT_EXPR" 0 "optimized" } } */
-/* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "BIT_INSERT_EXPR" 0 "optimized" { xfail 
s390_mvx } } } Xfail: PR114802 */
+/* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized" { xfail 
s390_mvx } } } Xfail: PR114802 */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-41.c 
b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-41.c
index b1e75797a90..a1f08289dd6 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-41.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-41.c
@@ -11,6 +11,6 @@ vector int g(vector int a, int c)
   return a;
 }
 
-/* { dg-final { scan-tree-dump-times "BIT_INSERT_EXPR" 1 "optimized" } } */
-/* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "BIT_INSERT_EXPR" 1 "optimized" { xfail 
s390_mvx } } } Xfail PR114802 */
+/* { dg-final { scan-tree-dump-times "BIT_FIELD_REF" 0 "optimized" { xfail 
s390_mvx } } } Xfail PR114802 */
 /* { dg-final { scan-tree-dump-times "VEC_PERM_EXPR" 0 "optimized" } } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..3a55b2a4159 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12392,6 +12392,20 @@ proc check_effective_target_profile_update_atomic {} {
 } "-fprofile-update=atomic -fprofile-generate"]
 }
 
+# Return 1 if the target has a vector facility.
+proc check_effective_target_s390_mvx { } {
+if ![istarget s390*-*-*] then {
+   return 0;
+}
+
+return [check_no_compiler_messages_nocache s390_mvx assembly {
+   #if !defined __VX__
+   #error no vector facility.
+   #endif
+   int dummy;
+} [current_compiler_flags]]
+}
+
 # Return 1 if vector (va - vector add) instructions are understood by
 # the assembler and can be executed.  This also covers checking for
 # the VX kernel feature.  A kernel without that feature does not

[gcc r15-100] s390: testsuite: Fix zero_bits_compound-1.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:6c4a745c6910659a75d1881cf3c4128f24b5666f

commit r15-100-g6c4a745c6910659a75d1881cf3c4128f24b5666f
Author: Stefan Schulze Frielinghaus 
Date:   Thu May 2 08:39:32 2024 +0200

s390: testsuite: Fix zero_bits_compound-1.c

Starting with r12-2731-g96146e61cd7aee we do not generate code like

_5 = (unsigned int) c_2(D);
i_6 = _5 << 8;
_7 = _5 << 20;
i_8 = i_6 | _7;

anymore but instead

_5 = (unsigned int) c_2(D);
_3 = _5 * 1048832;

which leads finally to slightly different assembly code where we
previously ended up for z10 or newer with

lr  %r1,%r2
sll %r1,8
rosbg   %r1,%r2,32,43,20
llgfr   %r2,%r1
br  %r14

and now

lr  %r1,%r2
sll %r1,12
ar  %r2,%r1
risbg   %r2,%r2,35,128+55,8
br  %r14

The zero-extend materializes via risbg for which the pattern contains an
"and" which is why the test fails.  Thus, instead of scanning for RTL
expressions rather scan for assembler instructions for s390.

gcc/testsuite/ChangeLog:

* gcc.dg/zero_bits_compound-1.c: Fix for s390.

Diff:
---
 gcc/testsuite/gcc.dg/zero_bits_compound-1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c 
b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
index e71594911b2..f1e267e0fb0 100644
--- a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
+++ b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c
@@ -39,4 +39,5 @@ unsigned long bar (unsigned char c)
 }
 
 /* Check that no pattern containing an AND expression was used.  */
-/* { dg-final { scan-assembler-not "\\(and:" } } */
+/* { dg-final { scan-assembler-not "\\(and:" { target { ! { s390*-*-* } } } } 
} */
+/* { dg-final { scan-assembler-not "\\tng?rk?\\t" { target { s390*-*-* } } } } 
*/

[gcc r15-102] s390: testsuite: Fix risbg-ll-2.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:66f49ccd409c7a3f6eb89dd78e275ab57c983c79

commit r15-102-g66f49ccd409c7a3f6eb89dd78e275ab57c983c79
Author: Stefan Schulze Frielinghaus 
Date:   Thu May 2 08:43:50 2024 +0200

s390: testsuite: Fix risbg-ll-2.c

Starting with r14-2047-gd0e891406b16dc we see through subregs which
means for f10 in risbg-ll-2.c we do not end up with rosbg_si_noshift but
rather rosbg_di_noshift which materializes in slightly different start
index.  This saves us an extend.

gcc/testsuite/ChangeLog:

* gcc.target/s390/risbg-ll-2.c: Fix start offset for rosbg of
f10.

Diff:
---
 gcc/testsuite/gcc.target/s390/risbg-ll-2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c 
b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
index 8bf1a0ff88b..ca80602a83f 100644
--- a/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
+++ b/gcc/testsuite/gcc.target/s390/risbg-ll-2.c
@@ -113,7 +113,7 @@ i32 f9 (i64 v_x, i32 v_y)
 // ands with incompatible masks.
 i32 f10 (i64 v_x, i32 v_y)
 {
-  /* { dg-final { scan-assembler 
"f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,32,39,0" { target { lp64 } } } } */
+  /* { dg-final { scan-assembler 
"f10:\n\tsrlg\t%r2,%r2,48\n\trosbg\t%r2,%r3,0,39,0" { target { lp64 } } } } */
   /* { dg-final { scan-assembler 
"f10:\n\tnilf\t%r4,4278190080\n\trosbg\t%r4,%r2,48,63,48" { target { ! lp64 } } 
} } */
   i64 v_shr6 = ((ui64)v_x) >> 48;
   i32 v_conv = (ui32)v_shr6;

[gcc r15-2918] s390: Fix high-level builtins vec_gfmsum{,_accum}_128

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e8a7142a697c5d2673adea33ba23af82a89c9559

commit r15-2918-ge8a7142a697c5d2673adea33ba23af82a89c9559
Author: Stefan Schulze Frielinghaus 
Date:   Wed Aug 14 20:01:36 2024 +0200

s390: Fix high-level builtins vec_gfmsum{,_accum}_128

Starting with r14-9449-g9f2b16ce1efef0 builtins were streamlined with
those in LLVM.  In particular s390_vgfm{,a}g have been changed from
UV16QI to UINT128 in order to match those in LLVM.  However, these
low-level builtins are directly used by the high-level builtins
vec_gfmsum{,_accum}_128 which expect UV16QI instead.  Therefore,
introduce new low-level builtins s390_vgfm{,a}g_128 and make use of
them, respectively.

gcc/ChangeLog:

* config/s390/s390-builtin-types.def (BT_FN_UV16QI_UV2DI_UV2DI):
New.
(BT_FN_UV16QI_UV2DI_UV2DI_UV16QI): New.
* config/s390/s390-builtins.def (s390_vgfmg_128): New.
(s390_vgfmag_128): New.
* config/s390/vecintrin.h (vec_gfmsum_128): Use s390_vgfmg_128.
(vec_gfmsum_accum_128): Use s390_vgfmag_128.

Diff:
---
 gcc/config/s390/s390-builtin-types.def | 2 ++
 gcc/config/s390/s390-builtins.def  | 2 ++
 gcc/config/s390/vecintrin.h| 4 ++--
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index d70eaade8eab..e6f5631ed7ae 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -221,6 +221,7 @@ DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR_UCHAR, BT_UV16QI, 
BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI)
+DEF_FN_TYPE_2 (BT_FN_UV16QI_UV2DI_UV2DI, BT_UV16QI, BT_UV2DI, BT_UV2DI)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV8HI_UV8HI, BT_UV16QI, BT_UV8HI, BT_UV8HI)
 DEF_FN_TYPE_2 (BT_FN_UV2DI_UCHAR_UCHAR, BT_UV2DI, BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_ULONGLONG, BT_INT)
@@ -299,6 +300,7 @@ DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, 
BT_UV16QI, BT_UCHAR, BT
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_UV16QI)
+DEF_FN_TYPE_3 (BT_FN_UV16QI_UV2DI_UV2DI_UV16QI, BT_UV16QI, BT_UV2DI, BT_UV2DI, 
BT_UV16QI)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_UV2DI, 
BT_ULONGLONG, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, 
BT_INT)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 3a63213e5719..7f6190fa8103 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1666,6 +1666,7 @@ B_DEF  (s390_vgfmb, vec_gfmsumv16qi,  
  0,
 B_DEF  (s390_vgfmh, vec_gfmsumv8hi, 0, 
 B_VX,   0,  BT_FN_UV4SI_UV8HI_UV8HI)
 B_DEF  (s390_vgfmf, vec_gfmsumv4si, 0, 
 B_VX,   0,  BT_FN_UV2DI_UV4SI_UV4SI)
 B_DEF  (s390_vgfmg, vec_gfmsum_128, 0, 
 B_VX,   0,  BT_FN_UINT128_UV2DI_UV2DI)
+B_DEF  (s390_vgfmg_128, vec_gfmsum_128, 0, 
 B_VX,   0,  BT_FN_UV16QI_UV2DI_UV2DI)
 
 OB_DEF (s390_vec_gfmsum_accum,  
s390_vec_gfmsum_accum_u8,s390_vec_gfmsum_accum_u32,B_VX,
BT_FN_OV4SI_OV4SI_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_gfmsum_accum_u8,   s390_vgfmab,0, 
 0,  BT_OV_UV8HI_UV16QI_UV16QI_UV8HI)
@@ -1676,6 +1677,7 @@ B_DEF  (s390_vgfmab,
vec_gfmsum_accumv16qi,0,
 B_DEF  (s390_vgfmah,vec_gfmsum_accumv8hi,0,
 B_VX,   0,  BT_FN_UV4SI_UV8HI_UV8HI_UV4SI)
 B_DEF  (s390_vgfmaf,vec_gfmsum_accumv4si,0,
 B_VX,   0,  BT_FN_UV2DI_UV4SI_UV4SI_UV2DI)
 B_DEF  (s390_vgfmag,vec_gfmsum_accum_128,0,
 B_VX,   0,  BT_FN_UINT128_UV2DI_UV2DI_UINT128)
+B_DEF  (s390_vgfmag_128,vec_gfmsum_accum_128,0,
 B_VX,   0,  BT_FN_UV16QI_UV2DI_UV2DI_UV16QI)
 
 OB_DEF (s390_vec_abs,   s390_vec_abs_s8,s390_vec_abs_dbl,  
 B_VX,   BT_FN_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_abs_s8,s390_vlpb,  0, 
 0,  BT_OV_

[gcc r15-2919] s390: Remove vector intrinsics

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:a247088adaf122116919235f4a40189506139495

commit r15-2919-ga247088adaf122116919235f4a40189506139495
Author: Stefan Schulze Frielinghaus 
Date:   Wed Aug 14 20:01:43 2024 +0200

s390: Remove vector intrinsics

The following intrinsics are not implemented.  Thus, remove them.

gcc/ChangeLog:

* config/s390/vecintrin.h (vec_vstbrh): Remove.
(vec_vstbrf): Remove.
(vec_vstbrg): Remove.
(vec_vstbrq): Remove.
(vec_vstbrf_flt): Remove.
(vec_vstbrg_dbl): Remove.
(vec_vsterb): Remove.
(vec_vsterh): Remove.
(vec_vsterf): Remove.
(vec_vsterg): Remove.
(vec_vsterf_flt): Remove.
(vec_vsterg_dbl): Remove.

Diff:
---
 gcc/config/s390/vecintrin.h | 14 --
 1 file changed, 14 deletions(-)

diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h
index daeed91ef972..de29f913637d 100644
--- a/gcc/config/s390/vecintrin.h
+++ b/gcc/config/s390/vecintrin.h
@@ -160,20 +160,6 @@ __lcbb(const void *ptr, int bndry)
   cc != 3 ? 1 : 0; \
 })
 
-#define vec_vstbrh vec_vlbrh
-#define vec_vstbrf vec_vlbrf
-#define vec_vstbrg vec_vlbrg
-#define vec_vstbrq vec_vlbrq
-#define vec_vstbrf_flt vec_vlbrf_flt
-#define vec_vstbrg_dbl vec_vlbrg_dbl
-
-#define vec_vsterb vec_vlerb
-#define vec_vsterh vec_vlerh
-#define vec_vsterf vec_vlerh
-#define vec_vsterg vec_vlerh
-#define vec_vsterf_flt vec_vlerf_flt
-#define vec_vsterg_dbl vec_vlerg_dbl
-
 #define vec_extend_to_fp32_hi __builtin_s390_vclfnhs
 #define vec_extend_to_fp32_lo __builtin_s390_vclfnls
 #define vec_round_from_fp32 __builtin_s390_vcrnfs

[gcc r14-10582] s390: Fix high-level builtins vec_gfmsum{, _accum}_128

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e903ada5e8881acec734eb3f89c3644bbd8da7e9

commit r14-10582-ge903ada5e8881acec734eb3f89c3644bbd8da7e9
Author: Stefan Schulze Frielinghaus 
Date:   Wed Aug 14 20:12:35 2024 +0200

s390: Fix high-level builtins vec_gfmsum{,_accum}_128

Starting with r14-9449-g9f2b16ce1efef0 builtins were streamlined with
those in LLVM.  In particular s390_vgfm{,a}g have been changed from
UV16QI to UINT128 in order to match those in LLVM.  However, these
low-level builtins are directly used by the high-level builtins
vec_gfmsum{,_accum}_128 which expect UV16QI instead.  Therefore,
introduce new low-level builtins s390_vgfm{,a}g_128 and make use of
them, respectively.

gcc/ChangeLog:

* config/s390/s390-builtin-types.def (BT_FN_UV16QI_UV2DI_UV2DI):
New.
(BT_FN_UV16QI_UV2DI_UV2DI_UV16QI): New.
* config/s390/s390-builtins.def (s390_vgfmg_128): New.
(s390_vgfmag_128): New.
* config/s390/vecintrin.h (vec_gfmsum_128): Use s390_vgfmg_128.
(vec_gfmsum_accum_128): Use s390_vgfmag_128.

(cherry picked from commit e8a7142a697c5d2673adea33ba23af82a89c9559)

Diff:
---
 gcc/config/s390/s390-builtin-types.def | 2 ++
 gcc/config/s390/s390-builtins.def  | 2 ++
 gcc/config/s390/vecintrin.h| 4 ++--
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index d70eaade8eab..e6f5631ed7ae 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -221,6 +221,7 @@ DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR_UCHAR, BT_UV16QI, 
BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI)
+DEF_FN_TYPE_2 (BT_FN_UV16QI_UV2DI_UV2DI, BT_UV16QI, BT_UV2DI, BT_UV2DI)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UV8HI_UV8HI, BT_UV16QI, BT_UV8HI, BT_UV8HI)
 DEF_FN_TYPE_2 (BT_FN_UV2DI_UCHAR_UCHAR, BT_UV2DI, BT_UCHAR, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_ULONGLONG, BT_INT)
@@ -299,6 +300,7 @@ DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, 
BT_UV16QI, BT_UCHAR, BT
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_UV16QI)
+DEF_FN_TYPE_3 (BT_FN_UV16QI_UV2DI_UV2DI_UV16QI, BT_UV16QI, BT_UV2DI, BT_UV2DI, 
BT_UV16QI)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_UV2DI, 
BT_ULONGLONG, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, 
BT_INT)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 3a63213e5719..7f6190fa8103 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1666,6 +1666,7 @@ B_DEF  (s390_vgfmb, vec_gfmsumv16qi,  
  0,
 B_DEF  (s390_vgfmh, vec_gfmsumv8hi, 0, 
 B_VX,   0,  BT_FN_UV4SI_UV8HI_UV8HI)
 B_DEF  (s390_vgfmf, vec_gfmsumv4si, 0, 
 B_VX,   0,  BT_FN_UV2DI_UV4SI_UV4SI)
 B_DEF  (s390_vgfmg, vec_gfmsum_128, 0, 
 B_VX,   0,  BT_FN_UINT128_UV2DI_UV2DI)
+B_DEF  (s390_vgfmg_128, vec_gfmsum_128, 0, 
 B_VX,   0,  BT_FN_UV16QI_UV2DI_UV2DI)
 
 OB_DEF (s390_vec_gfmsum_accum,  
s390_vec_gfmsum_accum_u8,s390_vec_gfmsum_accum_u32,B_VX,
BT_FN_OV4SI_OV4SI_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_gfmsum_accum_u8,   s390_vgfmab,0, 
 0,  BT_OV_UV8HI_UV16QI_UV16QI_UV8HI)
@@ -1676,6 +1677,7 @@ B_DEF  (s390_vgfmab,
vec_gfmsum_accumv16qi,0,
 B_DEF  (s390_vgfmah,vec_gfmsum_accumv8hi,0,
 B_VX,   0,  BT_FN_UV4SI_UV8HI_UV8HI_UV4SI)
 B_DEF  (s390_vgfmaf,vec_gfmsum_accumv4si,0,
 B_VX,   0,  BT_FN_UV2DI_UV4SI_UV4SI_UV2DI)
 B_DEF  (s390_vgfmag,vec_gfmsum_accum_128,0,
 B_VX,   0,  BT_FN_UINT128_UV2DI_UV2DI_UINT128)
+B_DEF  (s390_vgfmag_128,vec_gfmsum_accum_128,0,
 B_VX,   0,  BT_FN_UV16QI_UV2DI_UV2DI_UV16QI)
 
 OB_DEF (s390_vec_abs,   s390_vec_abs_s8,s390_vec_abs_dbl,  
 B_VX,   BT_FN_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_abs_s8,

[gcc r15-787] s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR109549]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:57e04879389f9c0d5d53f316b468ce1bddbab350

commit r15-787-g57e04879389f9c0d5d53f316b468ce1bddbab350
Author: Stefan Schulze Frielinghaus 
Date:   Thu May 23 08:43:35 2024 +0200

s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR109549]

Consider a NOCE conversion as profitable if there is at least one
conditional move.

gcc/ChangeLog:

PR target/109549
* config/s390/s390.cc (TARGET_NOCE_CONVERSION_PROFITABLE_P):
Define.
(s390_noce_conversion_profitable_p): Implement.

gcc/testsuite/ChangeLog:

* gcc.target/s390/ccor.c: Order of loads are reversed, now, as a
consequence the condition has to be reversed.

Diff:
---
 gcc/config/s390/s390.cc  | 32 
 gcc/testsuite/gcc.target/s390/ccor.c |  4 ++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 5968808fcb6..fa517bd3e77 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -78,6 +78,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tree-pass.h"
 #include "context.h"
 #include "builtins.h"
+#include "ifcvt.h"
 #include "rtl-iter.h"
 #include "intl.h"
 #include "tm-constrs.h"
@@ -18037,6 +18038,34 @@ s390_vectorize_vec_perm_const (machine_mode vmode, 
machine_mode op_mode,
   return vectorize_vec_perm_const_1 (d);
 }
 
+/* Consider a NOCE conversion as profitable if there is at least one
+   conditional move.  */
+
+static bool
+s390_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info)
+{
+  if (if_info->speed_p)
+{
+  for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
+   {
+ rtx set = single_set (insn);
+ if (set == NULL)
+   continue;
+ if (GET_CODE (SET_SRC (set)) != IF_THEN_ELSE)
+   continue;
+ rtx src = SET_SRC (set);
+ machine_mode mode = GET_MODE (src);
+ if (GET_MODE_CLASS (mode) != MODE_INT
+ && GET_MODE_CLASS (mode) != MODE_FLOAT)
+   continue;
+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+   continue;
+ return true;
+   }
+}
+  return default_noce_conversion_profitable_p (seq, if_info);
+}
+
 /* Initialize GCC target structure.  */
 
 #undef  TARGET_ASM_ALIGNED_HI_OP
@@ -18350,6 +18379,9 @@ s390_vectorize_vec_perm_const (machine_mode vmode, 
machine_mode op_mode,
 #undef TARGET_VECTORIZE_VEC_PERM_CONST
 #define TARGET_VECTORIZE_VEC_PERM_CONST s390_vectorize_vec_perm_const
 
+#undef TARGET_NOCE_CONVERSION_PROFITABLE_P
+#define TARGET_NOCE_CONVERSION_PROFITABLE_P s390_noce_conversion_profitable_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-s390.h"
diff --git a/gcc/testsuite/gcc.target/s390/ccor.c 
b/gcc/testsuite/gcc.target/s390/ccor.c
index 31f30f60314..36a3c3a999a 100644
--- a/gcc/testsuite/gcc.target/s390/ccor.c
+++ b/gcc/testsuite/gcc.target/s390/ccor.c
@@ -42,7 +42,7 @@ GENFUN1(2)
 
 GENFUN1(3)
 
-/* { dg-final { scan-assembler {locrno} } } */
+/* { dg-final { scan-assembler {locro} } } */
 
 GENFUN2(0,1)
 
@@ -58,7 +58,7 @@ GENFUN2(0,3)
 
 GENFUN2(1,2)
 
-/* { dg-final { scan-assembler {locrnlh} } } */
+/* { dg-final { scan-assembler {locrlh} } } */
 
 GENFUN2(1,3)

[gcc r15-1363] s390: testsuite: Fix ifcvt-one-insn-bool.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:ac66736bf2f8a10d2f43e83ed6377e4179027a39

commit r15-1363-gac66736bf2f8a10d2f43e83ed6377e4179027a39
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:34:34 2024 +0200

s390: testsuite: Fix ifcvt-one-insn-bool.c

With the change of r15-787-g57e04879389f9c I forgot to also update this
test.

gcc/testsuite/ChangeLog:

* gcc.target/s390/ifcvt-one-insn-bool.c: Fix loc.

Diff:
---
 gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c 
b/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c
index 0c8c2f879a69..4ae29dbd6b61 100644
--- a/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c
+++ b/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c
@@ -3,7 +3,7 @@
 /* { dg-do compile { target { s390*-*-* } } } */
 /* { dg-options "-O2 -march=z13 -mzarch" } */
 
-/* { dg-final { scan-assembler "lochinh\t%r.?,1" } } */
+/* { dg-final { scan-assembler "lochile\t%r.?,1" } } */
 #include 
 
 int foo (int *a, unsigned int n)

[gcc r15-1364] s390: testsuite: Fix nobp-table-jump-*.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:0bf3f14e0d79f3258d4e5570216b5d81af6d60ef

commit r15-1364-g0bf3f14e0d79f3258d4e5570216b5d81af6d60ef
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:35:27 2024 +0200

s390: testsuite: Fix nobp-table-jump-*.c

Starting with r14-5628-g53ba8d669550d3 interprocedural VRP became strong
enough in order to render these tests useless.  Fixed by disabling IPA.

gcc/testsuite/ChangeLog:

* gcc.target/s390/nobp-table-jump-inline-z10.c: Do not perform
IPA.
* gcc.target/s390/nobp-table-jump-inline-z900.c: Dito.
* gcc.target/s390/nobp-table-jump-z10.c: Dito.
* gcc.target/s390/nobp-table-jump-z900.c: Dito.

Diff:
---
 .../gcc.target/s390/nobp-table-jump-inline-z10.c   | 42 +++---
 .../gcc.target/s390/nobp-table-jump-inline-z900.c  | 42 +++---
 .../gcc.target/s390/nobp-table-jump-z10.c  | 42 +++---
 .../gcc.target/s390/nobp-table-jump-z900.c | 42 +++---
 4 files changed, 84 insertions(+), 84 deletions(-)

diff --git a/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c 
b/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c
index 8dfd7e4c7861..121751166d0a 100644
--- a/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c
+++ b/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z10.c
@@ -4,29 +4,29 @@
 /* case-values-threshold will be set to 20 by the back-end when jump
thunk are requested.  */
 
-int __attribute__((noinline,noclone)) foo1 (void) { return 1; }
-int __attribute__((noinline,noclone)) foo2 (void) { return 2; }
-int __attribute__((noinline,noclone)) foo3 (void) { return 3; }
-int __attribute__((noinline,noclone)) foo4 (void) { return 4; }
-int __attribute__((noinline,noclone)) foo5 (void) { return 5; }
-int __attribute__((noinline,noclone)) foo6 (void) { return 6; }
-int __attribute__((noinline,noclone)) foo7 (void) { return 7; }
-int __attribute__((noinline,noclone)) foo8 (void) { return 8; }
-int __attribute__((noinline,noclone)) foo9 (void) { return 9; }
-int __attribute__((noinline,noclone)) foo10 (void) { return 10; }
-int __attribute__((noinline,noclone)) foo11 (void) { return 11; }
-int __attribute__((noinline,noclone)) foo12 (void) { return 12; }
-int __attribute__((noinline,noclone)) foo13 (void) { return 13; }
-int __attribute__((noinline,noclone)) foo14 (void) { return 14; }
-int __attribute__((noinline,noclone)) foo15 (void) { return 15; }
-int __attribute__((noinline,noclone)) foo16 (void) { return 16; }
-int __attribute__((noinline,noclone)) foo17 (void) { return 17; }
-int __attribute__((noinline,noclone)) foo18 (void) { return 18; }
-int __attribute__((noinline,noclone)) foo19 (void) { return 19; }
-int __attribute__((noinline,noclone)) foo20 (void) { return 20; }
+int __attribute__((noipa)) foo1 (void) { return 1; }
+int __attribute__((noipa)) foo2 (void) { return 2; }
+int __attribute__((noipa)) foo3 (void) { return 3; }
+int __attribute__((noipa)) foo4 (void) { return 4; }
+int __attribute__((noipa)) foo5 (void) { return 5; }
+int __attribute__((noipa)) foo6 (void) { return 6; }
+int __attribute__((noipa)) foo7 (void) { return 7; }
+int __attribute__((noipa)) foo8 (void) { return 8; }
+int __attribute__((noipa)) foo9 (void) { return 9; }
+int __attribute__((noipa)) foo10 (void) { return 10; }
+int __attribute__((noipa)) foo11 (void) { return 11; }
+int __attribute__((noipa)) foo12 (void) { return 12; }
+int __attribute__((noipa)) foo13 (void) { return 13; }
+int __attribute__((noipa)) foo14 (void) { return 14; }
+int __attribute__((noipa)) foo15 (void) { return 15; }
+int __attribute__((noipa)) foo16 (void) { return 16; }
+int __attribute__((noipa)) foo17 (void) { return 17; }
+int __attribute__((noipa)) foo18 (void) { return 18; }
+int __attribute__((noipa)) foo19 (void) { return 19; }
+int __attribute__((noipa)) foo20 (void) { return 20; }
 
 
-int __attribute__((noinline,noclone))
+int __attribute__((noipa))
 bar (int a)
 {
   int ret = 0;
diff --git a/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c 
b/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c
index 46d2c54bcff1..5ad0c72afc36 100644
--- a/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c
+++ b/gcc/testsuite/gcc.target/s390/nobp-table-jump-inline-z900.c
@@ -4,29 +4,29 @@
 /* case-values-threshold will be set to 20 by the back-end when jump
thunk are requested.  */
 
-int __attribute__((noinline,noclone)) foo1 (void) { return 1; }
-int __attribute__((noinline,noclone)) foo2 (void) { return 2; }
-int __attribute__((noinline,noclone)) foo3 (void) { return 3; }
-int __attribute__((noinline,noclone)) foo4 (void) { return 4; }
-int __attribute__((noinline,noclone)) foo5 (void) { return 5; }
-int __attribute__((noinline,noclone)) foo6 (void) { return 6; }
-int __attribute__((noinline,noclone)) foo7 (void) { return 7; }
-int __attribute__((noinline,noclone)) foo8 (void) { return 8; }

[gcc r15-1365] s390: Extend two/four element integer vectors

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:2ab143df110a40bd41b5368ef84819953bf971b1

commit r15-1365-g2ab143df110a40bd41b5368ef84819953bf971b1
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:36:11 2024 +0200

s390: Extend two/four element integer vectors

For the moment I deliberately left out one-element QHS vectors since it
is unclear whether these are pathological cases or whether they are
really used.  If we ever get an extend for V1DI -> V1TI we should
reconsider this.

As a side-effect this fixes PR115261.

gcc/ChangeLog:

PR target/115261
* config/s390/s390.md (any_extend,extend_insn,zero_extend):
New code attributes and code iterator.
* config/s390/vector.md (V_EXTEND): New mode iterator.
(2): New insn.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-extend-1.c: New test.
* gcc.target/s390/vector/vec-extend-2.c: New test.

Diff:
---
 gcc/config/s390/s390.md|  4 ++
 gcc/config/s390/vector.md  | 29 ++--
 .../gcc.target/s390/vector/vec-extend-1.c  | 79 ++
 .../gcc.target/s390/vector/vec-extend-2.c  | 55 +++
 4 files changed, 162 insertions(+), 5 deletions(-)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index c607dce3cf0f..1311a5f01cf3 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -602,6 +602,10 @@
 
 (define_attr "relative_long" "no,yes" (const_string "no"))
 
+(define_code_attr extend_insn [(sign_extend "extend") (zero_extend 
"zero_extend")])
+(define_code_attr zero_extend [(sign_extend "") (zero_extend "l")])
+(define_code_iterator any_extend [sign_extend zero_extend])
+
 ;; Pipeline description for z900.
 (include "2064.md")
 
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index ed4742d93c91..a931a4b1b17e 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -87,6 +87,8 @@
 ; 32 bit int<->fp vector conversion instructions are available since VXE2 
(z15).
 (define_mode_iterator VX_VEC_CONV_BFP [V2DF (V4SF "TARGET_VXE2")])
 
+(define_mode_iterator VI_EXTEND [V2QI V2HI V2SI V4QI V4HI])
+
 ; Empty string for all but TImode.  This is used to hide the TImode
 ; expander name in case it is defined already.  See addti3 for an
 ; example.
@@ -195,13 +197,20 @@
(V1DF "V2DF") (V2DF "V4DF")])
 
 ; Vector with widened element size and the same number of elements.
-(define_mode_attr vec_2x_wide [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI 
"V8HI") (V16QI "V16HI")
+(define_mode_attr VEC_2X_WIDE [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI 
"V8HI") (V16QI "V16HI")
   (V1HI "V1SI") (V2HI "V2SI") (V4HI "V4SI") (V8HI 
"V8SI")
   (V1SI "V1DI") (V2SI "V2DI") (V4SI "V4DI")
   (V1DI "V1TI") (V2DI "V2TI")
   (V1SF "V1DF") (V2SF "V2DF") (V4SF "V4DF")
   (V1DF "V1TF") (V2DF "V2TF")])
 
+(define_mode_attr vec_2x_wide [(V1QI "v1hi") (V2QI "v2hi") (V4QI "v4hi") (V8QI 
"v8hi") (V16QI "v16hi")
+  (V1HI "v1si") (V2HI "v2si") (V4HI "v4si") (V8HI 
"v8si")
+  (V1SI "v1di") (V2SI "v2di") (V4SI "v4di")
+  (V1DI "v1ti") (V2DI "v2ti")
+  (V1SF "v1df") (V2SF "v2df") (V4SF "v4df")
+  (V1DF "v1tf") (V2DF "v2tf")])
+
 ; Vector with half the element size AND half the number of elements.
 (define_mode_attr vec_halfhalf
   [(V2HI "V2QI") (V4HI "V4QI") (V8HI "V8QI")
@@ -1604,7 +1613,7 @@
 UNSPEC_VEC_UMULT_ODD))
(set (match_operand: 0 "register_operand" "")
 (vec_select:
-(vec_concat: (match_dup 3) (match_dup 4))
+(vec_concat: (match_dup 3) (match_dup 4))
 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1623,7 +1632,7 @@
 UNSPEC_VEC_UMULT_ODD))
(set (match_operand: 0 "register_operand" "")
 (vec_select:
-(vec_concat: (match_dup 3) (match_dup 4))
+(vec_concat: (match_dup 3) (match_dup 4))
 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1642,7 +1651,7 @@
 UNSPEC_VEC_SMULT_ODD))
(set (match_operand: 0 "register_operand" "")
 (vec_select:
-(vec_concat: (match_dup 3) (match_dup 4))
+(vec_concat: (match_dup 3) (match_dup 4))
 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -1661,7 +1670,7 @@
 UNSPEC_VEC_SMULT_ODD))
(set (match_operand: 0 "register_operand" "")
 (vec_select:
-(vec_concat: (match_dup 3) (match_dup 4))
+(vec_concat: (match_dup 3) (match_dup 4))
 (match_dup 5)))]
   "TARGET_VX"
  {
@@ -2375,6 +2384,16 @@
   "vpkls\

[gcc r15-1366] s390: Extend two element float vector

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:9965acb77cbd686283a9d0a867c80b1e710f46b9

commit r15-1366-g9965acb77cbd686283a9d0a867c80b1e710f46b9
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:37:11 2024 +0200

s390: Extend two element float vector

This implements a V2SF -> V2DF extend.

gcc/ChangeLog:

* config/s390/vector.md (*vmrhf_half): New.
(extendv2sfv2df2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-extend-3.c: New test.

Diff:
---
 gcc/config/s390/vector.md  |  28 +++
 .../gcc.target/s390/vector/vec-extend-3.c  |  18 ++
 gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c|  30 +++
 gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c| 102 ++
 gcc/testsuite/gcc.target/s390/vector/vgm-hi-1.c| 212 
 .../gcc.target/s390/vector/vgm-int128-1.c  |  64 +++
 .../gcc.target/s390/vector/vgm-longdouble-1.c  |  55 ++
 gcc/testsuite/gcc.target/s390/vector/vgm-qi-1.c| 213 +
 gcc/testsuite/gcc.target/s390/vector/vgm-sf-1.c|  43 +
 gcc/testsuite/gcc.target/s390/vector/vgm-si-1.c| 146 ++
 gcc/testsuite/gcc.target/s390/vector/vgm-ti-1.c|  63 ++
 11 files changed, 974 insertions(+)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index a931a4b1b17e..40de0c75a7cf 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -895,6 +895,17 @@
   "vmrhf\t%0,%1,%2";
   [(set_attr "op_type" "VRR")])
 
+(define_insn "*vmrhf_half"
+  [(set (match_operand:V_HW_40 
"register_operand" "=v")
+   (vec_select:V_HW_4
+(vec_concat:V_HW_4 (match_operand: 1 
"register_operand"  "v")
+   (match_operand: 2 
"register_operand"  "v"))
+(parallel [(const_int 0) (const_int 2)
+   (const_int 1) (const_int 3)])))]
+  "TARGET_VX"
+  "vmrhf\t%0,%1,%2";
+  [(set_attr "op_type" "VRR")])
+
 (define_insn "*vmrlf"
   [(set (match_operand:V_HW_4  0 
"register_operand" "=v")
 (vec_select:V_HW_4
@@ -2394,6 +2405,23 @@
   "vuph\t%0,%1"
   [(set_attr "op_type" "VRR")])
 
+(define_expand "extendv2sfv2df2"
+  [(set (match_dup 2)
+   (vec_select:V4SF
+(vec_concat:V4SF (match_operand:V2SF 1 "register_operand")
+ (match_dup 1))
+(parallel [(const_int 0) (const_int 2)
+   (const_int 1) (const_int 3)])))
+   (set (match_operand:V2DF 0 "register_operand")
+   (float_extend:V2DF
+(vec_select:V2SF
+ (match_dup 2)
+ (parallel [(const_int 0) (const_int 2)]]
+  "TARGET_VX"
+{
+  operands[2] = gen_reg_rtx (V4SFmode);
+})
+
 ;; vector unpack v16qi
 
 ; signed
diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-extend-3.c 
b/gcc/testsuite/gcc.target/s390/vector/vec-extend-3.c
new file mode 100644
index ..2b02e7bf9f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-extend-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z13 -mzarch" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+typedef float v2sf __attribute__ ((vector_size (8)));
+typedef double v2df __attribute__ ((vector_size (16)));
+
+/*
+** extendv2sfv2df2:
+** vmrhf   %v24,%v24,%v24
+** vldeb   %v24,%v24
+** br  %r14
+*/
+
+v2df extendv2sfv2df2 (v2sf x)
+{
+  return __builtin_convertvector (x, v2df);
+}
diff --git a/gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c 
b/gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c
new file mode 100644
index ..07aa6b9deece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z13 -mzarch" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+typedef double v1df __attribute__ ((vector_size (8)));
+typedef double v2df __attribute__ ((vector_size (16)));
+
+/*
+** test_v1df_via_vgmb:
+** vgmb%v24,0,1
+** br  %r14
+*/
+
+v1df
+test_v1df_via_vgmb (void)
+{
+  return (v1df){-8577.505882352939806878566741943359375};
+}
+
+/*
+** test_v2df_via_vgmb:
+** vgmb%v24,0,1
+** br  %r14
+*/
+
+v2df
+test_v2df_via_vgmb (void)
+{
+  return (v2df){-8577.505882352939806878566741943359375, 
-8577.505882352939806878566741943359375};
+}
diff --git a/gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c 
b/gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c
new file mode 100644
index ..fa608f2b5ae8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c
@@ -0,0 +1,102 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z13 -mzarch" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+typedef long long v1di __attribute__ ((vector_size (8)));
+typedef long long v2di __attribute__ ((vector_size (16)));
+
+/*
+** test_v1di_via_vgmb:
+** vgmb%v24,0,2
+** br  %r14
+*/
+
+v1di
+test

[gcc r15-1367] s390: Delete mistakenly added tests

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:e86d4e4ac7d7438f2f1b2437508cfd394a0a34d9

commit r15-1367-ge86d4e4ac7d7438f2f1b2437508cfd394a0a34d9
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:46:38 2024 +0200

s390: Delete mistakenly added tests

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vgm-df-1.c: Removed.
* gcc.target/s390/vector/vgm-di-1.c: Removed.
* gcc.target/s390/vector/vgm-hi-1.c: Removed.
* gcc.target/s390/vector/vgm-int128-1.c: Removed.
* gcc.target/s390/vector/vgm-longdouble-1.c: Removed.
* gcc.target/s390/vector/vgm-qi-1.c: Removed.
* gcc.target/s390/vector/vgm-sf-1.c: Removed.
* gcc.target/s390/vector/vgm-si-1.c: Removed.
* gcc.target/s390/vector/vgm-ti-1.c: Removed.

Diff:
---
 gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c|  30 ---
 gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c| 102 --
 gcc/testsuite/gcc.target/s390/vector/vgm-hi-1.c| 212 
 .../gcc.target/s390/vector/vgm-int128-1.c  |  64 ---
 .../gcc.target/s390/vector/vgm-longdouble-1.c  |  55 --
 gcc/testsuite/gcc.target/s390/vector/vgm-qi-1.c| 213 -
 gcc/testsuite/gcc.target/s390/vector/vgm-sf-1.c|  43 -
 gcc/testsuite/gcc.target/s390/vector/vgm-si-1.c| 146 --
 gcc/testsuite/gcc.target/s390/vector/vgm-ti-1.c|  63 --
 9 files changed, 928 deletions(-)

diff --git a/gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c 
b/gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c
deleted file mode 100644
index 07aa6b9deece..
--- a/gcc/testsuite/gcc.target/s390/vector/vgm-df-1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=z13 -mzarch" } */
-/* { dg-final { check-function-bodies "**" "" "" } } */
-
-typedef double v1df __attribute__ ((vector_size (8)));
-typedef double v2df __attribute__ ((vector_size (16)));
-
-/*
-** test_v1df_via_vgmb:
-** vgmb%v24,0,1
-** br  %r14
-*/
-
-v1df
-test_v1df_via_vgmb (void)
-{
-  return (v1df){-8577.505882352939806878566741943359375};
-}
-
-/*
-** test_v2df_via_vgmb:
-** vgmb%v24,0,1
-** br  %r14
-*/
-
-v2df
-test_v2df_via_vgmb (void)
-{
-  return (v2df){-8577.505882352939806878566741943359375, 
-8577.505882352939806878566741943359375};
-}
diff --git a/gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c 
b/gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c
deleted file mode 100644
index fa608f2b5ae8..
--- a/gcc/testsuite/gcc.target/s390/vector/vgm-di-1.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=z13 -mzarch" } */
-/* { dg-final { check-function-bodies "**" "" "" } } */
-
-typedef long long v1di __attribute__ ((vector_size (8)));
-typedef long long v2di __attribute__ ((vector_size (16)));
-
-/*
-** test_v1di_via_vgmb:
-** vgmb%v24,0,2
-** br  %r14
-*/
-
-v1di
-test_v1di_via_vgmb (void)
-{
-  return (v1di){0xe0e0e0e0e0e0e0e0};
-}
-
-/*
-** test_v2di_via_vgmb:
-** vgmb%v24,0,2
-** br  %r14
-*/
-
-v2di
-test_v2di_via_vgmb (void)
-{
-  return (v2di){0xe0e0e0e0e0e0e0e0, 0xe0e0e0e0e0e0e0e0};
-}
-
-/*
-** test_v1di_via_vgmb_wrap:
-** vgmb%v24,5,2
-** br  %r14
-*/
-
-v1di
-test_v1di_via_vgmb_wrap (void)
-{
-  return (v1di){0xe7e7e7e7e7e7e7e7};
-}
-
-/*
-** test_v2di_via_vgmb_wrap:
-** vgmb%v24,5,2
-** br  %r14
-*/
-
-v2di
-test_v2di_via_vgmb_wrap (void)
-{
-  return (v2di){0xe7e7e7e7e7e7e7e7, 0xe7e7e7e7e7e7e7e7};
-}
-
-/*
-** test_v1di_via_vgmh:
-** vgmh%v24,5,10
-** br  %r14
-*/
-
-v1di
-test_v1di_via_vgmh (void)
-{
-  return (v1di){0x7e007e007e007e0};
-}
-
-/*
-** test_v2di_via_vgmh:
-** vgmh%v24,5,10
-** br  %r14
-*/
-
-v2di
-test_v2di_via_vgmh (void)
-{
-  return (v2di){0x7e007e007e007e0, 0x7e007e007e007e0};
-}
-
-/*
-** test_v1di_via_vgmg:
-** vgmg%v24,17,46
-** br  %r14
-*/
-
-v1di
-test_v1di_via_vgmg (void)
-{
-  return (v1di){0x7ffe};
-}
-
-/*
-** test_v2di_via_vgmg:
-** vgmg%v24,17,46
-** br  %r14
-*/
-
-v2di
-test_v2di_via_vgmg (void)
-{
-  return (v2di){0x7ffe, 0x7ffe};
-}
diff --git a/gcc/testsuite/gcc.target/s390/vector/vgm-hi-1.c 
b/gcc/testsuite/gcc.target/s390/vector/vgm-hi-1.c
deleted file mode 100644
index da064792cfc9..
--- a/gcc/testsuite/gcc.target/s390/vector/vgm-hi-1.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=z13 -mzarch" } */
-/* { dg-final { check-function-bodies "**" "" "" } } */
-
-typedef short  v1hi __attribute__ ((vector_size (2)));
-typedef short  v2hi __attribute__ ((vector_size (4)));
-typedef short  v4hi __attribute__ ((vector_size (8)));
-typedef short  v8hi __attribute__ ((vector_size (16)));
-
-/*
-** test_v1hi_via_vgmb:
-** vgmb%v24,0,2
-** br  %r14
-*/
-
-v1hi
-test_v1hi_via_vgmb (void)
-{
-  return (v1hi){

[gcc r14-10316] s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR109549]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:8f124e6b79daa43618dbb1e67c09629676d07396

commit r14-10316-g8f124e6b79daa43618dbb1e67c09629676d07396
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:52:20 2024 +0200

s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR109549]

Consider a NOCE conversion as profitable if there is at least one
conditional move.

gcc/ChangeLog:

PR target/109549
* config/s390/s390.cc (TARGET_NOCE_CONVERSION_PROFITABLE_P):
Define.
(s390_noce_conversion_profitable_p): Implement.

gcc/testsuite/ChangeLog:

* gcc.target/s390/ccor.c: Order of loads are reversed, now, as a
consequence the condition has to be reversed.

(cherry picked from commit 57e04879389f9c0d5d53f316b468ce1bddbab350)

Diff:
---
 gcc/config/s390/s390.cc  | 32 
 gcc/testsuite/gcc.target/s390/ccor.c |  4 ++--
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 5968808fcb6e..fa517bd3e77a 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -78,6 +78,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "tree-pass.h"
 #include "context.h"
 #include "builtins.h"
+#include "ifcvt.h"
 #include "rtl-iter.h"
 #include "intl.h"
 #include "tm-constrs.h"
@@ -18037,6 +18038,34 @@ s390_vectorize_vec_perm_const (machine_mode vmode, 
machine_mode op_mode,
   return vectorize_vec_perm_const_1 (d);
 }
 
+/* Consider a NOCE conversion as profitable if there is at least one
+   conditional move.  */
+
+static bool
+s390_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info)
+{
+  if (if_info->speed_p)
+{
+  for (rtx_insn *insn = seq; insn; insn = NEXT_INSN (insn))
+   {
+ rtx set = single_set (insn);
+ if (set == NULL)
+   continue;
+ if (GET_CODE (SET_SRC (set)) != IF_THEN_ELSE)
+   continue;
+ rtx src = SET_SRC (set);
+ machine_mode mode = GET_MODE (src);
+ if (GET_MODE_CLASS (mode) != MODE_INT
+ && GET_MODE_CLASS (mode) != MODE_FLOAT)
+   continue;
+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+   continue;
+ return true;
+   }
+}
+  return default_noce_conversion_profitable_p (seq, if_info);
+}
+
 /* Initialize GCC target structure.  */
 
 #undef  TARGET_ASM_ALIGNED_HI_OP
@@ -18350,6 +18379,9 @@ s390_vectorize_vec_perm_const (machine_mode vmode, 
machine_mode op_mode,
 #undef TARGET_VECTORIZE_VEC_PERM_CONST
 #define TARGET_VECTORIZE_VEC_PERM_CONST s390_vectorize_vec_perm_const
 
+#undef TARGET_NOCE_CONVERSION_PROFITABLE_P
+#define TARGET_NOCE_CONVERSION_PROFITABLE_P s390_noce_conversion_profitable_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-s390.h"
diff --git a/gcc/testsuite/gcc.target/s390/ccor.c 
b/gcc/testsuite/gcc.target/s390/ccor.c
index 31f30f60314e..36a3c3a999a9 100644
--- a/gcc/testsuite/gcc.target/s390/ccor.c
+++ b/gcc/testsuite/gcc.target/s390/ccor.c
@@ -42,7 +42,7 @@ GENFUN1(2)
 
 GENFUN1(3)
 
-/* { dg-final { scan-assembler {locrno} } } */
+/* { dg-final { scan-assembler {locro} } } */
 
 GENFUN2(0,1)
 
@@ -58,7 +58,7 @@ GENFUN2(0,3)
 
 GENFUN2(1,2)
 
-/* { dg-final { scan-assembler {locrnlh} } } */
+/* { dg-final { scan-assembler {locrlh} } } */
 
 GENFUN2(1,3)

[gcc r14-10317] s390: testsuite: Fix ifcvt-one-insn-bool.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:0ed63e3791345a9933cbbf28594ab5549d336bd4

commit r14-10317-g0ed63e3791345a9933cbbf28594ab5549d336bd4
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jun 17 08:52:28 2024 +0200

s390: testsuite: Fix ifcvt-one-insn-bool.c

With the change of r15-787-g57e04879389f9c I forgot to also update this
test.

gcc/testsuite/ChangeLog:

* gcc.target/s390/ifcvt-one-insn-bool.c: Fix loc.

(cherry picked from commit ac66736bf2f8a10d2f43e83ed6377e4179027a39)

Diff:
---
 gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c 
b/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c
index 0c8c2f879a69..4ae29dbd6b61 100644
--- a/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c
+++ b/gcc/testsuite/gcc.target/s390/ifcvt-one-insn-bool.c
@@ -3,7 +3,7 @@
 /* { dg-do compile { target { s390*-*-* } } } */
 /* { dg-options "-O2 -march=z13 -mzarch" } */
 
-/* { dg-final { scan-assembler "lochinh\t%r.?,1" } } */
+/* { dg-final { scan-assembler "lochile\t%r.?,1" } } */
 #include 
 
 int foo (int *a, unsigned int n)

[gcc r15-4318] MAINTAINERS (s390 port): Add myself

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:fa04a1713b54bdc4c7b686c88117c9c46043ec73

commit r15-4318-gfa04a1713b54bdc4c7b686c88117c9c46043ec73
Author: Stefan Schulze Frielinghaus 
Date:   Mon Oct 14 11:12:48 2024 +0200

MAINTAINERS (s390 port): Add myself

ChangeLog:

* MAINTAINERS (s390 port): Add myself.

Diff:
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f94aa9aeb791..cf1cf78e16cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -120,6 +120,7 @@ rs6000 vector extns Aldy Hernandez  

 rx port Nick Clifton
 s390 port   Ulrich Weigand  
 s390 port   Andreas Krebbel 
+s390 port   Stefan Schulze Frielinghaus 
 sh port Alexandre Oliva 
 sh port Oleg Endo   
 sparc port  David S. Miller 

[gcc r15-4538] testsuite: Fix typo in ext-floating19.C

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:9263523b7e522e5b8c9ac70df5efc73632c19380

commit r15-4538-g9263523b7e522e5b8c9ac70df5efc73632c19380
Author: Stefan Schulze Frielinghaus 
Date:   Tue Oct 22 08:58:14 2024 +0200

testsuite: Fix typo in ext-floating19.C

gcc/testsuite/ChangeLog:

* g++.dg/cpp23/ext-floating19.C: Fix typo for bfloat16 guard.

Diff:
---
 gcc/testsuite/g++.dg/cpp23/ext-floating19.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/cpp23/ext-floating19.C 
b/gcc/testsuite/g++.dg/cpp23/ext-floating19.C
index dfbedb986990..a79f7d6e202f 100644
--- a/gcc/testsuite/g++.dg/cpp23/ext-floating19.C
+++ b/gcc/testsuite/g++.dg/cpp23/ext-floating19.C
@@ -15,6 +15,6 @@ auto x64 = 3.14f64;
 #ifdef __STDCPP_FLOAT128_T__
 auto x128 = 3.14f128;
 #endif
-#ifdef __STDCPP_FLOAT16_T__
+#ifdef __STDCPP_BFLOAT16_T__
 auto xbf = 1.2bf16;
 #endif

[gcc r14-10713] s390: Fix TF to FPRX2 conversion [PR115860]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:3eb3fbc89c638a72611efdc54110b8113f79ee8d

commit r14-10713-g3eb3fbc89c638a72611efdc54110b8113f79ee8d
Author: Stefan Schulze Frielinghaus 
Date:   Thu Sep 26 19:38:02 2024 +0200

s390: Fix TF to FPRX2 conversion [PR115860]

Currently subregs originating from *tf_to_fprx2_0 and *tf_to_fprx2_1
survive register allocation.  This in turn leads to wrong register
renaming.  Keeping the current approach would mean we need two insns for
*tf_to_fprx2_0 and *tf_to_fprx2_1, respectively.  Something along the
lines

(define_insn "*tf_to_fprx2_0"
  [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0)
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "#")

(define_insn "*tf_to_fprx2_0"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "vpdi\t%v0,%v1,%v0,1
  [(set_attr "op_type" "VRR")])

and similar for *tf_to_fprx2_1.  Note, pre register allocation operand 0
has mode FPRX2 and afterwards DF once subregs have been eliminated.

Since we always copy a whole vector register into a floating-point
register pair, another way to fix this is to merge *tf_to_fprx2_0 and
*tf_to_fprx2_1 into a single insn which means we don't have to use
subregs at all.  The downside of this is that the assembler template
contains two instructions, now.  The upside is that we don't have to
come up with some artificial insn before RA which might be more
readable/maintainable.  That is implemented by this patch.

In commit r11-4872-ge627cda5686592, the output operand specifier %V was
introduced which is used in tf_to_fprx2 only, now.  Instead of coming up
with its counterpart %F for floating-point registers, which would also
only be used in tf_to_fprx2, I print the operands directly.  This
renders %V unused which is why it is removed by this patch.

gcc/ChangeLog:

PR target/115860
* config/s390/s390.cc (print_operand): Remove operand specifier
%V.
* config/s390/s390.md (UNSPEC_TF_TO_FPRX2): New.
* config/s390/vector.md (*tf_to_fprx2_0): Remove.
(*tf_to_fprx2_1): Remove.
(tf_to_fprx2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/long-double-asm-abi.c: Adapt
scan-assembler directive.
* gcc.target/s390/vector/long-double-to-i64.c: Adapt
scan-assembler directive.
* gcc.target/s390/pr115860-1.c: New test.

(cherry picked from commit 46c2538435dfc50dd5c67c4e03ce387d1f6ebe9b)

Diff:
---
 gcc/config/s390/s390.cc|  5 +-
 gcc/config/s390/s390.md|  2 +
 gcc/config/s390/vector.md  | 75 --
 gcc/testsuite/gcc.target/s390/pr115860-1.c | 26 
 .../gcc.target/s390/vector/long-double-asm-abi.c   |  2 +-
 .../gcc.target/s390/vector/long-double-to-i64.c|  2 -
 6 files changed, 72 insertions(+), 40 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 2619a9ac9861..a1c0a57a795f 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -8466,7 +8466,6 @@ print_operand_address (FILE *file, rtx addr)
 CONST_VECTOR: Generate a bitmask for vgbm instruction.
 'x': print integer X as if it's an unsigned halfword.
 'v': print register number as vector register (v1 instead of f1).
-'V': print the second word of a TFmode operand as vector register.
 */
 
 void
@@ -8659,13 +8658,13 @@ print_operand (FILE *file, rtx x, int code)
 case REG:
   /* Print FP regs as fx instead of vx when they are accessed
 through non-vector mode.  */
-  if ((code == 'v' || code == 'V')
+  if (code == 'v'
  || VECTOR_NOFP_REG_P (x)
  || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x)))
  || (VECTOR_REG_P (x)
  && (GET_MODE_SIZE (GET_MODE (x)) /
  s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8))
-   fprintf (file, "%%v%s", reg_names[REGNO (x) + (code == 'V')] + 2);
+   fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2);
   else
fprintf (file, "%s", reg_names[REGNO (x)]);
   break;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 17d31643dbc6..72e05be9b182 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -241,6 +241,8 @@
UNSPEC_VEC_VFMIN
UNSPEC_VEC_VFMAX
 
+   UNSPEC_TF_TO_FPRX2
+
UNSPEC_NNPA_VCLFNHS_V8HI
UNSPEC_NNPA_VCLFNLS_V8HI
UNSPEC_NNPA_VCRNFS_V8HI
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 55dc35a71bf5..35defb7043a4 100644
--- a/gcc/config/s390/vector.md
+

[gcc r14-10712] s390: Fix AQ and AR constraints

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1670d3259dec8abf445ed4f282dcbf3a1e0d3032

commit r14-10712-g1670d3259dec8abf445ed4f282dcbf3a1e0d3032
Author: Stefan Schulze Frielinghaus 
Date:   Thu Sep 26 19:38:02 2024 +0200

s390: Fix AQ and AR constraints

Ensure for AQ and AR constraints that the resulting displacement after
adding any positive offset less than the size of the object being
referenced is still valid.

gcc/ChangeLog:

* config/s390/s390.cc (s390_mem_constraint): Check displacement
for AQ and AR constraints.

(cherry picked from commit 1a71ff3b89aadc7fa0af0bca269d74bb23c1a957)

Diff:
---
 gcc/config/s390/s390.cc | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 4be95788094c..2619a9ac9861 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3552,6 +3552,18 @@ s390_mem_constraint (const char *str, rtx op)
   if ((reload_completed || reload_in_progress)
  ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
return 0;
+  /* offsettable_memref_p ensures only that any positive offset added to
+the address forms a valid general address.  For AQ and AR constraints
+we also have to verify that the resulting displacement after adding
+any positive offset less than the size of the object being referenced
+is still valid.  */
+  if (str[1] == 'Q' || str[1] == 'R')
+   {
+ int o = GET_MODE_SIZE (GET_MODE (op)) - 1;
+ rtx tmp = adjust_address (op, QImode, o);
+ if (!s390_check_qrst_address (str[1], XEXP (tmp, 0), true))
+   return 0;
+   }
   return s390_check_qrst_address (str[1], XEXP (op, 0), true);
 case 'B':
   /* Check for non-literal-pool variants of memory constraints.  */

[gcc r13-9058] s390: Fix TF to FPRX2 conversion [PR115860]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:f7037fd03ad842dc69e20c03942f29d982ad655e

commit r13-9058-gf7037fd03ad842dc69e20c03942f29d982ad655e
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 27 08:18:47 2024 +0200

s390: Fix TF to FPRX2 conversion [PR115860]

Currently subregs originating from *tf_to_fprx2_0 and *tf_to_fprx2_1
survive register allocation.  This in turn leads to wrong register
renaming.  Keeping the current approach would mean we need two insns for
*tf_to_fprx2_0 and *tf_to_fprx2_1, respectively.  Something along the
lines

(define_insn "*tf_to_fprx2_0"
  [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0)
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "#")

(define_insn "*tf_to_fprx2_0"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "vpdi\t%v0,%v1,%v0,1
  [(set_attr "op_type" "VRR")])

and similar for *tf_to_fprx2_1.  Note, pre register allocation operand 0
has mode FPRX2 and afterwards DF once subregs have been eliminated.

Since we always copy a whole vector register into a floating-point
register pair, another way to fix this is to merge *tf_to_fprx2_0 and
*tf_to_fprx2_1 into a single insn which means we don't have to use
subregs at all.  The downside of this is that the assembler template
contains two instructions, now.  The upside is that we don't have to
come up with some artificial insn before RA which might be more
readable/maintainable.  That is implemented by this patch.

In commit r11-4872-ge627cda5686592, the output operand specifier %V was
introduced which is used in tf_to_fprx2 only, now.  Instead of coming up
with its counterpart %F for floating-point registers, which would also
only be used in tf_to_fprx2, I print the operands directly.  This
renders %V unused which is why it is removed by this patch.

gcc/ChangeLog:

PR target/115860
* config/s390/s390.cc (print_operand): Remove operand specifier
%V.
* config/s390/s390.md (UNSPEC_TF_TO_FPRX2): New.
* config/s390/vector.md (*tf_to_fprx2_0): Remove.
(*tf_to_fprx2_1): Remove.
(tf_to_fprx2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/long-double-asm-abi.c: Adapt
scan-assembler directive.
* gcc.target/s390/vector/long-double-to-i64.c: Adapt
scan-assembler directive.
* gcc.target/s390/pr115860-1.c: New test.

(cherry picked from commit 46c2538435dfc50dd5c67c4e03ce387d1f6ebe9b)

Diff:
---
 gcc/config/s390/s390.cc|  5 +-
 gcc/config/s390/s390.md|  2 +
 gcc/config/s390/vector.md  | 75 --
 gcc/testsuite/gcc.target/s390/pr115860-1.c | 26 
 .../gcc.target/s390/vector/long-double-asm-abi.c   |  2 +-
 .../gcc.target/s390/vector/long-double-to-i64.c|  2 -
 6 files changed, 72 insertions(+), 40 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 26456ba3cc12..a0089e4c0f21 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -8122,7 +8122,6 @@ print_operand_address (FILE *file, rtx addr)
 CONST_VECTOR: Generate a bitmask for vgbm instruction.
 'x': print integer X as if it's an unsigned halfword.
 'v': print register number as vector register (v1 instead of f1).
-'V': print the second word of a TFmode operand as vector register.
 */
 
 void
@@ -8315,13 +8314,13 @@ print_operand (FILE *file, rtx x, int code)
 case REG:
   /* Print FP regs as fx instead of vx when they are accessed
 through non-vector mode.  */
-  if ((code == 'v' || code == 'V')
+  if (code == 'v'
  || VECTOR_NOFP_REG_P (x)
  || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x)))
  || (VECTOR_REG_P (x)
  && (GET_MODE_SIZE (GET_MODE (x)) /
  s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8))
-   fprintf (file, "%%v%s", reg_names[REGNO (x) + (code == 'V')] + 2);
+   fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2);
   else
fprintf (file, "%s", reg_names[REGNO (x)]);
   break;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 57bf4a86d32c..2e1229f5f411 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -243,6 +243,8 @@
 
UNSPEC_VEC_ELTSWAP
 
+   UNSPEC_TF_TO_FPRX2
+
UNSPEC_NNPA_VCLFNHS_V8HI
UNSPEC_NNPA_VCLFNLS_V8HI
UNSPEC_NNPA_VCRNFS_V8HI
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index f88e8b655fa8..8cf39e0cd4b6 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s3

[gcc r12-10729] s390: Fix TF to FPRX2 conversion [PR115860]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:7051fa5fa4eaa24785a64072490c1e0c65039915

commit r12-10729-g7051fa5fa4eaa24785a64072490c1e0c65039915
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 27 12:45:42 2024 +0200

s390: Fix TF to FPRX2 conversion [PR115860]

Currently subregs originating from *tf_to_fprx2_0 and *tf_to_fprx2_1
survive register allocation.  This in turn leads to wrong register
renaming.  Keeping the current approach would mean we need two insns for
*tf_to_fprx2_0 and *tf_to_fprx2_1, respectively.  Something along the
lines

(define_insn "*tf_to_fprx2_0"
  [(set (subreg:DF (match_operand:FPRX2 0 "nonimmediate_operand" "=f") 0)
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "#")

(define_insn "*tf_to_fprx2_0"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
(unspec:DF [(match_operand:TF 1 "general_operand" "v")]
   UNSPEC_TF_TO_FPRX2_0))]
  "TARGET_VXE"
  "vpdi\t%v0,%v1,%v0,1
  [(set_attr "op_type" "VRR")])

and similar for *tf_to_fprx2_1.  Note, pre register allocation operand 0
has mode FPRX2 and afterwards DF once subregs have been eliminated.

Since we always copy a whole vector register into a floating-point
register pair, another way to fix this is to merge *tf_to_fprx2_0 and
*tf_to_fprx2_1 into a single insn which means we don't have to use
subregs at all.  The downside of this is that the assembler template
contains two instructions, now.  The upside is that we don't have to
come up with some artificial insn before RA which might be more
readable/maintainable.  That is implemented by this patch.

In commit r11-4872-ge627cda5686592, the output operand specifier %V was
introduced which is used in tf_to_fprx2 only, now.  Instead of coming up
with its counterpart %F for floating-point registers, which would also
only be used in tf_to_fprx2, I print the operands directly.  This
renders %V unused which is why it is removed by this patch.

gcc/ChangeLog:

PR target/115860
* config/s390/s390.cc (print_operand): Remove operand specifier
%V.
* config/s390/s390.md (UNSPEC_TF_TO_FPRX2): New.
* config/s390/vector.md (*tf_to_fprx2_0): Remove.
(*tf_to_fprx2_1): Remove.
(tf_to_fprx2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/long-double-asm-abi.c: Adapt
scan-assembler directive.
* gcc.target/s390/vector/long-double-to-i64.c: Adapt
scan-assembler directive.
* gcc.target/s390/pr115860-1.c: New test.

(cherry picked from commit 46c2538435dfc50dd5c67c4e03ce387d1f6ebe9b)

Diff:
---
 gcc/config/s390/s390.cc|  5 +-
 gcc/config/s390/s390.md|  2 +
 gcc/config/s390/vector.md  | 75 --
 gcc/testsuite/gcc.target/s390/pr115860-1.c | 26 
 .../gcc.target/s390/vector/long-double-asm-abi.c   |  2 +-
 .../gcc.target/s390/vector/long-double-to-i64.c|  2 -
 6 files changed, 72 insertions(+), 40 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 2be3a873b891..a8f804ffe4f7 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -8028,7 +8028,6 @@ print_operand_address (FILE *file, rtx addr)
 CONST_VECTOR: Generate a bitmask for vgbm instruction.
 'x': print integer X as if it's an unsigned halfword.
 'v': print register number as vector register (v1 instead of f1).
-'V': print the second word of a TFmode operand as vector register.
 */
 
 void
@@ -8221,13 +8220,13 @@ print_operand (FILE *file, rtx x, int code)
 case REG:
   /* Print FP regs as fx instead of vx when they are accessed
 through non-vector mode.  */
-  if ((code == 'v' || code == 'V')
+  if (code == 'v'
  || VECTOR_NOFP_REG_P (x)
  || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x)))
  || (VECTOR_REG_P (x)
  && (GET_MODE_SIZE (GET_MODE (x)) /
  s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8))
-   fprintf (file, "%%v%s", reg_names[REGNO (x) + (code == 'V')] + 2);
+   fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2);
   else
fprintf (file, "%s", reg_names[REGNO (x)]);
   break;
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 2fc799695377..335aff9884e2 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -244,6 +244,8 @@
 
UNSPEC_VEC_ELTSWAP
 
+   UNSPEC_TF_TO_FPRX2
+
UNSPEC_NNPA_VCLFNHS_V8HI
UNSPEC_NNPA_VCLFNLS_V8HI
UNSPEC_NNPA_VCRNFS_V8HI
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 75912280c23d..ac3816a6f5c6 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s

[gcc r12-10728] s390: Fix AQ and AR constraints

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:8d29e1c4ceaea4d3ceec6b51de5b7c31a6bc5f85

commit r12-10728-g8d29e1c4ceaea4d3ceec6b51de5b7c31a6bc5f85
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 27 12:45:42 2024 +0200

s390: Fix AQ and AR constraints

Ensure for AQ and AR constraints that the resulting displacement after
adding any positive offset less than the size of the object being
referenced is still valid.

gcc/ChangeLog:

* config/s390/s390.cc (s390_mem_constraint): Check displacement
for AQ and AR constraints.

(cherry picked from commit 1a71ff3b89aadc7fa0af0bca269d74bb23c1a957)

Diff:
---
 gcc/config/s390/s390.cc | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index b66fc5be8719..2be3a873b891 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3405,6 +3405,18 @@ s390_mem_constraint (const char *str, rtx op)
   if ((reload_completed || reload_in_progress)
  ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
return 0;
+  /* offsettable_memref_p ensures only that any positive offset added to
+the address forms a valid general address.  For AQ and AR constraints
+we also have to verify that the resulting displacement after adding
+any positive offset less than the size of the object being referenced
+is still valid.  */
+  if (str[1] == 'Q' || str[1] == 'R')
+   {
+ int o = GET_MODE_SIZE (GET_MODE (op)) - 1;
+ rtx tmp = adjust_address (op, QImode, o);
+ if (!s390_check_qrst_address (str[1], XEXP (tmp, 0), true))
+   return 0;
+   }
   return s390_check_qrst_address (str[1], XEXP (op, 0), true);
 case 'B':
   /* Check for non-literal-pool variants of memory constraints.  */

[gcc r13-9057] s390: Fix AQ and AR constraints

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:14f0fbfb0a4518d507b4038e0757346567024934

commit r13-9057-g14f0fbfb0a4518d507b4038e0757346567024934
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 27 08:18:47 2024 +0200

s390: Fix AQ and AR constraints

Ensure for AQ and AR constraints that the resulting displacement after
adding any positive offset less than the size of the object being
referenced is still valid.

gcc/ChangeLog:

* config/s390/s390.cc (s390_mem_constraint): Check displacement
for AQ and AR constraints.

(cherry picked from commit 1a71ff3b89aadc7fa0af0bca269d74bb23c1a957)

Diff:
---
 gcc/config/s390/s390.cc | 12 
 1 file changed, 12 insertions(+)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 2a451c5ac5d1..26456ba3cc12 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3453,6 +3453,18 @@ s390_mem_constraint (const char *str, rtx op)
   if ((reload_completed || reload_in_progress)
  ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
return 0;
+  /* offsettable_memref_p ensures only that any positive offset added to
+the address forms a valid general address.  For AQ and AR constraints
+we also have to verify that the resulting displacement after adding
+any positive offset less than the size of the object being referenced
+is still valid.  */
+  if (str[1] == 'Q' || str[1] == 'R')
+   {
+ int o = GET_MODE_SIZE (GET_MODE (op)) - 1;
+ rtx tmp = adjust_address (op, QImode, o);
+ if (!s390_check_qrst_address (str[1], XEXP (tmp, 0), true))
+   return 0;
+   }
   return s390_check_qrst_address (str[1], XEXP (op, 0), true);
 case 'B':
   /* Check for non-literal-pool variants of memory constraints.  */

[gcc r14-10692] s390: Fix strict_low_part generation

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:bff6e5667d6a8bf8060e550bdcb40e094d00af41

commit r14-10692-gbff6e5667d6a8bf8060e550bdcb40e094d00af41
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 20 14:06:42 2024 +0200

s390: Fix strict_low_part generation

In s390_expand_insv(), if generating code for ICM et al. src is a MEM
and gen_lowpart might force src into a register such that we end up with
patterns which do not match anymore.  Use adjust_address() instead in
order to preserve a MEM.

Furthermore, it is not straight forward to enforce a subreg.  For
example, in case of a paradoxical subreg, gen_lowpart() may return a
register.  In order to compensate this, s390_gen_lowpart_subreg() emits
a reference to a pseudo which does not coincide with its definition
which is wrong.  Additionally, if dest is a paradoxical subreg, then do
not try to emit a strict_low_part since it could mean that dest was not
initialized even though this might be fixed up later by init-regs.

Splitter for insn *get_tp_64, *zero_extendhisi2_31,
*zero_extendqisi2_31, *zero_extendqihi2_31 are applied after reload.
Thus, operands[0] is a hard register and gen_lowpart (m, operands[0])
just returns the hard register for mode m which is fine to use as an
argument for strict_low_part, i.e., we do not need to enforce subregs
here since after reload subregs are supposed to be eliminated anyway.

This fixes gcc.dg/torture/pr111821.c.

gcc/ChangeLog:

* config/s390/s390-protos.h (s390_gen_lowpart_subreg): Remove.
* config/s390/s390.cc (s390_gen_lowpart_subreg): Remove.
(s390_expand_insv): Use adjust_address() and emit a
strict_low_part only in case of a natural subreg.
* config/s390/s390.md: Use gen_lowpart() instead of
s390_gen_lowpart_subreg().

(cherry picked from commit 9ebc9fbdddfe1ec85355b068354315a4da8e1ca0)

Diff:
---
 gcc/config/s390/s390-protos.h |  1 -
 gcc/config/s390/s390.cc   | 47 +--
 gcc/config/s390/s390.md   | 13 ++--
 3 files changed, 20 insertions(+), 41 deletions(-)

diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 8c2985a79c4d..4bda36e01ec2 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -50,7 +50,6 @@ extern void s390_set_has_landing_pad_p (bool);
 extern bool s390_hard_regno_rename_ok (unsigned int, unsigned int);
 extern int s390_class_max_nregs (enum reg_class, machine_mode);
 extern bool s390_return_addr_from_memory(void);
-extern rtx s390_gen_lowpart_subreg (machine_mode, rtx);
 extern bool s390_fma_allowed_p (machine_mode);
 #if S390_USE_TARGET_ATTRIBUTE
 extern tree s390_valid_target_attribute_tree (tree args,
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index ec836ec3cd4a..4be95788094c 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -516,31 +516,6 @@ s390_return_addr_from_memory ()
   return cfun_gpr_save_slot(RETURN_REGNUM) == SAVE_SLOT_STACK;
 }
 
-/* Generate a SUBREG for the MODE lowpart of EXPR.
-
-   In contrast to gen_lowpart it will always return a SUBREG
-   expression.  This is useful to generate STRICT_LOW_PART
-   expressions.  */
-rtx
-s390_gen_lowpart_subreg (machine_mode mode, rtx expr)
-{
-  rtx lowpart = gen_lowpart (mode, expr);
-
-  /* There might be no SUBREG in case it could be applied to the hard
- REG rtx or it could be folded with a paradoxical subreg.  Bring
- it back.  */
-  if (!SUBREG_P (lowpart))
-{
-  machine_mode reg_mode = TARGET_ZARCH ? DImode : SImode;
-  gcc_assert (REG_P (lowpart));
-  lowpart = gen_lowpart_SUBREG (mode,
-   gen_rtx_REG (reg_mode,
-REGNO (lowpart)));
-}
-
-  return lowpart;
-}
-
 /* Return nonzero if it's OK to use fused multiply-add for MODE.  */
 bool
 s390_fma_allowed_p (machine_mode mode)
@@ -6982,15 +6957,21 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
   /* Emit a strict_low_part pattern if possible.  */
   if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
{
- rtx low_dest = s390_gen_lowpart_subreg (smode, dest);
- rtx low_src = gen_lowpart (smode, src);
-
- switch (smode)
+ rtx low_dest = gen_lowpart (smode, dest);
+ if (SUBREG_P (low_dest) && !paradoxical_subreg_p (low_dest))
{
-   case E_QImode: emit_insn (gen_movstrictqi (low_dest, low_src)); 
return true;
-   case E_HImode: emit_insn (gen_movstricthi (low_dest, low_src)); 
return true;
-   case E_SImode: emit_insn (gen_movstrictsi (low_dest, low_src)); 
return true;
-   default: break;
+ poly_int64 offset = GET_MODE_SIZE (mode) - GET_MODE_SIZE (smode);
+ rtx low_src = adjust_address (src, smode, offset);
+ switc

[gcc r13-9045] s390: Fix strict_low_part generation

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:edda7ba3b569652eb782a7c47a4ad32e3c0e29dd

commit r13-9045-gedda7ba3b569652eb782a7c47a4ad32e3c0e29dd
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 20 14:07:36 2024 +0200

s390: Fix strict_low_part generation

In s390_expand_insv(), if generating code for ICM et al. src is a MEM
and gen_lowpart might force src into a register such that we end up with
patterns which do not match anymore.  Use adjust_address() instead in
order to preserve a MEM.

Furthermore, it is not straight forward to enforce a subreg.  For
example, in case of a paradoxical subreg, gen_lowpart() may return a
register.  In order to compensate this, s390_gen_lowpart_subreg() emits
a reference to a pseudo which does not coincide with its definition
which is wrong.  Additionally, if dest is a paradoxical subreg, then do
not try to emit a strict_low_part since it could mean that dest was not
initialized even though this might be fixed up later by init-regs.

Splitter for insn *get_tp_64, *zero_extendhisi2_31,
*zero_extendqisi2_31, *zero_extendqihi2_31 are applied after reload.
Thus, operands[0] is a hard register and gen_lowpart (m, operands[0])
just returns the hard register for mode m which is fine to use as an
argument for strict_low_part, i.e., we do not need to enforce subregs
here since after reload subregs are supposed to be eliminated anyway.

This fixes gcc.dg/torture/pr111821.c.

gcc/ChangeLog:

* config/s390/s390-protos.h (s390_gen_lowpart_subreg): Remove.
* config/s390/s390.cc (s390_gen_lowpart_subreg): Remove.
(s390_expand_insv): Use adjust_address() and emit a
strict_low_part only in case of a natural subreg.
* config/s390/s390.md: Use gen_lowpart() instead of
s390_gen_lowpart_subreg().

(cherry picked from commit 9ebc9fbdddfe1ec85355b068354315a4da8e1ca0)

Diff:
---
 gcc/config/s390/s390-protos.h |  1 -
 gcc/config/s390/s390.cc   | 47 +--
 gcc/config/s390/s390.md   | 13 ++--
 3 files changed, 20 insertions(+), 41 deletions(-)

diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 67fe09e732da..6a0cc2ca45c9 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -50,7 +50,6 @@ extern void s390_set_has_landing_pad_p (bool);
 extern bool s390_hard_regno_rename_ok (unsigned int, unsigned int);
 extern int s390_class_max_nregs (enum reg_class, machine_mode);
 extern bool s390_return_addr_from_memory(void);
-extern rtx s390_gen_lowpart_subreg (machine_mode, rtx);
 extern bool s390_fma_allowed_p (machine_mode);
 #if S390_USE_TARGET_ATTRIBUTE
 extern tree s390_valid_target_attribute_tree (tree args,
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 505de995da87..2a451c5ac5d1 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -505,31 +505,6 @@ s390_return_addr_from_memory ()
   return cfun_gpr_save_slot(RETURN_REGNUM) == SAVE_SLOT_STACK;
 }
 
-/* Generate a SUBREG for the MODE lowpart of EXPR.
-
-   In contrast to gen_lowpart it will always return a SUBREG
-   expression.  This is useful to generate STRICT_LOW_PART
-   expressions.  */
-rtx
-s390_gen_lowpart_subreg (machine_mode mode, rtx expr)
-{
-  rtx lowpart = gen_lowpart (mode, expr);
-
-  /* There might be no SUBREG in case it could be applied to the hard
- REG rtx or it could be folded with a paradoxical subreg.  Bring
- it back.  */
-  if (!SUBREG_P (lowpart))
-{
-  machine_mode reg_mode = TARGET_ZARCH ? DImode : SImode;
-  gcc_assert (REG_P (lowpart));
-  lowpart = gen_lowpart_SUBREG (mode,
-   gen_rtx_REG (reg_mode,
-REGNO (lowpart)));
-}
-
-  return lowpart;
-}
-
 /* Return nonzero if it's OK to use fused multiply-add for MODE.  */
 bool
 s390_fma_allowed_p (machine_mode mode)
@@ -6639,15 +6614,21 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
   /* Emit a strict_low_part pattern if possible.  */
   if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
{
- rtx low_dest = s390_gen_lowpart_subreg (smode, dest);
- rtx low_src = gen_lowpart (smode, src);
-
- switch (smode)
+ rtx low_dest = gen_lowpart (smode, dest);
+ if (SUBREG_P (low_dest) && !paradoxical_subreg_p (low_dest))
{
-   case E_QImode: emit_insn (gen_movstrictqi (low_dest, low_src)); 
return true;
-   case E_HImode: emit_insn (gen_movstricthi (low_dest, low_src)); 
return true;
-   case E_SImode: emit_insn (gen_movstrictsi (low_dest, low_src)); 
return true;
-   default: break;
+ poly_int64 offset = GET_MODE_SIZE (mode) - GET_MODE_SIZE (smode);
+ rtx low_src = adjust_address (src, smode, offset);
+ switch

[gcc r12-10717] s390: Fix strict_low_part generation

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:4fe0b88159a9548f90db4e846f2033d51e1506c7

commit r12-10717-g4fe0b88159a9548f90db4e846f2033d51e1506c7
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 20 14:08:32 2024 +0200

s390: Fix strict_low_part generation

In s390_expand_insv(), if generating code for ICM et al. src is a MEM
and gen_lowpart might force src into a register such that we end up with
patterns which do not match anymore.  Use adjust_address() instead in
order to preserve a MEM.

Furthermore, it is not straight forward to enforce a subreg.  For
example, in case of a paradoxical subreg, gen_lowpart() may return a
register.  In order to compensate this, s390_gen_lowpart_subreg() emits
a reference to a pseudo which does not coincide with its definition
which is wrong.  Additionally, if dest is a paradoxical subreg, then do
not try to emit a strict_low_part since it could mean that dest was not
initialized even though this might be fixed up later by init-regs.

Splitter for insn *get_tp_64, *zero_extendhisi2_31,
*zero_extendqisi2_31, *zero_extendqihi2_31 are applied after reload.
Thus, operands[0] is a hard register and gen_lowpart (m, operands[0])
just returns the hard register for mode m which is fine to use as an
argument for strict_low_part, i.e., we do not need to enforce subregs
here since after reload subregs are supposed to be eliminated anyway.

This fixes gcc.dg/torture/pr111821.c.

gcc/ChangeLog:

* config/s390/s390-protos.h (s390_gen_lowpart_subreg): Remove.
* config/s390/s390.cc (s390_gen_lowpart_subreg): Remove.
(s390_expand_insv): Use adjust_address() and emit a
strict_low_part only in case of a natural subreg.
* config/s390/s390.md: Use gen_lowpart() instead of
s390_gen_lowpart_subreg().

(cherry picked from commit 9ebc9fbdddfe1ec85355b068354315a4da8e1ca0)

Diff:
---
 gcc/config/s390/s390-protos.h |  1 -
 gcc/config/s390/s390.cc   | 47 +--
 gcc/config/s390/s390.md   | 13 ++--
 3 files changed, 20 insertions(+), 41 deletions(-)

diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 78117c36e030..7ce4c52abe9b 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -50,7 +50,6 @@ extern void s390_set_has_landing_pad_p (bool);
 extern bool s390_hard_regno_rename_ok (unsigned int, unsigned int);
 extern int s390_class_max_nregs (enum reg_class, machine_mode);
 extern bool s390_return_addr_from_memory(void);
-extern rtx s390_gen_lowpart_subreg (machine_mode, rtx);
 extern bool s390_fma_allowed_p (machine_mode);
 #if S390_USE_TARGET_ATTRIBUTE
 extern tree s390_valid_target_attribute_tree (tree args,
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index ae0cf9ef5b91..b66fc5be8719 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -457,31 +457,6 @@ s390_return_addr_from_memory ()
   return cfun_gpr_save_slot(RETURN_REGNUM) == SAVE_SLOT_STACK;
 }
 
-/* Generate a SUBREG for the MODE lowpart of EXPR.
-
-   In contrast to gen_lowpart it will always return a SUBREG
-   expression.  This is useful to generate STRICT_LOW_PART
-   expressions.  */
-rtx
-s390_gen_lowpart_subreg (machine_mode mode, rtx expr)
-{
-  rtx lowpart = gen_lowpart (mode, expr);
-
-  /* There might be no SUBREG in case it could be applied to the hard
- REG rtx or it could be folded with a paradoxical subreg.  Bring
- it back.  */
-  if (!SUBREG_P (lowpart))
-{
-  machine_mode reg_mode = TARGET_ZARCH ? DImode : SImode;
-  gcc_assert (REG_P (lowpart));
-  lowpart = gen_lowpart_SUBREG (mode,
-   gen_rtx_REG (reg_mode,
-REGNO (lowpart)));
-}
-
-  return lowpart;
-}
-
 /* Return nonzero if it's OK to use fused multiply-add for MODE.  */
 bool
 s390_fma_allowed_p (machine_mode mode)
@@ -6544,15 +6519,21 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
   /* Emit a strict_low_part pattern if possible.  */
   if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
{
- rtx low_dest = s390_gen_lowpart_subreg (smode, dest);
- rtx low_src = gen_lowpart (smode, src);
-
- switch (smode)
+ rtx low_dest = gen_lowpart (smode, dest);
+ if (SUBREG_P (low_dest) && !paradoxical_subreg_p (low_dest))
{
-   case E_QImode: emit_insn (gen_movstrictqi (low_dest, low_src)); 
return true;
-   case E_HImode: emit_insn (gen_movstricthi (low_dest, low_src)); 
return true;
-   case E_SImode: emit_insn (gen_movstrictsi (low_dest, low_src)); 
return true;
-   default: break;
+ poly_int64 offset = GET_MODE_SIZE (mode) - GET_MODE_SIZE (smode);
+ rtx low_src = adjust_address (src, smode, offset);
+ switc

[gcc r15-3733] s390: Remove -m{,no-}lra option

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:09a52cf036ba8f2fa7b60b18ba58ca17ffa1b146

commit r15-3733-g09a52cf036ba8f2fa7b60b18ba58ca17ffa1b146
Author: Stefan Schulze Frielinghaus 
Date:   Fri Sep 20 13:53:08 2024 +0200

s390: Remove -m{,no-}lra option

Since the old reload pass is about to be removed and we defaulted to LRA
for over a decade, remove option -m{,no-}lra.

PR target/113953

gcc/ChangeLog:

* config/s390/s390.cc (s390_lra_p): Remove.
(TARGET_LRA_P): Remove.
* config/s390/s390.opt (mlra): Remove.
* config/s390/s390.opt.urls (mlra): Remove.

gcc/testsuite/ChangeLog:

* gcc.target/s390/TI-constants-nolra.c: Removed.
* gcc.target/s390/pr79895.c: Removed.

Diff:
---
 gcc/config/s390/s390.cc| 10 -
 gcc/config/s390/s390.opt   |  4 --
 gcc/config/s390/s390.opt.urls  |  2 -
 gcc/testsuite/gcc.target/s390/TI-constants-nolra.c | 47 --
 gcc/testsuite/gcc.target/s390/pr79895.c|  9 -
 5 files changed, 72 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index c9172d1153ac..25d43ae3e138 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -11342,13 +11342,6 @@ s390_can_change_mode_class (machine_mode from_mode,
   return true;
 }
 
-/* Return true if we use LRA instead of reload pass.  */
-static bool
-s390_lra_p (void)
-{
-  return s390_lra_flag;
-}
-
 /* Return true if register FROM can be eliminated via register TO.  */
 
 static bool
@@ -18444,9 +18437,6 @@ s390_c_mode_for_floating_type (enum tree_index ti)
 #undef TARGET_LEGITIMATE_CONSTANT_P
 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
 
-#undef TARGET_LRA_P
-#define TARGET_LRA_P s390_lra_p
-
 #undef TARGET_CAN_ELIMINATE
 #define TARGET_CAN_ELIMINATE s390_can_eliminate
 
diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt
index a5b5aa95a122..23ea4b8232db 100644
--- a/gcc/config/s390/s390.opt
+++ b/gcc/config/s390/s390.opt
@@ -229,10 +229,6 @@ Set the branch costs for conditional branch instructions.  
Reasonable
 values are small, non-negative integers.  The default branch cost is
 1.
 
-mlra
-Target Var(s390_lra_flag) Init(1) Save
-Use LRA instead of reload.
-
 mpic-data-is-text-relative
 Target Var(s390_pic_data_is_text_relative) 
Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE)
 Assume data segments are relative to text segment.
diff --git a/gcc/config/s390/s390.opt.urls b/gcc/config/s390/s390.opt.urls
index ab1e761efa88..bc772d2ffc75 100644
--- a/gcc/config/s390/s390.opt.urls
+++ b/gcc/config/s390/s390.opt.urls
@@ -74,8 +74,6 @@ UrlSuffix(gcc/S_002f390-and-zSeries-Options.html#index-mzarch)
 
 ; skipping UrlSuffix for 'mbranch-cost=' due to finding no URLs
 
-; skipping UrlSuffix for 'mlra' due to finding no URLs
-
 ; skipping UrlSuffix for 'mpic-data-is-text-relative' due to finding no URLs
 
 ; skipping UrlSuffix for 'mindirect-branch=' due to finding no URLs
diff --git a/gcc/testsuite/gcc.target/s390/TI-constants-nolra.c 
b/gcc/testsuite/gcc.target/s390/TI-constants-nolra.c
deleted file mode 100644
index b9948fc4aa58..
--- a/gcc/testsuite/gcc.target/s390/TI-constants-nolra.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* { dg-do compile { target int128 } } */
-/* { dg-options "-O3 -mno-lra" } */
-
-/* 2x lghi */
-__int128 a() {
-  return 0;
-}
-
-/* 2x lghi */
-__int128 b() {
-  return -1;
-}
-
-/* 2x lghi */
-__int128 c() {
-  return -2;
-}
-
-/* lghi + llilh */
-__int128 d() {
-  return 16000 << 16;
-}
-
-/* lghi + llihf */
-__int128 e() {
-  return (unsigned long long)8 << 32;
-}
-
-/* lghi + llihf */
-__int128 f() {
-  return (unsigned __int128)8 << 96;
-}
-
-/* llihf + llihf - this is handled via movti_bigconst pattern */
-__int128 g() {
-  return ((unsigned __int128)8 << 96) | ((unsigned __int128)8 << 32);
-}
-
-/* Literal pool */
-__int128 h() {
-  return ((unsigned __int128)8 << 32) | 1;
-}
-
-/* Literal pool */
-__int128 i() {
-  return (((unsigned __int128)8 << 32) | 1) << 64;
-}
diff --git a/gcc/testsuite/gcc.target/s390/pr79895.c 
b/gcc/testsuite/gcc.target/s390/pr79895.c
deleted file mode 100644
index 02374e4b8a80..
--- a/gcc/testsuite/gcc.target/s390/pr79895.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* { dg-do compile { target int128 } } */
-/* { dg-options "-O1 -mno-lra" } */
-
-unsigned __int128 g;
-void
-foo ()
-{
-  g = (unsigned __int128)1 << 127;
-}

[gcc r15-6608] Fix type in some Min() calls (#119248)

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:7a7903dec533e02c58e634b6ddd680f36c4cd933

commit r15-6608-g7a7903dec533e02c58e634b6ddd680f36c4cd933
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 6 19:17:28 2025 +0100

Fix type in some Min() calls (#119248)

This is a follow-up to 6dec33834d1fd89f16e271dde9607c1de9554144 and
pull requests #116957 and #119114.

Cherry picked from LLVM commit 65a2eb0b1589590ae78cc1e5f05cd004b3b3bec5.

libsanitizer/ChangeLog:

PR sanitizer/117725
* sanitizer_common/sanitizer_common_interceptors.inc: Cherry
picked from LLVM commit 65a2eb0b1589590ae78cc1e5f05cd004b3b3bec5.

Diff:
---
 .../sanitizer_common/sanitizer_common_interceptors.inc | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc 
b/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
index b0adcf1ea4e4..f2a9348217c8 100644
--- a/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
+++ b/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
@@ -520,14 +520,14 @@ INTERCEPTOR(int, strncmp, const char *s1, const char *s2, 
usize size) {
   void *ctx;
   COMMON_INTERCEPTOR_ENTER(ctx, strncmp, s1, s2, size);
   unsigned char c1 = 0, c2 = 0;
-  uptr i;
+  usize i;
   for (i = 0; i < size; i++) {
 c1 = (unsigned char)s1[i];
 c2 = (unsigned char)s2[i];
 if (c1 != c2 || c1 == '\0') break;
   }
-  uptr i1 = i;
-  uptr i2 = i;
+  usize i1 = i;
+  usize i2 = i;
   if (common_flags()->strict_string_checks) {
 for (; i1 < size && s1[i1]; i1++) {}
 for (; i2 < size && s2[i2]; i2++) {}
@@ -583,14 +583,14 @@ INTERCEPTOR(int, strncasecmp, const char *s1, const char 
*s2, SIZE_T size) {
   void *ctx;
   COMMON_INTERCEPTOR_ENTER(ctx, strncasecmp, s1, s2, size);
   unsigned char c1 = 0, c2 = 0;
-  uptr i;
+  usize i;
   for (i = 0; i < size; i++) {
 c1 = (unsigned char)s1[i];
 c2 = (unsigned char)s2[i];
 if (CharCaseCmp(c1, c2) != 0 || c1 == '\0') break;
   }
-  uptr i1 = i;
-  uptr i2 = i;
+  usize i1 = i;
+  usize i2 = i;
   if (common_flags()->strict_string_checks) {
 for (; i1 < size && s1[i1]; i1++) {}
 for (; i2 < size && s2[i2]; i2++) {}
@@ -851,7 +851,7 @@ int MemcmpInterceptorCommon(void *ctx,
   unsigned char c1 = 0, c2 = 0;
   const unsigned char *s1 = (const unsigned char*)a1;
   const unsigned char *s2 = (const unsigned char*)a2;
-  uptr i;
+  usize i;
   for (i = 0; i < size; i++) {
 c1 = s1[i];
 c2 = s2[i];

[gcc r15-6605] Replace uptr by usize/SIZE_T in interfaces

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:0bb38b2786a097f97664afbcf6577b77dd305d44

commit r15-6605-g0bb38b2786a097f97664afbcf6577b77dd305d44
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 6 19:17:09 2025 +0100

Replace uptr by usize/SIZE_T in interfaces

For some targets uptr is mapped to unsigned int and size_t to unsigned
long and sizeof(int)==sizeof(long) holds.  Still, these are distinct
types and type checking may fail.  Therefore, replace uptr by
usize/SIZE_T wherever a size_t is expected.

Part of #116957

Cherry picked from LLVM commit 9a156f6b2b0c892d8713ba907f07f027b24953d8
(removed memprof, msan, and nsan parts).

libsanitizer/ChangeLog:

PR sanitizer/117725
* asan/asan_interceptors.cpp: Cherry picked LLVM commit
9a156f6b2b0c892d8713ba907f07f027b24953d8.
* asan/asan_interceptors.h: Ditto.
* asan/asan_interceptors_memintrinsics.h: Ditto.
* sanitizer_common/sanitizer_common_interceptors.inc: Ditto.
* sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc:
Ditto.
* sanitizer_common/sanitizer_platform_limits_posix.h: Ditto.
* tsan/tsan_interceptors_posix.cpp: Ditto.

Diff:
---
 libsanitizer/asan/asan_interceptors.cpp|  6 ++--
 libsanitizer/asan/asan_interceptors.h  |  6 ++--
 .../asan/asan_interceptors_memintrinsics.h |  4 +--
 .../sanitizer_common_interceptors.inc  | 26 -
 ...sanitizer_common_interceptors_memintrinsics.inc | 34 +++---
 .../sanitizer_platform_limits_posix.h  |  2 +-
 libsanitizer/tsan/tsan_interceptors_posix.cpp  |  4 +--
 7 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/libsanitizer/asan/asan_interceptors.cpp 
b/libsanitizer/asan/asan_interceptors.cpp
index c13bcf2382b0..48f7636fbcbc 100644
--- a/libsanitizer/asan/asan_interceptors.cpp
+++ b/libsanitizer/asan/asan_interceptors.cpp
@@ -85,7 +85,7 @@ int OnExit() {
 // -- Wrappers  {{{1
 using namespace __asan;
 
-DECLARE_REAL_AND_INTERCEPTOR(void *, malloc, uptr)
+DECLARE_REAL_AND_INTERCEPTOR(void *, malloc, usize)
 DECLARE_REAL_AND_INTERCEPTOR(void, free, void *)
 
 #define COMMON_INTERCEPT_FUNCTION_VER(name, ver) \
@@ -529,7 +529,7 @@ DEFINE_REAL(char*, index, const char *string, int c)
 return REAL(strcat)(to, from);
   }
 
-INTERCEPTOR(char*, strncat, char *to, const char *from, uptr size) {
+INTERCEPTOR(char*, strncat, char *to, const char *from, usize size) {
   void *ctx;
   ASAN_INTERCEPTOR_ENTER(ctx, strncat);
   AsanInitFromRtl();
@@ -617,7 +617,7 @@ INTERCEPTOR(char*, __strdup, const char *s) {
 }
 #endif // ASAN_INTERCEPT___STRDUP
 
-INTERCEPTOR(char*, strncpy, char *to, const char *from, uptr size) {
+INTERCEPTOR(char*, strncpy, char *to, const char *from, usize size) {
   void *ctx;
   ASAN_INTERCEPTOR_ENTER(ctx, strncpy);
   AsanInitFromRtl();
diff --git a/libsanitizer/asan/asan_interceptors.h 
b/libsanitizer/asan/asan_interceptors.h
index 652379d39a3c..85cde07ca7ee 100644
--- a/libsanitizer/asan/asan_interceptors.h
+++ b/libsanitizer/asan/asan_interceptors.h
@@ -129,11 +129,11 @@ void InitializePlatformInterceptors();
 # define ASAN_INTERCEPT_PTHREAD_ATFORK 0
 #endif
 
-DECLARE_REAL(int, memcmp, const void *a1, const void *a2, uptr size)
+DECLARE_REAL(int, memcmp, const void *a1, const void *a2, SIZE_T size)
 DECLARE_REAL(char*, strchr, const char *str, int c)
 DECLARE_REAL(SIZE_T, strlen, const char *s)
-DECLARE_REAL(char*, strncpy, char *to, const char *from, uptr size)
-DECLARE_REAL(uptr, strnlen, const char *s, uptr maxlen)
+DECLARE_REAL(char*, strncpy, char *to, const char *from, SIZE_T size)
+DECLARE_REAL(SIZE_T, strnlen, const char *s, SIZE_T maxlen)
 DECLARE_REAL(char*, strstr, const char *s1, const char *s2)
 
 #  if !SANITIZER_APPLE
diff --git a/libsanitizer/asan/asan_interceptors_memintrinsics.h 
b/libsanitizer/asan/asan_interceptors_memintrinsics.h
index eb44f8f2f729..14727a5d665e 100644
--- a/libsanitizer/asan/asan_interceptors_memintrinsics.h
+++ b/libsanitizer/asan/asan_interceptors_memintrinsics.h
@@ -18,8 +18,8 @@
 #include "asan_mapping.h"
 #include "interception/interception.h"
 
-DECLARE_REAL(void *, memcpy, void *to, const void *from, uptr size)
-DECLARE_REAL(void *, memset, void *block, int c, uptr size)
+DECLARE_REAL(void *, memcpy, void *to, const void *from, SIZE_T size)
+DECLARE_REAL(void *, memset, void *block, int c, SIZE_T size)
 
 namespace __asan {
 
diff --git a/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc 
b/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
index b8627f8557af..542176e6e5a7 100644
--- a/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
+++ b/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
@@ -445,7 +445,7 @@ INTERCEPTOR(SIZE_T, strnlen, const char *s, SIZE_T maxlen) {
 #endif
 
 #if SANITIZER

[gcc r15-6606] Add type __sanitizer::ssize (#116957)

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1bd03564f29dc31e67e67efd93137d50fa7bb8a4

commit r15-6606-g1bd03564f29dc31e67e67efd93137d50fa7bb8a4
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 6 19:17:09 2025 +0100

Add type __sanitizer::ssize (#116957)

Since the sanitizer merge in commit r15-5164-gfa321004f3f628 of GCC
which entails LLVM commit 61a6439f35b6de28ff4aff4450d6fca970292fd5, GCCs
bootstrap is broken on s390 -m31. This is due to commit
ec68dc1ca4d967b599f1202855917d5ec9cae52f which introduces stricter type
checking which is why GCC bootstrap fails with

```
In file included from /gcc/src/libsanitizer/interception/interception.h:18,
 from 
/gcc/src/libsanitizer/interception/interception_type_test.cpp:14:
/gcc/src/libsanitizer/interception/interception_type_test.cpp:30:61: error: 
static assertion failed
   30 | COMPILER_CHECK((__sanitizer::is_same<::SSIZE_T, ::ssize_t>::value));
  |~^~
/gcc/src/libsanitizer/sanitizer_common/sanitizer_internal_defs.h:363:44: 
note: in definition of macro 'COMPILER_CHECK'
  363 | #define COMPILER_CHECK(pred) static_assert(pred, "")
  |^~~~
make[8]: *** [Makefile:469: interception_type_test.lo] Error 1
```

The culprit seems to be that we don't check for equality of type sizes
anymore but rather whether the types are indeed the same. On s390 -m31
we have that `sizeof(int)==sizeof(long)` holds which is why previously
the checks succeeded. They fail now because

```
size_t  => unsigned long
ssize_t => long
ptrdiff_t   => int
::SSIZE_T   => __sanitizer::sptr => int
::PTRDIFF_T => __sanitizer::sptr => int
```

This is fixed by mapping `SSIZE_T` to `long` in the end.

```
typedef long ssize;
typedef sptr ssize;

```

Cherry picked from LLVM commit ce44640fe29550461120d22b0358e6cac4aed822.

libsanitizer/ChangeLog:

PR sanitizer/117725
* interception/interception.h: Cherry picked from LLVM commit
ce44640fe29550461120d22b0358e6cac4aed822.
* sanitizer_common/sanitizer_internal_defs.h: Ditto.

Diff:
---
 libsanitizer/interception/interception.h| 2 +-
 libsanitizer/sanitizer_common/sanitizer_internal_defs.h | 6 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/libsanitizer/interception/interception.h 
b/libsanitizer/interception/interception.h
index 0580d97edda6..3cb6b446638e 100644
--- a/libsanitizer/interception/interception.h
+++ b/libsanitizer/interception/interception.h
@@ -37,7 +37,7 @@
 #endif
 
 #define SIZE_T __sanitizer::usize
-#define SSIZE_T __sanitizer::sptr
+#define SSIZE_T __sanitizer::ssize
 typedef __sanitizer::sptrPTRDIFF_T;
 typedef __sanitizer::s64 INTMAX_T;
 typedef __sanitizer::u64 UINTMAX_T;
diff --git a/libsanitizer/sanitizer_common/sanitizer_internal_defs.h 
b/libsanitizer/sanitizer_common/sanitizer_internal_defs.h
index 9208b12552ff..fff60c96f632 100644
--- a/libsanitizer/sanitizer_common/sanitizer_internal_defs.h
+++ b/libsanitizer/sanitizer_common/sanitizer_internal_defs.h
@@ -203,6 +203,12 @@ typedef __SIZE_TYPE__ usize;
 typedef uptr usize;
 #endif
 
+#if defined(__s390__) && !defined(__s390x__)
+typedef long ssize;
+#else
+typedef sptr ssize;
+#endif
+
 typedef u64 tid_t;
 
 // --- ATTENTION -

[gcc r15-6607] Fix few size types in memprof (#119114)

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:f0b8256224ec082ecffddcb5624a4b5032c09113

commit r15-6607-gf0b8256224ec082ecffddcb5624a4b5032c09113
Author: Vitaly Buka 
Date:   Mon Jan 6 19:17:09 2025 +0100

Fix few size types in memprof (#119114)

Fix type in a few related Min() calls.

Follow up to #116957.

Cherry picked from LLVM commit 6dec33834d1fd89f16e271dde9607c1de9554144
(removed memprof part).

libsanitizer/ChangeLog:

PR sanitizer/117725
* asan/asan_interceptors.cpp: Cherry picked from LLVM commit
6dec33834d1fd89f16e271dde9607c1de9554144.
* sanitizer_common/sanitizer_common_interceptors.inc: Ditto.

Co-authored-by: Stefan Schulze Frielinghaus 

Diff:
---
 libsanitizer/asan/asan_interceptors.cpp | 4 ++--
 libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/libsanitizer/asan/asan_interceptors.cpp 
b/libsanitizer/asan/asan_interceptors.cpp
index 48f7636fbcbc..0239e0cdf537 100644
--- a/libsanitizer/asan/asan_interceptors.cpp
+++ b/libsanitizer/asan/asan_interceptors.cpp
@@ -535,7 +535,7 @@ INTERCEPTOR(char*, strncat, char *to, const char *from, 
usize size) {
   AsanInitFromRtl();
   if (flags()->replace_str) {
 uptr from_length = MaybeRealStrnlen(from, size);
-uptr copy_length = Min(size, from_length + 1);
+uptr copy_length = Min(size, from_length + 1);
 ASAN_READ_RANGE(ctx, from, copy_length);
 uptr to_length = internal_strlen(to);
 ASAN_READ_STRING_OF_LEN(ctx, to, to_length, to_length);
@@ -622,7 +622,7 @@ INTERCEPTOR(char*, strncpy, char *to, const char *from, 
usize size) {
   ASAN_INTERCEPTOR_ENTER(ctx, strncpy);
   AsanInitFromRtl();
   if (flags()->replace_str) {
-uptr from_size = Min(size, MaybeRealStrnlen(from, size) + 1);
+uptr from_size = Min(size, MaybeRealStrnlen(from, size) + 1);
 CHECK_RANGES_OVERLAP("strncpy", to, from_size, from, from_size);
 ASAN_READ_RANGE(ctx, from, from_size);
 ASAN_WRITE_RANGE(ctx, to, size);
diff --git a/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc 
b/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
index 542176e6e5a7..b0adcf1ea4e4 100644
--- a/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
+++ b/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc
@@ -347,7 +347,7 @@ extern const short *_tolower_tab_;
   uptr copy_length = internal_strnlen(s, size);   \
   char *new_mem = (char *)WRAP(malloc)(copy_length + 1);  \
   if (common_flags()->intercept_strndup) {\
-COMMON_INTERCEPTOR_READ_STRING(ctx, s, Min(size, copy_length + 1));   \
+COMMON_INTERCEPTOR_READ_STRING(ctx, s, Min(size, copy_length + 1)); \
   }   \
   if (new_mem) {  \
 COMMON_INTERCEPTOR_COPY_STRING(ctx, new_mem, s, copy_length); \

[gcc r15-7125] s390: Fix arch15 machine string for binutils

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:9ece1c247b4d8dbb997a3dc16daa613401c6a84a

commit r15-7125-g9ece1c247b4d8dbb997a3dc16daa613401c6a84a
Author: Stefan Schulze Frielinghaus 
Date:   Wed Jan 22 13:55:08 2025 +0100

s390: Fix arch15 machine string for binutils

gcc/ChangeLog:

* config/s390/s390.cc: Fix arch15 machine string which must not
be empty.

Diff:
---
 gcc/config/s390/s390.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 313f968c87e7..86a5f059b85d 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -342,7 +342,7 @@ const struct s390_processor processor_table[] =
   { "z14","arch12", PROCESSOR_3906_Z14,&zEC12_cost,  12 },
   { "z15","arch13", PROCESSOR_8561_Z15,&zEC12_cost,  13 },
   { "z16","arch14", PROCESSOR_3931_Z16,&zEC12_cost,  14 },
-  { "arch15", "",   PROCESSOR_ARCH15,  &zEC12_cost,  15 },
+  { "arch15", "arch15", PROCESSOR_ARCH15,  &zEC12_cost,  15 },
   { "native", "",   PROCESSOR_NATIVE,  NULL, 0  }
 };

[gcc r15-7176] s390: Implement isfinite and isnormal optabs

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:b00bd29286345cc90afc61dcb16d1fa44976dae6

commit r15-7176-gb00bd29286345cc90afc61dcb16d1fa44976dae6
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jan 24 12:53:44 2025 +0100

s390: Implement isfinite and isnormal optabs

Merge new optabs with the existing implementations for signbit and
isinf.

gcc/ChangeLog:

* config/s390/s390.h (S390_TDC_POSITIVE_ZERO): Remove.
(S390_TDC_NEGATIVE_ZERO): Remove.
(S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_POSITIVE_INFINITY): Remove.
(S390_TDC_NEGATIVE_INFINITY): Remove.
(S390_TDC_POSITIVE_QUIET_NAN): Remove.
(S390_TDC_NEGATIVE_QUIET_NAN): Remove.
(S390_TDC_POSITIVE_SIGNALING_NAN): Remove.
(S390_TDC_NEGATIVE_SIGNALING_NAN): Remove.
(S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_SIGNBIT_SET): Remove.
(S390_TDC_INFINITY): Remove.
* config/s390/s390.md (signbit2): Merge this one
(isinf2): and this one into
(2): new expander.
(isnormal2): New BFP expander.
(isnormal2): New DFP expander.
* config/s390/vector.md (signbittf2_vr): Merge this one
(isinftf2_vr): and this one into
(tf2_vr): new expander.
(signbittf2): Merge this one
(isinftf2): and this one into
(tf2): new expander.

gcc/testsuite/ChangeLog:

* gcc.target/s390/isfinite-isinf-isnormal-signbit-1.c: New test.
* gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c: New test.
* gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c: New test.
* gcc.target/s390/isfinite-isinf-isnormal-signbit.h: New test.

Diff:
---
 gcc/config/s390/s390.h |  31 --
 gcc/config/s390/s390.md| 114 +
 gcc/config/s390/vector.md  |  42 ++--
 .../s390/isfinite-isinf-isnormal-signbit-1.c   |  62 +++
 .../s390/isfinite-isinf-isnormal-signbit-2.c   |  13 +++
 .../s390/isfinite-isinf-isnormal-signbit-3.c   |  13 +++
 .../s390/isfinite-isinf-isnormal-signbit.h |  23 +
 7 files changed, 215 insertions(+), 83 deletions(-)

diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 957877b6a389..6f7195db04e1 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -305,37 +305,6 @@ extern const char *s390_host_detect_local_cpu (int argc, 
const char **argv);
   "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}",\
   "%{!march=*:-march=z900}"
 
-/* Constants needed to control the TEST DATA CLASS (TDC) instruction.  */
-#define S390_TDC_POSITIVE_ZERO (1 << 11)
-#define S390_TDC_NEGATIVE_ZERO (1 << 10)
-#define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER(1 << 9)
-#define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER(1 << 8)
-#define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER  (1 << 7)
-#define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER  (1 << 6)
-#define S390_TDC_POSITIVE_INFINITY (1 << 5)
-#define S390_TDC_NEGATIVE_INFINITY (1 << 4)
-#define S390_TDC_POSITIVE_QUIET_NAN(1 << 3)
-#define S390_TDC_NEGATIVE_QUIET_NAN(1 << 2)
-#define S390_TDC_POSITIVE_SIGNALING_NAN(1 << 1)
-#define S390_TDC_NEGATIVE_SIGNALING_NAN(1 << 0)
-
-/* The following values are different for DFP.  */
-#define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9)
-#define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8)
-#define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER   (1 << 7)
-#define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER   (1 << 6)
-
-/* For signbit, the BFP-DFP-difference makes no difference. */
-#define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \
- | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \
- | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\
- | S390_TDC_NEGATIVE_INFINITY \
- | S390_TDC_NEGATIVE_QUIET_NAN \
- | S390_TDC_NEGATIVE_SIGNALING_NAN )
-
-#define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \
- | S390_TDC_NEGATIVE_INFINITY )
-
 /* Target machine storage layout.  */
 
 /* Everything is big-endian.  */
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 8ce93a048734..c164ea72c78b 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390

[gcc r15-7044] s390: arch15: Load indexed address

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:86a1acfd86f881c32e0ae57036df65edd7d1d441

commit r15-7044-g86a1acfd86f881c32e0ae57036df65edd7d1d441
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Load indexed address

Add instructions lxa and llxa.

gcc/ChangeLog:

* config/s390/s390.md (*lxa_index): Add.
(*lxa_displacement_index): Add.
(*lxa_index_base): Add.
(*lxa_displacement_index_base): Add.
(*lxab_displacement_index_base): Add.
(*llxa_displacement_index): Add.
(*llxa_index_base): Add.
(*llxa_displacement_index_base): Add.
(*llxab_displacement_index_base): Add.

gcc/testsuite/ChangeLog:

* gcc.target/s390/llxa-1.c: New test.
* gcc.target/s390/llxa-2.c: New test.
* gcc.target/s390/llxa-3.c: New test.
* gcc.target/s390/lxa-1.c: New test.
* gcc.target/s390/lxa-2.c: New test.
* gcc.target/s390/lxa-3.c: New test.
* gcc.target/s390/lxa-4.c: New test.

Diff:
---
 gcc/config/s390/s390.md| 105 +
 gcc/testsuite/gcc.target/s390/llxa-1.c |  34 +++
 gcc/testsuite/gcc.target/s390/llxa-2.c |  34 +++
 gcc/testsuite/gcc.target/s390/llxa-3.c |  41 +
 gcc/testsuite/gcc.target/s390/lxa-1.c  |  34 +++
 gcc/testsuite/gcc.target/s390/lxa-2.c  |  34 +++
 gcc/testsuite/gcc.target/s390/lxa-3.c  |  34 +++
 gcc/testsuite/gcc.target/s390/lxa-4.c  |  42 +
 8 files changed, 358 insertions(+)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 6a660f108b79..6fed6bf42543 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1963,6 +1963,111 @@
   *,*,yes")
 ])
 
+; LOAD INDEXED ADDRESS
+; lxab, lxah, lxaf, lxag, lxaq
+
+(define_int_iterator LXAMODEITER [1 2 3 4])
+(define_int_attr lxamode [(1 "h") (2 "f") (3 "g") (4 "q")])
+
+; see testsuite/gcc.target/s390/lxa-1.c
+(define_insn "*lxa_index"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "a"))
+  (const_int LXAMODEITER)))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "lxa\t%0,0(%1,0)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/lxa-2.c
+(define_insn "*lxa_displacement_index"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (ashift:DI (sign_extend:DI (plus:SI (match_operand:SI 1 
"register_operand" "a")
+   (match_operand:SI 2 
"const_int_operand")))
+  (const_int LXAMODEITER)))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x8 && INTVAL 
(operands[2]) <= 0x7"
+  "lxa\t%0,%2(%1,0)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/lxa-3.c
+(define_insn "*lxa_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (plus:DI (ashift:DI (sign_extend:DI (match_operand:SI 1 
"register_operand" "a"))
+   (const_int LXAMODEITER))
+(match_operand:DI 2 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "lxa\t%0,0(%1,%2)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/lxa-4.c
+(define_insn "*lxa_displacement_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (plus:DI (ashift:DI (sign_extend:DI (plus:SI (match_operand:SI 1 
"register_operand" "a")
+(match_operand:SI 2 
"const_int_operand")))
+   (const_int LXAMODEITER))
+(match_operand:DI 3 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x8 && INTVAL 
(operands[2]) <= 0x7"
+  "lxa\t%0,%2(%1,%3)"
+  [(set_attr "op_type" "RXY")])
+
+(define_insn "*lxab_displacement_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (plus:DI (sign_extend:DI (plus:SI (match_operand:SI 1 
"register_operand" "a")
+ (match_operand:SI 2 
"const_int_operand")))
+(match_operand:DI 3 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x8 && INTVAL 
(operands[2]) <= 0x7"
+  "lxab\t%0,%2(%1,%3)"
+  [(set_attr "op_type" "RXY")])
+
+; LOAD LOGICAL INDEXED ADDRESS
+; llxab, llxah, llxaf, llxag, llxaq
+
+(define_int_attr LLXAMASK [(1 "8589934590") (2 "17179869180") (3 
"34359738360") (4 "68719476720")])
+
+; see testsuite/gcc.target/s390/llxa-1.c
+(define_insn "*llxa_displacement_index"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (and:DI (ashift:DI (subreg:DI (plus:SI (match_operand:SI 1 
"register_operand" "a")
+  (match_operand:SI 2 
"const_int_operand"))
+ 0)
+   

[gcc r15-7043] s390: arch15: New instruction variants supporting 128-bit integer

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:447b917e98ee34e2eae455b43784ab6a86b604f2

commit r15-7043-g447b917e98ee34e2eae455b43784ab6a86b604f2
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:08 2025 +0100

s390: arch15: New instruction variants supporting 128-bit integer

Add new instruction variants and also extend builtins in order to deal
with 128-bit integer.

gcc/ChangeLog:

* config/s390/s390-builtins.def: Add new instruction variants.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/vecintrin.h: Add new defines.
* config/s390/vector.md: Adapt insns for new instruction
variants.
* config/s390/vx-builtins.md: Ditto.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |  58 +++
 gcc/config/s390/s390-builtins.def  | 182 -
 gcc/config/s390/vecintrin.h|   7 ++
 gcc/config/s390/vector.md  |  60 ++-
 gcc/config/s390/vx-builtins.md | 146 +-
 5 files changed, 329 insertions(+), 124 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 2993aea3fb9b..f995fe47f1da 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -58,6 +58,7 @@ DEF_TYPE (BT_FLT, float_type_node, 0)
 DEF_TYPE (BT_FLTCONST, float_type_node, 1)
 DEF_TYPE (BT_INT, integer_type_node, 0)
 DEF_TYPE (BT_INT128, intTI_type_node, 0)
+DEF_TYPE (BT_INT128CONST, intTI_type_node, 1)
 DEF_TYPE (BT_INTCONST, integer_type_node, 1)
 DEF_TYPE (BT_LONG, long_integer_type_node, 0)
 DEF_TYPE (BT_LONGLONG, long_long_integer_type_node, 0)
@@ -70,6 +71,7 @@ DEF_TYPE (BT_UCHAR, unsigned_char_type_node, 0)
 DEF_TYPE (BT_UCHARCONST, unsigned_char_type_node, 1)
 DEF_TYPE (BT_UINT, unsigned_type_node, 0)
 DEF_TYPE (BT_UINT128, unsigned_intTI_type_node, 0)
+DEF_TYPE (BT_UINT128CONST, unsigned_intTI_type_node, 1)
 DEF_TYPE (BT_UINT64, c_uint64_type_node, 0)
 DEF_TYPE (BT_UINTCONST, unsigned_type_node, 1)
 DEF_TYPE (BT_ULONG, long_unsigned_type_node, 0)
@@ -80,10 +82,12 @@ DEF_TYPE (BT_USHORTCONST, short_unsigned_type_node, 1)
 DEF_TYPE (BT_VOID, void_type_node, 0)
 DEF_TYPE (BT_VOIDCONST, void_type_node, 1)
 DEF_VECTOR_TYPE (BT_UV16QI, BT_UCHAR, 16)
+DEF_VECTOR_TYPE (BT_UV1TI, BT_UINT128, 1)
 DEF_VECTOR_TYPE (BT_UV2DI, BT_ULONGLONG, 2)
 DEF_VECTOR_TYPE (BT_UV4SI, BT_UINT, 4)
 DEF_VECTOR_TYPE (BT_UV8HI, BT_USHORT, 8)
 DEF_VECTOR_TYPE (BT_V16QI, BT_SCHAR, 16)
+DEF_VECTOR_TYPE (BT_V1TI, BT_INT128, 1)
 DEF_VECTOR_TYPE (BT_V2DF, BT_DBL, 2)
 DEF_VECTOR_TYPE (BT_V2DI, BT_LONGLONG, 2)
 DEF_VECTOR_TYPE (BT_V4SF, BT_FLT, 4)
@@ -93,6 +97,8 @@ DEF_POINTER_TYPE (BT_DBLCONSTPTR, BT_DBLCONST)
 DEF_POINTER_TYPE (BT_DBLPTR, BT_DBL)
 DEF_POINTER_TYPE (BT_FLTCONSTPTR, BT_FLTCONST)
 DEF_POINTER_TYPE (BT_FLTPTR, BT_FLT)
+DEF_POINTER_TYPE (BT_INT128CONSTPTR, BT_INT128CONST)
+DEF_POINTER_TYPE (BT_INT128PTR, BT_INT128)
 DEF_POINTER_TYPE (BT_INTCONSTPTR, BT_INTCONST)
 DEF_POINTER_TYPE (BT_INTPTR, BT_INT)
 DEF_POINTER_TYPE (BT_LONGLONGCONSTPTR, BT_LONGLONGCONST)
@@ -103,6 +109,8 @@ DEF_POINTER_TYPE (BT_SHORTCONSTPTR, BT_SHORTCONST)
 DEF_POINTER_TYPE (BT_SHORTPTR, BT_SHORT)
 DEF_POINTER_TYPE (BT_UCHARCONSTPTR, BT_UCHARCONST)
 DEF_POINTER_TYPE (BT_UCHARPTR, BT_UCHAR)
+DEF_POINTER_TYPE (BT_UINT128CONSTPTR, BT_UINT128CONST)
+DEF_POINTER_TYPE (BT_UINT128PTR, BT_UINT128)
 DEF_POINTER_TYPE (BT_UINT64PTR, BT_UINT64)
 DEF_POINTER_TYPE (BT_UINTCONSTPTR, BT_UINTCONST)
 DEF_POINTER_TYPE (BT_UINTPTR, BT_UINT)
@@ -128,12 +136,14 @@ DEF_OPAQUE_VECTOR_TYPE (BT_OV4SI, BT_INT, 4)
 DEF_FN_TYPE_0 (BT_FN_INT, BT_INT)
 DEF_FN_TYPE_0 (BT_FN_UINT, BT_UINT)
 DEF_FN_TYPE_0 (BT_FN_VOID, BT_VOID)
+DEF_FN_TYPE_1 (BT_FN_INT128_V2DI, BT_INT128, BT_V2DI)
 DEF_FN_TYPE_1 (BT_FN_INT_INT, BT_INT, BT_INT)
 DEF_FN_TYPE_1 (BT_FN_INT_VOIDPTR, BT_INT, BT_VOIDPTR)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_INT, BT_OV4SI, BT_INT)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_INTCONSTPTR, BT_OV4SI, BT_INTCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI)
 DEF_FN_TYPE_1 (BT_FN_UINT128_UINT128, BT_UINT128, BT_UINT128)
+DEF_FN_TYPE_1 (BT_FN_UINT128_UV2DI, BT_UINT128, BT_UV2DI)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UCHAR, BT_UV16QI, BT_UCHAR)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UCHARCONSTPTR, BT_UV16QI, BT_UCHARCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_USHORT, BT_UV16QI, BT_USHORT)
@@ -187,6 +197,7 @@ DEF_FN_TYPE_1 (BT_FN_VOID_UINT, BT_VOID, BT_UINT)
 DEF_FN_TYPE_2 (BT_FN_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_INT128_INT128_INT128, BT_INT128, BT_INT128, BT_INT128)
+DEF_FN_TYPE_2 (BT_FN_INT128_V2DI_V2DI, BT_INT128, BT_V2DI, BT_V2DI)
 DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_INT, BT_INT, BT_OV4SI, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_OV4SI, BT_INT, BT_OV4SI, BT_OV4SI)
 DEF_FN_TYPE_2 (BT_FN_INT_UV16QI_UV16QI, BT_INT, BT_UV16QI, BT_UV16QI)
@@ -226,6 +237,7 @@ DEF_FN_TYPE_2 (BT_FN_UV16QI_UV

[gcc r15-7051] s390: arch15: Vector compare: Add 128-bit integer support

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:2e87d6e44198e2b134555d661366a2f941615511

commit r15-7051-g2e87d6e44198e2b134555d661366a2f941615511
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:10 2025 +0100

s390: arch15: Vector compare: Add 128-bit integer support

gcc/ChangeLog:

* config/s390/s390-builtins.def: Add 128-bit variants.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.cc (s390_expand_vec_compare_cc): Also
consider TI modes for vectors.
* config/s390/vector.md: Enable *vec_cmp et al. for VXE3.
* config/s390/vx-builtins.md: Ditto.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |   9 +++
 gcc/config/s390/s390-builtins.def  |  71 +++
 gcc/config/s390/s390.cc|   3 +-
 gcc/config/s390/vector.md  |  20 ---
 gcc/config/s390/vx-builtins.md | 100 -
 5 files changed, 143 insertions(+), 60 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 6f903deb7450..7aeea343126a 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -202,9 +202,12 @@ DEF_FN_TYPE_1 (BT_FN_VOID_UINT, BT_VOID, BT_UINT)
 DEF_FN_TYPE_2 (BT_FN_DBL_V2DF_INT, BT_DBL, BT_V2DF, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_INT128_INT128_INT128, BT_INT128, BT_INT128, BT_INT128)
+DEF_FN_TYPE_2 (BT_FN_INT128_UINT128_UINT128, BT_INT128, BT_UINT128, BT_UINT128)
 DEF_FN_TYPE_2 (BT_FN_INT128_V2DI_V2DI, BT_INT128, BT_V2DI, BT_V2DI)
+DEF_FN_TYPE_2 (BT_FN_INT_INT128_INT128, BT_INT, BT_INT128, BT_INT128)
 DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_INT, BT_INT, BT_OV4SI, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_INT_OV4SI_OV4SI, BT_INT, BT_OV4SI, BT_OV4SI)
+DEF_FN_TYPE_2 (BT_FN_INT_UINT128_UINT128, BT_INT, BT_UINT128, BT_UINT128)
 DEF_FN_TYPE_2 (BT_FN_INT_UV16QI_UV16QI, BT_INT, BT_UV16QI, BT_UV16QI)
 DEF_FN_TYPE_2 (BT_FN_INT_UV2DI_UV2DI, BT_INT, BT_UV2DI, BT_UV2DI)
 DEF_FN_TYPE_2 (BT_FN_INT_UV4SI_UV4SI, BT_INT, BT_UV4SI, BT_UV4SI)
@@ -304,6 +307,8 @@ DEF_FN_TYPE_2 (BT_FN_VOID_V2DF_FLTPTR, BT_VOID, BT_V2DF, 
BT_FLTPTR)
 DEF_FN_TYPE_3 (BT_FN_BV2DI_V2DF_USHORT_INTPTR, BT_BV2DI, BT_V2DF, BT_USHORT, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_BV4SI_V4SF_USHORT_INTPTR, BT_BV4SI, BT_V4SF, BT_USHORT, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_INT128_INT128_INT128_INT128, BT_INT128, BT_INT128, 
BT_INT128, BT_INT128)
+DEF_FN_TYPE_3 (BT_FN_INT128_INT128_INT128_INTPTR, BT_INT128, BT_INT128, 
BT_INT128, BT_INTPTR)
+DEF_FN_TYPE_3 (BT_FN_INT128_UINT128_UINT128_INTPTR, BT_INT128, BT_UINT128, 
BT_UINT128, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_INT128_V2DI_V2DI_INT128, BT_INT128, BT_V2DI, BT_V2DI, 
BT_INT128)
 DEF_FN_TYPE_3 (BT_FN_INT_OV4SI_OV4SI_INTPTR, BT_INT, BT_OV4SI, BT_OV4SI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_OV4SI_INT_OV4SI_INT, BT_OV4SI, BT_INT, BT_OV4SI, BT_INT)
@@ -433,6 +438,8 @@ DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_UV16QI, BT_BV1TI, 
BT_BV1TI, BT_BV1TI, BT_UV
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_UV1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_UV1TI)
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_V1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_V1TI)
 DEF_OV_TYPE (BT_OV_BV1TI_BV2DI, BT_BV1TI, BT_BV2DI)
+DEF_OV_TYPE (BT_OV_BV1TI_UV1TI_UV1TI, BT_BV1TI, BT_UV1TI, BT_UV1TI)
+DEF_OV_TYPE (BT_OV_BV1TI_V1TI_V1TI, BT_BV1TI, BT_V1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_BV2DI_BV1TI_BV1TI, BT_BV2DI, BT_BV1TI, BT_BV1TI)
 DEF_OV_TYPE (BT_OV_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI)
@@ -505,6 +512,7 @@ DEF_OV_TYPE (BT_OV_FLT_V4SF_INT, BT_FLT, BT_V4SF, BT_INT)
 DEF_OV_TYPE (BT_OV_INT_BV16QI_BV16QI, BT_INT, BT_BV16QI, BT_BV16QI)
 DEF_OV_TYPE (BT_OV_INT_BV16QI_UV16QI, BT_INT, BT_BV16QI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_INT_BV16QI_V16QI, BT_INT, BT_BV16QI, BT_V16QI)
+DEF_OV_TYPE (BT_OV_INT_BV1TI_BV1TI, BT_INT, BT_BV1TI, BT_BV1TI)
 DEF_OV_TYPE (BT_OV_INT_BV2DI_BV2DI, BT_INT, BT_BV2DI, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_INT_BV2DI_UV2DI, BT_INT, BT_BV2DI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_INT_BV2DI_V2DI, BT_INT, BT_BV2DI, BT_V2DI)
@@ -527,6 +535,7 @@ DEF_OV_TYPE (BT_OV_INT_V16QI_BV16QI, BT_INT, BT_V16QI, 
BT_BV16QI)
 DEF_OV_TYPE (BT_OV_INT_V16QI_UV16QI, BT_INT, BT_V16QI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_INT_V16QI_V16QI, BT_INT, BT_V16QI, BT_V16QI)
 DEF_OV_TYPE (BT_OV_INT_V1TI_UV1TI, BT_INT, BT_V1TI, BT_UV1TI)
+DEF_OV_TYPE (BT_OV_INT_V1TI_V1TI, BT_INT, BT_V1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_INT_V2DF_UV2DI, BT_INT, BT_V2DF, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_INT_V2DF_V2DF, BT_INT, BT_V2DF, BT_V2DF)
 DEF_OV_TYPE (BT_OV_INT_V2DI_BV2DI, BT_INT, BT_V2DI, BT_BV2DI)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 8eb07e6c79d3..9c3334453b81 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1007,6 +1007,7 @@ B_DEF  (s390_vceqbs,
vec_cmpeqv16qi_cc,  0,
 B_DEF  (s390_vceqh

[gcc r15-7055] s390: Update vec_(load,store)_len(,_r)

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:459816efa13d9d553a5c900336f6eef22072f1a1

commit r15-7055-g459816efa13d9d553a5c900336f6eef22072f1a1
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:10 2025 +0100

s390: Update vec_(load,store)_len(,_r)

Reflect latest updates for vec_(load,store)_len(,_r) which means that
all types except character based types are deprecated.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_vec_load_len): Deprecate
some overloads.
(s390_vec_store_len): Deprecate some overloads.
(s390_vec_load_len_r): Add.
(s390_vec_store_len_r): Add.
* config/s390/s390-c.cc (s390_vec_load_len_r): Add.
(s390_vec_store_len_r): Add.
* config/s390/vecintrin.h (vec_load_len_r): Redefine.
(vec_store_len_r): Redefine.

Diff:
---
 gcc/config/s390/s390-builtins.def | 40 +++
 gcc/config/s390/s390-c.cc |  2 ++
 gcc/config/s390/vecintrin.h   |  6 ++
 3 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 24941ed03515..d9af9b13def1 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -529,14 +529,18 @@ OB_DEF_VAR (s390_vec_load_pair_u64, MAX,  
  0,
 OB_DEF (s390_vec_load_len,  
s390_vec_load_len_s8,s390_vec_load_len_dbl,B_VX,
BT_FN_OV4SI_INTCONSTPTR_UINT)
 OB_DEF_VAR (s390_vec_load_len_s8,   s390_vll,   0, 
 0,  BT_OV_V16QI_SCHARCONSTPTR_UINT)
 OB_DEF_VAR (s390_vec_load_len_u8,   s390_vll,   0, 
 0,  BT_OV_UV16QI_UCHARCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_s16,  s390_vll,   0, 
 0,  BT_OV_V8HI_SHORTCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_u16,  s390_vll,   0, 
 0,  BT_OV_UV8HI_USHORTCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_s32,  s390_vll,   0, 
 0,  BT_OV_V4SI_INTCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_u32,  s390_vll,   0, 
 0,  BT_OV_UV4SI_UINTCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_s64,  s390_vll,   0, 
 0,  BT_OV_V2DI_LONGLONGCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_u64,  s390_vll,   0, 
 0,  BT_OV_UV2DI_ULONGLONGCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_flt,  s390_vll,   B_VXE, 
 0,  BT_OV_V4SF_FLTCONSTPTR_UINT)
-OB_DEF_VAR (s390_vec_load_len_dbl,  s390_vll,   0, 
 0,  BT_OV_V2DF_DBLCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_s16,  s390_vll,   B_DEP, 
 0,  BT_OV_V8HI_SHORTCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_u16,  s390_vll,   B_DEP, 
 0,  BT_OV_UV8HI_USHORTCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_s32,  s390_vll,   B_DEP, 
 0,  BT_OV_V4SI_INTCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_u32,  s390_vll,   B_DEP, 
 0,  BT_OV_UV4SI_UINTCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_s64,  s390_vll,   B_DEP, 
 0,  BT_OV_V2DI_LONGLONGCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_u64,  s390_vll,   B_DEP, 
 0,  BT_OV_UV2DI_ULONGLONGCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_flt,  s390_vll,   B_DEP | B_VXE, 
 0,  BT_OV_V4SF_FLTCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_dbl,  s390_vll,   B_DEP, 
 0,  BT_OV_V2DF_DBLCONSTPTR_UINT)
+
+OB_DEF (s390_vec_load_len_r,
s390_vec_load_len_r_s8,s390_vec_load_len_r_u8,B_VXE,
BT_FN_OV4SI_INTCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_r_s8, s390_vlrlr, 0, 
 0,  BT_OV_V16QI_SCHARCONSTPTR_UINT)
+OB_DEF_VAR (s390_vec_load_len_r_u8, s390_vlrlr, 0, 
 0,  BT_OV_UV16QI_UCHARCONSTPTR_UINT)
 
 B_DEF  (s390_vll,   vllv16qi,   0, 
 B_VX,   0,  BT_FN_V16QI_UINT_VOIDCONSTPTR)
 B_DEF  (s390_vlrlr, vlrlrv16qi, 0, 
 B_VXE,  0,  BT_FN_V16QI_UINT_VOIDCONSTPTR)
@@ -808,14 +812,18 @@ OB_DEF_VAR (s390_vec_xstw4_flt, MAX,  
  B_VXE,
 OB_DEF (s390_vec_store_len, 
s390_vec_store_len_s8,s390_vec_store_len_dbl,B_VX,  
BT_FN_VOID_OV4SI_VOIDPTR_UINT)
 OB_DEF_VAR (s390_vec_store_len_s8,  s390_vstl,  0, 
 0,  BT_OV_VOID_V16QI_SCHARPTR_UINT)
 O

[gcc r15-7053] s390: arch15: Vector maximum/minimum: Add 128-bit integer support

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:ec226016ca4954a431409699a52850717617bbfa

commit r15-7053-gec226016ca4954a431409699a52850717617bbfa
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:10 2025 +0100

s390: arch15: Vector maximum/minimum: Add 128-bit integer support

For previous architectures emulate operation max/min.

gcc/ChangeLog:

* config/s390/s390-builtins.def: Add 128-bit variants and remove
bool variants.
* config/s390/s390-builtin-types.def: Update accordinly.
* config/s390/s390.md: Emulate min/max for GPR.
* config/s390/vector.md: Add min/max patterns and emulate in
case of no VXE3.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-max-emu.c: New test.
* gcc.target/s390/vector/vec-min-emu.c: New test.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |   3 -
 gcc/config/s390/s390-builtins.def  |  20 ++--
 gcc/config/s390/s390.md|  23 +
 gcc/config/s390/vector.md  | 104 +
 gcc/testsuite/gcc.target/s390/vector/vec-max-emu.c |  57 +++
 gcc/testsuite/gcc.target/s390/vector/vec-min-emu.c |  57 +++
 6 files changed, 235 insertions(+), 29 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 398ea6eb60a1..dc61c04848ea 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -281,7 +281,6 @@ DEF_FN_TYPE_2 (BT_FN_V2DF_UV4SI_INT, BT_V2DF, BT_UV4SI, 
BT_INT)
 DEF_FN_TYPE_2 (BT_FN_V2DF_V2DF_UCHAR, BT_V2DF, BT_V2DF, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
 DEF_FN_TYPE_2 (BT_FN_V2DF_V2DI_INT, BT_V2DF, BT_V2DI, BT_INT)
-DEF_FN_TYPE_2 (BT_FN_V2DI_BV2DI_V2DI, BT_V2DI, BT_BV2DI, BT_V2DI)
 DEF_FN_TYPE_2 (BT_FN_V2DI_UV2DI_UV2DI, BT_V2DI, BT_UV2DI, BT_UV2DI)
 DEF_FN_TYPE_2 (BT_FN_V2DI_V2DF_INT, BT_V2DI, BT_V2DF, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_V2DI_V2DF_V2DF, BT_V2DI, BT_V2DF, BT_V2DF)
@@ -291,14 +290,12 @@ DEF_FN_TYPE_2 (BT_FN_V4SF_FLT_INT, BT_V4SF, BT_FLT, 
BT_INT)
 DEF_FN_TYPE_2 (BT_FN_V4SF_UV8HI_UINT, BT_V4SF, BT_UV8HI, BT_UINT)
 DEF_FN_TYPE_2 (BT_FN_V4SF_V4SF_UCHAR, BT_V4SF, BT_V4SF, BT_UCHAR)
 DEF_FN_TYPE_2 (BT_FN_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
-DEF_FN_TYPE_2 (BT_FN_V4SI_BV4SI_V4SI, BT_V4SI, BT_BV4SI, BT_V4SI)
 DEF_FN_TYPE_2 (BT_FN_V4SI_INT_VOIDCONSTPTR, BT_V4SI, BT_INT, BT_VOIDCONSTPTR)
 DEF_FN_TYPE_2 (BT_FN_V4SI_UV4SI_UV4SI, BT_V4SI, BT_UV4SI, BT_UV4SI)
 DEF_FN_TYPE_2 (BT_FN_V4SI_V2DI_V2DI, BT_V4SI, BT_V2DI, BT_V2DI)
 DEF_FN_TYPE_2 (BT_FN_V4SI_V4SF_V4SF, BT_V4SI, BT_V4SF, BT_V4SF)
 DEF_FN_TYPE_2 (BT_FN_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI)
 DEF_FN_TYPE_2 (BT_FN_V4SI_V8HI_V8HI, BT_V4SI, BT_V8HI, BT_V8HI)
-DEF_FN_TYPE_2 (BT_FN_V8HI_BV8HI_V8HI, BT_V8HI, BT_BV8HI, BT_V8HI)
 DEF_FN_TYPE_2 (BT_FN_V8HI_UV8HI_UV8HI, BT_V8HI, BT_UV8HI, BT_UV8HI)
 DEF_FN_TYPE_2 (BT_FN_V8HI_V16QI_V16QI, BT_V8HI, BT_V16QI, BT_V16QI)
 DEF_FN_TYPE_2 (BT_FN_V8HI_V4SI_V4SI, BT_V8HI, BT_V4SI, BT_V4SI)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 32ec2eb8a416..b1c3938abe5c 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1857,17 +1857,21 @@ OB_DEF_VAR (s390_vec_max_s64_c, s390_vmxg,  
B_DEP,
 OB_DEF_VAR (s390_vec_max_u64_a, s390_vmxlg, B_DEP, 
 0,  BT_OV_UV2DI_BV2DI_UV2DI)
 OB_DEF_VAR (s390_vec_max_u64_b, s390_vmxlg, 0, 
 0,  BT_OV_UV2DI_UV2DI_UV2DI)
 OB_DEF_VAR (s390_vec_max_u64_c, s390_vmxlg, B_DEP, 
 0,  BT_OV_UV2DI_UV2DI_BV2DI)
+OB_DEF_VAR (s390_vec_max_s128,  s390_vmxq,  0, 
 0,  BT_OV_V1TI_V1TI_V1TI)/* NOGEN */
+OB_DEF_VAR (s390_vec_max_u128,  s390_vmxlq, 0, 
 0,  BT_OV_UV1TI_UV1TI_UV1TI) /* NOGEN */
 OB_DEF_VAR (s390_vec_max_flt,   s390_vfmaxsb_4, B_VXE, 
 0,  BT_OV_V4SF_V4SF_V4SF)
 OB_DEF_VAR (s390_vec_max_dbl,   s390_vfmaxdb_4, 0, 
 0,  BT_OV_V2DF_V2DF_V2DF)
 
 B_DEF  (s390_vmxb,  smaxv16qi3, 0, 
 B_VX,   0,  BT_FN_V16QI_BV16QI_V16QI)
 B_DEF  (s390_vmxlb, umaxv16qi3, 0, 
 B_VX,   0,  BT_FN_UV16QI_UV16QI_UV16QI)
-B_DEF  (s390_vmxh,  smaxv8hi3,  0, 
 B_VX,   0,  BT_FN_V8HI_BV8HI_V8HI)
+B_DEF  (s390_vmxh,  smaxv8hi3,  0, 
 B_VX,   0,  BT_FN_V8HI_V8HI_V8HI)
 B_DEF  (s390_vmxlh, umaxv8hi3,  0,  

[gcc r15-7050] s390: arch15: Vector devide/remainder

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:f31dd2d9e683ddd8534663af092984ddb911

commit r15-7050-gf31dd2d9e683ddd8534663af092984ddb911
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Vector devide/remainder

gcc/ChangeLog:

* config/s390/vector.md (div3): Add.
(udiv3): Add.
(mod3): Add.
(umod3): Add.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vxe3/vd-1.c: New test.
* gcc.target/s390/vxe3/vd-2.c: New test.
* gcc.target/s390/vxe3/vdl-1.c: New test.
* gcc.target/s390/vxe3/vdl-2.c: New test.
* gcc.target/s390/vxe3/vr-1.c: New test.
* gcc.target/s390/vxe3/vr-2.c: New test.
* gcc.target/s390/vxe3/vrl-1.c: New test.
* gcc.target/s390/vxe3/vrl-2.c: New test.

Diff:
---
 gcc/config/s390/vector.md  | 36 ++
 gcc/testsuite/gcc.target/s390/vxe3/vd-1.c  | 27 ++
 gcc/testsuite/gcc.target/s390/vxe3/vd-2.c  | 21 +
 gcc/testsuite/gcc.target/s390/vxe3/vdl-1.c | 27 ++
 gcc/testsuite/gcc.target/s390/vxe3/vdl-2.c | 21 +
 gcc/testsuite/gcc.target/s390/vxe3/vr-1.c  | 27 ++
 gcc/testsuite/gcc.target/s390/vxe3/vr-2.c  | 21 +
 gcc/testsuite/gcc.target/s390/vxe3/vrl-1.c | 27 ++
 gcc/testsuite/gcc.target/s390/vxe3/vrl-2.c | 21 +
 9 files changed, 228 insertions(+)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 2e7419c45c38..606c68268606 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -1145,6 +1145,42 @@
   "vml\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
+; vdf, vdg, vdq
+(define_insn "div3"
+  [(set (match_operand:VI_HW_SDT0 "register_operand" "=v")
+   (div:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand"  "v")
+  (match_operand:VI_HW_SDT 2 "register_operand"  "v")))]
+  "TARGET_VXE3"
+  "vd\t%v0,%v1,%v2,0"
+  [(set_attr "op_type" "VRR")])
+
+; vdlf, vdlg, vdlq
+(define_insn "udiv3"
+  [(set (match_operand:VI_HW_SDT 0 "register_operand" "=v")
+   (udiv:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand"  "v")
+   (match_operand:VI_HW_SDT 2 "register_operand"  "v")))]
+  "TARGET_VXE3"
+  "vdl\t%v0,%v1,%v2,0"
+  [(set_attr "op_type" "VRR")])
+
+; vrf, vrg, vrq
+(define_insn "mod3"
+  [(set (match_operand:VI_HW_SDT0 "register_operand" "=v")
+   (mod:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand"  "v")
+  (match_operand:VI_HW_SDT 2 "register_operand"  "v")))]
+  "TARGET_VXE3"
+  "vr\t%v0,%v1,%v2,0"
+  [(set_attr "op_type" "VRR")])
+
+; vrlf, vrlg, vrlq
+(define_insn "umod3"
+  [(set (match_operand:VI_HW_SDT 0 "register_operand" "=v")
+   (umod:VI_HW_SDT (match_operand:VI_HW_SDT 1 "register_operand"  "v")
+   (match_operand:VI_HW_SDT 2 "register_operand"  "v")))]
+  "TARGET_VXE3"
+  "vrl\t%v0,%v1,%v2,0"
+  [(set_attr "op_type" "VRR")])
+
 ; vlcb, vlch, vlcf, vlcg
 (define_insn "neg2"
   [(set (match_operand:VI 0 "register_operand" "=v")
diff --git a/gcc/testsuite/gcc.target/s390/vxe3/vd-1.c 
b/gcc/testsuite/gcc.target/s390/vxe3/vd-1.c
new file mode 100644
index ..43a2666788d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vxe3/vd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler {\tvdf\t%v[0-9]+,%v[0-9]+,%v[0-9]+,0} } } */
+/* { dg-final { scan-assembler {\tvdg\t%v[0-9]+,%v[0-9]+,%v[0-9]+,0} } } */
+/* { dg-final { scan-assembler {\tvdq\t%v[0-9]+,%v[0-9]+,%v[0-9]+,0} } } */
+
+typedef int __attribute__ ((vector_size (16))) V4SI;
+typedef long long __attribute__ ((vector_size (16))) V2DI;
+typedef __int128 __attribute__ ((vector_size (16))) V1TI;
+
+V4SI
+vdf (V4SI x, V4SI y)
+{
+  return x / y;
+}
+
+V2DI
+vdg (V2DI x, V2DI y)
+{
+  return x / y;
+}
+
+V1TI
+vdq (V1TI x, V1TI y)
+{
+  return x / y;
+}
diff --git a/gcc/testsuite/gcc.target/s390/vxe3/vd-2.c 
b/gcc/testsuite/gcc.target/s390/vxe3/vd-2.c
new file mode 100644
index ..49c7abd03f64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vxe3/vd-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-final { scan-assembler {\tvdf\t%v[0-9]+,%v[0-9]+,%v[0-9]+,0} } } */
+/* { dg-final { scan-assembler {\tvdg\t%v[0-9]+,%v[0-9]+,%v[0-9]+,0} } } */
+/* { dg-final { scan-assembler {\tvdq\t%v[0-9]+,%v[0-9]+,%v[0-9]+,0} } } */
+
+typedef int int32;
+typedef long long int64;
+typedef __int128 int128;
+
+#define vd(T) \
+void \
+vd_##T (T *res, T *x, T *y) \
+{ \
+  for (int i = 0; i < 128; ++i) \
+res[i] = x[i] / *y; \
+}
+
+vd(int32)
+vd(int64)
+vd(int128)
diff --git a/gcc/testsuite/gcc.target/s390/vxe3/vdl-1.c 
b/gcc/tes

[gcc r15-7052] s390: arch15: Vector load positive: Add 128-bit integer support

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:4cf5e261df34878033e20fb2b8a13ea643ab7f4c

commit r15-7052-g4cf5e261df34878033e20fb2b8a13ea643ab7f4c
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:10 2025 +0100

s390: arch15: Vector load positive: Add 128-bit integer support

For previous architectures emulate operation abs.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_vec_abs_s128): Add.
(s390_vlpq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/vector.md (abs2): Emulate w/o VXE3.
(*abs2): Add 128-bit variant.
(*vec_sel0): Make it a ...
(vec_sel0): named pattern.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-abs-emu.c: New test.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |  1 +
 gcc/config/s390/s390-builtins.def  |  2 +
 gcc/config/s390/vector.md  | 29 +++---
 gcc/testsuite/gcc.target/s390/vector/vec-abs-emu.c | 46 ++
 4 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 7aeea343126a..398ea6eb60a1 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -136,6 +136,7 @@ DEF_OPAQUE_VECTOR_TYPE (BT_OV4SI, BT_INT, 4)
 DEF_FN_TYPE_0 (BT_FN_INT, BT_INT)
 DEF_FN_TYPE_0 (BT_FN_UINT, BT_UINT)
 DEF_FN_TYPE_0 (BT_FN_VOID, BT_VOID)
+DEF_FN_TYPE_1 (BT_FN_INT128_INT128, BT_INT128, BT_INT128)
 DEF_FN_TYPE_1 (BT_FN_INT128_V2DI, BT_INT128, BT_V2DI)
 DEF_FN_TYPE_1 (BT_FN_INT_INT, BT_INT, BT_INT)
 DEF_FN_TYPE_1 (BT_FN_INT_VOIDPTR, BT_INT, BT_VOIDPTR)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 9c3334453b81..32ec2eb8a416 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1820,6 +1820,7 @@ OB_DEF_VAR (s390_vec_abs_s8,s390_vlpb,
  0,
 OB_DEF_VAR (s390_vec_abs_s16,   s390_vlph,  0, 
 0,  BT_OV_V8HI_V8HI)
 OB_DEF_VAR (s390_vec_abs_s32,   s390_vlpf,  0, 
 0,  BT_OV_V4SI_V4SI)
 OB_DEF_VAR (s390_vec_abs_s64,   s390_vlpg,  0, 
 0,  BT_OV_V2DI_V2DI)
+OB_DEF_VAR (s390_vec_abs_s128,  s390_vlpq,  0, 
 0,  BT_OV_V1TI_V1TI)/* NOGEN */
 OB_DEF_VAR (s390_vec_abs_flt,   s390_vflpsb,B_VXE, 
 0,  BT_OV_V4SF_V4SF)
 OB_DEF_VAR (s390_vec_abs_dbl,   s390_vflpdb,0, 
 0,  BT_OV_V2DF_V2DF)
 
@@ -1827,6 +1828,7 @@ B_DEF  (s390_vlpb,  absv16qi2,
  0,
 B_DEF  (s390_vlph,  absv8hi2,   0, 
 B_VX,   0,  BT_FN_V8HI_V8HI)
 B_DEF  (s390_vlpf,  absv4si2,   0, 
 B_VX,   0,  BT_FN_V4SI_V4SI)
 B_DEF  (s390_vlpg,  absv2di2,   0, 
 B_VX,   0,  BT_FN_V2DI_V2DI)
+B_DEF  (s390_vlpq,  absti2, 0, 
 B_VX,   0,  BT_FN_INT128_INT128)
 B_DEF  (s390_vflpsb,absv4sf2,   0, 
 B_VXE,  0,  BT_FN_V4SF_V4SF)
 B_DEF  (s390_vflpdb,absv2df2,   0, 
 B_VX,   0,  BT_FN_V2DF_V2DF)
 
diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 57a9d20f7f76..8824c4fbebdb 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -1191,10 +1191,29 @@
   "vlc\t%v0,%v1"
   [(set_attr "op_type" "VRR")])
 
-; vlpb, vlph, vlpf, vlpg
-(define_insn "abs2"
-  [(set (match_operand:VI 0 "register_operand" "=v")
-   (abs:VI (match_operand:VI 1 "register_operand"  "v")))]
+(define_expand "abs2"
+  [(set (match_operand:VIT  0 "register_operand" "=v")
+   (abs:VIT (match_operand:VIT 1 "register_operand"  "v")))]
+  "TARGET_VX"
+{
+  // Emulate via vec_sel (op1, -op1, op1 < 0)
+  if ((mode == V1TImode || mode == TImode) && !TARGET_VXE3)
+{
+  rtx zero = gen_reg_rtx (mode);
+  rtx neg_op1 = gen_reg_rtx (mode);
+  rtx lt = gen_reg_rtx (mode);
+  emit_move_insn (zero, GEN_INT (0));
+  emit_move_insn (neg_op1, gen_rtx_MINUS (mode, zero, operands[1]));
+  s390_expand_vec_compare (lt, LT, operands[1], zero);
+  emit_insn (gen_vec_sel0 (operands[0], operands[1], neg_op1, lt, 
GEN_INT (0)));
+  DONE;
+}
+})
+
+; vlpb, vlph, vlpf, vlpg, vlpq
+(define_insn "*abs2"
+  [(set (match_operand:VIT_VXE3   0 "register_operand" "=v")
+   (abs:VIT_VXE3 (match_operand:VIT_VXE3 1 "register

[gcc r15-7049] s390: arch15: Count leading/trailing zeros

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:0f0b91ef70218e2cb4ab795ef04725a68ea04b15

commit r15-7049-g0f0b91ef70218e2cb4ab795ef04725a68ea04b15
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Count leading/trailing zeros

Add vector single element 128-bit integer support utilizing new
instructions vclzq and vctzq.  Furthermore, add scalar 64-bit integer
support utilizing new instructions clzg and ctzg.  For ctzg, also define
the resulting value if the input operand equals zero.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_vec_cntlz): Add 128-bit
integer overloads.
(s390_vclzq): Add.
(s390_vec_cnttz): Add 128-bit integer overloads.
(s390_vctzq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.h (CTZ_DEFINED_VALUE_AT_ZERO): Define.
* config/s390/s390.md (*clzg): New insn.
(clztidi2): Exploit new insn for target arch15.
(ctzdi2): New insn.
* config/s390/vector.md (clz2): Extend modes including
128-bit integer.
(ctz2): Likewise.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |  1 +
 gcc/config/s390/s390-builtins.def  | 10 +++--
 gcc/config/s390/s390.h |  3 +++
 gcc/config/s390/s390.md| 40 ++
 gcc/config/s390/vector.md  | 15 -
 5 files changed, 52 insertions(+), 17 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index f05618393092..6f903deb7450 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -610,6 +610,7 @@ DEF_OV_TYPE (BT_OV_UV1TI_UV2DI, BT_UV1TI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI_UV2DI, BT_UV1TI, BT_UV2DI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI_UV2DI_UV1TI, BT_UV1TI, BT_UV2DI, BT_UV2DI, 
BT_UV1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV4SI_UV4SI, BT_UV1TI, BT_UV4SI, BT_UV4SI)
+DEF_OV_TYPE (BT_OV_UV1TI_V1TI, BT_UV1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_UV2DI_BV2DI_UV2DI, BT_UV2DI, BT_BV2DI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV2DI_LONG_ULONGLONGCONSTPTR, BT_UV2DI, BT_LONG, 
BT_ULONGLONGCONSTPTR)
 DEF_OV_TYPE (BT_OV_UV2DI_ULONGLONG, BT_UV2DI, BT_ULONGLONG)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 2cf443f6cdba..8eb07e6c79d3 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -1639,7 +1639,7 @@ B_DEF  (vec_cmpltuv2di, vec_cmpltuv2di,   
  0,
 B_DEF  (vec_cmpltv4sf,  vec_cmpltv4sf_quiet_nocc,0,
 B_INT | B_VXE,  0,  BT_FN_V4SI_V4SF_V4SF)
 B_DEF  (vec_cmpltv2df,  vec_cmpltv2df_quiet_nocc,0,
 B_INT | B_VX,   0,  BT_FN_V2DI_V2DF_V2DF)
 
-OB_DEF (s390_vec_cntlz, s390_vec_cntlz_s8,  
s390_vec_cntlz_u64, B_VX,   BT_FN_OV4SI_OV4SI)
+OB_DEF (s390_vec_cntlz, s390_vec_cntlz_s8,  
s390_vec_cntlz_u128,B_VX,   BT_FN_OV4SI_OV4SI)
 OB_DEF_VAR (s390_vec_cntlz_s8,  s390_vclzb, 0, 
 0,  BT_OV_UV16QI_V16QI)
 OB_DEF_VAR (s390_vec_cntlz_u8,  s390_vclzb, 0, 
 0,  BT_OV_UV16QI_UV16QI)
 OB_DEF_VAR (s390_vec_cntlz_s16, s390_vclzh, 0, 
 0,  BT_OV_UV8HI_V8HI)
@@ -1648,13 +1648,16 @@ OB_DEF_VAR (s390_vec_cntlz_s32, s390_vclzf, 
0,
 OB_DEF_VAR (s390_vec_cntlz_u32, s390_vclzf, 0, 
 0,  BT_OV_UV4SI_UV4SI)
 OB_DEF_VAR (s390_vec_cntlz_s64, s390_vclzg, 0, 
 0,  BT_OV_UV2DI_V2DI)
 OB_DEF_VAR (s390_vec_cntlz_u64, s390_vclzg, 0, 
 0,  BT_OV_UV2DI_UV2DI)
+OB_DEF_VAR (s390_vec_cntlz_s128,s390_vclzq, B_VXE3,
 0,  BT_OV_UV1TI_V1TI)
+OB_DEF_VAR (s390_vec_cntlz_u128,s390_vclzq, B_VXE3,
 0,  BT_OV_UV1TI_UV1TI)
 
 B_DEF  (s390_vclzb, clzv16qi2,  0, 
 B_VX,   0,  BT_FN_UV16QI_UV16QI)
 B_DEF  (s390_vclzh, clzv8hi2,   0, 
 B_VX,   0,  BT_FN_UV8HI_UV8HI)
 B_DEF  (s390_vclzf, clzv4si2,   0, 
 B_VX,   0,  BT_FN_UV4SI_UV4SI)
 B_DEF  (s390_vclzg, clzv2di2,   0, 
 B_VX,   0,  BT_FN_UV2DI_UV2DI)
+B_DEF  (s390_vclzq, clzti2, 0, 
 B_VXE3, 0,  BT_FN_UINT128_UINT128)
 
-OB_DEF (s390_vec_cnttz, s390_vec_cnttz_s8,  
s

[gcc r15-7048] s390: arch15: Vector generate element masks

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:41a69915d06a707bb6c80cc1ebf5d1c1396d

commit r15-7048-g41a69915d06a707bb6c80cc1ebf5d1c1396d
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Vector generate element masks

Add instruction vgem and vector builtins
vec_gen_element_masks_{8,16,32,64,128}.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_vec_gen_element_masks_128): 
Add.
(s390_vgemb): Add.
(s390_vgemh): Add.
(s390_vgemf): Add.
(s390_vgemg): Add.
(s390_vgemq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_VEC_VGEM): Add.
* config/s390/vecintrin.h (vec_gen_element_masks_8): Define.
(vec_gen_element_masks_16): Define.
(vec_gen_element_masks_32): Define.
(vec_gen_element_masks_64): Define.
(vec_gen_element_masks_128): Define.
* config/s390/vx-builtins.md (vgemv16qi): Add.
(vgem): Add.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |  5 +
 gcc/config/s390/s390-builtins.def  |  8 
 gcc/config/s390/s390.md|  1 +
 gcc/config/s390/vecintrin.h|  6 ++
 gcc/config/s390/vx-builtins.md | 18 ++
 5 files changed, 38 insertions(+)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 1d361c27f63d..f05618393092 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -143,20 +143,25 @@ DEF_FN_TYPE_1 (BT_FN_OV4SI_INT, BT_OV4SI, BT_INT)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_INTCONSTPTR, BT_OV4SI, BT_INTCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI)
 DEF_FN_TYPE_1 (BT_FN_UINT128_UINT128, BT_UINT128, BT_UINT128)
+DEF_FN_TYPE_1 (BT_FN_UINT128_UV16QI, BT_UINT128, BT_UV16QI)
 DEF_FN_TYPE_1 (BT_FN_UINT128_UV2DI, BT_UINT128, BT_UV2DI)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UCHAR, BT_UV16QI, BT_UCHAR)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UCHARCONSTPTR, BT_UV16QI, BT_UCHARCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_USHORT, BT_UV16QI, BT_USHORT)
 DEF_FN_TYPE_1 (BT_FN_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI)
+DEF_FN_TYPE_1 (BT_FN_UV16QI_UV8HI, BT_UV16QI, BT_UV8HI)
+DEF_FN_TYPE_1 (BT_FN_UV1TI_UV16QI, BT_UV1TI, BT_UV16QI)
 DEF_FN_TYPE_1 (BT_FN_UV2DI_ULONGLONG, BT_UV2DI, BT_ULONGLONG)
 DEF_FN_TYPE_1 (BT_FN_UV2DI_ULONGLONGCONSTPTR, BT_UV2DI, BT_ULONGLONGCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_UV2DI_USHORT, BT_UV2DI, BT_USHORT)
+DEF_FN_TYPE_1 (BT_FN_UV2DI_UV16QI, BT_UV2DI, BT_UV16QI)
 DEF_FN_TYPE_1 (BT_FN_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI)
 DEF_FN_TYPE_1 (BT_FN_UV2DI_UV4SI, BT_UV2DI, BT_UV4SI)
 DEF_FN_TYPE_1 (BT_FN_UV2DI_V2DF, BT_UV2DI, BT_V2DF)
 DEF_FN_TYPE_1 (BT_FN_UV4SI_UINT, BT_UV4SI, BT_UINT)
 DEF_FN_TYPE_1 (BT_FN_UV4SI_UINTCONSTPTR, BT_UV4SI, BT_UINTCONSTPTR)
 DEF_FN_TYPE_1 (BT_FN_UV4SI_USHORT, BT_UV4SI, BT_USHORT)
+DEF_FN_TYPE_1 (BT_FN_UV4SI_UV16QI, BT_UV4SI, BT_UV16QI)
 DEF_FN_TYPE_1 (BT_FN_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI)
 DEF_FN_TYPE_1 (BT_FN_UV4SI_UV8HI, BT_UV4SI, BT_UV8HI)
 DEF_FN_TYPE_1 (BT_FN_UV4SI_V4SF, BT_UV4SI, BT_V4SF)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 9e861b122f3d..2cf443f6cdba 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -3213,3 +3213,11 @@ OB_DEF_VAR (s390_vec_evaluate_b128, s390_veval,  
   0,
 OB_DEF_VAR (s390_vec_evaluate_u128, s390_veval, 0, 
 O4_U8,  BT_OV_UV1TI_UV1TI_UV1TI_UV1TI_INT)/* veval */
 
 B_DEF  (s390_veval, vevalv16qi, 0, 
 B_VXE3, O4_U8,  BT_FN_UV16QI_UV16QI_UV16QI_UV16QI_INT)
+
+B_DEF  (s390_vec_gen_element_masks_128,vgemti,  0, 
 B_VXE3, 0,  BT_FN_UV1TI_UV16QI)
+
+B_DEF  (s390_vgemb, vgemv16qi,  0, 
 B_VXE3, 0,  BT_FN_UV16QI_UV8HI)
+B_DEF  (s390_vgemh, vgemv8hi,   0, 
 B_VXE3, 0,  BT_FN_UV8HI_UV16QI)
+B_DEF  (s390_vgemf, vgemv4si,   0, 
 B_VXE3, 0,  BT_FN_UV4SI_UV16QI)
+B_DEF  (s390_vgemg, vgemv2di,   0, 
 B_VXE3, 0,  BT_FN_UV2DI_UV16QI)
+B_DEF  (s390_vgemq, vgemti, 0, 
 B_VXE3, 0,  BT_FN_UINT128_UV16QI)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 53c4170ee46e..7b5b9709f56e 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -246,6 +246,7 @@
 
UNSPEC_VEC_VBLEND
UNSPEC_VEC_VEVAL
+   UNSPEC_VEC_VGEM
 
UNSPEC_TF_TO_FPRX2
 
diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h
in

[gcc r15-7039] s390: Sort definitions in vecintrin.h

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:2638aea49a927ed7419f334f3e3d44c49cf44a3e

commit r15-7039-g2638aea49a927ed7419f334f3e3d44c49cf44a3e
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:08 2025 +0100

s390: Sort definitions in vecintrin.h

gcc/ChangeLog:

* config/s390/vecintrin.h: Sort definitions.

Diff:
---
 gcc/config/s390/vecintrin.h | 229 ++--
 1 file changed, 115 insertions(+), 114 deletions(-)

diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h
index a30fa70bb7fc..ce422c7539d8 100644
--- a/gcc/config/s390/vecintrin.h
+++ b/gcc/config/s390/vecintrin.h
@@ -165,165 +165,166 @@ __lcbb(const void *ptr, int bndry)
 #define vec_round_from_fp32 __builtin_s390_vcrnfs
 #define vec_convert_to_fp16 __builtin_s390_vcfn
 #define vec_convert_from_fp16 __builtin_s390_vcnf
-#define vec_gather_element __builtin_s390_vec_gather_element
-#define vec_xl __builtin_s390_vec_xl
-#define vec_xld2 __builtin_s390_vec_xld2
-#define vec_xlw4 __builtin_s390_vec_xlw4
-#define vec_splats __builtin_s390_vec_splats
-#define vec_insert __builtin_s390_vec_insert
-#define vec_promote __builtin_s390_vec_promote
-#define vec_extract __builtin_s390_vec_extract
-#define vec_insert_and_zero __builtin_s390_vec_insert_and_zero
-#define vec_load_bndry __builtin_s390_vec_load_bndry
-#define vec_load_pair __builtin_s390_vec_load_pair
-#define vec_load_len __builtin_s390_vec_load_len
-#define vec_mergeh __builtin_s390_vec_mergeh
-#define vec_mergel __builtin_s390_vec_mergel
-#define vec_pack __builtin_s390_vec_pack
-#define vec_packs __builtin_s390_vec_packs
-#define vec_packs_cc __builtin_s390_vec_packs_cc
-#define vec_packsu __builtin_s390_vec_packsu
-#define vec_packsu_cc __builtin_s390_vec_packsu_cc
-#define vec_perm __builtin_s390_vec_perm
-#define vec_permi __builtin_s390_vec_permi
-#define vec_splat __builtin_s390_vec_splat
-#define vec_scatter_element __builtin_s390_vec_scatter_element
-#define vec_sel __builtin_s390_vec_sel
-#define vec_extend_s64 __builtin_s390_vec_extend_s64
-#define vec_xst __builtin_s390_vec_xst
-#define vec_xstd2 __builtin_s390_vec_xstd2
-#define vec_xstw4 __builtin_s390_vec_xstw4
-#define vec_store_len __builtin_s390_vec_store_len
-#define vec_bperm_u128 __builtin_s390_vec_bperm_u128
-#define vec_unpackh __builtin_s390_vec_unpackh
-#define vec_unpackl __builtin_s390_vec_unpackl
-#define vec_addc __builtin_s390_vec_addc
+
+#define vec_abs __builtin_s390_vec_abs
 #define vec_add_u128 __builtin_s390_vec_add_u128
+#define vec_addc __builtin_s390_vec_addc
 #define vec_addc_u128 __builtin_s390_vec_addc_u128
 #define vec_adde_u128 __builtin_s390_vec_adde_u128
 #define vec_addec_u128 __builtin_s390_vec_addec_u128
-#define vec_and __builtin_s390_vec_and
-#define vec_andc __builtin_s390_vec_andc
-#define vec_avg __builtin_s390_vec_avg
 #define vec_all_eq __builtin_s390_vec_all_eq
-#define vec_all_ne __builtin_s390_vec_all_ne
 #define vec_all_ge __builtin_s390_vec_all_ge
 #define vec_all_gt __builtin_s390_vec_all_gt
 #define vec_all_le __builtin_s390_vec_all_le
 #define vec_all_lt __builtin_s390_vec_all_lt
+#define vec_all_ne __builtin_s390_vec_all_ne
+#define vec_all_nge __builtin_s390_vec_all_nge
+#define vec_all_ngt __builtin_s390_vec_all_ngt
+#define vec_and __builtin_s390_vec_and
+#define vec_andc __builtin_s390_vec_andc
 #define vec_any_eq __builtin_s390_vec_any_eq
-#define vec_any_ne __builtin_s390_vec_any_ne
 #define vec_any_ge __builtin_s390_vec_any_ge
 #define vec_any_gt __builtin_s390_vec_any_gt
 #define vec_any_le __builtin_s390_vec_any_le
 #define vec_any_lt __builtin_s390_vec_any_lt
+#define vec_any_ne __builtin_s390_vec_any_ne
+#define vec_any_nge __builtin_s390_vec_any_nge
+#define vec_any_ngt __builtin_s390_vec_any_ngt
+#define vec_avg __builtin_s390_vec_avg
+#define vec_bperm_u128 __builtin_s390_vec_bperm_u128
 #define vec_cmpeq __builtin_s390_vec_cmpeq
+#define vec_cmpeq_idx __builtin_s390_vec_cmpeq_idx
+#define vec_cmpeq_idx_cc __builtin_s390_vec_cmpeq_idx_cc
+#define vec_cmpeq_or_0_idx __builtin_s390_vec_cmpeq_or_0_idx
+#define vec_cmpeq_or_0_idx_cc __builtin_s390_vec_cmpeq_or_0_idx_cc
 #define vec_cmpge __builtin_s390_vec_cmpge
 #define vec_cmpgt __builtin_s390_vec_cmpgt
 #define vec_cmple __builtin_s390_vec_cmple
 #define vec_cmplt __builtin_s390_vec_cmplt
+#define vec_cmpne_idx __builtin_s390_vec_cmpne_idx
+#define vec_cmpne_idx_cc __builtin_s390_vec_cmpne_idx_cc
+#define vec_cmpne_or_0_idx __builtin_s390_vec_cmpne_or_0_idx
+#define vec_cmpne_or_0_idx_cc __builtin_s390_vec_cmpne_or_0_idx_cc
+#define vec_cmpnrg __builtin_s390_vec_cmpnrg
+#define vec_cmpnrg_cc __builtin_s390_vec_cmpnrg_cc
+#define vec_cmpnrg_idx __builtin_s390_vec_cmpnrg_idx
+#define vec_cmpnrg_idx_cc __builtin_s390_vec_cmpnrg_idx_cc
+#define vec_cmpnrg_or_0_idx __builtin_s390_vec_cmpnrg_or_0_idx
+#define vec_cmpnrg_or_0_idx_cc __builtin_s390_vec_cmpnrg_or_0_idx_cc
+#define vec_cmprg __builtin_s390_vec_cmprg
+#define vec_cmprg_cc __builtin_s390_vec_cmp

[gcc r15-7046] s390: arch15: Vector blend

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:adeb6ecc5d906ce2389400085f3262b4a248c71c

commit r15-7046-gadeb6ecc5d906ce2389400085f3262b4a248c71c
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Vector blend

Add instruction vblend and builtin vec_blend.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_vec_blend): Add.
(s390_vblendb): Add.
(s390_vblendh): Add.
(s390_vblendf): Add.
(s390_vblendg): Add.
(s390_vblendq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_VEC_VBLEND): Add.
* config/s390/vecintrin.h (vec_blend): Define.
* config/s390/vx-builtins.md (vblend): Add.

Diff:
---
 gcc/config/s390/s390-builtin-types.def | 17 +
 gcc/config/s390/s390-builtins.def  | 25 +
 gcc/config/s390/s390.md|  2 ++
 gcc/config/s390/vecintrin.h|  1 +
 gcc/config/s390/vx-builtins.md | 11 +++
 5 files changed, 56 insertions(+)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 913bd0324cc0..14f4e92a858b 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -309,24 +309,28 @@ DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI, BT_OV4SI, 
BT_OV4SI, BT_OV4SI, BT_O
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_OV4SI, 
BT_UCHAR)
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UINT, BT_OV4SI, BT_OV4SI, BT_OV4SI, 
BT_UINT)
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG, BT_OV4SI, BT_OV4SI, 
BT_OV4SI, BT_ULONGLONG)
+DEF_FN_TYPE_3 (BT_FN_UINT128_UINT128_UINT128_INT128, BT_UINT128, BT_UINT128, 
BT_UINT128, BT_INT128)
 DEF_FN_TYPE_3 (BT_FN_UINT128_UINT128_UINT128_UINT128, BT_UINT128, BT_UINT128, 
BT_UINT128, BT_UINT128)
 DEF_FN_TYPE_3 (BT_FN_UINT128_UV2DI_UV2DI_UINT128, BT_UINT128, BT_UV2DI, 
BT_UV2DI, BT_UINT128)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, BT_UV16QI, BT_UCHAR, 
BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_UV16QI)
+DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_V16QI, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_V16QI)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV2DI_UV2DI_UV16QI, BT_UV16QI, BT_UV2DI, BT_UV2DI, 
BT_UV16QI)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV8HI_UV8HI_INTPTR, BT_UV16QI, BT_UV8HI, BT_UV8HI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV1TI_UV1TI_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_UV1TI)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_ULONGLONG_INT, BT_UV2DI, BT_UV2DI, 
BT_ULONGLONG, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, 
BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, 
BT_UV2DI)
+DEF_FN_TYPE_3 (BT_FN_UV2DI_UV2DI_UV2DI_V2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, 
BT_V2DI)
 DEF_FN_TYPE_3 (BT_FN_UV2DI_UV4SI_UV4SI_UV2DI, BT_UV2DI, BT_UV4SI, BT_UV4SI, 
BT_UV2DI)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV2DI_UV2DI_INTPTR, BT_UV4SI, BT_UV2DI, BT_UV2DI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UINT_INT, BT_UV4SI, BT_UV4SI, BT_UINT, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, 
BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UV4SI_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, 
BT_UV4SI)
+DEF_FN_TYPE_3 (BT_FN_UV4SI_UV4SI_UV4SI_V4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, 
BT_V4SI)
 DEF_FN_TYPE_3 (BT_FN_UV4SI_UV8HI_UV8HI_UV4SI, BT_UV4SI, BT_UV8HI, BT_UV8HI, 
BT_UV4SI)
 DEF_FN_TYPE_3 (BT_FN_UV8HI_UV16QI_UV16QI_UV8HI, BT_UV8HI, BT_UV16QI, 
BT_UV16QI, BT_UV8HI)
 DEF_FN_TYPE_3 (BT_FN_UV8HI_UV4SI_UV4SI_INTPTR, BT_UV8HI, BT_UV4SI, BT_UV4SI, 
BT_INTPTR)
@@ -334,6 +338,7 @@ DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_USHORT_INT, BT_UV8HI, 
BT_UV8HI, BT_USHORT, BT_I
 DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, 
BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, 
BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, 
BT_UV8HI)
+DEF_FN_TYPE_3 (BT_FN_UV8HI_UV8HI_UV8HI_V8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, 
BT_V8HI)
 DEF_FN_TYPE_3 (BT_FN_UV8HI_V4SF_V4SF_UINT, BT_UV8HI, BT_V4SF, BT_V4SF, BT_UINT)
 DEF_FN_TYPE_3 (BT_FN_V16QI_UV16QI_UV16QI_INTPTR, BT_V16QI, BT_UV16QI, 
BT_UV16QI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, 
BT_INTPTR)
@@ -401,6 +406,7 @@ DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_BV16QI,
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_INTPTR, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_INTPTR)
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_ULONGLONG, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_ULONGLONG)
 

[gcc r15-7047] s390: arch15: Vector eval

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:7fb7b36293519ed68481ca8477244b5a4f142d4a

commit r15-7047-g7fb7b36293519ed68481ca8477244b5a4f142d4a
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Vector eval

Add instruction veval and builtin vec_evaluate.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_vec_evaluate): Add.
(s390_veval): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_VEC_VEVAL): Add.
* config/s390/vecintrin.h (vec_evaluate): Define.
* config/s390/vector.md

(*veval_):
Add.
(veval): Add.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vxe3/veval-1.c: New test.
* gcc.target/s390/vxe3/veval-2.c: New test.
* gcc.target/s390/vxe3/veval-3.c: New test.
* gcc.target/s390/vxe3/veval-4.c: New test.
* gcc.target/s390/vxe3/veval-5.c: New test.
* gcc.target/s390/vxe3/veval-6.c: New test.
* gcc.target/s390/vxe3/veval-7.c: New test.
* gcc.target/s390/vxe3/veval-8.c: New test.
* gcc.target/s390/vxe3/veval-9.c: New test.

Diff:
---
 gcc/config/s390/s390-builtin-types.def   | 16 +
 gcc/config/s390/s390-builtins.def| 19 +++
 gcc/config/s390/s390.md  |  1 +
 gcc/config/s390/vecintrin.h  |  1 +
 gcc/config/s390/vector.md| 36 
 gcc/testsuite/gcc.target/s390/vxe3/veval-1.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-2.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-3.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-4.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-5.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-6.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-7.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-8.c |  9 +++
 gcc/testsuite/gcc.target/s390/vxe3/veval-9.c |  9 +++
 14 files changed, 154 insertions(+)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index 14f4e92a858b..1d361c27f63d 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -378,6 +378,7 @@ DEF_FN_TYPE_3 (BT_FN_VOID_OV4SI_INT_VOIDPTR, BT_VOID, 
BT_OV4SI, BT_INT, BT_VOIDP
 DEF_FN_TYPE_3 (BT_FN_VOID_OV4SI_VOIDPTR_UINT, BT_VOID, BT_OV4SI, BT_VOIDPTR, 
BT_UINT)
 DEF_FN_TYPE_3 (BT_FN_VOID_V16QI_UINT_VOIDPTR, BT_VOID, BT_V16QI, BT_UINT, 
BT_VOIDPTR)
 DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OUV4SI_INTCONSTPTR_UCHAR, BT_OV4SI, BT_OV4SI, 
BT_OUV4SI, BT_INTCONSTPTR, BT_UCHAR)
+DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INT, BT_OV4SI, BT_OV4SI, 
BT_OV4SI, BT_OV4SI, BT_INT)
 DEF_FN_TYPE_4 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, 
BT_OV4SI, BT_OV4SI, BT_INTPTR)
 DEF_FN_TYPE_4 (BT_FN_UINT128_UV2DI_UV2DI_UINT128_INT, BT_UINT128, BT_UV2DI, 
BT_UV2DI, BT_UINT128, BT_INT)
 DEF_FN_TYPE_4 (BT_FN_UV16QI_UV16QI_UV16QI_INT_INTPTR, BT_UV16QI, BT_UV16QI, 
BT_UV16QI, BT_INT, BT_INTPTR)
@@ -403,6 +404,7 @@ DEF_FN_TYPE_5 (BT_FN_UV8HI_UV8HI_UV8HI_UV8HI_INT_INTPTR, 
BT_UV8HI, BT_UV8HI, BT_
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI)
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI, BT_BV16QI)
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_BV16QI, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_BV16QI)
+DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_BV16QI_INT, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_BV16QI, BT_INT)
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_INTPTR, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_INTPTR)
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_ULONGLONG, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_BV16QI_BV16QI_BV16QI_UV16QI, BT_BV16QI, BT_BV16QI, 
BT_BV16QI, BT_UV16QI)
@@ -421,6 +423,7 @@ DEF_OV_TYPE (BT_OV_BV16QI_V16QI_V16QI, BT_BV16QI, BT_V16QI, 
BT_V16QI)
 DEF_OV_TYPE (BT_OV_BV16QI_V16QI_V16QI_INTPTR, BT_BV16QI, BT_V16QI, BT_V16QI, 
BT_INTPTR)
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI)
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_BV1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_BV1TI)
+DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_BV1TI_INT, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_BV1TI, BT_INT)
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_UV16QI, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_UV16QI)
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_UV1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_UV1TI)
 DEF_OV_TYPE (BT_OV_BV1TI_BV1TI_BV1TI_V1TI, BT_BV1TI, BT_BV1TI, BT_BV1TI, 
BT_V1TI)
@@ -429,6 +432,7 @@ DEF_OV_TYPE (BT_OV_BV2DI_BV1TI_BV1TI, BT_BV2DI, BT_BV1TI, 
BT_BV1TI)
 DEF_OV_TYPE (BT_OV_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_BV2DI, BT_BV2DI, BT_BV2DI, BT_BV2DI, 
BT_BV2DI)
+DEF_OV_TYPE (BT_OV_BV2DI_BV2DI_BV2DI_BV2DI_INT, BT_BV2DI, BT_BV2DI, BT_BV2DI, 
BT_BV2DI, BT_IN

[gcc r15-7045] s390: arch15: Bit deposit and extract

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:d71e20b889ac82c3ca14a1c5c420765a11b06df9

commit r15-7045-gd71e20b889ac82c3ca14a1c5c420765a11b06df9
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:09 2025 +0100

s390: arch15: Bit deposit and extract

Add instructions bdepg and bextg and corresponding builtins.

gcc/ChangeLog:

* config/s390/s390-builtins.def (s390_bdepg): Add.
(s390_bextg): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_BDEPG): Add.
(UNSPEC_BEXTG): Add.
(bdepg): Add.
(bextg): Add.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |  1 +
 gcc/config/s390/s390-builtins.def  |  5 +
 gcc/config/s390/s390.md| 30 ++
 3 files changed, 36 insertions(+)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index f995fe47f1da..913bd0324cc0 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -226,6 +226,7 @@ DEF_FN_TYPE_2 (BT_FN_UINT128_UV4SI_UV4SI, BT_UINT128, 
BT_UV4SI, BT_UV4SI)
 DEF_FN_TYPE_2 (BT_FN_UINT_UV4SI_INT, BT_UINT, BT_UV4SI, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_UINT_VOIDCONSTPTR_INT, BT_UINT, BT_VOIDCONSTPTR, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_ULONGLONG_UV2DI_INT, BT_ULONGLONG, BT_UV2DI, BT_INT)
+DEF_FN_TYPE_2 (BT_FN_ULONG_ULONG_ULONG, BT_ULONG, BT_ULONG, BT_ULONG)
 DEF_FN_TYPE_2 (BT_FN_USHORT_UV8HI_INT, BT_USHORT, BT_UV8HI, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR_INT, BT_UV16QI, BT_UCHAR, BT_INT)
 DEF_FN_TYPE_2 (BT_FN_UV16QI_UCHAR_UCHAR, BT_UV16QI, BT_UCHAR, BT_UCHAR)
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index b8e8b64587f2..a3515dcbff14 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -3164,3 +3164,8 @@ B_DEF  (s390_vcrnfs, vcrnfs_v8hi, 
  0,
 
 B_DEF  (s390_vcfn,   vcfn_v8hi, 0, 
 B_NNPA, O2_U4,  BT_FN_UV8HI_UV8HI_UINT)
 B_DEF  (s390_vcnf,   vcnf_v8hi, 0, 
 B_NNPA, O2_U4,  BT_FN_UV8HI_UV8HI_UINT)
+
+/* arch 15 builtins */
+
+B_DEF  (s390_bdepg, bdepg,  0, 
 B_ARCH15,   0,  BT_FN_ULONG_ULONG_ULONG)
+B_DEF  (s390_bextg, bextg,  0, 
 B_ARCH15,   0,  BT_FN_ULONG_ULONG_ULONG)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 6fed6bf42543..1230de0486f4 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -125,6 +125,9 @@
; Byte-wise Population Count
UNSPEC_POPCNT
 
+   UNSPEC_BDEPG
+   UNSPEC_BEXTG
+
; Load FP Integer
UNSPEC_FPINT_FLOOR
UNSPEC_FPINT_BTRUNC
@@ -4846,6 +4849,33 @@
   [(set_attr "op_type" "RIL")
(set_attr "z10prop" "z10_fwd_A1")])
 
+;
+; BIT DEPOSIT
+;
+
+(define_insn "bdepg"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (unspec:DI [(match_operand:DI 1 "register_operand" "d")
+   (match_operand:DI 2 "register_operand" "d")]
+  UNSPEC_BDEPG))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "bdepg\t%0,%1,%2"
+  [(set_attr "op_type" "RRF")])
+
+;
+; BIT EXTRACT
+;
+
+(define_insn "bextg"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+   (unspec:DI [(match_operand:DI 1 "register_operand" "d")
+   (match_operand:DI 2 "register_operand" "d")]
+  UNSPEC_BEXTG))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "bextg\t%0,%1,%2"
+  [(set_attr "op_type" "RRF")])
+
+
 ;
 ; extendsidi2 instruction pattern(s).
 ;

[gcc r15-7040] s390: arch15: Prepare for a future architecture

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:a8192b59175e2cfcf665573d8168a8be09bdfa51

commit r15-7040-ga8192b59175e2cfcf665573d8168a8be09bdfa51
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:08 2025 +0100

s390: arch15: Prepare for a future architecture

gcc/ChangeLog:

* common/config/s390/s390-common.cc: Add arch15 processor flags.
* config.gcc: Add arch15 for options --with-{arch,mtune}.
* config/s390/driver-native.cc (s390_host_detect_local_cpu):
Default to arch15.
* config/s390/s390-opts.h (enum processor_type): Add
PROCESSOR_ARCH15.
* config/s390/s390.cc (processor_table,s390_issue_rate,
s390_get_sched_attrmask,s390_get_unit_mask): Add arch15.
* config/s390/s390.h (enum processor_flags): Add processor flags
for VXE3 and ARCH15.
(TARGET_CPU_VXE3): Define.
(TARGET_CPU_VXE3_P): Define.
(TARGET_CPU_ARCH15): Define.
(TARGET_CPU_ARCH15_P): Define.
(TARGET_VXE3): Define.
(TARGET_VXE3_P): Define.
(TARGET_ARCH15): Define.
(TARGET_ARCH15_P): Define.
* config/s390/s390.md: Add VXE3 and ARCH15 to cpu_facility, and
let attribute "enabled" deal with them.
* config/s390/s390.opt: Add arch15.

gcc/testsuite/ChangeLog:

* gcc.target/s390/s390.exp: Set compiler flags for the vxe3
subdirectory of the testsuite as done e.g. for vxe2.

Diff:
---
 gcc/common/config/s390/s390-common.cc  |  6 +-
 gcc/config.gcc |  2 +-
 gcc/config/s390/driver-native.cc   |  2 +-
 gcc/config/s390/s390-opts.h|  1 +
 gcc/config/s390/s390.cc|  4 
 gcc/config/s390/s390.h | 19 ++-
 gcc/config/s390/s390.md| 10 +-
 gcc/config/s390/s390.opt   |  3 +++
 gcc/testsuite/gcc.target/s390/s390.exp |  3 +++
 9 files changed, 45 insertions(+), 5 deletions(-)

diff --git a/gcc/common/config/s390/s390-common.cc 
b/gcc/common/config/s390/s390-common.cc
index b723871e68b9..4b0691d5a16f 100644
--- a/gcc/common/config/s390/s390-common.cc
+++ b/gcc/common/config/s390/s390-common.cc
@@ -53,7 +53,11 @@ EXPORTED_CONST int processor_flags_table[] =
 /* z16 */PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
 | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
 | PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15
-| PF_NNPA | PF_Z16
+| PF_NNPA | PF_Z16,
+/* arch15 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
+| PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
+| PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15
+| PF_NNPA | PF_Z16 | PF_VXE3 | PF_ARCH15
   };
 
 /* Change optimizations to be performed, depending on the
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 371143e4f8d4..82227e86521c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5757,7 +5757,7 @@ case "${target}" in
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
-   "" | native | z900 | z990 | z9-109 | z9-ec | z10 | z196 
| zEC12 | z13 | z14 | z15 | z16 | arch5 | arch6 | arch7 | arch8 | arch9 | 
arch10 | arch11 | arch12 | arch13 | arch14 )
+   "" | native | z900 | z990 | z9-109 | z9-ec | z10 | z196 
| zEC12 | z13 | z14 | z15 | z16 | arch5 | arch6 | arch7 | arch8 | arch9 | 
arch10 | arch11 | arch12 | arch13 | arch14 | arch15 )
# OK
;;
*)
diff --git a/gcc/config/s390/driver-native.cc b/gcc/config/s390/driver-native.cc
index c6b56933654a..49e8fa01a19b 100644
--- a/gcc/config/s390/driver-native.cc
+++ b/gcc/config/s390/driver-native.cc
@@ -128,7 +128,7 @@ s390_host_detect_local_cpu (int argc, const char **argv)
  cpu = "arch14";
  break;
default:
- cpu = "arch14";
+ cpu = "arch15";
  break;
}
}
diff --git a/gcc/config/s390/s390-opts.h b/gcc/config/s390/s390-opts.h
index c100725de32a..437d3b9e4c79 100644
--- a/gcc/config/s390/s390-opts.h
+++ b/gcc/config/s390/s390-opts.h
@@ -39,6 +39,7 @@ enum processor_type
   PROCESSOR_3906_Z14,
   PROCESSOR_8561_Z15,
   PROCESSOR_3931_Z16,
+  PROCESSOR_ARCH15,
   PROCESSOR_NATIVE,
   PROCESSOR_max
 };
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index f166a8a07dd9..327e44c80784 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -342,6 +342,7 @@ const struct s390_processor processor_table[] =
   { "z14","arch12", PROCESSOR_3906_Z14,&zEC12_cost,  12 },
   { "z15","arch13", PROCESSOR_8561_Z15,&zEC12_cost,  13 },
   { "z16","arch14", PROCESSOR_3931_Z16,

[gcc r15-7041] s390: Bump __VEC__ and add 128-bit integer zvector types

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:13efa59ce66516937fd5e0608d2aa3aab46c5d76

commit r15-7041-g13efa59ce66516937fd5e0608d2aa3aab46c5d76
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:08 2025 +0100

s390: Bump __VEC__ and add 128-bit integer zvector types

Bump __VEC__ version to 10305 and add 128-bit integer vector types like
`vector __int128` et al. to the zvector extension.

gcc/ChangeLog:

* config/s390/s390-c.cc (rid_int128): New helper function.
(s390_macro_to_expand): Deal with `vector __int128`.
(s390_cpu_cpp_builtins_internal): Bump __VEC__.
* config/s390/s390.cc (s390_handle_vectorbool_attribute): Add
128-bit bool zvector.

Diff:
---
 gcc/config/s390/s390-c.cc | 21 +++--
 gcc/config/s390/s390.cc   |  3 +++
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390-c.cc b/gcc/config/s390/s390-c.cc
index bcb55d43861d..27e18f0b4754 100644
--- a/gcc/config/s390/s390-c.cc
+++ b/gcc/config/s390/s390-c.cc
@@ -174,6 +174,22 @@ s390_categorize_keyword (const cpp_token *tok)
 }
 
 
+/* Helper function to find out which RID_INT_N_* code is the one for
+   __int128, if any.  Returns RID_MAX+1 if none apply, which is safe
+   (for our purposes, since we always expect to have __int128) to
+   compare against.  */
+static inline int
+rid_int128 (void)
+{
+  for (int i = 0; i < NUM_INT_N_ENTS; ++i)
+if (int_n_enabled_p[i]
+   && int_n_data[i].bitsize == 128)
+  return RID_INT_N_0 + i;
+
+  return RID_MAX + 1;
+}
+
+
 /* Called to decide whether a conditional macro should be expanded.
Since we have exactly one such macro (i.e, 'vector'), we do not
need to examine the 'tok' parameter.  */
@@ -262,7 +278,8 @@ s390_macro_to_expand (cpp_reader *pfile, const cpp_token 
*tok)
   || rid_code == RID_SHORT || rid_code == RID_SIGNED
   || rid_code == RID_INT || rid_code == RID_CHAR
   || (rid_code == RID_FLOAT && TARGET_VXE)
-  || rid_code == RID_DOUBLE)
+  || rid_code == RID_DOUBLE
+  || rid_code == rid_int128 ())
 {
   expand_this = C_CPP_HASHNODE (__vector_keyword);
   /* If the next keyword is bool, it will need to be expanded as
@@ -341,7 +358,7 @@ s390_cpu_cpp_builtins_internal (cpp_reader *pfile,
   s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_OPT_VX), old_opts,
   opts, "__VX__", "__VX__");
   s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), old_opts,
-  opts, "__VEC__=10304", "__VEC__");
+  opts, "__VEC__=10305", "__VEC__");
   s390_def_or_undef_macro (pfile, target_flag_set_p (MASK_ZVECTOR), old_opts,
   opts, "__vector=__attribute__((vector_size(16)))",
   "__vector__");
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 327e44c80784..f5053781ffde 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -1199,6 +1199,9 @@ s390_handle_vectorbool_attribute (tree *node, tree name 
ATTRIBUTE_UNUSED,
   mode = TYPE_MODE (type);
   switch (mode)
 {
+case E_TImode: case E_V1TImode:
+  result = s390_builtin_types[BT_BV1TI];
+  break;
 case E_DImode: case E_V2DImode:
   result = s390_builtin_types[BT_BV2DI];
   break;

[gcc r15-7042] s390: arch15: Prepare for future builtins

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:b963174abfb601bc39504d09ac6b86c53660e170

commit r15-7042-gb963174abfb601bc39504d09ac6b86c53660e170
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:08 2025 +0100

s390: arch15: Prepare for future builtins

gcc/ChangeLog:

* config/s390/s390-builtins.def (B_VXE3): Define.
(B_ARCH15): Define.
* config/s390/s390-c.cc (s390_resolve_overloaded_builtin):
Consistency checks for VXE3.
* config/s390/s390.cc (s390_expand_builtin): Consistency checks
for VXE3.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: VXE3 effective target check.

Diff:
---
 gcc/config/s390/s390-builtins.def |  2 ++
 gcc/config/s390/s390-c.cc | 14 ++
 gcc/config/s390/s390.cc   |  6 ++
 gcc/testsuite/lib/target-supports.exp | 16 
 4 files changed, 38 insertions(+)

diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index 8186fad19f78..1700016fe4ce 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -300,6 +300,8 @@
 #define B_VXE2  (1 << 4)  /* Builtins requiring the z15 vector extensions.  */
 #define B_DEP   (1 << 5)  /* Builtin has been deprecated and a warning should 
be issued.  */
 #define B_NNPA  (1 << 6)  /* Builtins requiring the NNPA Facility.  */
+#define B_VXE3  (1 << 7)  /* Builtins requiring the arch15 vector extensions.  
*/
+#define B_ARCH15 (1 << 8) /* Builtins requiring arch15.  */
 
 /* B_DEF defines a standard (not overloaded) builtin
B_DEF (, , , , , )
diff --git a/gcc/config/s390/s390-c.cc b/gcc/config/s390/s390-c.cc
index 27e18f0b4754..bda60ef8670e 100644
--- a/gcc/config/s390/s390-c.cc
+++ b/gcc/config/s390/s390-c.cc
@@ -958,6 +958,12 @@ s390_resolve_overloaded_builtin (location_t loc, tree 
ob_fndecl,
   return error_mark_node;
 }
 
+  if (!TARGET_VXE3 && (ob_flags & B_VXE3))
+{
+  error_at (loc, "%qF requires arch15 or higher", ob_fndecl);
+  return error_mark_node;
+}
+
   ob_fcode -= S390_BUILTIN_MAX;
 
   for (b_arg_chain = TYPE_ARG_TYPES (TREE_TYPE (ob_fndecl));
@@ -1045,6 +1051,14 @@ s390_resolve_overloaded_builtin (location_t loc, tree 
ob_fndecl,
   return error_mark_node;
 }
 
+  if (!TARGET_VXE3
+  && bflags_overloaded_builtin_var[last_match_index] & B_VXE3)
+{
+  error_at (loc, "%qs matching variant requires arch15 or higher",
+   IDENTIFIER_POINTER (DECL_NAME (ob_fndecl)));
+  return error_mark_node;
+}
+
   if (bflags_overloaded_builtin_var[last_match_index] & B_DEP)
 warning_at (loc, 0, "%qs matching variant is deprecated",
IDENTIFIER_POINTER (DECL_NAME (ob_fndecl)));
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index f5053781ffde..f3b0061ac38d 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -913,6 +913,12 @@ s390_expand_builtin (tree exp, rtx target, rtx subtarget 
ATTRIBUTE_UNUSED,
  error ("Builtin %qF requires z15 or higher", fndecl);
  return const0_rtx;
}
+
+  if ((bflags & B_VXE3) && !TARGET_VXE3)
+   {
+ error ("Builtin %qF requires arch15 or higher", fndecl);
+ return const0_rtx;
+   }
 }
   if (fcode >= S390_OVERLOADED_BUILTIN_VAR_OFFSET
   && fcode < S390_ALL_BUILTIN_MAX)
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 939ef3a41196..ca85a47c9ed6 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12959,6 +12959,22 @@ proc check_effective_target_s390_vxe2 { } {
 } "-march=arch13 -mzarch" ]
 }
 
+# Same as above but for the arch15 vector enhancement facility. Test
+# is performed with the vector divide instruction.
+proc check_effective_target_s390_vxe3 { } {
+if ![istarget s390*-*-*] then {
+   return 0;
+}
+
+return [check_runtime s390_check_vxe3 {
+   int main (void)
+   {
+   asm ("vd %%v24, %%v26, %%v28, 2, 0" : : : "v24", "v26", "v28");
+   return 0;
+   }
+} "-march=arch15 -mzarch" ]
+}
+
 # Same as above but for the arch14 NNPA facility.
 proc check_effective_target_s390_nnpa { } {
 if ![istarget s390*-*-*] then {

[gcc r15-7038] s390: Stay scalar for TOINTVEC/tointvec

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:0c6fdb9befa611135f6f94f15d97664e8f02e41f

commit r15-7038-g0c6fdb9befa611135f6f94f15d97664e8f02e41f
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:08 2025 +0100

s390: Stay scalar for TOINTVEC/tointvec

Currently TOINTVEC maps scalar mode TI/TF to vector mode V1TI/V1TF,
respectively.  As a consequence we may end up with patterns with a
mixture of scalar and vector modes as e.g. for

(define_insn "vec_sel0"
  [(set (match_operand:VT 0 "register_operand" "=v")
(if_then_else:VT
 (eq (match_operand: 3 "register_operand" "v")
 (match_operand: 4 "const0_operand" ""))
 (match_operand:VT 1 "register_operand" "v")
 (match_operand:VT 2 "register_operand" "v")))]

This is cumbersome since gen_vec_sel0ti() and gen_vec_sel0tf() require
that operands 3 and 4 are of vector mode whereas the remainder of
operands must be of scalar mode.  Likewise for tointvec.

Fixed by staying scalar.

gcc/ChangeLog:

* config/s390/vector.md: Stay scalar for TOINTVEC/tointvec.

Diff:
---
 gcc/config/s390/vector.md | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 0616275a4c5b..66ce1599fa7d 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -147,19 +147,19 @@
(V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI 
"V8HI")
(V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI")
(V1DI "V1DI") (V2DI "V2DI")
-   (V1TI "V1TI") (TI "V1TI")
+   (V1TI "V1TI") (TI "TI")
(V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI")
(V1DF "V1DI") (V2DF "V2DI")
-   (V1TF "V1TI") (TF "V1TI")])
+   (V1TF "V1TI") (TF "TI")])
 
 (define_mode_attr tointvec [(V1QI "v1qi") (V2QI "v2qi") (V4QI "v4qi") (V8QI 
"v8qi") (V16QI "v16qi")
(V1HI "v1hi") (V2HI "v2hi") (V4HI "v4hi") (V8HI 
"v8hi")
(V1SI "v1si") (V2SI "v2si") (V4SI "v4si")
(V1DI "v1di") (V2DI "v2di")
-   (V1TI "v1ti") (TI "v1ti")
+   (V1TI "v1ti") (TI "ti")
(V1SF "v1si") (V2SF "v2si") (V4SF "v4si")
(V1DF "v1di") (V2DF "v2di")
-   (V1TF "v1ti") (TF   "v1ti")])
+   (V1TF "v1ti") (TF   "ti")])
 
 (define_mode_attr vw [(SF "w") (V1SF "w") (V2SF "v") (V4SF "v")
  (DF "w") (V1DF "w") (V2DF "v")
@@ -3077,7 +3077,7 @@
  (unspec:CCRAW [(match_operand:TF 1 "register_operand" "")
 (match_dup2)]
UNSPEC_VEC_VFTCICC))
- (clobber (scratch:V1TI))])
+ (clobber (scratch:TI))])
(set (match_operand:SI  0 "register_operand" "")
(const_int 0))
(set (match_dup 0)
@@ -3101,7 +3101,7 @@
  (unspec:CCRAW [(match_operand:TF 1 "register_operand" "")
 (match_dup2)]
UNSPEC_VEC_VFTCICC))
- (clobber (scratch:V1TI))])
+ (clobber (scratch:TI))])
(set (match_operand:SI  0 "register_operand" "")
(const_int 0))
(set (match_dup 0)

[gcc r15-7054] s390: Vector shift: Add 128-bit integer support

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:10c52b3866572df9f84e41d8045cbf8c6ce6ab04

commit r15-7054-g10c52b3866572df9f84e41d8045cbf8c6ce6ab04
Author: Stefan Schulze Frielinghaus 
Date:   Mon Jan 20 10:01:10 2025 +0100

s390: Vector shift: Add 128-bit integer support

Add 128-bit vector shift support.  Deprecate vector shift by byte
builtins where the shift amount is not of type unsigned character.

gcc/ChangeLog:

* config/s390/s390-builtins.def: Add 128-bit variants.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/vector.md (3): Add 128-bit
variants.
* config/s390/vx-builtins.md: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-shift-10.c: New test.
* gcc.target/s390/vector/vec-shift-11.c: New test.
* gcc.target/s390/vector/vec-shift-12.c: New test.
* gcc.target/s390/vector/vec-shift-3.c: New test.
* gcc.target/s390/vector/vec-shift-4.c: New test.
* gcc.target/s390/vector/vec-shift-5.c: New test.
* gcc.target/s390/vector/vec-shift-6.c: New test.
* gcc.target/s390/vector/vec-shift-7.c: New test.
* gcc.target/s390/vector/vec-shift-8.c: New test.
* gcc.target/s390/vector/vec-shift-9.c: New test.

Diff:
---
 gcc/config/s390/s390-builtin-types.def |  12 ++
 gcc/config/s390/s390-builtins.def  | 184 ++---
 gcc/config/s390/vector.md  |  47 +-
 gcc/config/s390/vx-builtins.md |  54 +++---
 .../gcc.target/s390/vector/vec-shift-10.c  |  54 ++
 .../gcc.target/s390/vector/vec-shift-11.c  |  39 +
 .../gcc.target/s390/vector/vec-shift-12.c  |  39 +
 gcc/testsuite/gcc.target/s390/vector/vec-shift-3.c |  34 
 gcc/testsuite/gcc.target/s390/vector/vec-shift-4.c |  29 
 gcc/testsuite/gcc.target/s390/vector/vec-shift-5.c |  34 
 gcc/testsuite/gcc.target/s390/vector/vec-shift-6.c |  29 
 gcc/testsuite/gcc.target/s390/vector/vec-shift-7.c |  34 
 gcc/testsuite/gcc.target/s390/vector/vec-shift-8.c |  29 
 gcc/testsuite/gcc.target/s390/vector/vec-shift-9.c |  54 ++
 14 files changed, 570 insertions(+), 102 deletions(-)

diff --git a/gcc/config/s390/s390-builtin-types.def 
b/gcc/config/s390/s390-builtin-types.def
index dc61c04848ea..37783734453f 100644
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -607,12 +607,17 @@ DEF_OV_TYPE (BT_OV_UV1TI_LONG_UINT128CONSTPTR, BT_UV1TI, 
BT_LONG, BT_UINT128CONS
 DEF_OV_TYPE (BT_OV_UV1TI_UINT128, BT_UV1TI, BT_UINT128)
 DEF_OV_TYPE (BT_OV_UV1TI_UINT128CONSTPTR_USHORT, BT_UV1TI, BT_UINT128CONSTPTR, 
BT_USHORT)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV16QI, BT_UV1TI, BT_UV1TI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_BV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_BV1TI)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_INT, BT_UV1TI, BT_UV1TI, BT_UV1TI, BT_INT)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UINT, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_UINT)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_ULONGLONG, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UV16QI, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_UV16QI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UV1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_UV1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_UV1TI_INT, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_UV1TI, BT_INT)
 DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_UV1TI_V1TI, BT_UV1TI, BT_UV1TI, BT_UV1TI, 
BT_V1TI)
+DEF_OV_TYPE (BT_OV_UV1TI_UV1TI_V1TI, BT_UV1TI, BT_UV1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI, BT_UV1TI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI_UV2DI, BT_UV1TI, BT_UV2DI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV1TI_UV2DI_UV2DI_UV1TI, BT_UV1TI, BT_UV2DI, BT_UV2DI, 
BT_UV1TI)
@@ -768,9 +773,14 @@ DEF_OV_TYPE (BT_OV_V1TI_INT128CONSTPTR_USHORT, BT_V1TI, 
BT_INT128CONSTPTR, BT_US
 DEF_OV_TYPE (BT_OV_V1TI_LONG_INT128CONSTPTR, BT_V1TI, BT_LONG, 
BT_INT128CONSTPTR)
 DEF_OV_TYPE (BT_OV_V1TI_UV1TI_V1TI_V1TI, BT_V1TI, BT_UV1TI, BT_V1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI, BT_V1TI, BT_V1TI)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_UV16QI, BT_V1TI, BT_V1TI, BT_UV16QI)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_UV1TI, BT_V1TI, BT_V1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_UV1TI_UV1TI, BT_V1TI, BT_V1TI, BT_UV1TI, BT_UV1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI, BT_V1TI, BT_V1TI, BT_V1TI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_BV1TI, BT_V1TI, BT_V1TI, BT_V1TI, BT_BV1TI)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_INT, BT_V1TI, BT_V1TI, BT_V1TI, BT_INT)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_UINT, BT_V1TI, BT_V1TI, BT_V1TI, BT_UINT)
+DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_ULONGLONG, BT_V1TI, BT_V1TI, BT_V1TI, 
BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_UV16QI, BT_V1TI, BT_V1TI, BT_V1TI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V1TI_V1TI_V1TI_UV1T

[gcc r15-6791] s390: Add expander for uaddc/usubc optabs

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:8a2d5bc28089b2660310b964ef75fb05eb387f88

commit r15-6791-g8a2d5bc28089b2660310b964ef75fb05eb387f88
Author: Stefan Schulze Frielinghaus 
Date:   Fri Jan 10 15:14:08 2025 +0100

s390: Add expander for uaddc/usubc optabs

gcc/ChangeLog:

* config/s390/s390-protos.h (s390_emit_compare): Add mode
parameter for the resulting RTX.
* config/s390/s390.cc (s390_emit_compare): Dito.
(s390_emit_compare_and_swap): Change.
(s390_expand_vec_strlen): Change.
(s390_expand_cs_hqi): Change.
(s390_expand_split_stack_prologue): Change.
* config/s390/s390.md (*add3_carry1_cc): Renamed to ...
(add3_carry1_cc): this and in order to use the
corresponding gen function, encode CC mode into pattern.
(*sub3_borrow_cc): Renamed to ...
(sub3_borrow_cc): this and in order to use the
corresponding gen function, encode CC mode into pattern.
(*add3_alc_carry1_cc): Renamed to ...
(add3_alc_carry1_cc): this and in order to use the
corresponding gen function, encode CC mode into pattern.
(sub3_slb_borrow1_cc): New.
(uaddc5): New.
(usubc5): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/uaddc-1.c: New test.
* gcc.target/s390/uaddc-2.c: New test.
* gcc.target/s390/uaddc-3.c: New test.
* gcc.target/s390/usubc-1.c: New test.
* gcc.target/s390/usubc-2.c: New test.
* gcc.target/s390/usubc-3.c: New test.

Diff:
---
 gcc/config/s390/s390-protos.h   |   2 +-
 gcc/config/s390/s390.cc |  20 ++--
 gcc/config/s390/s390.md | 115 ++-
 gcc/testsuite/gcc.target/s390/uaddc-1.c | 156 
 gcc/testsuite/gcc.target/s390/uaddc-2.c |  25 +
 gcc/testsuite/gcc.target/s390/uaddc-3.c |  27 ++
 gcc/testsuite/gcc.target/s390/usubc-1.c | 156 
 gcc/testsuite/gcc.target/s390/usubc-2.c |  25 +
 gcc/testsuite/gcc.target/s390/usubc-3.c |  29 ++
 9 files changed, 519 insertions(+), 36 deletions(-)

diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 00848008dcf0..e8c7f8308496 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -86,7 +86,7 @@ extern int tls_symbolic_operand (rtx);
 extern bool s390_match_ccmode (rtx_insn *, machine_mode);
 extern machine_mode s390_tm_ccmode (rtx, rtx, bool);
 extern machine_mode s390_select_ccmode (enum rtx_code, rtx, rtx);
-extern rtx s390_emit_compare (enum rtx_code, rtx, rtx);
+extern rtx s390_emit_compare (machine_mode, enum rtx_code, rtx, rtx);
 extern rtx_insn *s390_emit_jump (rtx, rtx);
 extern bool symbolic_reference_mentioned_p (rtx);
 extern bool tls_symbolic_reference_mentioned_p (rtx);
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 08acb69de3e8..a98e067bb06f 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -2029,9 +2029,9 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx 
*op1,
the IF_THEN_ELSE of the conditional branch testing the result.  */
 
 rtx
-s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
+s390_emit_compare (machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
 {
-  machine_mode mode = s390_select_ccmode (code, op0, op1);
+  machine_mode cc_mode = s390_select_ccmode (code, op0, op1);
   rtx cc;
 
   /* Force OP1 into register in order to satisfy VXE TFmode patterns.  */
@@ -2043,17 +2043,17 @@ s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
   /* Do not output a redundant compare instruction if a
 compare_and_swap pattern already computed the result and the
 machine modes are compatible.  */
-  gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
+  gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), cc_mode)
  == GET_MODE (op0));
   cc = op0;
 }
   else
 {
-  cc = gen_rtx_REG (mode, CC_REGNUM);
-  emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (mode, op0, op1)));
+  cc = gen_rtx_REG (cc_mode, CC_REGNUM);
+  emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (cc_mode, op0, op1)));
 }
 
-  return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
+  return gen_rtx_fmt_ee (code, mode, cc, const0_rtx);
 }
 
 /* If MEM is not a legitimate compare-and-swap memory operand, return a new
@@ -2103,7 +2103,7 @@ s390_emit_compare_and_swap (enum rtx_code code, rtx old, 
rtx mem,
 default:
   gcc_unreachable ();
 }
-  return s390_emit_compare (code, cc, const0_rtx);
+  return s390_emit_compare (VOIDmode, code, cc, const0_rtx);
 }
 
 /* Emit a jump instruction to TARGET and return it.  If COND is
@@ -6647,7 +6647,7 @@ s390_expand_vec_strlen (rtx target, rtx string, rtx 
alignment)
  Now we have to check whether the resulting index lies 

[gcc r15-6742] s390: Fix s390_constant_via_vgbm_p() [PR118362]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:2f31819a0ac7b000fa3a456e5b068242e954edac

commit r15-6742-g2f31819a0ac7b000fa3a456e5b068242e954edac
Author: Stefan Schulze Frielinghaus 
Date:   Thu Jan 9 17:49:02 2025 +0100

s390: Fix s390_constant_via_vgbm_p() [PR118362]

Optimization s390_constant_via_vgbm_p() should only apply to constant
vectors which can be expressed by the hardware, i.e., which have a size
of at most 16-bytes, similar as it is done for s390_constant_via_vgm_p()
and s390_constant_via_vrepi_p().

gcc/ChangeLog:

PR target/118362
* config/s390/s390.cc (s390_constant_via_vgbm_p): Allow at most
16-byte vectors.

Diff:
---
 gcc/config/s390/s390.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 918a2cd6c6df..08acb69de3e8 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -2818,7 +2818,7 @@ s390_constant_via_vgbm_p (rtx op, unsigned *mask)
   unsigned tmp_mask = 0;
   int nunit, unit_size;
 
-  if (GET_CODE (op) == CONST_VECTOR)
+  if (GET_CODE (op) == CONST_VECTOR && GET_MODE_SIZE (GET_MODE (op)) <= 16)
 {
   if (GET_MODE_INNER (GET_MODE (op)) == TImode
  || GET_MODE_INNER (GET_MODE (op)) == TFmode)

[gcc r15-7499] s390: Fix s390_valid_shift_count() for TI mode [PR118835]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:ac9806dae30d07ab082ac341fe5646987753adcb

commit r15-7499-gac9806dae30d07ab082ac341fe5646987753adcb
Author: Stefan Schulze Frielinghaus 
Date:   Thu Feb 13 09:13:06 2025 +0100

s390: Fix s390_valid_shift_count() for TI mode [PR118835]

During combine we may end up with

(set (reg:DI 66 [ _6 ])
 (ashift:DI (reg:DI 72 [ x ])
(subreg:QI (and:TI (reg:TI 67 [ _1 ])
   (const_wide_int 0x0aabf))
   15)))

where the shift count operand does not trivially fit the scheme of
address operands.  Reject those operands, especially since
strip_address_mutations() expects expressions of the form
(and ... (const_int ...)) and fails for (and ... (const_wide_int ...)).

Thus, be more strict here and accept only CONST_INT operands.  Done by
replacing immediate_operand() with const_int_operand() which is enough
since the former only additionally checks for LEGITIMATE_PIC_OPERAND_P
and targetm.legitimate_constant_p which are always true for CONST_INT
operands.

While on it, fix indentation of the if block.

gcc/ChangeLog:

PR target/118835
* config/s390/s390.cc (s390_valid_shift_count): Reject shift
count operands which do not trivially fit the scheme of
address operands.

gcc/testsuite/ChangeLog:

* gcc.target/s390/pr118835.c: New test.

Diff:
---
 gcc/config/s390/s390.cc  | 35 ++--
 gcc/testsuite/gcc.target/s390/pr118835.c | 21 +++
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 1d96df49feac..29aef501fdd2 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3510,26 +3510,31 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT 
implicit_mask)
 
   /* Check for an and with proper constant.  */
   if (GET_CODE (op) == AND)
-  {
-rtx op1 = XEXP (op, 0);
-rtx imm = XEXP (op, 1);
+{
+  rtx op1 = XEXP (op, 0);
+  rtx imm = XEXP (op, 1);
 
-if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
-  op1 = XEXP (op1, 0);
+  if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
+   op1 = XEXP (op1, 0);
 
-if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
-  return false;
+  if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
+   return false;
 
-if (!immediate_operand (imm, GET_MODE (imm)))
-  return false;
+  /* Accept only CONST_INT as immediates, i.e., reject shift count operands
+which do not trivially fit the scheme of address operands.  Especially
+since strip_address_mutations() expects expressions of the form
+(and ... (const_int ...)) and fails for
+(and ... (const_wide_int ...)).  */
+  if (!const_int_operand (imm, GET_MODE (imm)))
+   return false;
 
-HOST_WIDE_INT val = INTVAL (imm);
-if (implicit_mask > 0
-   && (val & implicit_mask) != implicit_mask)
-  return false;
+  HOST_WIDE_INT val = INTVAL (imm);
+  if (implicit_mask > 0
+ && (val & implicit_mask) != implicit_mask)
+   return false;
 
-op = op1;
-  }
+  op = op1;
+}
 
   /* Check the rest.  */
   return s390_decompose_addrstyle_without_index (op, NULL, NULL);
diff --git a/gcc/testsuite/gcc.target/s390/pr118835.c 
b/gcc/testsuite/gcc.target/s390/pr118835.c
new file mode 100644
index ..1ca6cd95543b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/pr118835.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+/* During combine we may end up with patterns of the form
+
+   (set (reg:DI 66 [ _6 ])
+(ashift:DI (reg:DI 72 [ x ])
+   (subreg:QI (and:TI (reg:TI 67 [ _1 ])
+  (const_wide_int 0x0aabf))
+  15)))
+
+   which should be rejected since the shift count does not trivially fit the
+   scheme of address operands.  */
+
+long
+test (long x, int y)
+{
+  __int128 z = 0xAABF;
+  z &= y;
+  return x << z;
+}

[gcc r15-8442] s390: testsuite: Fix vcond-shift.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:7e947040a48d3156c602e88fb938c7bd44e83b28

commit r15-8442-g7e947040a48d3156c602e88fb938c7bd44e83b28
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 19 16:35:12 2025 +0100

s390: testsuite: Fix vcond-shift.c

Previously we optimized expressions of the form a < 0 ? -1 : 0 to
(signed)a >> 31 during vcond expanding.  Since r15-1638-gaac00d09859cc5
this is done in match.pd.  The implementation in the back end as well as
in match.pd are basically the same but still distinct.  For the tests in
vcond-shift.c the back end emitted

  (xx - (xx >> 31)) >> 1

whereas now via match.pd

  ((int) ((unsigned int) xx >> 31) + xx) >> 1

which is basically the same.  We just have to adapt the scan-assembler
directives w.r.t. signed/unsigned shifts which is done by this patch.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vcond-shift.c: Adapt to new match.pd
rule and change scan-assembler-times for shifts.

Diff:
---
 gcc/testsuite/gcc.target/s390/vector/vcond-shift.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c 
b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
index a6b4e97aa502..b942f44039d2 100644
--- a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
@@ -3,13 +3,13 @@
 /* { dg-do compile { target { s390*-*-* } } } */
 /* { dg-options "-O3 -march=z13 -mzarch" } */
 
-/* { dg-final { scan-assembler-times "vesraf\t%v.?,%v.?,31" 6 } } */
-/* { dg-final { scan-assembler-times "vesrah\t%v.?,%v.?,15" 6 } } */
-/* { dg-final { scan-assembler-times "vesrab\t%v.?,%v.?,7" 6 } } */
+/* { dg-final { scan-assembler-times "vesraf\t%v.?,%v.?,31" 4 } } */
+/* { dg-final { scan-assembler-times "vesrah\t%v.?,%v.?,15" 4 } } */
+/* { dg-final { scan-assembler-times "vesrab\t%v.?,%v.?,7" 4 } } */
 /* { dg-final { scan-assembler-not "vzero\t*" } } */
-/* { dg-final { scan-assembler-times "vesrlf\t%v.?,%v.?,31" 4 } } */
-/* { dg-final { scan-assembler-times "vesrlh\t%v.?,%v.?,15" 4 } } */
-/* { dg-final { scan-assembler-times "vesrlb\t%v.?,%v.?,7" 4 } } */
+/* { dg-final { scan-assembler-times "vesrlf\t%v.?,%v.?,31" 6 } } */
+/* { dg-final { scan-assembler-times "vesrlh\t%v.?,%v.?,15" 6 } } */
+/* { dg-final { scan-assembler-times "vesrlb\t%v.?,%v.?,7" 6 } } */
 
 /* Make it expand to two vector operations.  */
 #define ITER(X) (2 * (16 / sizeof (X[1])))

[gcc r15-8086] testsuite: s390: Skip gcc.dg/vect/bb-slp-77.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:25cc0f28544a3d9d39f2c48c104b4c1f11b717a7

commit r15-8086-g25cc0f28544a3d9d39f2c48c104b4c1f11b717a7
Author: Stefan Schulze Frielinghaus 
Date:   Mon Mar 17 14:07:52 2025 +0100

testsuite: s390: Skip gcc.dg/vect/bb-slp-77.c

There exists no .REDUC_PLUS on s390.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/bb-slp-77.c: Skip on s390.

Diff:
---
 gcc/testsuite/gcc.dg/vect/bb-slp-77.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-77.c 
b/gcc/testsuite/gcc.dg/vect/bb-slp-77.c
index 2057f038f2f3..f533c41b7f64 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-77.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-77.c
@@ -71,4 +71,4 @@ void test(const int n, float * restrict s, const void * 
restrict vx, const void
 *s = sumf;
 }
 
-/* { dg-final { scan-tree-dump-times "optimized: basic block" 1 "slp1"  { 
target { { vect_int_mult && vect_element_align } && { ! { powerpc*-*-* 
x86_64-*-* i?86-*-* loongarch*-*-* } } } } } } */
+/* { dg-final { scan-tree-dump-times "optimized: basic block" 1 "slp1"  { 
target { { vect_int_mult && vect_element_align } && { ! { powerpc*-*-* 
x86_64-*-* i?86-*-* loongarch*-*-* s390*-*-* } } } } } } */

[gcc r15-8443] s390: testsuite: Fix autovec-double-signaling-eq-z13.c

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:abfdab9c7dd6c60641b203bf247bb1b8a1f218ec

commit r15-8443-gabfdab9c7dd6c60641b203bf247bb1b8a1f218ec
Author: Stefan Schulze Frielinghaus 
Date:   Wed Mar 19 16:35:12 2025 +0100

s390: testsuite: Fix autovec-double-signaling-eq-z13.c

Since r15-3992-g698e0ec89bc096 we optimize x<=y && x>=y to x==y.
Honour signaling NaNs by using option -fsignaling-nans in order to
prevent this.

gcc/testsuite/ChangeLog:

* gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c:
Honour sNaNs.

Diff:
---
 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c 
b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c
index 1806fa8c60e9..ad097efcee9a 100644
--- a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c
+++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=z13 -mzvector -mzarch" } */
+/* { dg-options "-O3 -march=z13 -mzvector -mzarch -fsignaling-nans" } */
 
 #include "autovec.h"

[gcc r15-8483] s390: Accept only Pmode for registers AP/FP/RA [PR119235]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:2b383ae2a6e5fc0530bfd8b86ad0e6b27e760bd2

commit r15-8483-g2b383ae2a6e5fc0530bfd8b86ad0e6b27e760bd2
Author: Stefan Schulze Frielinghaus 
Date:   Fri Mar 21 10:29:19 2025 +0100

s390: Accept only Pmode for registers AP/FP/RA [PR119235]

gcc/ChangeLog:

PR target/119235
* config/s390/s390.cc (s390_hard_regno_mode_ok): Accept only
Pmode for registers AP/FP/RA.

Diff:
---
 gcc/config/s390/s390.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 9df3c4edb0b2..0ff3fd54dc3f 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -11173,8 +11173,8 @@ s390_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
}
   break;
 case ADDR_REGS:
-  if (FRAME_REGNO_P (regno) && mode == Pmode)
-   return true;
+  if (FRAME_REGNO_P (regno))
+   return mode == Pmode;
 
   /* fallthrough */
 case GENERAL_REGS:

[gcc r14-11681] s390: Accept only Pmode for registers AP/FP/RA [PR119235]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:29004acab5caa46e59f53c8516619a9e996f8c49

commit r14-11681-g29004acab5caa46e59f53c8516619a9e996f8c49
Author: Stefan Schulze Frielinghaus 
Date:   Fri Mar 21 10:29:19 2025 +0100

s390: Accept only Pmode for registers AP/FP/RA [PR119235]

gcc/ChangeLog:

PR target/119235
* config/s390/s390.cc (s390_hard_regno_mode_ok): Accept only
Pmode for registers AP/FP/RA.

(cherry picked from commit 2b383ae2a6e5fc0530bfd8b86ad0e6b27e760bd2)

Diff:
---
 gcc/config/s390/s390.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 8b383034e036..9f09f0a3e1e9 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -10949,8 +10949,8 @@ s390_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
}
   break;
 case ADDR_REGS:
-  if (FRAME_REGNO_P (regno) && mode == Pmode)
-   return true;
+  if (FRAME_REGNO_P (regno))
+   return mode == Pmode;
 
   /* fallthrough */
 case GENERAL_REGS:

[gcc r13-9613] s390: Accept only Pmode for registers AP/FP/RA [PR119235]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:a6a66eca19b5c556e2be7ca8c2b0d556ef52374c

commit r13-9613-ga6a66eca19b5c556e2be7ca8c2b0d556ef52374c
Author: Stefan Schulze Frielinghaus 
Date:   Fri Mar 21 10:29:19 2025 +0100

s390: Accept only Pmode for registers AP/FP/RA [PR119235]

gcc/ChangeLog:

PR target/119235
* config/s390/s390.cc (s390_hard_regno_mode_ok): Accept only
Pmode for registers AP/FP/RA.

(cherry picked from commit 2b383ae2a6e5fc0530bfd8b86ad0e6b27e760bd2)

Diff:
---
 gcc/config/s390/s390.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 8593a636d122..59f2f4bf7db8 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -10595,8 +10595,8 @@ s390_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
}
   break;
 case ADDR_REGS:
-  if (FRAME_REGNO_P (regno) && mode == Pmode)
-   return true;
+  if (FRAME_REGNO_P (regno))
+   return mode == Pmode;
 
   /* fallthrough */
 case GENERAL_REGS:

[gcc r15-9408] s390: Add z17 scheduler description

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:171710bec51ebbe859bf3ff008e60dd018738026

commit r15-9408-g171710bec51ebbe859bf3ff008e60dd018738026
Author: Stefan Schulze Frielinghaus 
Date:   Sun Apr 13 10:59:18 2025 +0200

s390: Add z17 scheduler description

gcc/ChangeLog:

* config/s390/s390.cc: Add z17 scheduler description.
* config/s390/s390.h: Ditto.
* config/s390/s390.md: Ditto.
* config/s390/9175.md: New file.

Diff:
---
 gcc/config/s390/9175.md | 316 
 gcc/config/s390/s390.cc |  31 -
 gcc/config/s390/s390.h  |   2 +-
 gcc/config/s390/s390.md |   5 +-
 4 files changed, 348 insertions(+), 6 deletions(-)

diff --git a/gcc/config/s390/9175.md b/gcc/config/s390/9175.md
new file mode 100644
index ..d0ac0e1c9b59
--- /dev/null
+++ b/gcc/config/s390/9175.md
@@ -0,0 +1,316 @@
+;; Scheduling description for z17.
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it under
+;; the terms of the GNU General Public License as published by the Free
+;; Software Foundation; either version 3, or (at your option) any later
+;; version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+;; for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_attr "z17_unit_fpd" ""
+ (cond [(eq_attr "mnemonic" "ddb,ddbr,deb,debr,dxbr,sqdb,sqdbr,sqeb,sqebr,\
+sqxbr,vdf,vdg,vdlf,vdlg,vdlq,vdq,vfddb,vfdsb,vfsqdb,vfsqsb,vrf,vrg,vrlf,vrlg,\
+vrlq,vrq,wfddb,wfdsb,wfdxb,wfsqdb,wfsqxb")
+ (const_int 1)] (const_int 0)))
+
+(define_attr "z17_unit_fxa" ""
+ (cond [(eq_attr "mnemonic" 
"a,afi,ag,agf,agfi,agfr,agh,aghi,aghik,agr,agrk,ah,\
+ahi,ahik,ahy,al,alc,alcg,alcgr,alcr,alfi,alg,algf,algfi,algfr,alghsik,algr,\
+algrk,alhsik,alr,alrk,aly,ar,ark,ay,bdepg,bextg,clzg,ctzg,etnd,flogr,ic,icm,\
+icmh,icmy,icy,iihf,iilf,ipm,la,larl,lay,lb,lbr,lcgfr,lcgr,lcr,lgb,lgbr,lgf,\
+lgfi,lgfr,lgfrl,lgh,lghi,lghr,lghrl,lgr,lh,lhi,lhr,lhrl,lhy,llcr,llgcr,llgfr,\
+llghr,llgtr,llhr,llihf,llihh,llihl,llilf,llilh,llill,llxab,llxaf,llxag,llxah,\
+llxaq,lngfr,lngr,lnr,loc,locg,locghi,locgr,lochi,locr,lpgfr,lpgr,lpr,lr,lrv,\
+lrvg,lrvgr,lrvh,lrvr,lt,ltg,ltgf,ltgfr,ltgr,ltr,lxab,lxaf,lxag,lxah,lxaq,m,mfy,\
+mg,mgh,mghi,mgrk,mh,mhi,mhy,ml,mlg,mlgr,mlr,mr,ms,msc,msfi,msg,msgc,msgf,msgfi,\
+msgfr,msgr,msgrkc,msr,msrkc,msy,n,ncgrk,ncrk,ng,ngr,ngrk,nihf,nihh,nihl,nilf,\
+nilh,nill,nngrk,nnrk,nogrk,nork,nr,nrk,nxgrk,nxrk,ny,o,ocgrk,ocrk,og,ogr,ogrk,\
+oihf,oihh,oihl,oilf,oilh,oill,or,ork,oy,pfpo,popcnt,risbg,risbgn,rll,rllg,\
+rnsbg,rosbg,rxsbg,s,selgr,selr,sg,sgf,sgfr,sgh,sgr,sgrk,sh,shy,sl,slb,slbg,\
+slbgr,slbr,sldl,slfi,slg,slgf,slgfi,slgfr,slgr,slgrk,sll,sllg,sllk,slr,slrk,\
+sly,sr,sra,srag,srak,srda,srdl,srk,srl,srlg,srlk,sy,x,xg,xgr,xgrk,xihf,xilf,xr,\
+xrk,xy")
+ (const_int 1)] (const_int 0)))
+
+(define_attr "z17_unit_fxb" ""
+ (cond [(eq_attr "mnemonic" "agsi,algsi,alsi,asi,b,bc,bcr,bi,br,c,cfi,cg,cgf,\
+cgfi,cgfr,cgfrl,cgh,cghi,cghrl,cghsi,cgit,cgr,cgrl,cgrt,ch,chi,chrl,chsi,chy,\
+cit,cl,clfhsi,clfi,clfit,clg,clgf,clgfi,clgfr,clgfrl,clghrl,clghsi,clgit,clgr,\
+clgrl,clgrt,clgt,clhhsi,clhrl,cli,cliy,clm,clmy,clr,clrl,clrt,clt,cly,cr,crl,\
+crt,cy,laa,laag,lan,lang,lao,laog,lat,lax,laxg,lcdfr,ldgr,ldr,lgat,lgdr,lndfr,\
+lpdfr,lxr,lzdr,lzer,lzxr,mvghi,mvhhi,mvhi,mvi,mviy,ni,niy,nop,nopr,ntstg,oi,\
+oiy,ppa,st,stc,stcy,std,stdy,ste,stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,\
+strv,strvg,strvh,sty,tend,tm,tmh,tmhh,tmhl,tml,tmlh,tmll,tmy,vlgvb,vlgvf,vlgvg,\
+vlgvh,vlr,vlvgb,vlvgf,vlvgg,vlvgh,vlvgp,vscef,vsceg,vst,vstbrf,vstbrg,vstbrh,\
+vstbrq,vstebrf,vstebrg,vstef,vsteg,vsterf,vsterg,vsterh,vstl,vstrl,vstrlr,xi,\
+xiy")
+ (const_int 1)] (const_int 0)))
+
+(define_attr "z17_unit_fxd" ""
+ (cond [(eq_attr "mnemonic" "dlgr,dlr,dr,dsgfr,dsgr")
+ (const_int 1)] (const_int 0)))
+
+(define_attr "z17_unit_lsu" ""
+ (cond [(eq_attr "mnemonic" "clc,ear,l,lam,lcbb,ld,lde,ldy,lg,lgrl,llc,llgc,\
+llgf,llgfrl,llgh,llghrl,llgt,llh,llhrl,lm,lmg,lmy,lpq,lrl,ly,mvcrl,sar,sfpc,\
+tabort,vl,vlbb,vlbrf,vlbrg,vlbrh,vlbrq,vlbrrepf,vlbrrepg,vlbrreph,vlerf,vlerg,\
+vlerh,vll,vllebrzf,vllebrzg,vllebrzh,vllezb,vllezf,vllezg,vllezh,vllezlf,\
+vlrepb,vlrepf,vlrepg,vlreph,vlrl,vlrlr")
+ (const_int 1)] (const_int 0)))
+
+(define_attr "z17_unit_vfu" ""
+ (cond [(eq_attr "mnemonic" "adb,adbr,adtr,aeb,aebr,axbr,axtr,brcl,cdb,cdbr,\
+cdtr,ceb,cebr,cpsdr,cxbr,cxtr,ddtr,dxtr,fidbr,fidbra,fidtr,fiebr,fiebra,fixbr,\
+fixbra,fixtr,j,jg,kdb,kdbr,kdtr,keb,kebr,kxbr,kxtr,lcdbr,lcebr,lcxbr,ldeb,\
+ldebr,ldetr,le,ledbr,ledtr,ler,ley,lndbr,lnebr,lnxbr,lpdbr,lpebr,lpxbr,ltdbr,\
+ltdtr,ltebr,ltxbr,ltxtr,lxd

[gcc r15-9407] s390: Support z17 processor name

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:1b290c16e591f6df3c5896d21b610df3444052d9

commit r15-9407-g1b290c16e591f6df3c5896d21b610df3444052d9
Author: Stefan Schulze Frielinghaus 
Date:   Sun Apr 13 10:59:18 2025 +0200

s390: Support z17 processor name

The recently announced IBM z17 processor implements the architecture
already supported as arch15.  This patch adds support for z17 as an
alternative architecture name for arch15.

gcc/ChangeLog:

* common/config/s390/s390-common.cc: Rename arch15 to z17.
* config.gcc: Add z17.
* config/s390/driver-native.cc: Detect z17 machine.
* config/s390/s390-builtins.def (B_VXE3): Rename arch15 to z17.
* config/s390/s390-c.cc (s390_resolve_overloaded_builtin): Ditto.
* config/s390/s390-opts.h (enum processor_type): Ditto.
* config/s390/s390.cc: Ditto.
* config/s390/s390.h: Ditto.
* config/s390/s390.md: Ditto.
* config/s390/s390.opt: Add z17.
* doc/invoke.texi: Ditto.

Diff:
---
 gcc/common/config/s390/s390-common.cc |  4 ++--
 gcc/config.gcc|  2 +-
 gcc/config/s390/driver-native.cc  |  4 
 gcc/config/s390/s390-builtins.def |  8 
 gcc/config/s390/s390-c.cc |  4 ++--
 gcc/config/s390/s390-opts.h   |  2 +-
 gcc/config/s390/s390.cc   | 10 +-
 gcc/config/s390/s390.h| 16 
 gcc/config/s390/s390.md   | 34 +-
 gcc/config/s390/s390.opt  |  5 -
 gcc/doc/invoke.texi   |  2 +-
 11 files changed, 49 insertions(+), 42 deletions(-)

diff --git a/gcc/common/config/s390/s390-common.cc 
b/gcc/common/config/s390/s390-common.cc
index 4b0691d5a16f..8a147d7f8043 100644
--- a/gcc/common/config/s390/s390-common.cc
+++ b/gcc/common/config/s390/s390-common.cc
@@ -54,10 +54,10 @@ EXPORTED_CONST int processor_flags_table[] =
 | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
 | PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15
 | PF_NNPA | PF_Z16,
-/* arch15 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
+/* z17 */PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
 | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
 | PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15
-| PF_NNPA | PF_Z16 | PF_VXE3 | PF_ARCH15
+| PF_NNPA | PF_Z16 | PF_VXE3 | PF_Z17
   };
 
 /* Change optimizations to be performed, depending on the
diff --git a/gcc/config.gcc b/gcc/config.gcc
index f7f2002a45f3..40b50dc969ed 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5756,7 +5756,7 @@ case "${target}" in
for which in arch tune; do
eval "val=\$with_$which"
case ${val} in
-   "" | native | z900 | z990 | z9-109 | z9-ec | z10 | z196 
| zEC12 | z13 | z14 | z15 | z16 | arch5 | arch6 | arch7 | arch8 | arch9 | 
arch10 | arch11 | arch12 | arch13 | arch14 | arch15 )
+   "" | native | z900 | z990 | z9-109 | z9-ec | z10 | z196 
| zEC12 | z13 | z14 | z15 | z16 | z17 | arch5 | arch6 | arch7 | arch8 | arch9 | 
arch10 | arch11 | arch12 | arch13 | arch14 | arch15 )
# OK
;;
*)
diff --git a/gcc/config/s390/driver-native.cc b/gcc/config/s390/driver-native.cc
index 49e8fa01a19b..7a7ceea9739c 100644
--- a/gcc/config/s390/driver-native.cc
+++ b/gcc/config/s390/driver-native.cc
@@ -127,6 +127,10 @@ s390_host_detect_local_cpu (int argc, const char **argv)
case 0x3932:
  cpu = "arch14";
  break;
+   case 0x9175:
+   case 0x9176:
+ cpu = "arch15";
+ break;
default:
  cpu = "arch15";
  break;
diff --git a/gcc/config/s390/s390-builtins.def 
b/gcc/config/s390/s390-builtins.def
index d9af9b13def1..cee2326e25c8 100644
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -300,8 +300,8 @@
 #define B_VXE2  (1 << 4)  /* Builtins requiring the z15 vector extensions.  */
 #define B_DEP   (1 << 5)  /* Builtin has been deprecated and a warning should 
be issued.  */
 #define B_NNPA  (1 << 6)  /* Builtins requiring the NNPA Facility.  */
-#define B_VXE3  (1 << 7)  /* Builtins requiring the arch15 vector extensions.  
*/
-#define B_ARCH15 (1 << 8) /* Builtins requiring arch15.  */
+#define B_VXE3  (1 << 7)  /* Builtins requiring the z17 vector extensions.  */
+#define B_Z17   (1 << 8) /* Builtins requiring z17.  */
 
 /* B_DEF defines a standard (not overloaded) builtin
B_DEF (, , , , , )
@@ -3318,8 +3318,8 @@ B_DEF  (s390_vcnf,   vcnf_v8hi,   
  0,
 
 /* arch 15 builtins */
 
-B_DEF  (s390_bdepg, bdepg,  0

[gcc r12-11075] s390: Accept only Pmode for registers AP/FP/RA [PR119235]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:d41ce9f7c392d5110a63d61c4c85fb7a5f2f

commit r12-11075-gd41ce9f7c392d5110a63d61c4c85fb7a5f2f
Author: Stefan Schulze Frielinghaus 
Date:   Fri Mar 21 10:29:19 2025 +0100

s390: Accept only Pmode for registers AP/FP/RA [PR119235]

gcc/ChangeLog:

PR target/119235
* config/s390/s390.cc (s390_hard_regno_mode_ok): Accept only
Pmode for registers AP/FP/RA.

(cherry picked from commit 2b383ae2a6e5fc0530bfd8b86ad0e6b27e760bd2)

Diff:
---
 gcc/config/s390/s390.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 4e7a01ae6c9d..bf200efdfe6a 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -10474,8 +10474,8 @@ s390_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
}
   break;
 case ADDR_REGS:
-  if (FRAME_REGNO_P (regno) && mode == Pmode)
-   return true;
+  if (FRAME_REGNO_P (regno))
+   return mode == Pmode;
 
   /* fallthrough */
 case GENERAL_REGS:

[gcc r15-7945] s390: Deprecate ESA/390 support

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:3b1bd1fdcd241dd1e5b706b6937400d74ca43146

commit r15-7945-g3b1bd1fdcd241dd1e5b706b6937400d74ca43146
Author: Stefan Schulze Frielinghaus 
Date:   Tue Mar 11 09:28:06 2025 +0100

s390: Deprecate ESA/390 support

Deprecate support for the ESA/390 architecture which will be eventually
removed, and encourage the usage of the z/Architecture instead.

Furthermore, default for -m31 to -mzarch whereas previously we defaulted
to -mesa.

gcc/ChangeLog:

* config.gcc: Fail in case of option --with-mode=esa.
* config/s390/s390.cc (s390_option_override_internal): Default
to z/Architecture mode.
* config/s390/s390.h (DRIVER_SELF_SPECS): Ditto.
* config/s390/s390.opt: Emit a warning for option -mesa.
* doc/invoke.texi: Document the change.

gcc/testsuite/ChangeLog:

* gcc.target/s390/20020926-1.c: Deal with deprecation warning.
* gcc.target/s390/dwarfregtable-1.c: Ditto.
* gcc.target/s390/fp2int1.c: Ditto.
* gcc.target/s390/pr10.c: Ditto.
* gcc.target/s390/pr106355-3.c: Ditto.
* gcc.target/s390/pr61078.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-10.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-12.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-14.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-18.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-2.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-20.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-22.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-24.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-26.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-28.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-30.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-32.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-4.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-6.c: Ditto.
* gcc.target/s390/target-attribute/tattr-m31-8.c: Ditto.

Diff:
---
 gcc/config.gcc| 6 +-
 gcc/config/s390/s390.cc   | 7 +--
 gcc/config/s390/s390.h| 2 +-
 gcc/config/s390/s390.opt  | 2 +-
 gcc/doc/invoke.texi   | 6 +-
 gcc/testsuite/gcc.target/s390/20020926-1.c| 1 +
 gcc/testsuite/gcc.target/s390/dwarfregtable-1.c   | 1 +
 gcc/testsuite/gcc.target/s390/fp2int1.c   | 1 +
 gcc/testsuite/gcc.target/s390/pr10.c  | 1 +
 gcc/testsuite/gcc.target/s390/pr106355-3.c| 1 +
 gcc/testsuite/gcc.target/s390/pr61078.c   | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-10.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-12.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-14.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-18.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-2.c  | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-20.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-22.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-24.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-26.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-28.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-30.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-32.c | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-4.c  | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-6.c  | 1 +
 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m31-8.c  | 1 +
 26 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index a518e976b82e..c4816e26f82f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5768,9 +5768,13 @@ case "${target}" in
done
 
case ${with_mode} in
-   "" | esa | zarch)
+   "" | zarch)
# OK
;;
+   esa)
+   echo "Support for ESA/390 is deprecated; use 
z/Architecture instead." 1>&2
+   exit 1
+   ;;
*)
echo "Unknown architecture mode used in 
--with-mode=$with_mode." 1>&2
exit 1
diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 2f516967e7b1..645aedba67f0 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -162

[gcc r15-7944] s390: Implement TARGET_INSN_COST [PR115835]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:229f4f040485c0c05cfb707b30c9b983ed1f95d3

commit r15-7944-g229f4f040485c0c05cfb707b30c9b983ed1f95d3
Author: Stefan Schulze Frielinghaus 
Date:   Tue Mar 11 08:59:15 2025 +0100

s390: Implement TARGET_INSN_COST [PR115835]

Currently insn_cost() only considers the source part of a SET.
Implement TARGET_INSN_COST in order to also take the destination into
account.  This may make a difference in case of a MEM where the address
is a SYMBOL_REF.

Fixes testsuite/gcc.target/s390/section-anchors.c.

gcc/ChangeLog:

PR target/115835
* config/s390/s390.cc (s390_insn_cost): Implement.
(TARGET_INSN_COST): Define.

Diff:
---
 gcc/config/s390/s390.cc | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index 29aef501fdd2..2f516967e7b1 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3900,6 +3900,26 @@ s390_memory_move_cost (machine_mode mode 
ATTRIBUTE_UNUSED,
   return 2;
 }
 
+/* Implement TARGET_INSN_COST.  */
+
+static int
+s390_insn_cost (rtx_insn *insn, bool speed)
+{
+  /* For stores also consider the destination.  Penalize if the address
+ contains a SYMBOL_REF since this has to be fixed up by reload.  */
+  rtx pat = single_set (insn);
+  if (pat && MEM_P (SET_DEST (pat)))
+{
+  rtx mem = SET_DEST (pat);
+  rtx addr = XEXP (mem, 0);
+  int penalty = contains_symbol_ref_p (addr) ? COSTS_N_INSNS (1) : 0;
+  int src_cost = set_src_cost (SET_SRC (pat), GET_MODE (mem), speed);
+  src_cost = src_cost > 0 ? src_cost : COSTS_N_INSNS (1);
+  return penalty + src_cost;
+}
+  return pattern_cost (PATTERN (insn), speed);
+}
+
 /* Compute a (partial) cost for rtx X.  Return true if the complete
cost has been computed, and false if subexpressions should be
scanned.  In either case, *TOTAL contains the cost result.  The
@@ -18355,6 +18375,8 @@ s390_c_mode_for_floating_type (enum tree_index ti)
 
 #undef TARGET_CANNOT_COPY_INSN_P
 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
+#undef TARGET_INSN_COST
+#define TARGET_INSN_COST s390_insn_cost
 #undef TARGET_RTX_COSTS
 #define TARGET_RTX_COSTS s390_rtx_costs
 #undef TARGET_ADDRESS_COST

[gcc r14-11342] s390: Fix s390_valid_shift_count() for TI mode [PR118835]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:ce4cb48c3396837cf1562882b3f23f768558945b

commit r14-11342-gce4cb48c3396837cf1562882b3f23f768558945b
Author: Stefan Schulze Frielinghaus 
Date:   Thu Feb 13 09:13:06 2025 +0100

s390: Fix s390_valid_shift_count() for TI mode [PR118835]

During combine we may end up with

(set (reg:DI 66 [ _6 ])
 (ashift:DI (reg:DI 72 [ x ])
(subreg:QI (and:TI (reg:TI 67 [ _1 ])
   (const_wide_int 0x0aabf))
   15)))

where the shift count operand does not trivially fit the scheme of
address operands.  Reject those operands, especially since
strip_address_mutations() expects expressions of the form
(and ... (const_int ...)) and fails for (and ... (const_wide_int ...)).

Thus, be more strict here and accept only CONST_INT operands.  Done by
replacing immediate_operand() with const_int_operand() which is enough
since the former only additionally checks for LEGITIMATE_PIC_OPERAND_P
and targetm.legitimate_constant_p which are always true for CONST_INT
operands.

While on it, fix indentation of the if block.

gcc/ChangeLog:

PR target/118835
* config/s390/s390.cc (s390_valid_shift_count): Reject shift
count operands which do not trivially fit the scheme of
address operands.

gcc/testsuite/ChangeLog:

* gcc.target/s390/pr118835.c: New test.

(cherry picked from commit ac9806dae30d07ab082ac341fe5646987753adcb)

Diff:
---
 gcc/config/s390/s390.cc  | 35 ++--
 gcc/testsuite/gcc.target/s390/pr118835.c | 21 +++
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index f2e4f5e101cb..8b383034e036 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3363,26 +3363,31 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT 
implicit_mask)
 
   /* Check for an and with proper constant.  */
   if (GET_CODE (op) == AND)
-  {
-rtx op1 = XEXP (op, 0);
-rtx imm = XEXP (op, 1);
+{
+  rtx op1 = XEXP (op, 0);
+  rtx imm = XEXP (op, 1);
 
-if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
-  op1 = XEXP (op1, 0);
+  if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
+   op1 = XEXP (op1, 0);
 
-if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
-  return false;
+  if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
+   return false;
 
-if (!immediate_operand (imm, GET_MODE (imm)))
-  return false;
+  /* Accept only CONST_INT as immediates, i.e., reject shift count operands
+which do not trivially fit the scheme of address operands.  Especially
+since strip_address_mutations() expects expressions of the form
+(and ... (const_int ...)) and fails for
+(and ... (const_wide_int ...)).  */
+  if (!const_int_operand (imm, GET_MODE (imm)))
+   return false;
 
-HOST_WIDE_INT val = INTVAL (imm);
-if (implicit_mask > 0
-   && (val & implicit_mask) != implicit_mask)
-  return false;
+  HOST_WIDE_INT val = INTVAL (imm);
+  if (implicit_mask > 0
+ && (val & implicit_mask) != implicit_mask)
+   return false;
 
-op = op1;
-  }
+  op = op1;
+}
 
   /* Check the rest.  */
   return s390_decompose_addrstyle_without_index (op, NULL, NULL);
diff --git a/gcc/testsuite/gcc.target/s390/pr118835.c 
b/gcc/testsuite/gcc.target/s390/pr118835.c
new file mode 100644
index ..1ca6cd95543b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/pr118835.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+/* During combine we may end up with patterns of the form
+
+   (set (reg:DI 66 [ _6 ])
+(ashift:DI (reg:DI 72 [ x ])
+   (subreg:QI (and:TI (reg:TI 67 [ _1 ])
+  (const_wide_int 0x0aabf))
+  15)))
+
+   which should be rejected since the shift count does not trivially fit the
+   scheme of address operands.  */
+
+long
+test (long x, int y)
+{
+  __int128 z = 0xAABF;
+  z &= y;
+  return x << z;
+}

[gcc r12-10967] s390: Fix s390_valid_shift_count() for TI mode [PR118835]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:b27fa6a7ca86a9b885cb4dbe8a55991e7fb666f0

commit r12-10967-gb27fa6a7ca86a9b885cb4dbe8a55991e7fb666f0
Author: Stefan Schulze Frielinghaus 
Date:   Thu Feb 13 09:13:06 2025 +0100

s390: Fix s390_valid_shift_count() for TI mode [PR118835]

During combine we may end up with

(set (reg:DI 66 [ _6 ])
 (ashift:DI (reg:DI 72 [ x ])
(subreg:QI (and:TI (reg:TI 67 [ _1 ])
   (const_wide_int 0x0aabf))
   15)))

where the shift count operand does not trivially fit the scheme of
address operands.  Reject those operands, especially since
strip_address_mutations() expects expressions of the form
(and ... (const_int ...)) and fails for (and ... (const_wide_int ...)).

Thus, be more strict here and accept only CONST_INT operands.  Done by
replacing immediate_operand() with const_int_operand() which is enough
since the former only additionally checks for LEGITIMATE_PIC_OPERAND_P
and targetm.legitimate_constant_p which are always true for CONST_INT
operands.

While on it, fix indentation of the if block.

gcc/ChangeLog:

PR target/118835
* config/s390/s390.cc (s390_valid_shift_count): Reject shift
count operands which do not trivially fit the scheme of
address operands.

gcc/testsuite/ChangeLog:

* gcc.target/s390/pr118835.c: New test.

(cherry picked from commit ac9806dae30d07ab082ac341fe5646987753adcb)

Diff:
---
 gcc/config/s390/s390.cc  | 35 ++--
 gcc/testsuite/gcc.target/s390/pr118835.c | 21 +++
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index a8f804ffe4f7..4e7a01ae6c9d 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3216,26 +3216,31 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT 
implicit_mask)
 
   /* Check for an and with proper constant.  */
   if (GET_CODE (op) == AND)
-  {
-rtx op1 = XEXP (op, 0);
-rtx imm = XEXP (op, 1);
+{
+  rtx op1 = XEXP (op, 0);
+  rtx imm = XEXP (op, 1);
 
-if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
-  op1 = XEXP (op1, 0);
+  if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
+   op1 = XEXP (op1, 0);
 
-if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
-  return false;
+  if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
+   return false;
 
-if (!immediate_operand (imm, GET_MODE (imm)))
-  return false;
+  /* Accept only CONST_INT as immediates, i.e., reject shift count operands
+which do not trivially fit the scheme of address operands.  Especially
+since strip_address_mutations() expects expressions of the form
+(and ... (const_int ...)) and fails for
+(and ... (const_wide_int ...)).  */
+  if (!const_int_operand (imm, GET_MODE (imm)))
+   return false;
 
-HOST_WIDE_INT val = INTVAL (imm);
-if (implicit_mask > 0
-   && (val & implicit_mask) != implicit_mask)
-  return false;
+  HOST_WIDE_INT val = INTVAL (imm);
+  if (implicit_mask > 0
+ && (val & implicit_mask) != implicit_mask)
+   return false;
 
-op = op1;
-  }
+  op = op1;
+}
 
   /* Check the rest.  */
   return s390_decompose_addrstyle_without_index (op, NULL, NULL);
diff --git a/gcc/testsuite/gcc.target/s390/pr118835.c 
b/gcc/testsuite/gcc.target/s390/pr118835.c
new file mode 100644
index ..1ca6cd95543b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/pr118835.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+/* During combine we may end up with patterns of the form
+
+   (set (reg:DI 66 [ _6 ])
+(ashift:DI (reg:DI 72 [ x ])
+   (subreg:QI (and:TI (reg:TI 67 [ _1 ])
+  (const_wide_int 0x0aabf))
+  15)))
+
+   which should be rejected since the shift count does not trivially fit the
+   scheme of address operands.  */
+
+long
+test (long x, int y)
+{
+  __int128 z = 0xAABF;
+  z &= y;
+  return x << z;
+}

[gcc r13-9399] s390: Fix s390_valid_shift_count() for TI mode [PR118835]

[Stefan Schulze Frielinghaus via Gcc-cvs]

https://gcc.gnu.org/g:b7466cff8cd4984cea6a2a134c54ca18e20f3fb3

commit r13-9399-gb7466cff8cd4984cea6a2a134c54ca18e20f3fb3
Author: Stefan Schulze Frielinghaus 
Date:   Thu Feb 13 09:13:06 2025 +0100

s390: Fix s390_valid_shift_count() for TI mode [PR118835]

During combine we may end up with

(set (reg:DI 66 [ _6 ])
 (ashift:DI (reg:DI 72 [ x ])
(subreg:QI (and:TI (reg:TI 67 [ _1 ])
   (const_wide_int 0x0aabf))
   15)))

where the shift count operand does not trivially fit the scheme of
address operands.  Reject those operands, especially since
strip_address_mutations() expects expressions of the form
(and ... (const_int ...)) and fails for (and ... (const_wide_int ...)).

Thus, be more strict here and accept only CONST_INT operands.  Done by
replacing immediate_operand() with const_int_operand() which is enough
since the former only additionally checks for LEGITIMATE_PIC_OPERAND_P
and targetm.legitimate_constant_p which are always true for CONST_INT
operands.

While on it, fix indentation of the if block.

gcc/ChangeLog:

PR target/118835
* config/s390/s390.cc (s390_valid_shift_count): Reject shift
count operands which do not trivially fit the scheme of
address operands.

gcc/testsuite/ChangeLog:

* gcc.target/s390/pr118835.c: New test.

(cherry picked from commit ac9806dae30d07ab082ac341fe5646987753adcb)

Diff:
---
 gcc/config/s390/s390.cc  | 35 ++--
 gcc/testsuite/gcc.target/s390/pr118835.c | 21 +++
 2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc
index a0089e4c0f21..8593a636d122 100644
--- a/gcc/config/s390/s390.cc
+++ b/gcc/config/s390/s390.cc
@@ -3264,26 +3264,31 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT 
implicit_mask)
 
   /* Check for an and with proper constant.  */
   if (GET_CODE (op) == AND)
-  {
-rtx op1 = XEXP (op, 0);
-rtx imm = XEXP (op, 1);
+{
+  rtx op1 = XEXP (op, 0);
+  rtx imm = XEXP (op, 1);
 
-if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
-  op1 = XEXP (op1, 0);
+  if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
+   op1 = XEXP (op1, 0);
 
-if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
-  return false;
+  if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
+   return false;
 
-if (!immediate_operand (imm, GET_MODE (imm)))
-  return false;
+  /* Accept only CONST_INT as immediates, i.e., reject shift count operands
+which do not trivially fit the scheme of address operands.  Especially
+since strip_address_mutations() expects expressions of the form
+(and ... (const_int ...)) and fails for
+(and ... (const_wide_int ...)).  */
+  if (!const_int_operand (imm, GET_MODE (imm)))
+   return false;
 
-HOST_WIDE_INT val = INTVAL (imm);
-if (implicit_mask > 0
-   && (val & implicit_mask) != implicit_mask)
-  return false;
+  HOST_WIDE_INT val = INTVAL (imm);
+  if (implicit_mask > 0
+ && (val & implicit_mask) != implicit_mask)
+   return false;
 
-op = op1;
-  }
+  op = op1;
+}
 
   /* Check the rest.  */
   return s390_decompose_addrstyle_without_index (op, NULL, NULL);
diff --git a/gcc/testsuite/gcc.target/s390/pr118835.c 
b/gcc/testsuite/gcc.target/s390/pr118835.c
new file mode 100644
index ..1ca6cd95543b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/pr118835.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2" } */
+
+/* During combine we may end up with patterns of the form
+
+   (set (reg:DI 66 [ _6 ])
+(ashift:DI (reg:DI 72 [ x ])
+   (subreg:QI (and:TI (reg:TI 67 [ _1 ])
+  (const_wide_int 0x0aabf))
+  15)))
+
+   which should be rejected since the shift count does not trivially fit the
+   scheme of address operands.  */
+
+long
+test (long x, int y)
+{
+  __int128 z = 0xAABF;
+  z &= y;
+  return x << z;
+}