[gcc r13-9005] Arm: Fix incorrect tailcall-generation for indirect calls [PR113780]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:c56dc83e82af319d02a19f0703c301523ab1ef25

commit r13-9005-gc56dc83e82af319d02a19f0703c301523ab1ef25
Author: Tejas Belagod 
Date:   Thu Jan 25 16:05:36 2024 +0530

Arm: Fix incorrect tailcall-generation for indirect calls [PR113780]

This patch fixes a bug that causes indirect calls in PAC-enabled functions
to be tailcalled incorrectly when all argument registers R0-R3 are used.

2024-02-07  Tejas Belagod  

PR target/113780
* config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow 
tailcalls
for indirect calls with 4 or more arguments in pac-enabled 
functions.

* lib/target-supports.exp (v8_1m_main_pacbti): Add 
__ARM_FEATURE_PAUTH.
* gcc.target/arm/pac-sibcall.c: New.

(cherry picked from commit f436a2ab6ad15968275c9bbf3bd56647e5559e68)

Diff:
---
 gcc/config/arm/arm.cc  | 11 +++
 gcc/testsuite/gcc.target/arm/pac-sibcall.c | 14 ++
 gcc/testsuite/lib/target-supports.exp  |  2 ++
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index c00c6d7c1e6..bf1c6e36dfc 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -7947,10 +7947,13 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
   && DECL_WEAK (decl))
 return false;
 
-  /* We cannot do a tailcall for an indirect call by descriptor if all the
- argument registers are used because the only register left to load the
- address is IP and it will already contain the static chain.  */
-  if (!decl && CALL_EXPR_BY_DESCRIPTOR (exp) && !flag_trampolines)
+  /* We cannot tailcall an indirect call by descriptor if all the 
call-clobbered
+ general registers are live (r0-r3 and ip).  This can happen when:
+  - IP contains the static chain, or
+  - IP is needed for validating the PAC signature.  */
+  if (!decl
+  && ((CALL_EXPR_BY_DESCRIPTOR (exp) && !flag_trampolines)
+ || arm_current_function_pac_enabled_p()))
 {
   tree fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
   CUMULATIVE_ARGS cum;
diff --git a/gcc/testsuite/gcc.target/arm/pac-sibcall.c 
b/gcc/testsuite/gcc.target/arm/pac-sibcall.c
new file mode 100644
index 000..e15bd2f478d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pac-sibcall.c
@@ -0,0 +1,14 @@
+/* If all call-clobbered general registers are live (r0-r3, ip), disable
+   indirect tail-call for a PAC-enabled function.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "-mbranch-protection=pac-ret+leaf -O2" } */
+
+void fail(void (*f)(int, int, int, int))
+{
+  f(1, 2, 3, 4);
+}
+
+/* { dg-final { scan-assembler-not "bx\tip\t@ indirect register sibling call" 
} } */
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index c81313ea717..be97693e895 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5057,6 +5057,8 @@ foreach { armfunc armflag armdefs } {
__ARM_ARCH_8M_BASE__
v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
v8_1m_main "-march=armv8.1-m.main -mthumb" __ARM_ARCH_8M_MAIN__
+   v8_1m_main_pacbti "-march=armv8.1-m.main+pacbti+fp -mthumb"
+   "__ARM_ARCH_8M_MAIN__ && __ARM_FEATURE_BTI && 
__ARM_FEATURE_PAUTH"
v9a "-march=armv9-a" __ARM_ARCH_9A__ } {
 eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
proc check_effective_target_arm_arch_FUNC_ok { } {

[gcc r15-3588] arm: avoid indirect sibcalls when IP is live [PR116597]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:670cfd5fe6433ee8f2e86eedb197d2523dbb033b

commit r15-3588-g670cfd5fe6433ee8f2e86eedb197d2523dbb033b
Author: Richard Earnshaw 
Date:   Wed Aug 21 16:15:34 2024 +0100

arm: avoid indirect sibcalls when IP is live [PR116597]

On Arm only r0-r3 (the argument registers) and IP are available for
use as an address for an indirect sibcall.  But if all the argument
registers are used and IP is clobbered during the epilogue, or is used
to pass closure information, then there is no spare register to hold
the address and we must reject the sibcall.

arm_function_ok_for_sibcall did try to handle this, but it did this by
examining the function declaration.  That doesn't work if the function
has no prototype, or if the prototype has variadic arguments: we must,
instead, look at the list of actuals for the call rather than the list
of formals.

The old code also worked by laying out all the arguments and then
trying to add one more integer argument at the end of the list, but
this missed a corner case where a hole had been left in the argument
register list due to argument alignment.

We fix all of this by now scanning the list of actual values to be
passed and then checking if a core register has been assigned to that
argument.  If it has, then we record which registers were assigned.
Once done we then look to see if all the argument registers have been
assigned and only block the sibcall if that is the case.  This permits
us to sibcall:

int (*d)(int, ...);
int g(void);
int i () { return d(g(), 2LL);}

because r1 remains free (the 2LL argument is passed in {r2,r3}).

gcc/
PR target/116597
* config/arm/arm.cc (arm_function_ok_for_sibcall): Use the list of
actuals for the call, not the list of formals.

gcc/testsuite/
PR target/116597
* gcc.target/arm/pac-sibcall-2.c: New test.
* gcc.target/arm/pac-sibcall-3.c: New test.

Diff:
---
 gcc/config/arm/arm.cc| 38 
 gcc/testsuite/gcc.target/arm/pac-sibcall-2.c | 14 ++
 gcc/testsuite/gcc.target/arm/pac-sibcall-3.c | 14 ++
 3 files changed, 55 insertions(+), 11 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 17485447693b..de34e9867e67 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -8007,10 +8007,11 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
   && DECL_WEAK (decl))
 return false;
 
-  /* We cannot tailcall an indirect call by descriptor if all the 
call-clobbered
- general registers are live (r0-r3 and ip).  This can happen when:
-  - IP contains the static chain, or
-  - IP is needed for validating the PAC signature.  */
+  /* Indirect tailcalls need a call-clobbered register to hold the function
+ address.  But we only have r0-r3 and ip in that class.  If r0-r3 all hold
+ function arguments, then we can only use IP.  But IP may be needed in the
+ epilogue (for PAC validation), or for passing the static chain.  We have
+ to disable the tail call if nothing is available.  */
   if (!decl
   && ((CALL_EXPR_BY_DESCRIPTOR (exp) && !flag_trampolines)
  || arm_current_function_pac_enabled_p()))
@@ -8022,18 +8023,33 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
   arm_init_cumulative_args (&cum, fntype, NULL_RTX, NULL_TREE);
   cum_v = pack_cumulative_args (&cum);
 
-  for (tree t = TYPE_ARG_TYPES (fntype); t; t = TREE_CHAIN (t))
+  tree arg;
+  call_expr_arg_iterator iter;
+  unsigned used_regs = 0;
+
+  /* Layout each actual argument in turn.  If it is allocated to
+core regs, note which regs have been allocated.  */
+  FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
{
- tree type = TREE_VALUE (t);
- if (!VOID_TYPE_P (type))
+ tree type = TREE_TYPE (arg);
+ function_arg_info arg_info (type, /*named=*/true);
+ rtx reg = arm_function_arg (cum_v, arg_info);
+ if (reg && REG_P (reg)
+ && REGNO (reg) <= LAST_ARG_REGNUM)
{
- function_arg_info arg (type, /*named=*/true);
- arm_function_arg_advance (cum_v, arg);
+ /* Avoid any chance of UB here.  We don't care if TYPE
+is very large since it will use up all the argument regs.  */
+ unsigned nregs = MIN (ARM_NUM_REGS2 (GET_MODE (reg), type),
+   LAST_ARG_REGNUM + 1);
+ used_regs |= ((1 << nregs) - 1) << REGNO (reg);
}
+ arm_function_arg_advance (cum_v, arg_info);
}
 
-  function_arg_info arg (integer_type_node, /*named=*/true);
-  if (!arm_function_arg (cum_v, arg))
+  /* We've used all the argument regs, and we know IP is live during the
+epilogue for some re

[gcc r15-3607] arm: testsuite: make use of -mcpu=unset/-march=unset

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:9a94c8ffdc8b554a2d95e0101e96830efee58add

commit r15-3607-g9a94c8ffdc8b554a2d95e0101e96830efee58add
Author: Richard Earnshaw 
Date:   Thu Sep 12 14:24:55 2024 +0100

arm: testsuite: make use of -mcpu=unset/-march=unset

This patch makes use of the new ability to unset the CPU or
architecture flags on the command line to enable several more tests on
Arm.  It doesn't cover every case and it does enable some tests that
now fail for different reasons when the tests are no-longer skipped;
these were failing anyway for other testsuite configurations, so it's
still an overall improvement.

There's some restructuring required to fully implement this change: we
could previously treat Xscale as an architecture, even though the
option set -mcpu=, we now need to handle this correctly so that we
unset the architecture rather than the CPU.  To do this I've added a
new table for these variants and renamed the template functions to use
'cpu' rather than 'arch'.  This entailed updating the two XScale
related tests accordingly.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Move xscale to new generator table.
(check_effective_target_arm_arch_FUNC_ok): Add -mcpu=unset to the
list of flags.
(add_options_for_arm_arch_FUNC): Likewise.
(check_effective_target_arm_cpu_FUNC_ok): New function.
(add_options_for_arm_cpu_FUNC): Likewise.
(check_effective_target_arm_cpu_FUNC_link): Likewise.
(check_effective_target_arm_cpu_FUNC_multilib): Likewise.
* gcc.target/arm/g2.c: Update dg directives.
* gcc.target/arm/scd42-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/arm/g2.c  |  4 +--
 gcc/testsuite/gcc.target/arm/scd42-2.c |  4 +--
 gcc/testsuite/lib/target-supports.exp  | 59 --
 3 files changed, 60 insertions(+), 7 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/g2.c 
b/gcc/testsuite/gcc.target/arm/g2.c
index 04334c97713b..7e43a907a4c5 100644
--- a/gcc/testsuite/gcc.target/arm/g2.c
+++ b/gcc/testsuite/gcc.target/arm/g2.c
@@ -1,8 +1,8 @@
 /* Verify that hardware multiply is preferred on XScale. */
 /* { dg-do compile } */
 /* { dg-options "-O2" } */
-/* { dg-require-effective-target arm_arch_xscale_arm_ok } */
-/* { dg-add-options arm_arch_xscale_arm } */
+/* { dg-require-effective-target arm_cpu_xscale_arm_ok } */
+/* { dg-add-options arm_cpu_xscale_arm } */
 
 
 /* Brett Gaines' test case. */
diff --git a/gcc/testsuite/gcc.target/arm/scd42-2.c 
b/gcc/testsuite/gcc.target/arm/scd42-2.c
index cd416885a804..a263c1fbff92 100644
--- a/gcc/testsuite/gcc.target/arm/scd42-2.c
+++ b/gcc/testsuite/gcc.target/arm/scd42-2.c
@@ -1,8 +1,8 @@
 /* Verify that mov is preferred on XScale for loading a 2 byte constant. */
 /* { dg-do compile } */
-/* { dg-require-effective-target arm_arch_xscale_arm_ok } */
+/* { dg-require-effective-target arm_cpu_xscale_arm_ok } */
 /* { dg-options "-O" } */
-/* { dg-add-options arm_arch_xscale_arm } */
+/* { dg-add-options arm_cpu_xscale_arm } */
 
 unsigned load2(void) __attribute__ ((naked));
 unsigned load2(void)
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index cb9971d53980..c4d2c33cf628 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5679,6 +5679,9 @@ proc check_effective_target_arm_fp16_hw { } {
 # Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
 #/* { dg-add-options arm_arch_v5t } */
 #   /* { dg-require-effective-target arm_arch_v5t_multilib } */
+
+# This table should only be used to set -march= (and associated
+# flags).  See below for setting -mcpu
 foreach { armfunc armflag armdefs } {
v4 "-march=armv4 -marm" __ARM_ARCH_4__
v4t "-march=armv4t -mfloat-abi=softfp" __ARM_ARCH_4T__
@@ -5690,7 +5693,6 @@ foreach { armfunc armflag armdefs } {
v5te "-march=armv5te+fp -mfloat-abi=softfp" __ARM_ARCH_5TE__
v5te_arm "-march=armv5te+fp -marm" "__ARM_ARCH_5TE__ && !__thumb__"
v5te_thumb "-march=armv5te+fp -mthumb -mfloat-abi=softfp" 
"__ARM_ARCH_5TE__ && __thumb__"
-   xscale_arm "-mcpu=xscale -mfloat-abi=soft -marm" "__XSCALE__ && 
!__thumb__"
v6 "-march=armv6+fp -mfloat-abi=softfp" __ARM_ARCH_6__
v6_arm "-march=armv6+fp -marm" "__ARM_ARCH_6__ && !__thumb__"
v6_thumb "-march=armv6+fp -mthumb -mfloat-abi=softfp" "__ARM_ARCH_6__ 
&& __thumb__"
@@ -5735,11 +5737,11 @@ foreach { armfunc armflag armdefs } {
{
return 0;
}
-   } "FLAG" ]
+   } "-mcpu=unset FLAG" ]
}
 
proc add_options_for_arm_arch_FUNC { flags } {
-   return "$flags FLAG"
+   return "$flags -mcpu=unset FLAG"
}
 
proc check_effective_target_arm_arch_FUNC_link { } {
@@ -5762,6 +5764,57 @@ for

[gcc r15-3606] arm: Allow -mcpu and -march options to be unset

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:7d6c6a0d15c136a68d066c60da0f48265a2b1886

commit r15-3606-g7d6c6a0d15c136a68d066c60da0f48265a2b1886
Author: Richard Earnshaw 
Date:   Wed Sep 11 17:06:12 2024 +0100

arm: Allow -mcpu and -march options to be unset

The compiler will warn if the architectural specification derived from
a -mcpu option is not the same as that specified by -march.  This is
because it was never intended that the two should be used at the same
time: -mcpu= is supposed to be shorthand for -mtune=
-march=arch-of().

Unfortunately, there are times when the two options passed to the
compiler may come from distinct sources: one example is makefiles
which accumulate options; another is the testsuite itself, when some
tests require a particular architecture setting to be useful - only
running the tests when the compiler/testsuite configuration exactly
matched the requirements would make regression testing especially hard
(we have too many permutations).

So this patch allows a user to cancel any earlier setting of a
particular flag and to make the compiler behave as though it was never
passed.  The intended usecase is (sources of options are shown in
parenthesis, but that's just for grouping:

 (-march=armv7-a+simd) (-march=unset -mcpu=cortex-m33)

The option processing logic will now simplify this to:

 -mcpu=cortex-m33

A useful corollary of this is that

 -march=armv7-a -march=unset

will now cause the compiler to behave as though neither the
architecture nor the CPU was ever set and to default back to the
configure-time settings.

gcc/ChangeLog:

* config/arm/arm.h (OPTION_DEFAULT_SPECS): Allow -mcpu and -march
to be unset.
(ARCH_CPU_CLEANUP_SPECS): Likewise
(DRIVER_SELF_SPECS): Add ARCH_CPU_CLEANUP_SPECS
* doc/invoke.texi (arm: -mcpu= and -march=): Document use of 
'unset'.

Diff:
---
 gcc/config/arm/arm.h | 14 +++---
 gcc/doc/invoke.texi  | 12 
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 0cd5d733952d..b092ba6ffe01 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -394,9 +394,11 @@ emission of floating point pcs attributes.  */
TARGET_MODE_CHECK that also takes into account the selected CPU and
architecture.  */
 #define OPTION_DEFAULT_SPECS \
-  {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
-  {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
-  {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
+  {"arch", "%{!march=*|march=unset:"\
+  "%{!mcpu=*|mcpu=unset:%

[gcc r15-1840] arm: Use LDMIA/STMIA for thumb1 DI/DF loads/stores

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:236d6fef2479654b3011f8208e1bd7f078700109

commit r15-1840-g236d6fef2479654b3011f8208e1bd7f078700109
Author: Siarhei Volkau 
Date:   Thu Jun 20 10:24:31 2024 +0300

arm: Use LDMIA/STMIA for thumb1 DI/DF loads/stores

If the address register is dead after load/store operation it looks
beneficial to use LDMIA/STMIA instead of pair of LDR/STR instructions,
at least if optimizing for size.

gcc/ChangeLog:

* config/arm/arm.cc (thumb_load_double_from_address): Emit ldmia
when address reg rewritten by load.
* config/arm/thumb1.md (peephole2 to rewrite DI/DF load): New.
(peephole2 to rewrite DI/DF store): New.
* config/arm/iterators.md (DIDF): New.

gcc/testsuite:

* gcc.target/arm/thumb1-load-store-64bit.c: Add new test.

Signed-off-by: Siarhei Volkau 

Diff:
---
 gcc/config/arm/arm.cc  | 10 ++
 gcc/config/arm/iterators.md|  3 ++
 gcc/config/arm/thumb1.md   | 37 +-
 .../gcc.target/arm/thumb1-load-store-64bit.c   | 16 ++
 4 files changed, 58 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 6dab65f493b..bb9c7c3b5c4 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -28374,15 +28374,11 @@ thumb_load_double_from_address (rtx *operands)
   switch (GET_CODE (addr))
 {
 case REG:
-  operands[2] = adjust_address (operands[1], SImode, 4);
-
-  if (REGNO (operands[0]) == REGNO (addr))
-   {
- output_asm_insn ("ldr\t%H0, %2", operands);
- output_asm_insn ("ldr\t%0, %1", operands);
-   }
+  if (reg_overlap_mentioned_p (addr, operands[0]))
+   output_asm_insn ("ldmia\t%m1, {%0, %H0}", operands);
   else
{
+ operands[2] = adjust_address (operands[1], SImode, 4);
  output_asm_insn ("ldr\t%0, %1", operands);
  output_asm_insn ("ldr\t%H0, %2", operands);
}
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 987602da1bf..b9ff01cb104 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -50,6 +50,9 @@
 ;; A list of the 32bit and 64bit integer modes
 (define_mode_iterator SIDI [SI DI])
 
+;; A list of the 64bit modes for thumb1.
+(define_mode_iterator DIDF [DI DF])
+
 ;; A list of atomic compare and swap success return modes
 (define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")])
 
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index d7074b43f60..b4d7c6ea981 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -655,6 +655,42 @@
(set_attr "pool_range" "*,*,*,*,*,*,1018,*,*")]
 )
 
+
+;; match patterns usable by ldmia/stmia
+(define_peephole2
+  [(set (match_operand:DIDF 0 "low_register_operand" "")
+   (match_operand:DIDF 1 "memory_operand" ""))]
+  "TARGET_THUMB1
+   && low_register_operand (XEXP (operands[1], 0), SImode)
+   && !reg_overlap_mentioned_p (XEXP (operands[1], 0), operands[0])
+   && peep2_reg_dead_p (1, XEXP (operands[1], 0))"
+  [(set (match_dup 0)
+   (match_dup 1))]
+  {
+operands[1] = change_address (operands[1], VOIDmode,
+ gen_rtx_POST_INC (SImode,
+   XEXP (operands[1], 0)));
+  }
+)
+
+(define_peephole2
+  [(set (match_operand:DIDF 0 "memory_operand" "")
+   (match_operand:DIDF 1 "low_register_operand" ""))]
+  "TARGET_THUMB1
+   && low_register_operand (XEXP (operands[0], 0), SImode)
+   && peep2_reg_dead_p (1, XEXP (operands[0], 0))
+   /* The low register in the transfer list may overlap the address,
+  but the second cannot.  */
+   && REGNO (XEXP (operands[0], 0)) != (REGNO (operands[1]) + 1)"
+  [(set (match_dup 0)
+   (match_dup 1))]
+  {
+operands[0] = change_address (operands[0], VOIDmode,
+ gen_rtx_POST_INC (SImode,
+   XEXP (operands[0], 0)));
+  }
+)
+
 (define_insn "*thumb1_movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,r,l,l,l,>,l, l, 
m,*l*h*k")
(match_operand:SI 1 "general_operand"  "l, I,j,J,K,>,l,i, 
mi,l,*l*h*k"))]
@@ -2055,4 +2091,3 @@
(set_attr "conds" "clob")
(set_attr "type" "multiple")]
 )
-
diff --git a/gcc/testsuite/gcc.target/arm/thumb1-load-store-64bit.c 
b/gcc/testsuite/gcc.target/arm/thumb1-load-store-64bit.c
new file mode 100644
index 000..167fa9ec876
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb1-load-store-64bit.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+void copy_df(double *dst, const double *src)
+{
+*dst = *src;
+}
+
+void copy_di(unsigned long long *dst, const unsigned long long *src)
+{
+*dst = *src;
+}
+
+/* { dg-final

[gcc r15-1912] arm: clean up some legacy FPA related cruft.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:959c168e77f2e1a02b086536c69c99f7413e08bf

commit r15-1912-g959c168e77f2e1a02b086536c69c99f7413e08bf
Author: Richard Earnshaw 
Date:   Mon Jul 8 23:14:03 2024 +0100

arm: clean up some legacy FPA related cruft.

Support for the FPA on Arm was removed after gcc-4.7, but this little
bit of crufty code was left behind.  In particular the code to support
the 'N' modifier in assembly code was left behind and this lead to a
trail of other code that depended on it, even though most of the
constants that it supported had been removed in the original cleanup.

This patch removes most of the remaining cruft and simplifies the one
bit that remains: to determine whether an RTL construct contains 0.0 we
don't need to convert it to a real value, we can simply compare it to
CONST0_RTX of the appropriate mode.

gcc/

* config/arm/arm.cc (fp_consts_initited): Delete variable.
(value_fp0): Likewise.
(init_fp_table): Delete function.
(fp_const_from_val): Likewise.
(arm_const_double_rtx): Rework to avoid converting to 
REAL_VALUE_TYPE.
(arm_print_operand, case 'N'): Make use of this case an error.

Diff:
---
 gcc/config/arm/arm.cc | 61 +--
 1 file changed, 10 insertions(+), 51 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 459b7e648aba..93993d95eb96 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -117,7 +117,6 @@ static bool arm_assemble_integer (rtx, unsigned int, int);
 static void arm_print_operand (FILE *, rtx, int);
 static void arm_print_operand_address (FILE *, machine_mode, rtx);
 static bool arm_print_operand_punct_valid_p (unsigned char code);
-static const char *fp_const_from_val (REAL_VALUE_TYPE *);
 static arm_cc get_arm_condition_code (rtx);
 static bool arm_fixed_condition_code_regs (unsigned int *, unsigned int *);
 static const char *output_multi_immediate (rtx *, const char *, const char *,
@@ -12822,37 +12821,12 @@ arm_cortex_m7_branch_cost (bool speed_p, bool 
predictable_p)
   return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p);
 }
 
-static bool fp_consts_inited = false;
-
-static REAL_VALUE_TYPE value_fp0;
-
-static void
-init_fp_table (void)
-{
-  REAL_VALUE_TYPE r;
-
-  r = REAL_VALUE_ATOF ("0", DFmode);
-  value_fp0 = r;
-  fp_consts_inited = true;
-}
-
 /* Return TRUE if rtx X is a valid immediate FP constant.  */
 int
 arm_const_double_rtx (rtx x)
 {
-  const REAL_VALUE_TYPE *r;
-
-  if (!fp_consts_inited)
-init_fp_table ();
-
-  r = CONST_DOUBLE_REAL_VALUE (x);
-  if (REAL_VALUE_MINUS_ZERO (*r))
-return 0;
-
-  if (real_equal (r, &value_fp0))
-return 1;
-
-  return 0;
+  return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT
+ && x == CONST0_RTX (GET_MODE (x)));
 }
 
 /* VFPv3 has a fairly wide range of representable immediates, formed from
@@ -19793,17 +19767,6 @@ arm_reorg (void)
 
 /* Routines to output assembly language.  */
 
-/* Return string representation of passed in real value.  */
-static const char *
-fp_const_from_val (REAL_VALUE_TYPE *r)
-{
-  if (!fp_consts_inited)
-init_fp_table ();
-
-  gcc_assert (real_equal (r, &value_fp0));
-  return "0";
-}
-
 /* OPERANDS[0] is the entire list of insns that constitute pop,
OPERANDS[1] is the base register, RETURN_PC is true iff return insn
is in the list, UPDATE is true iff the list contains explicit
@@ -24160,8 +24123,8 @@ arm_print_condition (FILE *stream)
 /* Globally reserved letters: acln
Puncutation letters currently used: @_|?().!#
Lower case letters currently used: bcdefhimpqtvwxyz
-   Upper case letters currently used: ABCDEFGHIJKLMNOPQRSTUV
-   Letters previously used, but now deprecated/obsolete: sWXYZ.
+   Upper case letters currently used: ABCDEFGHIJKLMOPQRSTUV
+   Letters previously used, but now deprecated/obsolete: sNWXYZ.
 
Note that the global reservation for 'c' is only for CONSTANT_ADDRESS_P.
 
@@ -24174,8 +24137,6 @@ arm_print_condition (FILE *stream)
in these cases the instruction pattern will take care to make sure that
an instruction containing %d will follow, thereby undoing the effects of
doing this instruction unconditionally.
-   If CODE is 'N' then X is a floating point operand that must be negated
-   before output.
If CODE is 'B' then output a bitwise inverted value of X (a const int).
If X is a REG and CODE is `M', output a ldm/stm style multi-reg.
If CODE is 'V', then the operand must be a CONST_INT representing
@@ -24226,14 +24187,6 @@ arm_print_operand (FILE *stream, rtx x, int code)
 case '#':
   return;
 
-case 'N':
-  {
-   REAL_VALUE_TYPE r;
-   r = real_value_negate (CONST_DOUBLE_REAL_VALUE (x));
-   fprintf (stream, "%s", fp_const_from_val (&r));
-  }
-  return;
-
 /* An integer or symbol address without a preceding # sign.  */
 ca

[gcc r15-1938] arm: cleanup legacy ARM_PE code

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:73f5a3aa3e2f468d2c1a0f6884fe433a4f30

commit r15-1938-g73f5a3aa3e2f468d2c1a0f6884fe433a4f30
Author: Richard Earnshaw 
Date:   Tue Jul 9 22:31:32 2024 +0100

arm: cleanup legacy ARM_PE code

The arm 'pe' target was removed back in 2012 when the FPA support was
removed, but in a small number of places some conditional code was
accidentally left behind.  It's no-longer needed, so remove it.

gcc/ChangeLog:

* config/arm/arm-protos.h (arm_dllexport_name_p): Remove prototype.
(arm_dllimport_name_p): Likewise.
(arm_pe_unique_section): Likewise.
(arm_pe_encode_section_info): Likewise.
(arm_dllexport_p): Likewise.
(arm_dllimport_p): Likewise.
(arm_mark_dllexport): Likewise.
(arm_mark_dllimport): Likewise.
(arm_change_mode_p): Likewise.
* config/arm/arm.cc (arm_gnu_attributes): Remove attributes for 
ARM_PE.
(TARGET_ENCODE_SECTION_INFO): Remove setting for ARM_PE.
(is_called_in_ARM_mode): Remove ARM_PE conditional code.
(thumb1_output_interwork): Remove obsolete ARM_PE code.
(arm_encode_section_info): Remove surrounding #ifndef.

Diff:
---
 gcc/config/arm/arm-protos.h | 12 
 gcc/config/arm/arm.cc   | 32 +---
 2 files changed, 1 insertion(+), 43 deletions(-)

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 34d6be76e94a..50cae2b513a2 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -266,19 +266,7 @@ extern const char *thumb1_output_casesi (rtx *);
 extern const char *thumb2_output_casesi (rtx *);
 #endif
 
-/* Defined in pe.c.  */
-extern int arm_dllexport_name_p (const char *);
-extern int arm_dllimport_name_p (const char *);
-
-#ifdef TREE_CODE
-extern void arm_pe_unique_section (tree, int);
-extern void arm_pe_encode_section_info (tree, rtx, int);
-extern int arm_dllexport_p (tree);
-extern int arm_dllimport_p (tree);
-extern void arm_mark_dllexport (tree);
-extern void arm_mark_dllimport (tree);
 extern bool arm_change_mode_p (tree);
-#endif
 
 extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
 struct gcc_options *);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 93993d95eb96..92cd168e6593 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -208,9 +208,7 @@ static int aapcs_select_return_coproc (const_tree, 
const_tree);
 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
 static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
 #endif
-#ifndef ARM_PE
 static void arm_encode_section_info (tree, rtx, int);
-#endif
 
 static void arm_file_end (void);
 static void arm_file_start (void);
@@ -352,21 +350,7 @@ static const attribute_spec arm_gnu_attributes[] =
 NULL },
   { "naked",0, 0, true,  false, false, false,
 arm_handle_fndecl_attribute, NULL },
-#ifdef ARM_PE
-  /* ARM/PE has three new attributes:
- interfacearm - ?
- dllexport - for exporting a function/variable that will live in a dll
- dllimport - for importing a function/variable from a dll
-
- Microsoft allows multiple declspecs in one __declspec, separating
- them with spaces.  We do NOT support this.  Instead, use __declspec
- multiple times.
-  */
-  { "dllimport",0, 0, true,  false, false, false, NULL, NULL },
-  { "dllexport",0, 0, true,  false, false, false, NULL, NULL },
-  { "interfacearm", 0, 0, true,  false, false, false,
-arm_handle_fndecl_attribute, NULL },
-#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
+#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
   { "dllimport",0, 0, false, false, false, false, handle_dll_attribute,
 NULL },
   { "dllexport",0, 0, false, false, false, false, handle_dll_attribute,
@@ -488,11 +472,7 @@ static const scoped_attribute_specs *const 
arm_attribute_table[] =
 #define TARGET_MEMORY_MOVE_COST arm_memory_move_cost
 
 #undef TARGET_ENCODE_SECTION_INFO
-#ifdef ARM_PE
-#define TARGET_ENCODE_SECTION_INFO  arm_pe_encode_section_info
-#else
 #define TARGET_ENCODE_SECTION_INFO  arm_encode_section_info
-#endif
 
 #undef  TARGET_STRIP_NAME_ENCODING
 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
@@ -26821,11 +26801,7 @@ is_called_in_ARM_mode (tree func)
   if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
 return true;
 
-#ifdef ARM_PE
-  return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != 
NULL_TREE;
-#else
   return false;
-#endif
 }
 
 /* Given the stack offsets and register mask in OFFSETS, decide how
@@ -28301,10 +28277,6 @@ thumb1_output_interwork (void)
 #define STUB_NAME ".real_start_of"
 
   fprintf (f, "\t.code\t16\n");
-#ifdef ARM_PE
-  if (arm_dllexport_name_p (name))
-name = arm_strip_name_encoding (name);
-#endif
   asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
   fprintf 

[gcc r14-9399] arm: testsuite: tweak bics_3.c [PR113542]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:ac829a89fb56cfd914d5e29ed4695e499b0dbc95

commit r14-9399-gac829a89fb56cfd914d5e29ed4695e499b0dbc95
Author: Richard Earnshaw 
Date:   Fri Mar 8 16:23:53 2024 +

arm: testsuite: tweak bics_3.c [PR113542]

This test was too simple, which meant that the compiler was sometimes
able to find a better optimization of the code than using a BICS
instruction.  Fix this by changing the test slightly to produce a
sequence where BICS should always be the preferred solution.

gcc/testsuite:
PR target/113542
* gcc.target/arm/bics_3.c: Adjust code to something which should
always result in BICS.

Diff:
---
 gcc/testsuite/gcc.target/arm/bics_3.c | 19 ---
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/bics_3.c 
b/gcc/testsuite/gcc.target/arm/bics_3.c
index e056b264e15..4d6938948a1 100644
--- a/gcc/testsuite/gcc.target/arm/bics_3.c
+++ b/gcc/testsuite/gcc.target/arm/bics_3.c
@@ -2,13 +2,11 @@
 /* { dg-options "-O2 --save-temps -fno-inline" } */
 /* { dg-require-effective-target arm32 } */
 
-extern void abort (void);
-
 int
 bics_si_test (int a, int b)
 {
-  if (a & ~b)
-return 1;
+  if ((a & ~b) >= 0)
+return 3;
   else
 return 0;
 }
@@ -16,8 +14,8 @@ bics_si_test (int a, int b)
 int
 bics_si_test2 (int a, int b)
 {
-  if (a & ~ (b << 2))
-return 1;
+  if ((a & ~ (b << 2)) >= 0)
+return 3;
   else
 return 0;
 }
@@ -28,13 +26,12 @@ main (void)
   int a = 5;
   int b = 5;
   int c = 20;
-  if (bics_si_test (a, b))
-abort ();
-  if (bics_si_test2 (c, b))
-abort ();
+  if (bics_si_test (a, b) != 3)
+__builtin_abort ();
+  if (bics_si_test2 (c, b) != 3)
+__builtin_abort ();
   return 0;
 }
 
 /* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 
} } */
 /* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, 
.sl #2" 1 } } */
-

[gcc r14-9430] gomp: testsuite: improve compatibility of bad-array-section-3.c [PR113428]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:c27b30552e6cc789425d3628d294dafc5f3a0861

commit r14-9430-gc27b30552e6cc789425d3628d294dafc5f3a0861
Author: Richard Earnshaw 
Date:   Wed Mar 6 13:41:02 2024 +

gomp: testsuite: improve compatibility of bad-array-section-3.c [PR113428]

This test generates different warnings on ilp32 targets because the size
of an integer matches the size of a pointer.  Avoid this by using
signed char.

gcc/testsuite:

PR testsuite/113428
* gcc.dg/gomp/bad-array-section-c-3.c: Use signed char instead
of int.

Diff:
---
 gcc/testsuite/gcc.dg/gomp/bad-array-section-c-3.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/gomp/bad-array-section-c-3.c 
b/gcc/testsuite/gcc.dg/gomp/bad-array-section-c-3.c
index 8be15ced8c0..431af71c422 100644
--- a/gcc/testsuite/gcc.dg/gomp/bad-array-section-c-3.c
+++ b/gcc/testsuite/gcc.dg/gomp/bad-array-section-c-3.c
@@ -1,15 +1,15 @@
 /* { dg-do compile } */
 
 struct S {
-  int *ptr;
+  signed char *ptr;
 };
 
 int main()
 {
-  int arr[20];
+  signed char arr[20];
 
   /* Reject array section in compound initialiser.  */
-#pragma omp target map( (struct S) { .ptr = (int *) arr[5:5] } )
+#pragma omp target map( (struct S) { .ptr = (signed char *) arr[5:5] } )
 /* { dg-error {expected '\]' before ':' token} "" { target *-*-* } .-1 } */
 /* { dg-warning {cast to pointer from integer of different size} "" { target 
*-*-* } .-2 } */
 /* { dg-message {sorry, unimplemented: unsupported map expression} "" { target 
*-*-* } .-3 } */

[gcc r14-9521] testsuite: Turn errors back into warnings in arm/acle/cde-mve-error-2.c

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:9316d021ebb95062f5e3ed9d67734863279671fe

commit r14-9521-g9316d021ebb95062f5e3ed9d67734863279671fe
Author: Thiago Jung Bauermann 
Date:   Fri Mar 15 12:13:29 2024 -0300

testsuite: Turn errors back into warnings in arm/acle/cde-mve-error-2.c

Since commit 2c3db94d9fd ("c: Turn int-conversion warnings into
permerrors") the test fails with errors such as:

  FAIL: gcc.target/arm/acle/cde-mve-error-2.c   -O0   (test for errors, 
line 32)
  FAIL: gcc.target/arm/acle/cde-mve-error-2.c   -O0   (test for errors, 
line 33)
  FAIL: gcc.target/arm/acle/cde-mve-error-2.c   -O0   (test for errors, 
line 34)
  FAIL: gcc.target/arm/acle/cde-mve-error-2.c   -O0   (test for errors, 
line 35)
⋮
  FAIL: gcc.target/arm/acle/cde-mve-error-2.c   -O0  (test for excess 
errors)

There's a total of 1016 errors.  Here's a sample of the excess errors:

  Excess errors:
  /path/gcc.git/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c:117:31: 
error: passing argument 2 of '__builtin_arm_vcx1qv16qi' makes integer from 
pointer without a cast [-Wint-conversion]
  /path/gcc.git/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c:119:3: 
error: passing argument 3 of '__builtin_arm_vcx1qav16qi' makes integer from 
pointer without a cast [-Wint-conversion]
  /path/gcc.git/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c:121:3: 
error: passing argument 3 of '__builtin_arm_vcx2qv16qi' makes integer from 
pointer without a cast [-Wint-conversion]
  /path/gcc.git/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c:123:3: 
error: passing argument 3 of '__builtin_arm_vcx2qv16qi' makes integer from 
pointer without a cast [-Wint-conversion]

The test expects these messages to be warnings, not errors.  My first
try was to change it to expect them as errors instead.  This didn't
work, IIUC because the error prevents the compiler from continuing
processing the file and thus other errors which are expected by the
test don't get emitted.

Therefore, add -fpermissive so that the test behaves as it did
previously.  Because of the additional line in the header, the line
numbers of the expected warnings don't match anymore so replace them
with ".-1" as suggested by Richard Earnshaw.

Tested on armv8l-linux-gnueabihf.

gcc/testsuite/ChangeLog:
* gcc.target/arm/acle/cde-mve-error-2.c: Add -fpermissive.  Use
relative offsets for line numbers.

Diff:
---
 .../gcc.target/arm/acle/cde-mve-error-2.c  | 63 +++---
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c 
b/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c
index 5b777482544..0f605083c5c 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cde-mve-error-2.c
@@ -2,6 +2,7 @@
 
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_v8_1m_main_cde_mve_fp_ok } */
+/* { dg-options "-fpermissive" } */
 /* { dg-add-options arm_v8_1m_main_cde_mve_fp } */
 
 /* The error checking files are split since there are three kinds of
@@ -115,73 +116,73 @@ uint8x16_t test_bad_immediates (uint8x16_t n, uint8x16_t 
m, int someval,
 
   /* `imm' is of wrong type.  */
   accum += __arm_vcx1q_u8 (0, "");/* { dg-error {argument 
2 to '__builtin_arm_vcx1qv16qi' must be a constant immediate in range 
\[0-4095\]} } */
-  /* { dg-warning {passing argument 2 of '__builtin_arm_vcx1qv16qi' makes 
integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 
117 } */
+  /* { dg-warning {passing argument 2 of '__builtin_arm_vcx1qv16qi' makes 
integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 
.-1 } */
   accum += __arm_vcx1qa (0, accum, "");   /* { dg-error {argument 
3 to '__builtin_arm_vcx1qav16qi' must be a constant immediate in range 
\[0-4095\]} } */
-  /* { dg-warning {passing argument 3 of '__builtin_arm_vcx1qav16qi' makes 
integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 
119 } */
+  /* { dg-warning {passing argument 3 of '__builtin_arm_vcx1qav16qi' makes 
integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 
.-1 } */
   accum += __arm_vcx2q (0, n, "");/* { dg-error {argument 
3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range 
\[0-127\]} } */
-  /* { dg-warning {passing argument 3 of '__builtin_arm_vcx2qv16qi' makes 
integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 
121 } */
+  /* { dg-warning {passing argument 3 of '__builtin_arm_vcx2qv16qi' makes 
integer from pointer without a cast \[-Wint-conversion\]} "" { target *-*-* } 
.-1 } */
   accum += __arm_vcx2q_u8 (0, n, "x");/* { dg-error {argument 
3 to '__builtin_arm_vcx2qv16qi' must be a constant immediate in range 
\[0-127\]} 

[gcc r14-9572] aarch64: Sync aarch64-sys-regs.def with Binutils

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:47cdd86cd5d3d3fd26f9764020c4502ea8eca27b

commit r14-9572-g47cdd86cd5d3d3fd26f9764020c4502ea8eca27b
Author: Yury Khrustalev 
Date:   Wed Mar 20 11:21:04 2024 +

aarch64: Sync aarch64-sys-regs.def with Binutils

This patch updates `aarch64-sys-regs.def', bringing it into sync with
the Binutils source.

gcc/ChangeLog:

* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.

Diff:
---
 gcc/config/aarch64/aarch64-sys-regs.def | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/config/aarch64/aarch64-sys-regs.def 
b/gcc/config/aarch64/aarch64-sys-regs.def
index 6a948171d6e..8b65673a5d6 100644
--- a/gcc/config/aarch64/aarch64-sys-regs.def
+++ b/gcc/config/aarch64/aarch64-sys-regs.def
@@ -521,6 +521,7 @@
   SYSREG ("id_aa64isar0_el1",  CPENC (3,0,0,6,0),  F_REG_READ, 
AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar1_el1",  CPENC (3,0,0,6,1),  F_REG_READ, 
AARCH64_NO_FEATURES)
   SYSREG ("id_aa64isar2_el1",  CPENC (3,0,0,6,2),  F_REG_READ, 
AARCH64_NO_FEATURES)
+  SYSREG ("id_aa64isar3_el1",  CPENC (3,0,0,6,3),  F_REG_READ, 
AARCH64_NO_FEATURES)
   SYSREG ("id_aa64mmfr0_el1",  CPENC (3,0,0,7,0),  F_REG_READ, 
AARCH64_NO_FEATURES)
   SYSREG ("id_aa64mmfr1_el1",  CPENC (3,0,0,7,1),  F_REG_READ, 
AARCH64_NO_FEATURES)
   SYSREG ("id_aa64mmfr2_el1",  CPENC (3,0,0,7,2),  F_REG_READ, 
AARCH64_NO_FEATURES)

[gcc r15-3930] aarch64: fix build failure on aarch64-none-elf

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:0ff49a5c1d39382c57d614a29510559068947376

commit r15-3930-g0ff49a5c1d39382c57d614a29510559068947376
Author: Matthieu Longo 
Date:   Thu Sep 26 18:14:23 2024 +0100

aarch64: fix build failure on aarch64-none-elf

A previous patch ([1]) introduced a build regression on aarch64-none-elf
target. The changes were primarilly tested on aarch64-unknown-linux-gnu,
so the issue was missed during development.
The includes are slighly different between the two targets, and due to some
include rules ([2]), "aarch64-unwind-def.h" was not found.

[1]: 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=bdf41d627c13bc5f0dc676991f4513daa9d9ae36

[2]: https://gcc.gnu.org/onlinedocs/cpp/Include-Syntax.html
> include "file"
> ...  It searches for a file named file first in the directory
> containing the current file, ...

libgcc/ChangeLog:

* config/aarch64/aarch64-unwind.h: Fix header path.

Diff:
---
 libgcc/config/aarch64/aarch64-unwind.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libgcc/config/aarch64/aarch64-unwind.h 
b/libgcc/config/aarch64/aarch64-unwind.h
index 2b774eb263cf..4d36f0b26f70 100644
--- a/libgcc/config/aarch64/aarch64-unwind.h
+++ b/libgcc/config/aarch64/aarch64-unwind.h
@@ -25,7 +25,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #if !defined (AARCH64_UNWIND_H) && !defined (__ILP32__)
 #define AARCH64_UNWIND_H
 
-#include "aarch64-unwind-def.h"
+#include "config/aarch64/aarch64-unwind-def.h"
 
 #include "ansidecl.h"
 #include 

[gcc r15-5949] arm: remove support for iWMMX/iWMMX2 intrinsics

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:a92b2be97f369ae4c6e1cdcbb7a45525994afaad

commit r15-5949-ga92b2be97f369ae4c6e1cdcbb7a45525994afaad
Author: Richard Earnshaw 
Date:   Thu Dec 5 15:14:09 2024 +

arm: remove support for iWMMX/iWMMX2 intrinsics

The mmintrin.h header was adjusted for GCC-14 to generate a
(suppressible) warning if it was used, saying that support would be
removed in GCC-15.

Make that come true by removing the contents of this header and
emitting an error.

At this point in time I've not removed the internal support for the
intrinsics, just the wrappers that enable access to them.  That can be
done at leisure from now on.

gcc/ChangeLog:

* config/arm/mmintrin.h: Raise an error if this header is used.
Remove other content.

Diff:
---
 gcc/config/arm/mmintrin.h | 1812 +
 1 file changed, 1 insertion(+), 1811 deletions(-)

diff --git a/gcc/config/arm/mmintrin.h b/gcc/config/arm/mmintrin.h
index e9cc3ddd7ab7..65b6f943cf3d 100644
--- a/gcc/config/arm/mmintrin.h
+++ b/gcc/config/arm/mmintrin.h
@@ -24,1816 +24,6 @@
 #ifndef _MMINTRIN_H_INCLUDED
 #define _MMINTRIN_H_INCLUDED
 
-#ifndef __IWMMXT__
-#error mmintrin.h included without enabling WMMX/WMMX2 instructions (e.g. 
-march=iwmmxt or -march=iwmmxt2)
-#endif
-
-#ifndef __ENABLE_DEPRECATED_IWMMXT
-#warning support for WMMX/WMMX2 is deprecated and will be removed in GCC 15.  
Define __ENABLE_DEPRECATED_IWMMXT to suppress this warning
-#endif
-
-#if defined __cplusplus
-extern "C" {
-/* Intrinsics use C name-mangling.  */
-#endif /* __cplusplus */
-
-/* The data type intended for user use.  */
-typedef unsigned long long __m64, __int64;
-
-/* Internal data types for implementing the intrinsics.  */
-typedef int __v2si __attribute__ ((vector_size (8)));
-typedef short __v4hi __attribute__ ((vector_size (8)));
-typedef signed char __v8qi __attribute__ ((vector_size (8)));
-
-/* Provided for source compatibility with MMX.  */
-extern __inline void __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
-_mm_empty (void)
-{
-}
-
-/* "Convert" __m64 and __int64 into each other.  */
-static __inline __m64
-_mm_cvtsi64_m64 (__int64 __i)
-{
-  return __i;
-}
-
-static __inline __int64
-_mm_cvtm64_si64 (__m64 __i)
-{
-  return __i;
-}
-
-static __inline int
-_mm_cvtsi64_si32 (__int64 __i)
-{
-  return __i;
-}
-
-static __inline __int64
-_mm_cvtsi32_si64 (int __i)
-{
-  return (__i & 0x);
-}
-
-/* Pack the four 16-bit values from M1 into the lower four 8-bit values of
-   the result, and the four 16-bit values from M2 into the upper four 8-bit
-   values of the result, all with signed saturation.  */
-static __inline __m64
-_mm_packs_pi16 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wpackhss ((__v4hi)__m1, (__v4hi)__m2);
-}
-
-/* Pack the two 32-bit values from M1 in to the lower two 16-bit values of
-   the result, and the two 32-bit values from M2 into the upper two 16-bit
-   values of the result, all with signed saturation.  */
-static __inline __m64
-_mm_packs_pi32 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wpackwss ((__v2si)__m1, (__v2si)__m2);
-}
-
-/* Copy the 64-bit value from M1 into the lower 32-bits of the result, and
-   the 64-bit value from M2 into the upper 32-bits of the result, all with
-   signed saturation for values that do not fit exactly into 32-bits.  */
-static __inline __m64
-_mm_packs_pi64 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wpackdss ((long long)__m1, (long long)__m2);
-}
-
-/* Pack the four 16-bit values from M1 into the lower four 8-bit values of
-   the result, and the four 16-bit values from M2 into the upper four 8-bit
-   values of the result, all with unsigned saturation.  */
-static __inline __m64
-_mm_packs_pu16 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wpackhus ((__v4hi)__m1, (__v4hi)__m2);
-}
-
-/* Pack the two 32-bit values from M1 into the lower two 16-bit values of
-   the result, and the two 32-bit values from M2 into the upper two 16-bit
-   values of the result, all with unsigned saturation.  */
-static __inline __m64
-_mm_packs_pu32 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wpackwus ((__v2si)__m1, (__v2si)__m2);
-}
-
-/* Copy the 64-bit value from M1 into the lower 32-bits of the result, and
-   the 64-bit value from M2 into the upper 32-bits of the result, all with
-   unsigned saturation for values that do not fit exactly into 32-bits.  */
-static __inline __m64
-_mm_packs_pu64 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wpackdus ((long long)__m1, (long long)__m2);
-}
-
-/* Interleave the four 8-bit values from the high half of M1 with the four
-   8-bit values from the high half of M2.  */
-static __inline __m64
-_mm_unpackhi_pi8 (__m64 __m1, __m64 __m2)
-{
-  return (__m64) __builtin_arm_wunpckihb ((__v8qi)__m1, (__v8qi)__m2);
-}
-
-/* Interleave the two 16-bit values 

[gcc r15-6038] arm: remove obsolete vcond expanders

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:2c9b69594665a87f74c6d5cb39fc6e075d75d771

commit r15-6038-g2c9b69594665a87f74c6d5cb39fc6e075d75d771
Author: Richard Earnshaw 
Date:   Fri Dec 6 12:57:52 2024 +

arm: remove obsolete vcond expanders

The vcond{,u} expander paterns have been declared as obsolete.  Remove
them from the Arm backend.

gcc/ChangeLog:

PR target/114189
* config/arm/arm-protos.h (arm_expand_vcond): Delete prototype.
* config/arm/arm.cc (arm_expand_vcond): Delete function.
* config/arm/vec-common.md (vcond): Delete pattern
(vcond): Likewise.
(vcond): Likewise.
(vcondu): Likewise.

Diff:
---
 gcc/config/arm/arm-protos.h  |  1 -
 gcc/config/arm/arm.cc| 44 ---
 gcc/config/arm/vec-common.md | 71 
 3 files changed, 116 deletions(-)

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 7311ad4d8e4a..155507f4745d 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -406,7 +406,6 @@ extern bool arm_expand_vector_compare (rtx, rtx_code, rtx, 
rtx, bool);
 #endif /* RTX_CODE */
 
 extern bool arm_gen_setmem (rtx *);
-extern void arm_expand_vcond (rtx *, machine_mode);
 extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
 
 extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 1fbc4c22f223..bc6f9345d1e8 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -31803,50 +31803,6 @@ arm_expand_vector_compare (rtx target, rtx_code code, 
rtx op0, rtx op1,
 }
 }
 
-/* Expand a vcond or vcondu pattern with operands OPERANDS.
-   CMP_RESULT_MODE is the mode of the comparison result.  */
-
-void
-arm_expand_vcond (rtx *operands, machine_mode cmp_result_mode)
-{
-  /* When expanding for MVE, we do not want to emit a (useless) vpsel in
- arm_expand_vector_compare, and another one here.  */
-  rtx mask;
-
-  if (TARGET_HAVE_MVE)
-mask = gen_reg_rtx (arm_mode_to_pred_mode (cmp_result_mode).require ());
-  else
-mask = gen_reg_rtx (cmp_result_mode);
-
-  bool inverted = arm_expand_vector_compare (mask, GET_CODE (operands[3]),
-operands[4], operands[5], true);
-  if (inverted)
-std::swap (operands[1], operands[2]);
-  if (TARGET_NEON)
-  emit_insn (gen_neon_vbsl (GET_MODE (operands[0]), operands[0],
-   mask, operands[1], operands[2]));
-  else
-{
-  machine_mode cmp_mode = GET_MODE (operands[0]);
-
-  switch (GET_MODE_CLASS (cmp_mode))
-   {
-   case MODE_VECTOR_INT:
- emit_insn (gen_mve_q (VPSELQ_S, VPSELQ_S, cmp_mode, operands[0],
-   operands[1], operands[2], mask));
- break;
-   case MODE_VECTOR_FLOAT:
- if (TARGET_HAVE_MVE_FLOAT)
-   emit_insn (gen_mve_q_f (VPSELQ_F, cmp_mode, operands[0],
-   operands[1], operands[2], mask));
- else
-   gcc_unreachable ();
- break;
-   default:
- gcc_unreachable ();
-   }
-}
-}
 
 #define MAX_VECT_LEN 16
 
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index ff1c27a0d717..0b426cdaff7f 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -416,77 +416,6 @@
 }
 })
 
-;; Conditional instructions.  These are comparisons with conditional moves for
-;; vectors.  They perform the assignment:
-;;
-;; Vop0 = (Vop4  Vop5) ? Vop1 : Vop2;
-;;
-;; where op3 is <, <=, ==, !=, >= or >.  Operations are performed
-;; element-wise.
-
-(define_expand "vcond"
-  [(set (match_operand:VDQWH 0 "s_register_operand")
-   (if_then_else:VDQWH
- (match_operator 3 "comparison_operator"
-   [(match_operand:VDQWH 4 "s_register_operand")
-(match_operand:VDQWH 5 "reg_or_zero_operand")])
- (match_operand:VDQWH 1 "s_register_operand")
- (match_operand:VDQWH 2 "s_register_operand")))]
-  "ARM_HAVE__ARITH
-   && !TARGET_REALLY_IWMMXT
-   && (! || flag_unsafe_math_optimizations)"
-{
-  arm_expand_vcond (operands, mode);
-  DONE;
-})
-
-(define_expand "vcond"
-  [(set (match_operand: 0 "s_register_operand")
-   (if_then_else:
- (match_operator 3 "comparison_operator"
-   [(match_operand:V32 4 "s_register_operand")
-(match_operand:V32 5 "reg_or_zero_operand")])
- (match_operand: 1 "s_register_operand")
- (match_operand: 2 "s_register_operand")))]
-  "ARM_HAVE__ARITH
-   && !TARGET_REALLY_IWMMXT
-   && (! || flag_unsafe_math_optimizations)"
-{
-  arm_expand_vcond (operands, mode);
-  DONE;
-})
-
-(define_expand "vcond"
-  [(set (match_operand: 0 "s_register_operand")
-   (if_then_else:
- (match_operator 3 "comparison_operator"
-   [(match_operand:V16 4 "s_register_op

[gcc r15-7371] arm: cleanup code in ldm_stm_operation_p; relax limits on ldm/stm

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:aead1d44b7df50c77ff63482f5548f237ff29033

commit r15-7371-gaead1d44b7df50c77ff63482f5548f237ff29033
Author: Richard Earnshaw 
Date:   Thu Dec 19 15:32:36 2024 +

arm: cleanup code in ldm_stm_operation_p; relax limits on ldm/stm

I needed to make some adjustments to this function to permit a push or
pop of a single register in thumb2 code, since ldm/stm can be a
two-byte instruction instead of 4.  Trying to read the code as it was
made me scratch my head as the logic was not very clear.  So this
patch cleans up the code somewhat, fixes a couple of minor bugs and
removes the limit of having to use multiple registers when using this
form of the instruction (the shape of this pattern is such that I
can't see it being generated automatically by the compiler, so there
should be no adverse affects of this).

Buglets fixed:
  - Validate that the first element contains RETURN if we're matching
a return instruction.
  - Don't allow the base address register to be stored if saving regs
and the address is being updated (this is unpredictable in the
architecture).
  - Verify that the last register loaded in a RETURN insn is the PC.

gcc/
* config/arm/arm.cc (decompose_addr_for_ldm_stm): New function.
(ldm_stm_operation_p): Rework to clarify logic.  Allow single
registers to be pushed or popped using LDM/STM.

Diff:
---
 gcc/config/arm/arm.cc | 224 --
 1 file changed, 126 insertions(+), 98 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 86838ebde5f8..4ee84361dc6e 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -14267,6 +14267,30 @@ adjacent_mem_locations (rtx a, rtx b)
   return 0;
 }
 
+/* Helper routine for ldm_stm_operation_p.  Decompose a simple offset
+   address into the base register and the offset.  Return false iff
+   it is more complex than this.  */
+static inline bool
+decompose_addr_for_ldm_stm (rtx addr, rtx *base, HOST_WIDE_INT *offset)
+{
+  if (REG_P (addr))
+{
+  *base = addr;
+  *offset = 0;
+  return true;
+}
+  else if (GET_CODE (addr) == PLUS
+  && REG_P (XEXP (addr, 0))
+  && CONST_INT_P (XEXP (addr, 1)))
+{
+  *base = XEXP (addr, 0);
+  *offset = INTVAL (XEXP (addr, 1));
+  return true;
+}
+
+  return false;
+}
+
 /* Return true if OP is a valid load or store multiple operation.  LOAD is true
for load operations, false for store operations.  CONSECUTIVE is true
if the register numbers in the operation must be consecutive in the register
@@ -14282,23 +14306,25 @@ adjacent_mem_locations (rtx a, rtx b)
  1.  If offset is 0, first insn should be (SET (R_d0) (MEM (src_addr))).
  2.  REGNO (R_d0) < REGNO (R_d1) < ... < REGNO (R_dn).
  3.  If consecutive is TRUE, then for kth register being loaded,
- REGNO (R_dk) = REGNO (R_d0) + k.
+REGNO (R_dk) = REGNO (R_d0) + k.
The pattern for store is similar.  */
 bool
 ldm_stm_operation_p (rtx op, bool load, machine_mode mode,
- bool consecutive, bool return_pc)
+bool consecutive, bool return_pc)
 {
-  HOST_WIDE_INT count = XVECLEN (op, 0);
-  rtx reg, mem, addr;
-  unsigned regno;
-  unsigned first_regno;
-  HOST_WIDE_INT i = 1, base = 0, offset = 0;
+  int count = XVECLEN (op, 0);
+  rtx reg, mem;
+  rtx addr_base;
+  int reg_loc, mem_loc;
+  unsigned prev_regno;
+  HOST_WIDE_INT addr_offset;
   rtx elt;
   bool addr_reg_in_reglist = false;
   bool update = false;
-  int reg_increment;
-  int offset_adj;
-  int regs_per_val;
+  int reg_bytes;
+  int words_per_reg;  /* How many words in memory a register takes.  */
+  int elt_num = 0;
+  int base_elt_num;  /* Element number of the first transfer operation.  */
 
   /* If not in SImode, then registers must be consecutive
  (e.g., VLDM instructions for DFmode).  */
@@ -14306,138 +14332,140 @@ ldm_stm_operation_p (rtx op, bool load, 
machine_mode mode,
   /* Setting return_pc for stores is illegal.  */
   gcc_assert (!return_pc || load);
 
-  /* Set up the increments and the regs per val based on the mode.  */
-  reg_increment = GET_MODE_SIZE (mode);
-  regs_per_val = reg_increment / 4;
-  offset_adj = return_pc ? 1 : 0;
+  /* Set up the increments and sizes for the mode.  */
+  reg_bytes = GET_MODE_SIZE (mode);
+  words_per_reg = ARM_NUM_REGS (mode);
+
+  /* If this is a return, then the first element in the par must be
+ (return).  */
+  if (return_pc)
+{
+  if (GET_CODE (XVECEXP (op, 0, 0)) != RETURN)
+   return false;
+  elt_num++;
+}
 
-  if (count <= 1
-  || GET_CODE (XVECEXP (op, 0, offset_adj)) != SET
-  || (load && !REG_P (SET_DEST (XVECEXP (op, 0, offset_adj)
+  if (elt_num >= count)
 return false;
 
   /* Check if this is a write-back.  */
-  elt = XVECEXP (op, 0, offset_adj);
+  elt

[gcc r15-7373] arm: Use POP {pc} to return when returning [PR118089]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:5163cf2ae14c5e7ec730ad72680564001d0d0441

commit r15-7373-g5163cf2ae14c5e7ec730ad72680564001d0d0441
Author: Richard Earnshaw 
Date:   Thu Dec 19 16:00:48 2024 +

arm: Use POP {pc} to return when returning [PR118089]

When generating thumb2 code,
LDM SP!, {PC}
is a two-byte instruction, whereas
LDR PC, [SP], #4
is needs 4 bytes.  When optimizing for size, or when there's no obvious
performance benefit prefer the former.

gcc/ChangeLog:

PR target/118089
* config/arm/arm.cc (thumb2_expand_return): Use LDM SP!, {PC}
when optimizing for size, or when there's no performance benefit 
over
LDR PC, [SP], #4.
(arm_expand_epilogue): Likewise.

Diff:
---
 gcc/config/arm/arm.cc | 62 +--
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 4ee84361dc6e..7e2082101d83 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -27762,35 +27762,40 @@ thumb2_expand_return (bool simple_return)
   /* TODO: Verify that this path is never taken for cmse_nonsecure_entry
 functions or adapt code to handle according to ACLE.  This path should
 not be reachable for cmse_nonsecure_entry functions though we prefer
-to assert it for now to ensure that future code changes do not silently
-change this behavior.  */
+to assert it for now to ensure that future code changes do not
+silently change this behavior.  */
   gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ()));
   if (arm_current_function_pac_enabled_p ())
-{
-  gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM)));
-  arm_emit_multi_reg_pop (saved_regs_mask);
-  emit_insn (gen_aut_nop ());
-  emit_jump_insn (simple_return_rtx);
-}
-  else if (num_regs == 1)
-{
-  rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-  rtx reg = gen_rtx_REG (SImode, PC_REGNUM);
-  rtx addr = gen_rtx_MEM (SImode,
-  gen_rtx_POST_INC (SImode,
-stack_pointer_rtx));
-  set_mem_alias_set (addr, get_frame_alias_set ());
-  XVECEXP (par, 0, 0) = ret_rtx;
-  XVECEXP (par, 0, 1) = gen_rtx_SET (reg, addr);
-  RTX_FRAME_RELATED_P (XVECEXP (par, 0, 1)) = 1;
-  emit_jump_insn (par);
-}
+   {
+ gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM)));
+ arm_emit_multi_reg_pop (saved_regs_mask);
+ emit_insn (gen_aut_nop ());
+ emit_jump_insn (simple_return_rtx);
+   }
+  /* Use LDR PC, [sp], #4.  Only do this if not optimizing for size and
+there's a known performance benefit (we don't know this exactly, but
+preferring LDRD/STRD over LDM/STM is a reasonable proxy).  */
+  else if (num_regs == 1
+  && !optimize_size
+  && current_tune->prefer_ldrd_strd)
+   {
+ rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
+ rtx reg = gen_rtx_REG (SImode, PC_REGNUM);
+ rtx addr = gen_rtx_MEM (SImode,
+ gen_rtx_POST_INC (SImode,
+   stack_pointer_rtx));
+ set_mem_alias_set (addr, get_frame_alias_set ());
+ XVECEXP (par, 0, 0) = ret_rtx;
+ XVECEXP (par, 0, 1) = gen_rtx_SET (reg, addr);
+ RTX_FRAME_RELATED_P (XVECEXP (par, 0, 1)) = 1;
+ emit_jump_insn (par);
+   }
   else
-{
-  saved_regs_mask &= ~ (1 << LR_REGNUM);
-  saved_regs_mask |=   (1 << PC_REGNUM);
-  arm_emit_multi_reg_pop (saved_regs_mask);
-}
+   {
+ saved_regs_mask &= ~ (1 << LR_REGNUM);
+ saved_regs_mask |=   (1 << PC_REGNUM);
+ arm_emit_multi_reg_pop (saved_regs_mask);
+   }
 }
   else
 {
@@ -28204,7 +28209,10 @@ arm_expand_epilogue (bool really_return)
   return_in_pc = true;
 }
 
-  if (num_regs == 1 && (!IS_INTERRUPT (func_type) || !return_in_pc))
+  if (num_regs == 1
+ && !optimize_size
+ && current_tune->prefer_ldrd_strd
+ && !(IS_INTERRUPT (func_type) && return_in_pc))
 {
   for (i = 0; i <= LAST_ARM_REGNUM; i++)
 if (saved_regs_mask & (1 << i))

[gcc r15-7372] arm: remove constraints from *pop_multiple_with_writeback_and_return

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:b47c7a5a3c8280ea64754a6c24582236eacef8a2

commit r15-7372-gb47c7a5a3c8280ea64754a6c24582236eacef8a2
Author: Richard Earnshaw 
Date:   Thu Dec 19 15:54:16 2024 +

arm: remove constraints from *pop_multiple_with_writeback_and_return

This pattern is intended to be used only by the epilogue generation
code and will always use fixed hard registers.  As such, it does not
need any register constraints, which might be misleading if a
post-reload pass wanted to try renumbering various registers.  So
remove the constraints.

Futhermore, to permit this pattern to match when popping just the PC
(which is not a valid register_operand), remove the match on the first
transfer register: pop_multiple_return will validate everything it
needs to.

gcc/ChangeLog:

* config/arm/arm.md (*pop_multiple_with_writeback_and_return): 
Remove
constraints.  Don't validate the first transfer register here.

Diff:
---
 gcc/config/arm/arm.md | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 842903e0bcdb..442d86b93292 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11964,12 +11964,10 @@
 (define_insn "*pop_multiple_with_writeback_and_return"
   [(match_parallel 0 "pop_multiple_return"
 [(return)
- (set (match_operand:SI 1 "s_register_operand" "+rk")
+ (set (match_operand:SI 1 "register_operand" "")
   (plus:SI (match_dup 1)
-   (match_operand:SI 2 "const_int_I_operand" "I")))
- (set (match_operand:SI 3 "s_register_operand" "=rk")
-  (mem:SI (match_dup 1)))
-])]
+   (match_operand:SI 2 "const_int_I_operand" "")))
+])]
   "TARGET_32BIT && (reload_in_progress || reload_completed)"
   "*
   {

[gcc r15-7455] arm: fix typo in dg-require-effective-target [PR118089]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:6ed1b40268ed56c82ea75e7403ded7750d01c85a

commit r15-7455-g6ed1b40268ed56c82ea75e7403ded7750d01c85a
Author: Richard Earnshaw 
Date:   Mon Feb 10 10:50:36 2025 +

arm: fix typo in dg-require-effective-target [PR118089]

Trivial typo.

gcc/testsuite:
PR target/118089
* gcc.target/arm/thumb2-pop-loreg.c (dg-require-effective-target): 
Fix
typo in directive.

Diff:
---
 gcc/testsuite/gcc.target/arm/thumb2-pop-loreg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/arm/thumb2-pop-loreg.c 
b/gcc/testsuite/gcc.target/arm/thumb2-pop-loreg.c
index 6db66b84cd96..c8397f64318f 100644
--- a/gcc/testsuite/gcc.target/arm/thumb2-pop-loreg.c
+++ b/gcc/testsuite/gcc.target/arm/thumb2-pop-loreg.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective_target arm_thumb2_ok } */
+/* { dg-require-effective-target arm_thumb2_ok } */
 /* { dg-options "-Os" } */
 
 int __attribute__((noinline)) f (void)

[gcc r15-7430] arm: Prefer POP {lo-reg} over LDR lo-reg, ... for thumb2 [PR118089]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:0b6453d5575d4aa773a1fe25060123bc6f539891

commit r15-7430-g0b6453d5575d4aa773a1fe25060123bc6f539891
Author: Richard Earnshaw 
Date:   Fri Feb 7 13:55:58 2025 +

arm: Prefer POP {lo-reg} over LDR lo-reg, ... for thumb2 [PR118089]

For thumb2, popping a single low register off the stack should prefer
POP over LDR to mirror the behaviour of the PUSH on entry.  This saves
a couple of bytes in the resulting image.  This is a relatively niche
case as it's rare to push a single low register onto the stack, but
still worth getting right.

Whilst fixing this I've also restructured the code here somewhat to
fix a bug I observed by inspection and to improve the code slightly.

Firstly, the single register case is hoisted above the main loop.
This not only avoids creating some RTL that immediately becomes
garbage but also avoids us needing to check for this case in every
iteration of the main loop body.

Secondly, we iterate over just the non-zero bits in the reg mask
rather than every bit and then checking if there's work to do for that
bit.

Finally, when emitting a pop that also pops SP off the stack we
shouldn't be emitting a stack-adjust CFA note.  The new SP value comes
from the popped value, not from an adjustment of the previous SP
value.

gcc:
PR target/118089
* config/arm/arm.cc (arm_emit_multi_reg_pop): Restructure.
Don't emit LDR on thumb2 when POP can be used for smaller code.
Don't add a CFA adjust note when SP is popped off the stack.

gcc/testsuite:
PR target/118089
* gcc.target/arm/thumb2-pop-loreg.c: New test.

Diff:
---
 gcc/config/arm/arm.cc   | 99 ++---
 gcc/testsuite/gcc.target/arm/thumb2-pop-loreg.c | 18 +
 2 files changed, 75 insertions(+), 42 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 503401544cbe..a95ddf8201fa 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -22543,24 +22543,50 @@ static void
 arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
 {
   int num_regs = 0;
-  int i, j;
   rtx par;
   rtx dwarf = NULL_RTX;
   rtx tmp, reg;
   bool return_in_pc = saved_regs_mask & (1 << PC_REGNUM);
   int offset_adj;
   int emit_update;
+  unsigned long reg_bits;
 
   offset_adj = return_in_pc ? 1 : 0;
-  for (i = 0; i <= LAST_ARM_REGNUM; i++)
-if (saved_regs_mask & (1 << i))
-  num_regs++;
+  for (reg_bits = saved_regs_mask; reg_bits;
+   reg_bits &= ~(reg_bits & -reg_bits))
+num_regs++;
 
   gcc_assert (num_regs && num_regs <= 16);
 
   /* If SP is in reglist, then we don't emit SP update insn.  */
   emit_update = (saved_regs_mask & (1 << SP_REGNUM)) ? 0 : 1;
 
+  /* If popping just one register, use LDR reg, [SP], #4, unless
+ we're generating Thumb code and reg is a low reg.  */
+  if (num_regs == 1
+  && emit_update
+  && !return_in_pc
+  && (TARGET_ARM
+ /* For Thumb we want to use POP for a single low register.  */
+ || (saved_regs_mask & ~0xff)))
+{
+  int i = exact_log2 (saved_regs_mask);
+
+  rtx dwarf_reg = reg = gen_rtx_REG (SImode, i);
+  if (arm_current_function_pac_enabled_p () && i == IP_REGNUM)
+   dwarf_reg = gen_rtx_REG (SImode, RA_AUTH_CODE);
+  /* Emit single load with writeback.   */
+  tmp = gen_frame_mem (SImode,
+  gen_rtx_POST_INC (Pmode,
+stack_pointer_rtx));
+  tmp = emit_insn (gen_rtx_SET (reg, tmp));
+  REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, dwarf_reg,
+   dwarf);
+  arm_add_cfa_adjust_cfa_note (tmp, UNITS_PER_WORD,
+  stack_pointer_rtx, stack_pointer_rtx);
+  return;
+}
+
   /* The parallel needs to hold num_regs SETs
  and one SET for the stack update.  */
   par = gen_rtx_PARALLEL (VOIDmode,
@@ -22582,50 +22608,39 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
 }
 
   /* Now restore every reg, which may include PC.  */
-  for (j = 0, i = 0; j < num_regs; i++)
-if (saved_regs_mask & (1 << i))
-  {
-   rtx dwarf_reg = reg = gen_rtx_REG (SImode, i);
-   if (arm_current_function_pac_enabled_p () && i == IP_REGNUM)
- dwarf_reg = gen_rtx_REG (SImode, RA_AUTH_CODE);
-   if ((num_regs == 1) && emit_update && !return_in_pc)
- {
-   /* Emit single load with writeback.  */
-   tmp = gen_frame_mem (SImode,
-gen_rtx_POST_INC (Pmode,
-  stack_pointer_rtx));
-   tmp = emit_insn (gen_rtx_SET (reg, tmp));
-   REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, dwarf_reg,
- dwarf);
-   arm_add_cfa_adjust_cfa_note (tmp,

[gcc r15-7429] arm: fix ICE due to fix for POP {PC} change

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:7bee37094c502de7c191ee5f2f9ce72789d27c99

commit r15-7429-g7bee37094c502de7c191ee5f2f9ce72789d27c99
Author: Richard Earnshaw 
Date:   Fri Feb 7 11:34:13 2025 +

arm: fix ICE due to fix for POP {PC} change

My earlier change for making the compiler prefer

POP {PC}

over

LDR PC, [SP], #4

had a slightly unexpected consequence in that we now also call
arm_emit_multi_reg_pop to handle single register pops when the
register is not PC.  This exposed a latent bug in this function where
the dwarf unwinding notes on the single-register POP were not being
set correctly.

gcc/
PR target/118089
* config/arm/arm.cc (arm_emit_multi_reg_pop): Add a CFA adjust
note to single-register POP instructions.

Diff:
---
 gcc/config/arm/arm.cc | 51 +++
 1 file changed, 27 insertions(+), 24 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 7e2082101d83..503401544cbe 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -22563,7 +22563,8 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
 
   /* The parallel needs to hold num_regs SETs
  and one SET for the stack update.  */
-  par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs + emit_update + 
offset_adj));
+  par = gen_rtx_PARALLEL (VOIDmode,
+ rtvec_alloc (num_regs + emit_update + offset_adj));
 
   if (return_in_pc)
 XVECEXP (par, 0, 0) = ret_rtx;
@@ -22571,11 +22572,11 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
   if (emit_update)
 {
   /* Increment the stack pointer, based on there being
- num_regs 4-byte registers to restore.  */
+num_regs 4-byte registers to restore.  */
   tmp = gen_rtx_SET (stack_pointer_rtx,
- plus_constant (Pmode,
-stack_pointer_rtx,
-4 * num_regs));
+plus_constant (Pmode,
+   stack_pointer_rtx,
+   4 * num_regs));
   RTX_FRAME_RELATED_P (tmp) = 1;
   XVECEXP (par, 0, offset_adj) = tmp;
 }
@@ -22587,31 +22588,33 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
rtx dwarf_reg = reg = gen_rtx_REG (SImode, i);
if (arm_current_function_pac_enabled_p () && i == IP_REGNUM)
  dwarf_reg = gen_rtx_REG (SImode, RA_AUTH_CODE);
-if ((num_regs == 1) && emit_update && !return_in_pc)
-  {
-/* Emit single load with writeback.  */
-tmp = gen_frame_mem (SImode,
- gen_rtx_POST_INC (Pmode,
-   stack_pointer_rtx));
-tmp = emit_insn (gen_rtx_SET (reg, tmp));
+   if ((num_regs == 1) && emit_update && !return_in_pc)
+ {
+   /* Emit single load with writeback.  */
+   tmp = gen_frame_mem (SImode,
+gen_rtx_POST_INC (Pmode,
+  stack_pointer_rtx));
+   tmp = emit_insn (gen_rtx_SET (reg, tmp));
REG_NOTES (tmp) = alloc_reg_note (REG_CFA_RESTORE, dwarf_reg,
  dwarf);
-return;
-  }
+   arm_add_cfa_adjust_cfa_note (tmp, UNITS_PER_WORD,
+stack_pointer_rtx, stack_pointer_rtx);
+   return;
+ }
 
-tmp = gen_rtx_SET (reg,
-   gen_frame_mem
-   (SImode,
-plus_constant (Pmode, stack_pointer_rtx, 4 * j)));
-RTX_FRAME_RELATED_P (tmp) = 1;
-XVECEXP (par, 0, j + emit_update + offset_adj) = tmp;
+   tmp = gen_rtx_SET (reg,
+  gen_frame_mem
+  (SImode,
+   plus_constant (Pmode, stack_pointer_rtx, 4 * j)));
+   RTX_FRAME_RELATED_P (tmp) = 1;
+   XVECEXP (par, 0, j + emit_update + offset_adj) = tmp;
 
-/* We need to maintain a sequence for DWARF info too.  As dwarf info
-   should not have PC, skip PC.  */
-if (i != PC_REGNUM)
+   /* We need to maintain a sequence for DWARF info too.  As dwarf info
+  should not have PC, skip PC.  */
+   if (i != PC_REGNUM)
  dwarf = alloc_reg_note (REG_CFA_RESTORE, dwarf_reg, dwarf);
 
-j++;
+   j++;
   }
 
   if (return_in_pc)

[gcc r15-5990] arm: testsuite: fix some legacy C tests

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:92c7a190d7e87100d7e2015220baa127480492ba

commit r15-5990-g92c7a190d7e87100d7e2015220baa127480492ba
Author: Richard Earnshaw 
Date:   Fri Dec 6 17:05:27 2024 +

arm: testsuite: fix some legacy C tests

These tests all lack ISO-C style function definitions.  Some
deliberatly so.  Rather than try to adjust the code and risk changing
the nature of the test, add -std=c17 to the test options.

gcc/testsuite/ChangeLog:

* gcc.target/arm/20031108-1.c: Add -std=c17.
* gcc.target/arm/fp16-unprototyped-1.c: Likewise.
* gcc.target/arm/fp16-unprototyped-2.c: Likewise.
* gcc.target/arm/neon-thumb2-move.c: Likewise.
* gcc.target/arm/pr67756.c: Likewise.
* gcc.target/arm/pr81863.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/arm/20031108-1.c  | 2 +-
 gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c | 2 +-
 gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c | 2 +-
 gcc/testsuite/gcc.target/arm/neon-thumb2-move.c| 2 +-
 gcc/testsuite/gcc.target/arm/pr67756.c | 2 +-
 gcc/testsuite/gcc.target/arm/pr81863.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/20031108-1.c 
b/gcc/testsuite/gcc.target/arm/20031108-1.c
index 7923e1151395..b99db7aa1944 100644
--- a/gcc/testsuite/gcc.target/arm/20031108-1.c
+++ b/gcc/testsuite/gcc.target/arm/20031108-1.c
@@ -1,7 +1,7 @@
 /* PR optimization/10467  */
 /* { dg-do compile } */
 /* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
-/* { dg-options "-O2 -mthumb" } */
+/* { dg-options "-O2 -mthumb -std=c17" } */
 
 typedef enum {Ident_1} Enumeration;
 
diff --git a/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c 
b/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c
index 70c295648889..c76f5377ca39 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c
@@ -2,7 +2,7 @@
function in another compilation unit.  */
 
 /* { dg-do run } */
-/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-options "-mfp16-format=ieee -std=c17" } */
 /* { dg-additional-sources "fp16-unprototyped-2.c" } */
 
 #include 
diff --git a/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c 
b/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c
index 0c0f9cda6ba9..2aee1dc4a152 100644
--- a/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-options "-mfp16-format=ieee -std=c17" } */
 
 extern int f ();
 
diff --git a/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c 
b/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
index d8c6748d4ee9..b155be08820b 100644
--- a/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
+++ b/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
 /* { dg-require-effective-target arm_thumb2_ok } */
-/* { dg-options "-O2 -mthumb" } */
+/* { dg-options "-O2 -mthumb -std=c17" } */
 /* { dg-add-options arm_neon } */
 /* { dg-prune-output "switch .* conflicts with" } */
 
diff --git a/gcc/testsuite/gcc.target/arm/pr67756.c 
b/gcc/testsuite/gcc.target/arm/pr67756.c
index d2e1a8270d67..240192dd56ce 100644
--- a/gcc/testsuite/gcc.target/arm/pr67756.c
+++ b/gcc/testsuite/gcc.target/arm/pr67756.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_hard_vfp_ok } */
-/* { dg-options "-O2 -mapcs -march=armv7-a -mfloat-abi=hard -mfpu=vfpv3-d16" } 
*/
+/* { dg-options "-O2 -mapcs -march=armv7-a -mfloat-abi=hard -mfpu=vfpv3-d16 
-std=c17" } */
 
 int inode_permission (), try_break_deleg ();
 int mutex_lock (), mutex_unlock ();
diff --git a/gcc/testsuite/gcc.target/arm/pr81863.c 
b/gcc/testsuite/gcc.target/arm/pr81863.c
index a96f3b584110..25f8966e73ca 100644
--- a/gcc/testsuite/gcc.target/arm/pr81863.c
+++ b/gcc/testsuite/gcc.target/arm/pr81863.c
@@ -3,7 +3,7 @@
 /* { dg-require-effective-target arm_arch_v7a_arm_ok } */
 /* { dg-skip-if "-mslow-flash-data and -mword-relocations incompatible" { 
*-*-* } { "-mslow-flash-data" } } */
 /* { dg-skip-if "-mpure-code and -mword-relocations incompatible" { *-*-* } { 
"-mpure-code" } } */
-/* { dg-options "-O2 -mword-relocations" } */
+/* { dg-options "-O2 -mword-relocations -std=c17" } */
 /* { dg-add-options arm_arch_v7a_arm } */
 /* { dg-final { scan-assembler-not "\[\\t \]+movw" } } */

[gcc r15-5941] arm: Add CDE options for star-mc1 cpu

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:237fdf51fbfcfa4829471c18fe67535ae9c3efdb

commit r15-5941-g237fdf51fbfcfa4829471c18fe67535ae9c3efdb
Author: Arvin Zhong 
Date:   Thu Dec 5 13:43:14 2024 +

arm: Add CDE options for star-mc1 cpu

This patch adds the CDE options support for the -mcpu=star-mc1.
The star-mc1 is an Armv8-m Mainline CPU supporting CDE feature.

gcc/ChangeLog:

* config/arm/arm-cpus.in (star-mc1): Add CDE options.
* doc/invoke.texi (cdecp options): Document for star-mc1.

Signed-off-by: Qingxin Zhong 

Diff:
---
 gcc/config/arm/arm-cpus.in | 8 
 gcc/doc/invoke.texi| 6 --
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 451b15fe9f93..5c12ffb807ba 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1689,6 +1689,14 @@ begin cpu star-mc1
  architecture armv8-m.main+dsp+fp
  option nofp remove ALL_FP
  option nodsp remove armv7em
+ option cdecp0 add cdecp0
+ option cdecp1 add cdecp1
+ option cdecp2 add cdecp2
+ option cdecp3 add cdecp3
+ option cdecp4 add cdecp4
+ option cdecp5 add cdecp5
+ option cdecp6 add cdecp6
+ option cdecp7 add cdecp7
  isa quirk_no_asmcpu quirk_vlldm
  costs v7m
 end cpu star-mc1
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 78ead0e494e1..e85a1495b70f 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23760,7 +23760,8 @@ on @samp{cortex-m52} and @samp{cortex-m85}.
 
 @item +nomve
 Disable the M-Profile Vector Extension (MVE) integer and single precision
-floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and 
@samp{cortex-m85}.
+floating-point instructions on @samp{cortex-m52}, @samp{cortex-m55} and
+@samp{cortex-m85}.
 
 @item +nomve.fp
 Disable the M-Profile Vector Extension (MVE) single precision floating-point
@@ -23768,7 +23769,8 @@ instructions on @samp{cortex-m52}, @samp{cortex-m55} 
and @samp{cortex-m85}.
 
 @item +cdecp0, +cdecp1, ... , +cdecp7
 Enable the Custom Datapath Extension (CDE) on selected coprocessors according
-to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52} 
and @samp{cortex-m55}.
+to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52},
+@samp{cortex-m55} and @samp{star-mc1}.
 
 @item  +nofp
 Disables the floating-point instructions on @samp{arm9e},

[gcc r15-7251] arm: libbacktrace: Check if the compiler supports __sync atomics

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:a235c45354de9a89ba2f6f12d3aac42efc18f311

commit r15-7251-ga235c45354de9a89ba2f6f12d3aac42efc18f311
Author: Richard Earnshaw 
Date:   Mon Jan 27 13:52:05 2025 +

arm: libbacktrace: Check if the compiler supports __sync atomics

Older versions of the Arm architecture lack support for __sync
operations directly in hardware and require calls into appropriate
operating-system hooks.  But such hooks obviously don't exist in a
freestanding environment.

Consquently, it is incorrect to assume during configure that such
functions will exist and we need a configure-time check to determine
whether or not these routines will work.

libbacktrace:

* configure.ac: Always check if the compiler supports __sync
operations.
* configure: Regenerated.

Diff:
---
 libbacktrace/configure| 23 +++
 libbacktrace/configure.ac | 10 ++
 2 files changed, 33 insertions(+)

diff --git a/libbacktrace/configure b/libbacktrace/configure
index db491a782349..0ecdd3ec0a3d 100755
--- a/libbacktrace/configure
+++ b/libbacktrace/configure
@@ -12760,6 +12760,29 @@ else
   if test -n "${with_target_subdir}"; then
case "${host}" in
hppa*-*-hpux*) libbacktrace_cv_sys_sync=no ;;
+   arm*-*-eabi*)
+ # Older versions of the Arm architecture lack the necessary instructions
+ # for these constructs, so check whether we can use them.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+int i;
+int
+main ()
+{
+__sync_bool_compare_and_swap (&i, i, i);
+ __sync_lock_test_and_set (&i, 1);
+ __sync_lock_release (&i);
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+  libbacktrace_cv_sys_sync=yes
+else
+  libbacktrace_cv_sys_sync=no
+fi
+rm -f core conftest.err conftest.$ac_objext \
+conftest$ac_exeext conftest.$ac_ext;;
*) libbacktrace_cv_sys_sync=yes ;;
esac
  else
diff --git a/libbacktrace/configure.ac b/libbacktrace/configure.ac
index b700bf9d4f94..75b3a7536f1e 100644
--- a/libbacktrace/configure.ac
+++ b/libbacktrace/configure.ac
@@ -199,6 +199,16 @@ AC_CACHE_CHECK([__sync extensions],
 [if test -n "${with_target_subdir}"; then
case "${host}" in
hppa*-*-hpux*) libbacktrace_cv_sys_sync=no ;;
+   arm*-*-eabi*)
+ # Older versions of the Arm architecture lack the necessary instructions
+ # for these constructs, so check whether we can use them.
+ AC_LINK_IFELSE(
+   [AC_LANG_PROGRAM([int i;],
+[__sync_bool_compare_and_swap (&i, i, i);
+ __sync_lock_test_and_set (&i, 1);
+ __sync_lock_release (&i);])],
+   [libbacktrace_cv_sys_sync=yes],
+   [libbacktrace_cv_sys_sync=no]);;
*) libbacktrace_cv_sys_sync=yes ;;
esac
  else

[gcc r15-7258] arm: libgcc: make -spec=sync-*.specs compatible with LTO [PR118642]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:0204dcf930b5093d0811a007b7f47aa42e55e787

commit r15-7258-g0204dcf930b5093d0811a007b7f47aa42e55e787
Author: Richard Earnshaw 
Date:   Tue Jan 28 16:14:35 2025 +

arm: libgcc: make -spec=sync-*.specs compatible with LTO [PR118642]

The arm-none-eabi port provides some alternative implementations of
__sync_synchronize for different implementations of the architecture.
These can be selected using one of -specs=sync-{none,dmb,cp15dmb}.specs.

These specs fragments fail, however, when LTO is used because they
unconditionally add a --defsym=__sync_synchronize= to
the linker arguments and that fails if libgcc is not added to the list
of libraries.

Fix this by only adding the defsym if libgcc will be passed to the
linker.

libgcc/

PR target/118642
* config/arm/sync-none.specs (link): Only add the defsym if
libgcc will be used.
* config/arm/sync-dmb.specs: Likewise.
* config/arm/sync-cp15dmb.specs: Likewise.

Diff:
---
 libgcc/config/arm/sync-cp15dmb.specs | 2 +-
 libgcc/config/arm/sync-dmb.specs | 2 +-
 libgcc/config/arm/sync-none.specs| 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/libgcc/config/arm/sync-cp15dmb.specs 
b/libgcc/config/arm/sync-cp15dmb.specs
index 0bb64b97a0da..47bf68b6b99c 100644
--- a/libgcc/config/arm/sync-cp15dmb.specs
+++ b/libgcc/config/arm/sync-cp15dmb.specs
@@ -1,4 +1,4 @@
 %rename link sync_sync_link
 
 *link:
---defsym=__sync_synchronize=__sync_synchronize_cp15dmb %(sync_sync_link)
+%{!nostdlib|lgcc: --defsym=__sync_synchronize=__sync_synchronize_cp15dmb} 
%(sync_sync_link)
diff --git a/libgcc/config/arm/sync-dmb.specs b/libgcc/config/arm/sync-dmb.specs
index 13e59bdd22d9..cadad6d4626b 100644
--- a/libgcc/config/arm/sync-dmb.specs
+++ b/libgcc/config/arm/sync-dmb.specs
@@ -1,4 +1,4 @@
 %rename link sync_sync_link
 
 *link:
---defsym=__sync_synchronize=__sync_synchronize_dmb %(sync_sync_link)
+%{!nostdlib|lgcc: --defsym=__sync_synchronize=__sync_synchronize_dmb} 
%(sync_sync_link)
diff --git a/libgcc/config/arm/sync-none.specs 
b/libgcc/config/arm/sync-none.specs
index 0aa49602c8b6..46071ca7b04b 100644
--- a/libgcc/config/arm/sync-none.specs
+++ b/libgcc/config/arm/sync-none.specs
@@ -1,4 +1,4 @@
 %rename link sync_sync_link
 
 *link:
---defsym=__sync_synchronize=__sync_synchronize_none %(sync_sync_link)
+%{!nostdlib|lgcc: --defsym=__sync_synchronize=__sync_synchronize_none} 
%(sync_sync_link)

[gcc r15-8882] arm: add commutative alternatives to mull pattern.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:a86891525d200c1ae81d9f5f441a5b8e24b647ca

commit r15-8882-ga86891525d200c1ae81d9f5f441a5b8e24b647ca
Author: Richard Earnshaw 
Date:   Tue Mar 25 11:50:30 2025 +

arm: add commutative alternatives to mull pattern.

Prior to Armv6, the SMULL and UMULL instructions, which have the form

 UMULL Rdlo, Rdhi, Rm, Rs

had an operand restriction such that Rdlo, Rdhi and Rm must all be
different registers.  Rs, however can overlap either of the
destination registers.  Add some register-tie alternatives to allow
the register allocator to find these forms without having to use
additional register moves.

In addition to this, the test is pretty meaningless on Thumb-1 targets
as the S/UMULL instructions do not exist in a 16-bit encoding.  So skip
the test in this case.

gcc/ChangeLog:

* config/arm/arm.md (mull): Add alternatives that allow Rs
to be tied to either Rdlo or Rdhi.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr42575.c: Skip test if thumb1.

Diff:
---
 gcc/config/arm/arm.md  | 10 +-
 gcc/testsuite/gcc.target/arm/pr42575.c |  1 +
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 442d86b93292..597ef6725bb7 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2432,11 +2432,11 @@
 )
 
 (define_insn "mull"
-  [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
+  [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r")
(mult:SI
-(match_operand:SI 2 "s_register_operand" "%r,r")
-(match_operand:SI 3 "s_register_operand" "r,r")))
-   (set (match_operand:SI 1 "s_register_operand" "=r,&r")
+(match_operand:SI 2 "s_register_operand" "%r,r,r,r")
+(match_operand:SI 3 "s_register_operand" "r,r,0,1")))
+   (set (match_operand:SI 1 "s_register_operand" "=r,&r,&r,&r")
(truncate:SI
 (lshiftrt:DI
  (mult:DI (SE:DI (match_dup 2)) (SE:DI (match_dup 3)))
@@ -2445,7 +2445,7 @@
   "mull%?\\t%0, %1, %2, %3"
   [(set_attr "type" "umull")
(set_attr "predicable" "yes")
-   (set_attr "arch" "v6,nov6")]
+   (set_attr "arch" "v6,nov6,nov6,nov6")]
 )
 
 (define_expand "maddsidi4"
diff --git a/gcc/testsuite/gcc.target/arm/pr42575.c 
b/gcc/testsuite/gcc.target/arm/pr42575.c
index 1998e323df17..3906c77ed569 100644
--- a/gcc/testsuite/gcc.target/arm/pr42575.c
+++ b/gcc/testsuite/gcc.target/arm/pr42575.c
@@ -1,4 +1,5 @@
 /* { dg-options "-O2" }  */
+/* { dg-skip-if "Thumb1 lacks UMULL" { arm_thumb1 } } */
 /* Make sure RA does good job allocating registers and avoids
unnecessary moves.  */
 /* { dg-final { scan-assembler-not "mov" } } */

[gcc r15-8881] opcodes: fix wrong code in expand_binop_directly [PR117811]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:7679b826840c58343d72d05922355b646db4bdcc

commit r15-8881-g7679b826840c58343d72d05922355b646db4bdcc
Author: Richard Earnshaw 
Date:   Thu Mar 20 14:42:59 2025 +

opcodes: fix wrong code in expand_binop_directly [PR117811]

If expand_binop_directly fails to add a REG_EQUAL note it tries to
unwind and restart.  But it can unwind too far if expand_binop changed
some of the operands before calling it.  We don't need to unwind that
far anyway since we should end up taking exactly the same route next
time, just without a target rtx.

To fix this we remove LAST from the argument list and let the callers
(all in expand_binop) do their own unwinding if the call fails.
Instead we unwind just as far as the entry to expand_binop_directly
and recurse within this function instead of all the way back up.

gcc/ChangeLog:

PR middle-end/117811
* optabs.cc (expand_binop_directly): Remove LAST as an argument,
instead record the last insn on entry.  Only delete insns if
we need to restart and restart by calling ourself, not expand_binop.
(expand_binop): Update callers to expand_binop_directly.  If it
fails to expand the operation, delete back to LAST.

gcc/testsuite:

PR middle-end/117811
* gcc.dg/torture/pr117811.c: New test.

Diff:
---
 gcc/optabs.cc   | 24 
 gcc/testsuite/gcc.dg/torture/pr117811.c | 27 +++
 2 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index 36f2e6af8b5c..0a14b1eef8a5 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -1369,8 +1369,7 @@ avoid_expensive_constant (machine_mode mode, optab 
binoptab,
 static rtx
 expand_binop_directly (enum insn_code icode, machine_mode mode, optab binoptab,
   rtx op0, rtx op1,
-  rtx target, int unsignedp, enum optab_methods methods,
-  rtx_insn *last)
+  rtx target, int unsignedp, enum optab_methods methods)
 {
   machine_mode xmode0 = insn_data[(int) icode].operand[1].mode;
   machine_mode xmode1 = insn_data[(int) icode].operand[2].mode;
@@ -1380,6 +1379,7 @@ expand_binop_directly (enum insn_code icode, machine_mode 
mode, optab binoptab,
   rtx_insn *pat;
   rtx xop0 = op0, xop1 = op1;
   bool canonicalize_op1 = false;
+  rtx_insn *last = get_last_insn ();
 
   /* If it is a commutative operator and the modes would match
  if we would swap the operands, we can save the conversions.  */
@@ -1444,10 +1444,7 @@ expand_binop_directly (enum insn_code icode, 
machine_mode mode, optab binoptab,
   tmp_mode = insn_data[(int) icode].operand[0].mode;
   if (VECTOR_MODE_P (mode)
  && maybe_ne (GET_MODE_NUNITS (tmp_mode), 2 * GET_MODE_NUNITS (mode)))
-   {
- delete_insns_since (last);
- return NULL_RTX;
-   }
+   return NULL_RTX;
 }
   else
 tmp_mode = mode;
@@ -1467,14 +1464,14 @@ expand_binop_directly (enum insn_code icode, 
machine_mode mode, optab binoptab,
   ops[1].value, ops[2].value, mode0))
{
  delete_insns_since (last);
- return expand_binop (mode, binoptab, op0, op1, NULL_RTX,
-  unsignedp, methods);
+ return expand_binop_directly (icode, mode, binoptab, op0, op1,
+   NULL_RTX, unsignedp, methods);
}
 
   emit_insn (pat);
   return ops[0].value;
 }
-  delete_insns_since (last);
+
   return NULL_RTX;
 }
 
@@ -1543,9 +1540,10 @@ expand_binop (machine_mode mode, optab binoptab, rtx 
op0, rtx op1,
   if (icode != CODE_FOR_nothing)
{
  temp = expand_binop_directly (icode, mode, binoptab, op0, op1,
-   target, unsignedp, methods, last);
+   target, unsignedp, methods);
  if (temp)
return temp;
+ delete_insns_since (last);
}
 }
 
@@ -1571,9 +1569,10 @@ expand_binop (machine_mode mode, optab binoptab, rtx 
op0, rtx op1,
   NULL_RTX, unsignedp, OPTAB_DIRECT);
 
   temp = expand_binop_directly (icode, int_mode, otheroptab, op0, newop1,
-   target, unsignedp, methods, last);
+   target, unsignedp, methods);
   if (temp)
return temp;
+  delete_insns_since (last);
 }
 
   /* If this is a multiply, see if we can do a widening operation that
@@ -1637,9 +1636,10 @@ expand_binop (machine_mode mode, optab binoptab, rtx 
op0, rtx op1,
  if (vop1)
{
  temp = expand_binop_directly (icode, mode, otheroptab, op0, vop1,
-   target, unsignedp, methods, last);
+

[gcc r15-8648] arm: testsuite: memcpy-aligned requires unaligned accesses

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:b1ac0c5f1986d0774cfc980da8323f17747a1ce9

commit r15-8648-gb1ac0c5f1986d0774cfc980da8323f17747a1ce9
Author: Richard Earnshaw 
Date:   Fri Mar 21 15:15:21 2025 +

arm: testsuite: memcpy-aligned requires unaligned accesses

This test is designed to check that if one of the operands is
aligned (but the other isn't) we expand to a sensible sequence and
bypass most of the overhead of doing a memcpy.  But on targets without
unaligned accessess, we still end up calling memcpy.  It's then a
lottery as to whether the prologue and epilogue code, plus the
set-up for the memcpy itself, generate instructions that match the
scan patterns.

Since in those cases we're not actually testing what the test is looking
for anyway, just skip the test on strict-alignment targets.

gcc/testsuite:
* gcc.target/arm/memcpy-aligned-1.c: Require unaligned accesses.

Diff:
---
 gcc/testsuite/gcc.target/arm/memcpy-aligned-1.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.target/arm/memcpy-aligned-1.c 
b/gcc/testsuite/gcc.target/arm/memcpy-aligned-1.c
index 852b391388bd..42e2a6bbdf74 100644
--- a/gcc/testsuite/gcc.target/arm/memcpy-aligned-1.c
+++ b/gcc/testsuite/gcc.target/arm/memcpy-aligned-1.c
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-require-effective-target arm_unaligned } */
 /* { dg-options "-O2 -save-temps" } */
 
 void *memcpy (void *dest, const void *src, unsigned int n);

[gcc r15-8889] arm: testsuite use -std=gnu17 for pr65647.c

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:143ad00ccd63a6cf38d8067d5fa79bd9a81e3144

commit r15-8889-g143ad00ccd63a6cf38d8067d5fa79bd9a81e3144
Author: Richard Earnshaw 
Date:   Tue Mar 25 13:18:06 2025 +

arm: testsuite use -std=gnu17 for pr65647.c

This test has missing prototypes.  To avoid disturbing the test, use gnu17.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr65647.c (dg-options): Add -std=gnu17.

Diff:
---
 gcc/testsuite/gcc.target/arm/pr65647.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/arm/pr65647.c 
b/gcc/testsuite/gcc.target/arm/pr65647.c
index e0c534bc813a..663157c9c66f 100644
--- a/gcc/testsuite/gcc.target/arm/pr65647.c
+++ b/gcc/testsuite/gcc.target/arm/pr65647.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_arch_v6m_ok } */
-/* { dg-options "-O3 -w -fpermissive" } */
+/* { dg-options "-O3 -w -fpermissive -std=gnu17" } */
 /* { dg-add-options arm_arch_v6m } */
 
 a, b, c, e, g = &e, h, i = 7, l = 1, m, n, o, q = &m, r, s = &r, u, w = 9, x,

[gcc r16-474] aarch64: Fix up commutative and early-clobber markers on compact insns

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:f260146bc05f6fba7b2a67a62063c770588b769d

commit r16-474-gf260146bc05f6fba7b2a67a62063c770588b769d
Author: Richard Earnshaw 
Date:   Mon Apr 14 16:41:16 2025 +0100

aarch64: Fix up commutative and early-clobber markers on compact insns

For constraints there are operand modifiers and constraint qualifiers.
Operand modifiers apply to all alternatives and must appear, in
traditional syntax before the first alternative.  Constraint
qualifiers, on the other hand must appear in each alternative to which
they apply.

There's no easy way to validate the distinction in the traditional md
format, but when using the new compact format we can enforce some
semantic checking of these characters to avoid some potentially
surprising code generation.

Fortunately, all of these errors are benign, but the two misplaced
early-clobber markers were quite suspicious at first sight - it's only
by luck that the second alternative does not need an early-clobber.

The syntax checking will be added in the following patch, but first of
all, fix up the errors in aarch64.md.

gcc/
* config/aarch64/aarch64-sve.md (@aarch64_pred_): Move
commutative marker to the cons specification.
(add3): Likewise.
(@aarch64_pred_abd): Likewise.
(@aarch64_pred_): Likewise.
(*cond__z): Likewise.
(3): Likewise.
(@aarch64_pred_): Likewise.
(*aarch64_pred_abd_relaxed): Likewise.
(*aarch64_pred_abd_strict): Likewise.
(@aarch64_pred_): Likewise.
(@aarch64_pred_): Likewise.
(@aarch64_pred_fma): Likewise.
(@aarch64_pred_fnma): Likewise.
(@aarch64_pred_): Likewise.

* config/aarch64/aarch64-sve2.md (@aarch64_sve_clamp): 
Move
commutative marker to the cons specification.
(*aarch64_sve_clamp_x): Likewise.
(@aarch64_sve_fclamp): Likewise.
(*aarch64_sve_fclamp_x): Likewise.
(*aarch64_sve2_nor): Likewise.
(*aarch64_sve2_nand): Likewise.
(*aarch64_pred_faminmax_fused): Likewise.

* config/aarch64/aarch64.md (*loadwb_pre_pair_): Move the
early-clobber marker to the relevant alternative.
(*storewb_pre_pair_): Likewise.
(*add3_aarch64): Move commutative marker to the cons
specification.
(*addsi3_aarch64_uxtw): Likewise.
(*add3_poly_1): Likewise.
(add3_compare0): Likewise.
(*addsi3_compare0_uxtw): Likewise.
(*add3nr_compare0): Likewise.
(3): Likewise.
(*si3_uxtw): Likewise.
(*and3_compare0): Likewise.
(*andsi3_compare0_uxtw): Likewise.
(@aarch64_and3nr_compare0): Likewise.

Diff:
---
 gcc/config/aarch64/aarch64-sve.md  |  56 ++--
 gcc/config/aarch64/aarch64-sve2.md |  28 +-
 gcc/config/aarch64/aarch64.md  | 102 ++---
 3 files changed, 93 insertions(+), 93 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-sve.md 
b/gcc/config/aarch64/aarch64-sve.md
index f39af6e24d51..bf0e57df62dc 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3984,8 +3984,8 @@
 (match_operand:SVE_I_SIMD_DI 3 
"aarch64_sve__operand"))]
  UNSPEC_PRED_X))]
   "TARGET_SVE"
-  {@ [ cons: =0 , 1   , 2  , 3 ; attrs: movprfx ]
- [ w, Upl , %0 ,  ; *  ] #
+  {@ [ cons: =0 , 1   , %2 , 3 ; attrs: movprfx ]
+ [ w, Upl , 0  ,  ; *  ] #
  [ w, Upl , 0  , w ; *  ] 
\t%Z0., %1/m, %Z0., %Z3.
  [ ?&w  , Upl , w  ,  ; yes] #
  [ ?&w  , Upl , w  , w ; yes] movprfx\t%Z0, 
%Z2\;\t%Z0., %1/m, %Z0., %Z3.
@@ -4114,8 +4114,8 @@
  (match_operand:SVE_I 1 "register_operand")
  (match_operand:SVE_I 2 "aarch64_sve_add_operand")))]
   "TARGET_SVE"
-  {@ [ cons: =0 , 1  , 2   ; attrs: movprfx ]
- [ w, %0 , vsa ; *  ] add\t%0., %0., 
#%D2
+  {@ [ cons: =0 , %1 , 2   ; attrs: movprfx ]
+ [ w, 0  , vsa ; *  ] add\t%0., %0., 
#%D2
  [ w, 0  , vsn ; *  ] sub\t%0., %0., 
#%N2
  [ w, 0  , vsi ; *  ] << 
aarch64_output_sve_vector_inc_dec ("%0.", operands[2]);
  [ ?w   , w  , vsa ; yes] movprfx\t%0, 
%1\;add\t%0., %0., #%D2
@@ -4333,8 +4333,8 @@
   (match_dup 3))]
UNSPEC_PRED_X)))]
   "TARGET_SVE"
-  {@ [ cons: =0 , 1   , 2  , 3 ; attrs: movprfx ]
- [ w, Upl , %0 , w ; *  ] abd\t%0., %1/m, 
%0., %3.
+  {@ [ cons: =0 , 1   , %2 , 3 ; attrs: movprfx ]
+ [ w, Upl , 0  , w ; *  ] abd\t%0., %1/m, 
%0., %3.
 

[gcc r15-7796] arm: remove some redundant zero_extend ops on thumb1

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:2a502f9e4c5c6a8e908ef1b0b5c03fb2e4bd4390

commit r15-7796-g2a502f9e4c5c6a8e908ef1b0b5c03fb2e4bd4390
Author: Richard Earnshaw 
Date:   Mon Mar 3 15:30:58 2025 +

arm: remove some redundant zero_extend ops on thumb1

The code in gcc.target/unsigned-extend-1.c really should not need an
unsigned extension operations when the optimizers are used.  For Arm
and thumb2 that is indeed the case, but for thumb1 code it gets more
complicated as there are too many instructions for combine to look at.
For thumb1 we end up with two redundant zero_extend patterns which are
not removed: the first after the subtract instruction and the second of
the final boolean result.

We can partially fix this (for the second case above) by adding a new
split pattern for LEU and GEU patterns which work because the two
instructions for the [LG]EU pattern plus the redundant extension
instruction are combined into a single insn, which we can then split
using the 3->2 method back into the two insns of the [LG]EU sequence.

Because we're missing the optimization for all thumb1 cases (not just
those architectures with UXTB), I've adjust the testcase to detect all
the idioms that we might use for zero-extending a value, namely:

   UXTB
   AND ...#255 (in thumb1 this would require a register to hold 255)
   LSL ... #24; LSR ... #24

but I've also marked this test as XFAIL for thumb1 because we can't yet
eliminate the first of the two extend instructions.

gcc/
* config/arm/thumb1.md (split patterns for GEU and LEU): New.

gcc/testsuite:
* gcc.target/arm/unsigned-extend-1.c: Expand check for any
insn suggesting a zero-extend.  XFAIL for thumb1 code.

Diff:
---
 gcc/config/arm/thumb1.md | 28 
 gcc/testsuite/gcc.target/arm/unsigned-extend-1.c |  4 ++--
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 548c36979f12..f9e89e991d9b 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -1810,6 +1810,34 @@
(set_attr "type" "multiple")]
 )
 
+;; Re-split an LEU/GEU sequence if combine tries to oversimplify a 3-plus
+;; insn sequence.  Beware of the early-clobber of operand0
+(define_split
+ [(set (match_operand:SI 0 "s_register_operand")
+   (leu:SI (match_operand:SI 1 "s_register_operand")
+  (match_operand:SI 2 "s_register_operand")))]
+ "TARGET_THUMB1
+  && !reg_overlap_mentioned_p (operands[0], operands[1])
+  && !reg_overlap_mentioned_p (operands[0], operands[2])"
+ [(set (match_dup 0) (const_int 0))
+  (set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
+ (geu:SI (match_dup 2) (match_dup 1]
+ {}
+)
+
+(define_split
+ [(set (match_operand:SI 0 "s_register_operand")
+   (geu:SI (match_operand:SI 1 "s_register_operand")
+  (match_operand:SI 2 "thumb1_cmp_operand")))]
+ "TARGET_THUMB1
+  && !reg_overlap_mentioned_p (operands[0], operands[1])
+  && !reg_overlap_mentioned_p (operands[0], operands[2])"
+ [(set (match_dup 0) (const_int 0))
+  (set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
+ (geu:SI (match_dup 1) (match_dup 2]
+ {}
+)
+
 
 (define_insn "*thumb_jump"
   [(set (pc)
diff --git a/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c 
b/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
index 3b4ab048fb09..fa3d34400bfa 100644
--- a/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
+++ b/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
@@ -5,5 +5,5 @@ unsigned char foo (unsigned char c)
 {
   return (c >= '0') && (c <= '9');
 }
-
-/* { dg-final { scan-assembler-not "uxtb" } } */
+/* We shouldn't need any zero-extension idioms here.  */
+/* { dg-final { scan-assembler-not "\t(uxtb|and|lsr|lsl)" { xfail arm_thumb1 } 
} } */

[gcc r15-7889] arm: make arm_neon.h compatible with '-march= -mfloat-abi=softfp'

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:104d86ceb14bfa30e6b9fdff494f3ce7246f46d0

commit r15-7889-g104d86ceb14bfa30e6b9fdff494f3ce7246f46d0
Author: Richard Earnshaw 
Date:   Fri Mar 7 15:17:14 2025 +

arm: make arm_neon.h compatible with '-march= -mfloat-abi=softfp'

With -mfpu set to auto, an architecture specification that lacks
floating-point, but has -mfloat-abi=softfp will cause a misleading
error.  Specifically, if we have

gcc -c test.c -mfloat-abi=softfp -march=armv7-a -mfpu=auto

where test.c contains #include 

then we get a misleading error:

test.c:11:2: error: #error "NEON intrinsics not available with the
soft-float ABI.  Please use -mfloat-abi=softfp or -mfloat-abi=hard"

... the error message is advising us to add -mfloat-abi=softfp when we
already have it.

The difficulty is that we can't directly detect the softfp abi from
the available set of pre-defines.

Consider the options in this table, assuming -mfpu=auto:

-mfloat-abi
hardsoftfp  soft
   +---
 -march=armv7-a|*build-error*   __ARM_FP=0  __ARM_FP=0
 -march=armv7-a+fp |__ARM_FP=12 __ARM_FP=12 __ARM_FP=0

However, for the first line, if we subsequently add
 #pragma GCC target ("fpu=vfp")
then the value of __ARM_FP will change as follows:

-mfloat-abi
hardsoftfp  soft
   +---
 -march=armv7-a|*build-error*   __ARM_FP=12 __ARM_FP=0
 -march=armv7-a+fp |__ARM_FP=12 __ARM_FP=12 __ARM_FP=0

We can therefore distinguish between the soft and softfp ABIs by
temporarily forcing VFP instructions into the ISA.  If __ARM_FP is
still zero after doing this then we must be using the soft ABI.

gcc:
* config/arm/arm_neon.h: Try harder to detect if we have
the softfp ABI enabled.

Diff:
---
 gcc/config/arm/arm_neon.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 578ada88fa69..cba50de07204 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -27,7 +27,21 @@
 #ifndef _GCC_ARM_NEON_H
 #define _GCC_ARM_NEON_H 1
 
+/* This header is only useful if we're compiling with -mfloat-abi=hard or
+   -mfloat-abi=softfp.  But we can't detect that directly here as the
+   compiler does not provide a pre-define for it.  However, we can check
+   whether forcing VFP will cause __ARM_FP to become defined and use that.  */
+
+#pragma GCC push_options
+#pragma GCC target ("fpu=vfp")
 #ifndef __ARM_FP
+#define __ARM_SOFT_ABI 1
+#else
+#define __ARM_SOFT_ABI 0
+#endif
+#pragma GCC pop_options
+
+#if __ARM_SOFT_ABI
 #error "NEON intrinsics not available with the soft-float ABI.  Please use 
-mfloat-abi=softfp or -mfloat-abi=hard"
 #else
 
@@ -21489,4 +21503,7 @@ vst4q_lane_bf16 (bfloat16_t * __a, bfloat16x8x4_t __b, 
const int __c)
 #pragma GCC pop_options
 
 #endif
+
+#undef __ARM_SOFT_ABI
+
 #endif

[gcc r15-7890] arm: testsuite: improve guard checks for arm_neon.h

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:b7f5d9114801716924a67ea393f0c30ab793e505

commit r15-7890-gb7f5d9114801716924a67ea393f0c30ab793e505
Author: Richard Earnshaw 
Date:   Tue Mar 4 16:17:32 2025 +

arm: testsuite: improve guard checks for arm_neon.h

The header file arm_neon.h provides the Advanced SIMD intrinsics that
are available on armv7 or later A & R profile cores.  However, they
are not compatible with M-profile and we also need to ensure that the
FP instructions are enabled (with -mfloat-abi=softfp/hard).  That
leads to some complicated checking as arm_neon.h includes stdint.h
and, at least on linux, that can require that the appropriate ABI
bits/ headers are also installed.

This patch adds a new check to target-supports.exp to establish the
minimal set of option overrides needed to enable use of this header in
a test.

gcc/testsuite:
* lib/target-supports.exp
(check_effective_target_arm_neon_h_ok_nocache): New function.
(check_effective_target_arm_neon_h_ok): Likewise.
(add_options_for_arm_neon_h): Likewise.
(check_effective_target_arm_libc_fp_abi_ok_nocache): Allow any
Arm target, not just arm32.
* gcc.target/arm/attr-neon-builtin-fail.c: Use it.
* gcc.target/arm/attr-neon-builtin-fail2.c: Likewise.
* gcc.target/arm/attr-neon-fp16.c: Likewise.
* gcc.target/arm/attr-neon2.c: Likewise.

Diff:
---
 .../gcc.target/arm/attr-neon-builtin-fail.c|  6 +--
 .../gcc.target/arm/attr-neon-builtin-fail2.c   |  5 +-
 gcc/testsuite/gcc.target/arm/attr-neon-fp16.c  |  4 +-
 gcc/testsuite/gcc.target/arm/attr-neon2.c  |  5 +-
 gcc/testsuite/lib/target-supports.exp  | 53 +-
 5 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c 
b/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c
index fb6e0b9cd66a..645d708f0050 100644
--- a/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c
+++ b/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c
@@ -1,9 +1,8 @@
 /* Check that calling a neon builtin from a function compiled with vfp fails.  
*/
 /* { dg-do compile } */
-/* { dg-require-effective-target arm_fp_ok } */
-/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm_neon_h_ok } */
 /* { dg-options "-O2" } */
-/* { dg-add-options arm_fp } */
+/* { dg-add-options arm_neon_h } */
 
 #include 
 
@@ -15,4 +14,3 @@ foo (uint8x16_t *p)
 }
 
 /* { dg-error "inlining failed in call to 'always_inline'" "" { target *-*-* } 
0 } */
-
diff --git a/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail2.c 
b/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail2.c
index 9cb5a2ebb905..ed0c4634b772 100644
--- a/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail2.c
+++ b/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail2.c
@@ -1,8 +1,8 @@
 /* Check that calling a neon builtin from a function compiled with vfp fails.  
*/
 /* { dg-do compile } */
-/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-require-effective-target arm_neon_h_ok } */
 /* { dg-options "-O2" } */
-/* { dg-add-options arm_vfp } */
+/* { dg-add-options arm_neon_h } */
 
 extern __simd64_int8_t a, b;
 
@@ -13,4 +13,3 @@ foo (__simd128_int16_t *p)
   *p = (__simd128_int16_t)__builtin_neon_vaddlsv8qi (a, b); /* { dg-error "You 
must enable NEON instructions .*" } */
 
 }
-
diff --git a/gcc/testsuite/gcc.target/arm/attr-neon-fp16.c 
b/gcc/testsuite/gcc.target/arm/attr-neon-fp16.c
index d7b75645bc45..a5982604f9ed 100644
--- a/gcc/testsuite/gcc.target/arm/attr-neon-fp16.c
+++ b/gcc/testsuite/gcc.target/arm/attr-neon-fp16.c
@@ -1,8 +1,8 @@
 /* { dg-do compile } */
 /* { dg-skip-if "-mpure-code supports M-profile only and without Neon" { *-*-* 
} { "-mpure-code" } } */
-/* { dg-require-effective-target arm_fp_ok } */
+/* { dg-require-effective-target arm_neon_h_ok } */
 /* { dg-options "-mfp16-format=ieee" } */
-/* { dg-add-options arm_fp } */
+/* { dg-add-options arm_neon_h } */
 
 #include "arm_neon.h"
 
diff --git a/gcc/testsuite/gcc.target/arm/attr-neon2.c 
b/gcc/testsuite/gcc.target/arm/attr-neon2.c
index a7a72dac379d..c0f7667c2dcd 100644
--- a/gcc/testsuite/gcc.target/arm/attr-neon2.c
+++ b/gcc/testsuite/gcc.target/arm/attr-neon2.c
@@ -1,8 +1,7 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-require-effective-target arm_fp_ok } */
+/* { dg-require-effective-target arm_neon_h_ok } */
 /* { dg-options "-Ofast" } */
-/* { dg-add-options arm_fp } */
+/* { dg-add-options arm_neon_h } */
 
 /* Reset fpu to a value compatible with the next pragmas.  */
 #pragma GCC target ("fpu=vfp")
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index d02d1fa9becb..a184ef37ccb4 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5127,7 

[gcc r15-7954] arm: testsuite: fix arm_neon_h checks with conflicting cpu/arch

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:1b7a05770833eb210783ec8babd0027ec237d191

commit r15-7954-g1b7a05770833eb210783ec8babd0027ec237d191
Author: Richard Earnshaw 
Date:   Tue Mar 11 10:48:54 2025 +

arm: testsuite: fix arm_neon_h checks with conflicting cpu/arch

GCC will complain if the -mcpu flag specifies a different architecture
to that specified in -march, but if the floating-point ABI is "soft",
then differences in the floating-point architecture features are
ignored.

However, the arm_libc_fp_abi checks whether we change the FP ABI by
adding -mfloat-abi=hard/softfp to override the defaults.  If that
fails it won't add anything.

Unfortunately arm_neon_h_ok wasn't correctly checking whether the libc
check had worked and just assumed that it would always add something
to enable FP.  That's insufficient and we need to consider this failure.
We simply mark tests as unsupported in this case.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp
(check_effective_target_arm_neon_h_ok_nocache): Return zero if
check_effective_target_arm_libc_fp_abi_ok reports failure.

Diff:
---
 gcc/testsuite/lib/target-supports.exp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index a184ef37ccb4..c456f7d2c6fa 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5167,7 +5167,8 @@ proc add_options_for_arm_libc_fp_abi { flags } {
 proc check_effective_target_arm_neon_h_ok_nocache { } {
 # none-arm or thumb1 cannot support neon, so there's no point in
 # looking further.
-if { [istarget arm*-*-*] } {
+if { [istarget arm*-*-*]
+&& [check_effective_target_arm_libc_fp_abi_ok]} {
global et_arm_neon_h_flags
set base_flags [add_options_for_arm_libc_fp_abi ""]
foreach flags {"" "-mfpu=auto" "-marm" "-marm -mfpu=auto" \

[gcc r15-7727] testsuite: arm: Avoid incremental link warnings in pr61123-enum-size

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:767a7a06915651da173b6751959a47487351ed3a

commit r15-7727-g767a7a06915651da173b6751959a47487351ed3a
Author: Richard Earnshaw 
Date:   Thu Feb 27 15:11:47 2025 +

testsuite: arm: Avoid incremental link warnings in pr61123-enum-size

This test uses incremental linking, but that can generate warnings if
the LTO step contains a mix of LTO and non-LTO object files (this can
happen when there's a testglue file that is normally included during
linking).

We don't care about the testglue, though, so just tell the LTO
optimizer to generate nolto-rel output, which is what it is falling
back to anyway.

gcc/testsuite:
* gcc.target/arm/lto/pr61123-enum-size_0.c: (dg-lto-options) Move
linker related options to ...
(dg-extra-ld-options): ... here.  Add -flinker-output=nolto-rel.

Diff:
---
 gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c 
b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c
index c23f9d857605..4ccbeb39f43f 100644
--- a/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c
+++ b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c
@@ -1,5 +1,6 @@
 /* { dg-lto-do link } */
-/* { dg-lto-options { { -fno-short-enums -Wl,-Ur,--no-enum-size-warning -Os 
-nostdlib -flto } } } */
+/* { dg-lto-options { { -fno-short-enums -Os -flto } } } */
+/* { dg-extra-ld-options "-flinker-output=nolto-rel 
-Wl,-Ur,--no-enum-size-warning -nostdlib" } */
 
 #include 

[gcc r15-7998] arm: allow type-punning subregs in vpr_register_operand [PR115439]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:6e4045513d789587b2c7750e9016c7035b461299

commit r15-7998-g6e4045513d789587b2c7750e9016c7035b461299
Author: Richard Earnshaw 
Date:   Mon Mar 10 14:12:38 2025 +

arm: allow type-punning subregs in vpr_register_operand [PR115439]

Subregs that only change the mode of an operand (ie don't change the
size) should be safe for the VPR register.  If we don't permit them
we may end up with some redundant copy instructions.

gcc:
PR target/115439
* config/arm/predicates.md (vpr_register_operand): Allow 
type-punning
subregs.

Diff:
---
 gcc/config/arm/predicates.md | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 5c78421ff697..75c06d9be255 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -99,11 +99,21 @@
 })
 
 (define_predicate "vpr_register_operand"
-  (match_code "reg")
+  (match_code "reg,subreg")
 {
-  return REG_P (op)
+  if (SUBREG_P (op))
+{
+  /* Only allow subregs if they are strictly type punning. */
+  if ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (op)))
+  != GET_MODE_SIZE (GET_MODE (op)))
+ || SUBREG_BYTE (op) != 0)
+   return false;
+  op = SUBREG_REG (op);
+}
+
+  return (REG_P (op)
  && (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || IS_VPR_REGNUM (REGNO (op)));
+ || IS_VPR_REGNUM (REGNO (op;
 })
 
 (define_predicate "imm_for_neon_inv_logic_operand"

[gcc r15-7836] arm: Fix signedness of vld1q intrinsic parms [PR118942]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:4d0a333ef13e2da140cd44c4941b20f48a80dc0f

commit r15-7836-g4d0a333ef13e2da140cd44c4941b20f48a80dc0f
Author: Hannes Braun 
Date:   Thu Feb 20 15:09:41 2025 +0100

arm: Fix signedness of vld1q intrinsic parms [PR118942]

vld1q_s8_x3, vld1q_s16_x3, vld1q_s8_x4 and vld1q_s16_x4 were expecting
pointers to unsigned integers. These parameters should be pointers to
signed integers.

gcc/ChangeLog:
PR target/118942
* config/arm/arm_neon.h (vld1q_s8_x3): Use int8_t instead of
uint16_t.
(vld1q_s16_x3): Use int16_t instead of uint16_t.
(vld1q_s8_x4): Likewise.
(vld1q_s16_x4): Likewise.

gcc/testsuite/ChangeLog:
PR target/118942
* gcc.target/arm/simd/vld1q_base_xN_1.c: Add -Wpointer-sign.

Signed-off-by: Hannes Braun 

Diff:
---
 gcc/config/arm/arm_neon.h   | 8 
 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 5b1c55c8d9f8..578ada88fa69 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10854,7 +10854,7 @@ vld1q_s64_x2 (const int64_t * __a)
 
 __extension__ extern __inline int8x16x3_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s8_x3 (const uint8_t * __a)
+vld1q_s8_x3 (const int8_t * __a)
 {
   union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a);
@@ -10863,7 +10863,7 @@ vld1q_s8_x3 (const uint8_t * __a)
 
 __extension__ extern __inline int16x8x3_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s16_x3 (const uint16_t * __a)
+vld1q_s16_x3 (const int16_t * __a)
 {
   union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a);
@@ -10890,7 +10890,7 @@ vld1q_s64_x3 (const int64_t * __a)
 
 __extension__ extern __inline int8x16x4_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s8_x4 (const uint8_t * __a)
+vld1q_s8_x4 (const int8_t * __a)
 {
   union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a);
@@ -10899,7 +10899,7 @@ vld1q_s8_x4 (const uint8_t * __a)
 
 __extension__ extern __inline int16x8x4_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s16_x4 (const uint16_t * __a)
+vld1q_s16_x4 (const int16_t * __a)
 {
   union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a);
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
index 01b29b600847..c73afe2b723b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -1,6 +1,6 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-save-temps -O2" } */
+/* { dg-options "-save-temps -O2 -Wpointer-sign" } */
 /* { dg-add-options arm_neon } */
 
 #include "arm_neon.h"

[gcc r14-11385] arm: Fix signedness of vld1q intrinsic parms [PR118942]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:6e17b356a78635e66d1a895b86fbcc0bde0589bb

commit r14-11385-g6e17b356a78635e66d1a895b86fbcc0bde0589bb
Author: Hannes Braun 
Date:   Thu Feb 20 15:09:41 2025 +0100

arm: Fix signedness of vld1q intrinsic parms [PR118942]

vld1q_s8_x3, vld1q_s16_x3, vld1q_s8_x4 and vld1q_s16_x4 were expecting
pointers to unsigned integers. These parameters should be pointers to
signed integers.

gcc/ChangeLog:
PR target/118942
* config/arm/arm_neon.h (vld1q_s8_x3): Use int8_t instead of
uint16_t.
(vld1q_s16_x3): Use int16_t instead of uint16_t.
(vld1q_s8_x4): Likewise.
(vld1q_s16_x4): Likewise.

gcc/testsuite/ChangeLog:
PR target/118942
* gcc.target/arm/simd/vld1q_base_xN_1.c: Add -Wpointer-sign.

Signed-off-by: Hannes Braun 
(cherry picked from commit 4d0a333ef13e2da140cd44c4941b20f48a80dc0f)

Diff:
---
 gcc/config/arm/arm_neon.h   | 8 
 gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 8e70c7177315..11d2dc06877a 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -10854,7 +10854,7 @@ vld1q_s64_x2 (const int64_t * __a)
 
 __extension__ extern __inline int8x16x3_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s8_x3 (const uint8_t * __a)
+vld1q_s8_x3 (const int8_t * __a)
 {
   union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x3v16qi ((const __builtin_neon_qi *) __a);
@@ -10863,7 +10863,7 @@ vld1q_s8_x3 (const uint8_t * __a)
 
 __extension__ extern __inline int16x8x3_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s16_x3 (const uint16_t * __a)
+vld1q_s16_x3 (const int16_t * __a)
 {
   union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x3v8hi ((const __builtin_neon_hi *) __a);
@@ -10890,7 +10890,7 @@ vld1q_s64_x3 (const int64_t * __a)
 
 __extension__ extern __inline int8x16x4_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s8_x4 (const uint8_t * __a)
+vld1q_s8_x4 (const int8_t * __a)
 {
   union { int8x16x4_t __i; __builtin_neon_xi __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x4v16qi ((const __builtin_neon_qi *) __a);
@@ -10899,7 +10899,7 @@ vld1q_s8_x4 (const uint8_t * __a)
 
 __extension__ extern __inline int16x8x4_t
 __attribute__  ((__always_inline__, __gnu_inline__, __artificial__))
-vld1q_s16_x4 (const uint16_t * __a)
+vld1q_s16_x4 (const int16_t * __a)
 {
   union { int16x8x4_t __i; __builtin_neon_xi __o; } __rv;
   __rv.__o = __builtin_neon_vld1q_x4v8hi ((const __builtin_neon_hi *) __a);
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c 
b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
index 01b29b600847..c73afe2b723b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -1,6 +1,6 @@
 /* { dg-do assemble } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-save-temps -O2" } */
+/* { dg-options "-save-temps -O2 -Wpointer-sign" } */
 /* { dg-add-options arm_neon } */
 
 #include "arm_neon.h"

[gcc r15-8008] arm: testsuite: remove gcc.target/arm/lp1243022.c [PR117931]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:9ee6c2619b256878d43800a16f7b98b3ddf59e52

commit r15-8008-g9ee6c2619b256878d43800a16f7b98b3ddf59e52
Author: Richard Earnshaw 
Date:   Wed Mar 12 18:48:55 2025 +

arm: testsuite: remove gcc.target/arm/lp1243022.c [PR117931]

This test has been failing since gcc-6.  The test was always very
fragile anyway since it relied on an auto-inc being created and then
split by the subreg2 (later the subreg3) pass.  But the code to get
precisely these conditions was very long-winded and unlikely to be
immune to other changes in the compiler (as proved to be the case).

There's no obvious way to recreate the exact conditions we were
testing for, so just remove the test.

gcc/testsuite:

PR target/117931
* gcc.target/arm/lp1243022.c: Delete non-functional test.

Diff:
---
 gcc/testsuite/gcc.target/arm/lp1243022.c | 202 ---
 1 file changed, 202 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/lp1243022.c 
b/gcc/testsuite/gcc.target/arm/lp1243022.c
deleted file mode 100644
index 11025eebd712..
--- a/gcc/testsuite/gcc.target/arm/lp1243022.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/* { dg-do compile { target arm_thumb2 } } */
-/* { dg-options "-O2 -fdump-rtl-subreg2" } */
-
-/* { dg-final { scan-rtl-dump "REG_INC" "subreg2" { target { ! arm_neon } } } 
} */
-struct device;
-typedef unsigned int __u32;
-typedef unsigned long long u64;
-typedef __u32 __le32;
-typedef u64 dma_addr_t;
-typedef unsigned gfp_t;
-int dev_warn (const struct device *dev, const char *fmt, ...);
-struct usb_bus
-{
-struct device *controller;
-};
-struct usb_hcd
-{
-struct usb_bus self;
-};
-struct xhci_generic_trb
-{
-__le32 field[4];
-};
-union xhci_trb
-{
-struct xhci_generic_trb generic;
-};
-struct xhci_segment
-{
-union xhci_trb *trbs;
-dma_addr_t dma;
-};
-struct xhci_ring
-{
-struct xhci_segment *first_seg;
-};
-struct xhci_hcd
-{
-struct xhci_ring *cmd_ring;
-struct xhci_ring *event_ring;
-};
-struct usb_hcd *xhci_to_hcd (struct xhci_hcd *xhci)
-{
-}
-dma_addr_t xhci_trb_virt_to_dma (struct xhci_segment * seg,
-union xhci_trb * trb);
-struct xhci_segment *trb_in_td (struct xhci_segment *start_seg,
-   dma_addr_t suspect_dma);
-int
-xhci_test_trb_in_td (struct xhci_hcd *xhci, struct xhci_segment *input_seg,
-union xhci_trb *start_trb, union xhci_trb *end_trb,
-dma_addr_t input_dma, struct xhci_segment *result_seg,
-char *test_name, int test_number)
-{
-unsigned long long start_dma;
-unsigned long long end_dma;
-struct xhci_segment *seg;
-start_dma = xhci_trb_virt_to_dma (input_seg, start_trb);
-end_dma = xhci_trb_virt_to_dma (input_seg, end_trb);
-{
-dev_warn (xhci_to_hcd (xhci)->self.controller,
-  "%d\n", test_number);
-dev_warn (xhci_to_hcd (xhci)->self.controller,
-  "Expected seg %p, got seg %p\n", result_seg, seg);
-}
-}
-int
-xhci_check_trb_in_td_math (struct xhci_hcd *xhci, gfp_t mem_flags)
-{
-struct
-{
-dma_addr_t input_dma;
-struct xhci_segment *result_seg;
-}
-simple_test_vector[] =
-{
-{
-0, ((void *) 0)
-}
-,
-{
-xhci->event_ring->first_seg->dma - 16, ((void *) 0)}
-,
-{
-xhci->event_ring->first_seg->dma - 1, ((void *) 0)}
-,
-{
-xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg}
-,
-{
-xhci->event_ring->first_seg->dma + (64 - 1) * 16,
-xhci->event_ring->first_seg
-}
-,
-{
-xhci->event_ring->first_seg->dma + (64 - 1) * 16 + 1, ((void 
*) 0)}
-,
-{
-xhci->event_ring->first_seg->dma + (64) * 16, ((void *) 0)}
-,
-{
-(dma_addr_t) (~0), ((void *) 0)
-}
-};
-struct
-{
-struct xhci_segment *input_seg;
-union xhci_trb *start_trb;
-union xhci_trb *end_trb;
-dma_addr_t input_dma;
-struct xhci_segment *result_seg;
-}
-complex_test_vector[] =
-{
-{
-.input_seg = xhci->event_ring->first_seg,.start_trb =
-xhci->event_ring->first_seg->trbs,.end_trb =
-&xhci->event_ring->first_seg->trbs[64 - 1],.input_dma =
-xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0),
-}
-,
-{
-.input_seg = xhci->event_ring->first_seg,.start_trb =
-xhci->event_ring->first_seg->trbs,.end_trb =
-&xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma =
-xhc

[gcc r15-9064] arm: testsuite: fix vect-fmaxmin.c test

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:f30e180194bfbcd7594566ef050534388be31e8d

commit r15-9064-gf30e180194bfbcd7594566ef050534388be31e8d
Author: Richard Earnshaw 
Date:   Mon Mar 31 10:37:11 2025 +0100

arm: testsuite: fix vect-fmaxmin.c test

This is another case of a test that was both an executable test
requiring specific hardware and an assembler scan test.  The
requirement for the hardware was masking some useful testing that
could be done (by scanning the assembly output) on almost all test
runs.  Fixed in a similar manner to fmaxmin{,-2}.c by splitting the
test into two, one that scans the assembler output and one that
executes the compiled code if suitable hardware is available.

The masked issue was that this test was expecting vectorization to
occur that was incorrect given the options passed.  For correct
vectorization we need -funsafe-math-optimizations as the vector
version of the single-precision operation will apply a truncation of
denormal values.

gcc/testsuite/ChangeLog:

* gcc.target/arm/vect-fmaxmin-2.c: New compile test.  Split from ...
* gcc.target/arm/vect-fmaxmin.c: ... here.  Remove scan-assembler
subtests.  For both, add -funsafe-math-optimizations.

Diff:
---
 gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c | 14 ++
 gcc/testsuite/gcc.target/arm/vect-fmaxmin.c   | 10 +-
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c 
b/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c
new file mode 100644
index ..57b0a3ad8019
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vect-fmaxmin-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_hard_ok } */
+/* { dg-options "-O2 -ftree-vectorize -funsafe-math-optimizations -fno-inline 
-save-temps" } */
+/* { dg-add-options arm_arch_v8a_hard } */
+
+#include "fmaxmin.x"
+
+/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, 
q\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, 
q\[0-9\]+" 1 } } */
+
+/* NOTE: There are no double precision vector versions of vmaxnm/vminnm.  */
+/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, 
d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, 
d\[0-9\]+" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c 
b/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c
index ba45c4d379e7..89dc14bd594e 100644
--- a/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c
+++ b/gcc/testsuite/gcc.target/arm/vect-fmaxmin.c
@@ -1,14 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target arm_v8_neon_hw } */
-/* { dg-options "-O2 -ftree-vectorize -fno-inline -march=armv8-a -save-temps" 
} */
+/* { dg-options "-O2 -ftree-vectorize -fno-inline -funsafe-math-optimizations" 
} */
 /* { dg-add-options arm_v8_neon } */
 
 #include "fmaxmin.x"
-
-/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, 
q\[0-9\]+" 1 } } */
-/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, 
q\[0-9\]+" 1 } } */
-
-/* NOTE: There are no double precision vector versions of vmaxnm/vminnm.  */
-/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, 
d\[0-9\]+" 1 } } */
-/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, 
d\[0-9\]+" 1 } } */
-

[gcc r15-9200] arm: testsuite: restore dg-do-what-default in mve.exp

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:6e79fa4a25769b2facf519aaf04b2a757dd3c887

commit r15-9200-g6e79fa4a25769b2facf519aaf04b2a757dd3c887
Author: Richard Earnshaw 
Date:   Fri Apr 4 13:38:35 2025 +0100

arm: testsuite: restore dg-do-what-default in mve.exp

On Arm, running

make check-gcc RUNTESTFLAGS="dwarf2.exp=pr43190.c"

with a target list of "arm-qemu{,-mthumb}"

results in no errors.  But running it with

make check-gcc RUNTESTFLAGS="{mve,dwarf2}.exp=pr43190.c"

results in unresolved tests while running the thumb variant.  The problem
is that mve.exp is changing dg-do-what-default to "assemble", but failing
to restore the original value once its tests are complete.  The result is
that all subsequent tests run with an incorrect underlying default value.

The fix is easy - save dg-do-what-default and restore it after the tests
are complete.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/mve.exp: Save dg-do-what-default before
changing it.  Restore it once done.

Diff:
---
 gcc/testsuite/gcc.target/arm/mve/mve.exp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/testsuite/gcc.target/arm/mve/mve.exp 
b/gcc/testsuite/gcc.target/arm/mve/mve.exp
index a5d8511afdac..9dc56c9b2d9f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/mve.exp
+++ b/gcc/testsuite/gcc.target/arm/mve/mve.exp
@@ -35,6 +35,7 @@ global dg_runtest_extra_prunes
 set dg_runtest_extra_prunes ""
 lappend dg_runtest_extra_prunes "warning: switch '-m(cpu|arch)=.*' conflicts 
with switch '-m(cpu|arch)=.*'"
 
+set saved-dg-do-what-default ${dg-do-what-default}
 set dg-do-what-default "assemble"
 
 # Initialize `dg'.
@@ -53,6 +54,8 @@ dg-runtest [lsort [glob -nocomplain 
$srcdir/$subdir/general-c/*.\[cCS\]]] \
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
"" $DEFAULT_CFLAGS
 
+set dg-do-what-default ${saved-dg-do-what-default}
+
 # All done.
 set dg_runtest_extra_prunes ""
 dg-finish

[gcc r15-8722] arm: testsuite: tighten scan-assembler in unaligned-memcpy-4.c

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:beec790e2b5d55058c4323731ccffd07c203fd71

commit r15-8722-gbeec790e2b5d55058c4323731ccffd07c203fd71
Author: Richard Earnshaw 
Date:   Mon Mar 24 11:22:05 2025 +

arm: testsuite: tighten scan-assembler in unaligned-memcpy-4.c

The scan-assembler-not pattern in this test was too broad and matched
the 'unaligned' from the .file directive from the file name.  Tighten it
to require a leading comment character.

gcc/testsuite:

* gcc.target/arm/unaligned-memcpy-4.c: Tighten scan-assembler-not
pattern.

Diff:
---
 gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c 
b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c
index 3f074e30d864..1c79f3bf791c 100644
--- a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c
+++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c
@@ -23,4 +23,4 @@ int main ()
 }
 
 /* There should be no 'unaligned' comments.  */
-/* { dg-final { scan-assembler-not "unaligned" } } */
+/* { dg-final { scan-assembler-not "@ unaligned" } } */

[gcc r15-8899] arm: testsuite: skip mtp tests on thumb1

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:ca0a8421f7aa2191b2b867ff24888223d6cde433

commit r15-8899-gca0a8421f7aa2191b2b867ff24888223d6cde433
Author: Richard Earnshaw 
Date:   Tue Mar 25 16:30:36 2025 +

arm: testsuite: skip mtp tests on thumb1

These tests need access to the MRC instruction, but that isn't part of
of the Thumb1 ISA.  So skip the tests when this isn't the case.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mtp_1.c: Require arm32.
* gcc.target/arm/mtp_2.c: Likewise.
* gcc.target/arm/mtp_3.c: Likewise.
* gcc.target/arm/mtp_4.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/arm/mtp_1.c | 1 +
 gcc/testsuite/gcc.target/arm/mtp_2.c | 1 +
 gcc/testsuite/gcc.target/arm/mtp_3.c | 1 +
 gcc/testsuite/gcc.target/arm/mtp_4.c | 1 +
 4 files changed, 4 insertions(+)

diff --git a/gcc/testsuite/gcc.target/arm/mtp_1.c 
b/gcc/testsuite/gcc.target/arm/mtp_1.c
index 678d27d92344..f78ceb8574e0 100644
--- a/gcc/testsuite/gcc.target/arm/mtp_1.c
+++ b/gcc/testsuite/gcc.target/arm/mtp_1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target tls_native } */
+/* { dg-require-effective-target arm32 } */
 /* { dg-options "-O -mtp=cp15" } */
 
 #include "mtp.c"
diff --git a/gcc/testsuite/gcc.target/arm/mtp_2.c 
b/gcc/testsuite/gcc.target/arm/mtp_2.c
index bcb308f2637c..1368fe4a3a3f 100644
--- a/gcc/testsuite/gcc.target/arm/mtp_2.c
+++ b/gcc/testsuite/gcc.target/arm/mtp_2.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target tls_native } */
+/* { dg-require-effective-target arm32 } */
 /* { dg-options "-O -mtp=tpidrprw" } */
 
 #include "mtp.c"
diff --git a/gcc/testsuite/gcc.target/arm/mtp_3.c 
b/gcc/testsuite/gcc.target/arm/mtp_3.c
index 7d5cea3cab61..2ef2e95b62dd 100644
--- a/gcc/testsuite/gcc.target/arm/mtp_3.c
+++ b/gcc/testsuite/gcc.target/arm/mtp_3.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target tls_native } */
+/* { dg-require-effective-target arm32 } */
 /* { dg-options "-O -mtp=tpidruro" } */
 
 #include "mtp.c"
diff --git a/gcc/testsuite/gcc.target/arm/mtp_4.c 
b/gcc/testsuite/gcc.target/arm/mtp_4.c
index 068078df84ed..121fc836513c 100644
--- a/gcc/testsuite/gcc.target/arm/mtp_4.c
+++ b/gcc/testsuite/gcc.target/arm/mtp_4.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target tls_native } */
+/* { dg-require-effective-target arm32 } */
 /* { dg-options "-O -mtp=tpidrurw" } */
 
 #include "mtp.c"

[gcc r15-8897] arm: testsuite: adjust ftest tests

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:91051d60d95156e830423fd258dedfb574b42195

commit r15-8897-g91051d60d95156e830423fd258dedfb574b42195
Author: Richard Earnshaw 
Date:   Tue Mar 25 15:36:02 2025 +

arm: testsuite: adjust ftest tests

The ftest-*.c tests for Arm check certain ACLE mandated macros to ensure
they are correctly defined based on the selected architecture.  ACLE
states that the macro should be defined if the operation exists in
the hardware, but it doesn't have to exist in the current ISA because
and interworking call to the library function will still result in using
the hardware operation (both GCC and Clang agree on this).  So adjust
the tests accordingly.

Whilst cleaning this up, also remove the now redundant dg-skip-if operations
that were testing for incompatible command-line options.  That should now
be a thing of the past as the framework will clean this up more thoroughly
before running the test, or detect incompatible option combinations.

gcc/testsuite/ChangeLog:

* gcc.target/arm/ftest-armv4t-thumb.c:  Expect __ARM_FEATURE_CLZ to 
be
defined.  Remove redundant dg-skip-if rules.
* gcc.target/arm/ftest-armv5t-thumb.c: Likewise.
* gcc.target/arm/ftest-armv5te-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6k-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6z-thumb.c: Likewise.
* gcc.target/arm/ftest-armv7em-thumb.c: Remove redundant dg-skip-if
rules.  Add a require-effective-target for armv7em.
* gcc.target/arm/ftest-armv7a-arm.c: Likewise.
* gcc.target/arm/ftest-armv7a-thumb.c: Likewise.
* gcc.target/arm/ftest-armv7r-arm.c: Likewise.
* gcc.target/arm/ftest-armv7r-thumb.c: Likewise.
* gcc.target/arm/ftest-armv7ve-arm.c: Likewise.
* gcc.target/arm/ftest-armv7ve-thumb.c: Likewise.
* gcc.target/arm/ftest-armv8a-arm.c: Likewise.
* gcc.target/arm/ftest-armv8a-thumb.c: Likewise.
* gcc.target/arm/ftest-armv4-arm.c: Remove redundant dg-skip-if 
rules.
* gcc.target/arm/ftest-armv4t-arm.c: Likewise.
* gcc.target/arm/ftest-armv5t-arm.c: Likewise.
* gcc.target/arm/ftest-armv5te-arm.c: Likewise.
* gcc.target/arm/ftest-armv6-arm.c: Likewise.
* gcc.target/arm/ftest-armv6k-arm.c: Likewise.
* gcc.target/arm/ftest-armv6m-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6t2-arm.c: Likewise.
* gcc.target/arm/ftest-armv6t2-thumb.c: Likewise.
* gcc.target/arm/ftest-armv6z-arm.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c| 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c  | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c| 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c  | 7 +--
 gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c   | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c | 7 +--
 gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c   | 7 +--
 gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c| 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c  | 7 +--
 gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c  | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c   | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c | 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c| 2 --
 gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c  | 7 +--
 gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c| 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c  | 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c | 3 +--
 gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c| 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c  | 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c   | 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c | 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c| 4 +---
 gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c  | 4 +---
 25 files changed, 34 insertions(+), 58 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c 
b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
index 447a8ec16ae6..63d57d41d3f5 100644
--- a/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
+++ b/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
@@ -1,6 +1,4 @@
 /* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } 
{ "-march=armv4" } } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { 
"" } } */
 /* { dg-require-effective-target arm_arch_v4_ok } */
 /* { dg-options "-marm" } */
 /* { dg-add-options arm_arch_v4 } */
diff --git a/gcc/testsuite/gcc.target/arm/ftest-ar

[gcc r15-8891] arm: testsuite: avoid dg-options in primary LTO file

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:927cfea902c330092848bd7a228b714b07d08f6b

commit r15-8891-g927cfea902c330092848bd7a228b714b07d08f6b
Author: Richard Earnshaw 
Date:   Tue Mar 25 13:48:06 2025 +

arm: testsuite: avoid dg-options in primary LTO file

As the primary LTO file in this test, it cannot use dg-options.  Move
the flags from there to dg-lto-options.

gcc/testsuite/ChangeLog:

* gcc.target/arm/lto/pr96939_0.c (dg-options):  Delete.  Move the
options from here ...
(dg-lto-options): ... to here.

Diff:
---
 gcc/testsuite/gcc.target/arm/lto/pr96939_0.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c 
b/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c
index 21d2c1d70a40..8dfbc0610090 100644
--- a/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c
+++ b/gcc/testsuite/gcc.target/arm/lto/pr96939_0.c
@@ -1,8 +1,7 @@
 /* PR target/96939 */
 /* { dg-lto-do link } */
 /* { dg-require-effective-target arm_arch_v8a_link } */
-/* { dg-options "-mcpu=unset -march=armv8-a+simd -mfpu=auto" } */
-/* { dg-lto-options { { -flto -O2 } } } */
+/* { dg-lto-options { { -flto -O2 -mcpu=unset -march=armv8-a+simd -mfpu=auto} 
} } */
 
 extern unsigned crc (unsigned, const void *);
 typedef unsigned (*fnptr) (unsigned, const void *);

[gcc r15-8890] arm: testsuite: update expected output in vect-early-break-cbranch.c

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:2f4c5cf2c9bad6a6207b3377cf3179ed00cfcf11

commit r15-8890-g2f4c5cf2c9bad6a6207b3377cf3179ed00cfcf11
Author: Richard Earnshaw 
Date:   Tue Mar 25 13:31:54 2025 +

arm: testsuite: update expected output in vect-early-break-cbranch.c

Similar to r15-4930-gd56d2f3102ada3, update the branch operations when not
using CBN?Z for inverting the direction of the branch operations.

gcc/testsuite/ChangeLog:

* gcc.target/arm/vect-early-break-cbranch.c: Allow BEQ as well as 
BNE.

Diff:
---
 gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c 
b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c
index 4dc0edd874b4..045f143fb930 100644
--- a/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c
+++ b/gcc/testsuite/gcc.target/arm/vect-early-break-cbranch.c
@@ -18,7 +18,7 @@ int b[N] = {0};
 ** vmovr[0-9]+, s[0-9]+@ int
 ** (
 ** cmp r[0-9]+, #0
-** bne \.L[0-9]+
+** b(ne|eq)\.L[0-9]+
 ** |
 ** cbn?z   r[0-9]+, \.L.+
 ** )
@@ -43,7 +43,7 @@ void f1 ()
 ** vmovr[0-9]+, s[0-9]+@ int
 ** (
 ** cmp r[0-9]+, #0
-** bne \.L[0-9]+
+** b(ne|eq)\.L[0-9]+
 ** |
 ** cbn?z   r[0-9]+, \.L.+
 ** )
@@ -68,7 +68,7 @@ void f2 ()
 ** vmovr[0-9]+, s[0-9]+@ int
 ** (
 ** cmp r[0-9]+, #0
-** bne \.L[0-9]+
+** b(ne|eq)\.L[0-9]+
 ** |
 ** cbn?z   r[0-9]+, \.L.+
 ** )
@@ -94,7 +94,7 @@ void f3 ()
 ** vmovr[0-9]+, s[0-9]+@ int
 ** (
 ** cmp r[0-9]+, #0
-** bne \.L[0-9]+
+** b(ne|eq)\.L[0-9]+
 ** |
 ** cbn?z   r[0-9]+, \.L.+
 ** )
@@ -119,7 +119,7 @@ void f4 ()
 ** vmovr[0-9]+, s[0-9]+@ int
 ** (
 ** cmp r[0-9]+, #0
-** bne \.L[0-9]+
+** b(ne|eq)\.L[0-9]+
 ** |
 ** cbn?z   r[0-9]+, \.L.+
 ** )
@@ -144,7 +144,7 @@ void f5 ()
 ** vmovr[0-9]+, s[0-9]+@ int
 ** (
 ** cmp r[0-9]+, #0
-** bne \.L[0-9]+
+** b(ne|eq)\.L[0-9]+
 ** |
 ** cbn?z   r[0-9]+, \.L.+
 ** )

[gcc r15-8965] arm: don't vectorize fmaxf() unless unsafe math opts are enabled

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:b631ff45f231db55b28b4c92cf1a1b46b3638ddd

commit r15-8965-gb631ff45f231db55b28b4c92cf1a1b46b3638ddd
Author: Richard Earnshaw 
Date:   Wed Mar 26 15:56:18 2025 +

arm: don't vectorize fmaxf() unless unsafe math opts are enabled

This test has presumably been failing since vectorization was enabled
at -O2.  I suspect part of the reason this wasn't picked up sooner is
that the test is a hybrid execution/scan-assembler test and the
execution part requires appropriate hardware.

The problem is that we are vectorizing an expansion of fmaxf() when
the vector version of the instruction does not preserve denormal
values.  This means we should only apply this optimization when
-funsafe-math-optimizations is enabled.

This fix does a few things:

- Moves the expand pattern to vec-common.md.  Although I haven't changed
its behaviour (beyond fixing the bug), this should really be enabled for
MVE as well (but that will need to wait for gcc-16 since the MVE code
needs some additional changes first).
- Adds support for HF mode vectors.
- splits the test that was exposing the bug into two parts: an executable
test and a scan-assembler test.  The scan-assembler version is more
widely enabled, since it does not require a suitable executable environment.

gcc/ChangeLog:

* config/arm/neon.md (3): Move pattern from here...
* config/arm/vec-common.md (3): ... to here.  Convert
to define_expand and disable the pattern when denormal values might
get truncated to zero.  Iterate on VF to add V4HF and V8HF variants.

gcc/testsuite/ChangeLog:

* gcc.target/arm/fmaxmin.c: Move scan-assembler checks to ...
* gcc.target/arm/fmaxmin-2.c: ... here.  New test.

Diff:
---
 gcc/config/arm/neon.md   | 11 ---
 gcc/config/arm/vec-common.md | 11 +++
 gcc/testsuite/gcc.target/arm/fmaxmin-2.c | 12 
 gcc/testsuite/gcc.target/arm/fmaxmin.c   |  9 +
 4 files changed, 24 insertions(+), 19 deletions(-)

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index ef3310605cab..8446dd7f964b 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2738,17 +2738,6 @@
   [(set_attr "type" "neon_fp_minmax_s")]
 )
 
-;; Vector forms for the IEEE-754 fmax()/fmin() functions
-(define_insn "3"
-  [(set (match_operand:VCVTF 0 "s_register_operand" "=w")
-   (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
-  (match_operand:VCVTF 2 "s_register_operand" "w")]
-  VMAXMINFNM))]
-  "TARGET_NEON && TARGET_VFP5"
-  ".\t%0, %1, %2"
-  [(set_attr "type" "neon_fp_minmax_s")]
-)
-
 (define_expand "neon_vpadd"
   [(match_operand:VD 0 "s_register_operand")
(match_operand:VD 1 "s_register_operand")
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 204205cb0b77..a485d057f0f1 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -137,6 +137,17 @@
"ARM_HAVE__ARITH"
 )
 
+;; Vector forms for the IEEE-754 fmax()/fmin() functions
+;; Fixme: Should be enabled for MVE as well, but currently that uses an
+;; incompatible expasion.
+(define_expand "3"
+  [(set (match_operand:VF 0 "s_register_operand" "")
+   (unspec:VF [(match_operand:VF 1 "s_register_operand")
+   (match_operand:VF 2 "s_register_operand")]
+  VMAXMINFNM))]
+  "TARGET_NEON && TARGET_VFP5 && ARM_HAVE__ARITH"
+)
+
 (define_expand "vec_perm"
   [(match_operand:VE 0 "s_register_operand")
(match_operand:VE 1 "s_register_operand")
diff --git a/gcc/testsuite/gcc.target/arm/fmaxmin-2.c 
b/gcc/testsuite/gcc.target/arm/fmaxmin-2.c
new file mode 100644
index ..a9990e192435
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fmaxmin-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_hard_ok } */
+/* { dg-options "-O2 -fno-inline" } */
+/* { dg-add-options arm_arch_v8a_hard } */
+
+#include "fmaxmin.x"
+
+/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+, s\[0-9\]+, 
s\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+, s\[0-9\]+, 
s\[0-9\]+" 1 } } */
+
+/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, 
d\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, 
d\[0-9\]+" 1 } } */
diff --git a/gcc/testsuite/gcc.target/arm/fmaxmin.c 
b/gcc/testsuite/gcc.target/arm/fmaxmin.c
index 5a6fb804e3d0..7f30c1237ab3 100644
--- a/gcc/testsuite/gcc.target/arm/fmaxmin.c
+++ b/gcc/testsuite/gcc.target/arm/fmaxmin.c
@@ -1,13 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target arm_v8_neon_hw } */
-/* { dg-options "-O2 -fno-inline -march=armv8-a -save-temps" } */
+/* { dg-options "-O2 -fno-inline" } */
 /* { dg-add-options arm_v8_neon } */
 
 #includ

[gcc r15-8649] arm: testsuite: make unaligned-memcpy-*.c executable tests [PR91614]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:1d2257dc850d088f6d9267b4624ba08533ab2475

commit r15-8649-g1d2257dc850d088f6d9267b4624ba08533ab2475
Author: Richard Earnshaw 
Date:   Fri Mar 21 15:20:03 2025 +

arm: testsuite: make unaligned-memcpy-*.c executable tests [PR91614]

These tests have been looking for a very specific instruction sequence
which has the tendency to be fairly unstable as a result.  But what is
more interesting is that the the tests must not contain instructions
that can't be used for unaligned data, and whether or not the copy is
executed correctly.

So make these tests executable and scan the assembler only to confirm
the absence of instructions that must not be used when the data is not
aligned.

These tests also used to be restricted to targets that support
unaligned accesses (because you get very different code otherwise).
But now we've made the tests executable and to check for the absence
of problem instructions, just falling back to memcpy *is* an
acceptable implementation.  So remove the requirement for unaligned
accesses.

gcc/testsuite:
PR target/91614
* gcc.target/arm/unaligned-memcpy-1.c: Make the test executable.
Only scan for the absence of instructions that cannot access
misaligned data.  Remove constraint of having unaligned accesses.
* gcc.target/arm/unaligned-memcpy-2.c: Likewise.
* gcc.target/arm/unaligned-memcpy-3.c: Likewise.
* gcc.target/arm/unaligned-memcpy-4.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c | 34 +++
 gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c | 33 --
 gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c | 33 --
 gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c | 32 +++--
 4 files changed, 77 insertions(+), 55 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c 
b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c
index c4f564042252..0d883e3c1739 100644
--- a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c
+++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c
@@ -1,19 +1,31 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target arm_unaligned } */
-/* { dg-options "-O2" } */
+/* { dg-do run } */
+/* { dg-options "-O2 -save-temps" } */
 
 #include 
 
-void unknown_alignment (char *dest, char *src)
+char src[17] __attribute__ ((aligned(8))) = "abcdefghijklmnopq";
+char result[17] __attribute__ ((aligned(8))) = {0};
+
+void __attribute__ ((noinline,noclone))
+unknown_alignment (char *dest, char *src)
 {
   memcpy (dest, src, 15);
 }
 
-/* We should see three unaligned word loads and store pairs, one unaligned
-   ldrh/strh pair, and an ldrb/strb pair.  Sanity check that.  */
+int main ()
+{
+  int i;
+  unknown_alignment (result+1, src+2);
+  for (i = 0; i < 15; i++)
+if (result[i+1] != src[i+2])
+  __builtin_abort ();
+  if (result[16] != 0)
+__builtin_abort ();
+  return 0;
+}
+
+/* Check that we don't use any instructions that assume an aligned source.  */
+/* { dg-final { scan-assembler-not {(ldm(ia)?\tr[0-9]|ldrd\t.*\[r[0-9]|vldr)} 
} } */
 
-/* { dg-final { scan-assembler-times "@ unaligned" 8 } } */
-/* { dg-final { scan-assembler-times "ldrh" 1 } } */
-/* { dg-final { scan-assembler-times "strh" 1 } } */
-/* { dg-final { scan-assembler-times "ldrb" 1 } } */
-/* { dg-final { scan-assembler-times "strb" 1 } } */
+/* Check that we don't use any instructions that assume an aligned dest.  */
+/* { dg-final { scan-assembler-not {(stm(ia)?\tr[0-9]|strd\t.*\[r[0-9]|vstr)} 
} } */
diff --git a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c 
b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c
index 1ad730d6407f..0da0bcd1c247 100644
--- a/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c
+++ b/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c
@@ -1,24 +1,27 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target arm_unaligned } */
-/* { dg-options "-O2" } */
+/* { dg-do run } */
+/* { dg-options "-O2 -save-temps" } */
 
 #include 
 
-char dest[16] = { 0 };
+char dest[16] __attribute__((aligned(8))) = { 0 } ;
+char input[17] __attribute__ ((aligned(8))) = "abcdefghijklmnop";
 
-void aligned_dest (char *src)
+void __attribute__ ((noinline,noclone)) aligned_dest (char *src)
 {
   memcpy (dest, src, 15);
 }
 
-/* Expect a multi-word store for the main part of the copy, but subword
-   loads/stores for the remainder.  */
+int main ()
+{
+  int i;
+  aligned_dest (input+1);
+  for (i = 0; i < 15; i++)
+if (dest[i] != input[i+1])
+  __builtin_abort ();
+  if (dest[15] != 0)
+__builtin_abort ();
+  return 0;
+}
 
-/* { dg-final { scan-assembler-times "ldmia" 0 } } */
-/* { dg-final { scan-assembler-times "ldrd" 0 } } */
-/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { 
arm_prefer_ldrd_strd } } } } } */
-/* { dg-final { scan-assembler

[gcc r16-542] arm: testsuite: remove iwmmxt tests

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:844dcbc362dead95e832685d64ed094afcf238b4

commit r16-542-g844dcbc362dead95e832685d64ed094afcf238b4
Author: Richard Earnshaw 
Date:   Mon Apr 28 11:15:16 2025 +0100

arm: testsuite: remove iwmmxt tests

These two tests were specific to iWMMXT, but we're about to remove
that code, so the tests are now redundant.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mmx-1.c: Removed.
* gcc.target/arm/mmx-2.c: Removed.
* gcc.target/arm/pr64208.c: Removed.
* gcc.target/arm/pr79145.c: Removed.
* gcc.target/arm/pr99724.c: Removed.
* gcc.target/arm/pr99786.c: Removed.

Diff:
---
 gcc/testsuite/gcc.target/arm/mmx-1.c   |  26 --
 gcc/testsuite/gcc.target/arm/mmx-2.c   | 166 -
 gcc/testsuite/gcc.target/arm/pr64208.c |  25 -
 gcc/testsuite/gcc.target/arm/pr79145.c |  16 
 gcc/testsuite/gcc.target/arm/pr99724.c |  31 --
 gcc/testsuite/gcc.target/arm/pr99786.c |  30 --
 6 files changed, 294 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/mmx-1.c 
b/gcc/testsuite/gcc.target/arm/mmx-1.c
deleted file mode 100644
index 8060dbd40af0..
--- a/gcc/testsuite/gcc.target/arm/mmx-1.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Verify that if IP is saved to ensure stack alignment, we don't load
-   it into sp.  */
-/* { dg-do compile } */
-/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { 
"-mcpu=iwmmxt" } } */
-/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { 
"-mabi=iwmmxt" } } */
-/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { 
"-march=iwmmxt" } } */
-/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" 
} } */
-/* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */
-/* { dg-require-effective-target arm32 } */
-/* { dg-require-effective-target arm_iwmmxt_ok } */
-/* { dg-final { scan-assembler "push.*ip,\[ ]*pc" } } */
-/* { dg-skip-if "r9 is reserved in FDPIC" { arm*-*-uclinuxfdpiceabi } "*" "" } 
*/
-
-/* This function uses all the call-saved registers, namely r4, r5, r6,
-   r7, r8, r9, sl, fp.  Since we also save lr, that leaves an odd
-   number of registers, and the compiler will push ip to align the
-   stack.  Make sure that we restore ip into ip, not into sp as is
-   done when using a frame pointer.  The -mno-apcs-frame option
-   permits the frame pointer to be used as an ordinary register.  */
-
-void
-foo(void)
-{
-  __asm volatile ("" : : :
- "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr");
-}
diff --git a/gcc/testsuite/gcc.target/arm/mmx-2.c 
b/gcc/testsuite/gcc.target/arm/mmx-2.c
deleted file mode 100644
index 0540f659d1aa..
--- a/gcc/testsuite/gcc.target/arm/mmx-2.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* { dg-do compile } */
-/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { 
"-mcpu=iwmmxt" } } */
-/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { 
"-mabi=iwmmxt" } } */
-/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { 
"-march=iwmmxt" } } */
-/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" 
} } */
-/* { dg-require-effective-target arm32 } */
-/* { dg-require-effective-target arm_iwmmxt_ok } */
-/* { dg-options "-mcpu=iwmmxt -flax-vector-conversions -std=gnu99" } */
-
-/* Internal data types for implementing the intrinsics.  */
-typedef int __v2si __attribute__ ((vector_size (8)));
-typedef short __v4hi __attribute__ ((vector_size (8)));
-typedef signed char __v8qi __attribute__ ((vector_size (8)));
-
-void
-foo(void)
-{
-  volatile int isink;
-  volatile long long llsink;
-  volatile __v8qi v8sink;
-  volatile __v4hi v4sink;
-  volatile __v2si v2sink;
-
-  isink = __builtin_arm_getwcgr0 ();
-  __builtin_arm_setwcgr0 (isink);
-  isink = __builtin_arm_getwcgr1 ();
-  __builtin_arm_setwcgr1 (isink);
-  isink = __builtin_arm_getwcgr2 ();
-  __builtin_arm_setwcgr2 (isink);
-  isink = __builtin_arm_getwcgr3 ();
-  __builtin_arm_setwcgr3 (isink);
-
-  isink = __builtin_arm_textrmsb (v8sink, 0);
-  isink = __builtin_arm_textrmsh (v4sink, 0);
-  isink = __builtin_arm_textrmsw (v2sink, 0);
-  isink = __builtin_arm_textrmub (v8sink, 0);
-  isink = __builtin_arm_textrmuh (v4sink, 0);
-  isink = __builtin_arm_textrmuw (v2sink, 0);
-  v8sink = __builtin_arm_tinsrb (v8sink, isink, 0);
-  v4sink = __builtin_arm_tinsrh (v4sink, isink, 0);
-  v2sink = __builtin_arm_tinsrw (v2sink, isink, 0);
-  llsink = __builtin_arm_tmia (llsink, isink, isink);
-  llsink = __builtin_arm_tmiabb (llsink, isink, isink);
-  llsink = __builtin_arm_tmiabt (llsink, isink, isink);
-  llsink = __builtin_arm_tmiaph (llsink, isink, isink);
-  llsink = __builtin_arm_tmiatb (llsink, isink, isink);
-  llsink = __builtin_arm_tmiatt (llsink, isink, isink);
-  isink = __builtin_arm_tmovmskb (v8sink);
-  isink = __builti

[gcc r16-543] arm: treat -mcpu/arch=iwmmxt{,2} like XScale

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:38179738abf34897eb03e17426c0507a595c9862

commit r16-543-g38179738abf34897eb03e17426c0507a595c9862
Author: Richard Earnshaw 
Date:   Mon Apr 28 14:55:43 2025 +0100

arm: treat -mcpu/arch=iwmmxt{,2} like XScale

Treat options that select iwmmxt variants as we would for xscale.  We
leave the feature bits in for now, since they are still needed
elsewhere, but they are never enabled.

Also remove the remaining testsuite framework support for iwmmxt,
since this will never trigger now.

gcc/

* config/arm/arm-cpus.in (arch iwmmxt): treat in the same
way as we would treat XScale.
(arch iwmmxt2): Likewise.
(cpu xscale): Add aliases for iwmmxt and iwmmxt2.
(cpu iwmmxt): Delete.
(cpu iwmmxt2): Delete.
* config/arm/arm-generic.md (load_ldsched_xscale): Remove references
to iwmmxt.
(load_ldsched): Likewise.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* doc/sourcebuild.texi (arm_iwmmxt_ok): Delete.

gcc/testsuite/ChangeLog:

* gcc.target/arm/ivopts.c: Remove test for iwmmxt
* lib/target-supports.exp
(check_effective_target_arm_iwmmxt_ok): Delete.

Diff:
---
 gcc/config/arm/arm-cpus.in| 22 ---
 gcc/config/arm/arm-generic.md |  4 +--
 gcc/config/arm/arm-tables.opt |  6 
 gcc/config/arm/arm-tune.md| 53 +--
 gcc/doc/sourcebuild.texi  |  4 ---
 gcc/testsuite/gcc.target/arm/ivopts.c |  3 +-
 gcc/testsuite/lib/target-supports.exp | 13 -
 7 files changed, 35 insertions(+), 70 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index 1939d55b9fdb..b34c441ec76d 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -778,18 +778,19 @@ begin arch armv9-a
  option bf16 add bf16 FP_ARMv8 DOTPROD
 end arch armv9-a
 
+# We no-longer support the iwmmxt{,2} extensions, so treat these like xscale.
 begin arch iwmmxt
- tune for iwmmxt
+ tune for xscale
  tune flags LDSCHED STRONG XSCALE
  base 5TE
- isa ARMv5te xscale iwmmxt
+ isa ARMv5te xscale
 end arch iwmmxt
 
 begin arch iwmmxt2
- tune for iwmmxt2
+ tune for xscale
  tune flags LDSCHED STRONG XSCALE
  base 5TE
- isa ARMv5te xscale iwmmxt iwmmxt2
+ isa ARMv5te xscale
 end arch iwmmxt2
 
 # CPU entries
@@ -924,23 +925,12 @@ end cpu arm10e
 
 begin cpu xscale
  tune flags LDSCHED XSCALE
+ alias iwmmxt iwmmxt2
  architecture armv5te
  isa xscale
  costs xscale
 end cpu xscale
 
-begin cpu iwmmxt
- tune flags LDSCHED XSCALE
- architecture iwmmxt
- costs xscale
-end cpu iwmmxt
-
-begin cpu iwmmxt2
- tune flags LDSCHED XSCALE
- architecture iwmmxt2
- costs xscale
-end cpu iwmmxt2
-
 begin cpu fa606te
  tune flags LDSCHED
  architecture armv5te
diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md
index c2700568c00a..a8af0e6f2556 100644
--- a/gcc/config/arm/arm-generic.md
+++ b/gcc/config/arm/arm-generic.md
@@ -96,14 +96,14 @@
   (and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes") 
(and (eq_attr "type" "load_byte,load_4")
-(eq_attr "tune" "xscale,iwmmxt,iwmmxt2"
+(eq_attr "tune" "xscale"
   "core")
 
 (define_insn_reservation "load_ldsched" 2
   (and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "yes") 
(and (eq_attr "type" "load_byte,load_4")
-(eq_attr "tune" "!xscale,iwmmxt,iwmmxt2"
+(eq_attr "tune" "!xscale"
   "core")
 
 (define_insn_reservation "load_or_store" 2
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index db7767a2d6cf..544de84df809 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -66,12 +66,6 @@ Enum(processor_type) String(arm10e) Value( TARGET_CPU_arm10e)
 EnumValue
 Enum(processor_type) String(xscale) Value( TARGET_CPU_xscale)
 
-EnumValue
-Enum(processor_type) String(iwmmxt) Value( TARGET_CPU_iwmmxt)
-
-EnumValue
-Enum(processor_type) String(iwmmxt2) Value( TARGET_CPU_iwmmxt2)
-
 EnumValue
 Enum(processor_type) String(fa606te) Value( TARGET_CPU_fa606te)
 
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index a04d1eeb62dd..20b5f932344d 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -25,31 +25,30 @@
fa526,fa626,arm7tdmi,
arm710t,arm9,arm9tdmi,
arm920t,arm10tdmi,arm9e,
-   arm10e,xscale,iwmmxt,
-   iwmmxt2,fa606te,fa626te,
-   fmp626,fa726te,arm926ejs,
-   arm1026ejs,arm1136js,arm1136jfs,
-   arm1176jzs,arm1176jzfs,mpcorenovfp,
-   mpcore,arm1156t2s,arm1156t2fs,
-   cortexm1,cortexm0,cortexm0plus,
-   cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
-   genericv7a,cortexa5,corte

[gcc r16-541] arm: clarify the logic of SECONDARY_(INPUT/OUTPUT)_RELOAD_CLASS

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:a5af89df186d7dbeabf6b337b39d33f8b2784833

commit r16-541-ga5af89df186d7dbeabf6b337b39d33f8b2784833
Author: Richard Earnshaw 
Date:   Mon Apr 28 18:43:49 2025 +0100

arm: clarify the logic of SECONDARY_(INPUT/OUTPUT)_RELOAD_CLASS

The flattened logic of these functions and the complexity of the
numerous clauses makes it very difficult to understand what's written
in these macros.  Additionally, SECONDARY_INPUT_RELOAD_CLASS was not
laid out with the correct formatting.

Add some parenthesis and re-indent to make the logic clearer.

No functional change.

gcc:
* config/arm/arm.h (SECONDARY_OUTPUT_RELOAD_CLASS): Add parentheis
and re-indent.
(SECONDARY_INPUT_RELOAD_CLASS): Likewise.

Diff:
---
 gcc/config/arm/arm.h | 55 +++-
 1 file changed, 29 insertions(+), 26 deletions(-)

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 08d3f0dae3da..f8a2da32255a 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1460,34 +1460,37 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS];
 /* Return the register class of a scratch register needed to copy IN into
or out of a register in CLASS in MODE.  If it can be done directly,
NO_REGS is returned.  */
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)  \
-  /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
-  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
-   ? coproc_secondary_reload_class (MODE, X, FALSE)\
-   : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
-   ? coproc_secondary_reload_class (MODE, X, TRUE) \
-   : TARGET_32BIT  \
-   ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
-? GENERAL_REGS : NO_REGS)  \
-   : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X)  \
+  /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */
\
+  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
+   ? coproc_secondary_reload_class (MODE, X, FALSE)\
+   : ((TARGET_IWMMXT && (CLASS) == IWMMXT_REGS)
\
+  ? coproc_secondary_reload_class (MODE, X, TRUE)  \
+  : (TARGET_32BIT  \
+? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1)  \
+   ? GENERAL_REGS  \
+   : NO_REGS)  \
+: THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X
 
 /* If we need to load shorts byte-at-a-time, then we need a scratch.  */
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)   \
-  /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */ \
-  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
-? coproc_secondary_reload_class (MODE, X, FALSE) : \
-(TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ?\
-coproc_secondary_reload_class (MODE, X, TRUE) :\
-   (TARGET_32BIT ? \
-(((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
- && CONSTANT_P (X))\
-? GENERAL_REGS :   \
-(((MODE) == HImode && ! arm_arch4  \
-  && (MEM_P (X)\
- || ((REG_P (X) || GET_CODE (X) == SUBREG) \
- && true_regnum (X) == -1)))   \
- ? GENERAL_REGS : NO_REGS) \
-: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X)   \
+  /* Restrict which direct reloads are allowed for VFP/iWMMXt regs.  */
\
+  ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
+   ? coproc_secondary_reload_class (MODE, X, FALSE)\
+   : ((TARGET_IWMMXT && (CLASS) == IWMMXT_REGS)
\
+  ? coproc_secondary_reload_class (MODE, X, TRUE)  \
+  : (TARGET_32BIT  \
+? CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS)  \
+&& CONSTANT_P (X)) \
+   ? GENERAL_REGS  \
+   : (((MODE) == HImode\
+   && ! arm_arch4  \
+   && (MEM_P (X)   \
+   || ((REG_P (X) || GET_CODE (X) == 

[gcc r16-544] arm: remove iWMMX builtins support.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:3410eadcaa2ac6dce5f4af391e82f83ee3041866

commit r16-544-g3410eadcaa2ac6dce5f4af391e82f83ee3041866
Author: Richard Earnshaw 
Date:   Mon Apr 28 11:03:34 2025 +0100

arm: remove iWMMX builtins support.

This is the first step of removing the various builtins for iwmmxt,
removing the builtins expansion code.  It leaves a lot of code
elsewhere, but we'll clean that up in subsequent patches.

I'm not sure why safe_vector_operand would unconditionally try to
expand to an iwmmxt instruction if passed (const_int 0).  Clearly
that's meaningless on other architectures, but perhaps this can't
happen elsewhere.  Anyway, for now, just mark this as unreachable so
that we'll know about it if it ever happens.

gcc/ChangeLog:

* config/arm/arm-builtins.cc (enum arm_builtins): Delete iWMMX
builtin values.
(bdesc_2arg): Likewise.
(bdesc_1arg): Likewise.
(arm_init_iwmmxt_builtins): Delete.
(arm_init_builtins): Don't call arm_init_iwmmxt_builtins.
(safe_vector_operand): Use __builtin_unreachable instead of emitting
an iwmmxt builtin.
(arm_general_expand_builtin): Remove iWMMX builtins support.

Diff:
---
 gcc/config/arm/arm-builtins.cc | 1276 +---
 1 file changed, 2 insertions(+), 1274 deletions(-)

diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc
index c56ab5db985b..0ddc66695097 100644
--- a/gcc/config/arm/arm-builtins.cc
+++ b/gcc/config/arm/arm-builtins.cc
@@ -816,252 +816,6 @@ static arm_builtin_cde_datum cde_builtin_data[] =
 
 enum arm_builtins
 {
-  ARM_BUILTIN_GETWCGR0,
-  ARM_BUILTIN_GETWCGR1,
-  ARM_BUILTIN_GETWCGR2,
-  ARM_BUILTIN_GETWCGR3,
-
-  ARM_BUILTIN_SETWCGR0,
-  ARM_BUILTIN_SETWCGR1,
-  ARM_BUILTIN_SETWCGR2,
-  ARM_BUILTIN_SETWCGR3,
-
-  ARM_BUILTIN_WZERO,
-
-  ARM_BUILTIN_WAVG2BR,
-  ARM_BUILTIN_WAVG2HR,
-  ARM_BUILTIN_WAVG2B,
-  ARM_BUILTIN_WAVG2H,
-
-  ARM_BUILTIN_WACCB,
-  ARM_BUILTIN_WACCH,
-  ARM_BUILTIN_WACCW,
-
-  ARM_BUILTIN_WMACS,
-  ARM_BUILTIN_WMACSZ,
-  ARM_BUILTIN_WMACU,
-  ARM_BUILTIN_WMACUZ,
-
-  ARM_BUILTIN_WSADB,
-  ARM_BUILTIN_WSADBZ,
-  ARM_BUILTIN_WSADH,
-  ARM_BUILTIN_WSADHZ,
-
-  ARM_BUILTIN_WALIGNI,
-  ARM_BUILTIN_WALIGNR0,
-  ARM_BUILTIN_WALIGNR1,
-  ARM_BUILTIN_WALIGNR2,
-  ARM_BUILTIN_WALIGNR3,
-
-  ARM_BUILTIN_TMIA,
-  ARM_BUILTIN_TMIAPH,
-  ARM_BUILTIN_TMIABB,
-  ARM_BUILTIN_TMIABT,
-  ARM_BUILTIN_TMIATB,
-  ARM_BUILTIN_TMIATT,
-
-  ARM_BUILTIN_TMOVMSKB,
-  ARM_BUILTIN_TMOVMSKH,
-  ARM_BUILTIN_TMOVMSKW,
-
-  ARM_BUILTIN_TBCSTB,
-  ARM_BUILTIN_TBCSTH,
-  ARM_BUILTIN_TBCSTW,
-
-  ARM_BUILTIN_WMADDS,
-  ARM_BUILTIN_WMADDU,
-
-  ARM_BUILTIN_WPACKHSS,
-  ARM_BUILTIN_WPACKWSS,
-  ARM_BUILTIN_WPACKDSS,
-  ARM_BUILTIN_WPACKHUS,
-  ARM_BUILTIN_WPACKWUS,
-  ARM_BUILTIN_WPACKDUS,
-
-  ARM_BUILTIN_WADDB,
-  ARM_BUILTIN_WADDH,
-  ARM_BUILTIN_WADDW,
-  ARM_BUILTIN_WADDSSB,
-  ARM_BUILTIN_WADDSSH,
-  ARM_BUILTIN_WADDSSW,
-  ARM_BUILTIN_WADDUSB,
-  ARM_BUILTIN_WADDUSH,
-  ARM_BUILTIN_WADDUSW,
-  ARM_BUILTIN_WSUBB,
-  ARM_BUILTIN_WSUBH,
-  ARM_BUILTIN_WSUBW,
-  ARM_BUILTIN_WSUBSSB,
-  ARM_BUILTIN_WSUBSSH,
-  ARM_BUILTIN_WSUBSSW,
-  ARM_BUILTIN_WSUBUSB,
-  ARM_BUILTIN_WSUBUSH,
-  ARM_BUILTIN_WSUBUSW,
-
-  ARM_BUILTIN_WAND,
-  ARM_BUILTIN_WANDN,
-  ARM_BUILTIN_WOR,
-  ARM_BUILTIN_WXOR,
-
-  ARM_BUILTIN_WCMPEQB,
-  ARM_BUILTIN_WCMPEQH,
-  ARM_BUILTIN_WCMPEQW,
-  ARM_BUILTIN_WCMPGTUB,
-  ARM_BUILTIN_WCMPGTUH,
-  ARM_BUILTIN_WCMPGTUW,
-  ARM_BUILTIN_WCMPGTSB,
-  ARM_BUILTIN_WCMPGTSH,
-  ARM_BUILTIN_WCMPGTSW,
-
-  ARM_BUILTIN_TEXTRMSB,
-  ARM_BUILTIN_TEXTRMSH,
-  ARM_BUILTIN_TEXTRMSW,
-  ARM_BUILTIN_TEXTRMUB,
-  ARM_BUILTIN_TEXTRMUH,
-  ARM_BUILTIN_TEXTRMUW,
-  ARM_BUILTIN_TINSRB,
-  ARM_BUILTIN_TINSRH,
-  ARM_BUILTIN_TINSRW,
-
-  ARM_BUILTIN_WMAXSW,
-  ARM_BUILTIN_WMAXSH,
-  ARM_BUILTIN_WMAXSB,
-  ARM_BUILTIN_WMAXUW,
-  ARM_BUILTIN_WMAXUH,
-  ARM_BUILTIN_WMAXUB,
-  ARM_BUILTIN_WMINSW,
-  ARM_BUILTIN_WMINSH,
-  ARM_BUILTIN_WMINSB,
-  ARM_BUILTIN_WMINUW,
-  ARM_BUILTIN_WMINUH,
-  ARM_BUILTIN_WMINUB,
-
-  ARM_BUILTIN_WMULUM,
-  ARM_BUILTIN_WMULSM,
-  ARM_BUILTIN_WMULUL,
-
-  ARM_BUILTIN_PSADBH,
-  ARM_BUILTIN_WSHUFH,
-
-  ARM_BUILTIN_WSLLH,
-  ARM_BUILTIN_WSLLW,
-  ARM_BUILTIN_WSLLD,
-  ARM_BUILTIN_WSRAH,
-  ARM_BUILTIN_WSRAW,
-  ARM_BUILTIN_WSRAD,
-  ARM_BUILTIN_WSRLH,
-  ARM_BUILTIN_WSRLW,
-  ARM_BUILTIN_WSRLD,
-  ARM_BUILTIN_WRORH,
-  ARM_BUILTIN_WRORW,
-  ARM_BUILTIN_WRORD,
-  ARM_BUILTIN_WSLLHI,
-  ARM_BUILTIN_WSLLWI,
-  ARM_BUILTIN_WSLLDI,
-  ARM_BUILTIN_WSRAHI,
-  ARM_BUILTIN_WSRAWI,
-  ARM_BUILTIN_WSRADI,
-  ARM_BUILTIN_WSRLHI,
-  ARM_BUILTIN_WSRLWI,
-  ARM_BUILTIN_WSRLDI,
-  ARM_BUILTIN_WRORHI,
-  ARM_BUILTIN_WRORWI,
-  ARM_BUILTIN_WRORDI,
-
-  ARM_BUILTIN_WUNPCKIHB,
-  ARM_BUILTIN_WUNPCKIHH,
-  ARM_BUILTIN_WUNPCKIHW,
-  ARM_BUILTIN_WUNPCKILB,
-  ARM_BUILTIN_WUNPCKILH,
-  ARM_BUILTIN_WUNPCKILW,
-
-  ARM_BUILTIN_WUNPCKEHSB,
-  ARM_BUILTIN_WUNPCKEHSH,

[gcc r16-545] arm: Remove iwmmxt patterns.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:e579f85f3bfead8d224d4e163273db8b09d8d1c5

commit r16-545-ge579f85f3bfead8d224d4e163273db8b09d8d1c5
Author: Richard Earnshaw 
Date:   Mon Apr 28 13:08:38 2025 +0100

arm: Remove iwmmxt patterns.

This patch deletes the patterns relating to iwmmxt and iwmmxt2 and
updates the relevant dependencies.

gcc/ChangeLog:

* config/arm/arm.md: Don't include iwmmxt.md.
* config/arm/t-arm (MD_INCLUDES): Remove iwmmxt*.md.
* config/arm/iwmmxt.md: Removed.
* config/arm/iwmmxt2.md: Removed.
* config/arm/unspecs.md: Remove comment referring to
iwmmxt2.md.
(enum unspec): Remove iWMMXt unspec values.
(enum unspecv): Likewise.
* config/arm/predicates.md (imm_or_reg_operand): Delete.

Diff:
---
 gcc/config/arm/arm.md|2 -
 gcc/config/arm/iwmmxt.md | 1766 --
 gcc/config/arm/iwmmxt2.md|  903 -
 gcc/config/arm/predicates.md |8 +-
 gcc/config/arm/t-arm |2 -
 gcc/config/arm/unspecs.md|   29 -
 6 files changed, 1 insertion(+), 2709 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 597ef6725bb7..af0564c36a9b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -13125,8 +13125,6 @@
 
 ;; Vector bits common to IWMMXT, Neon and MVE
 (include "vec-common.md")
-;; Load the Intel Wireless Multimedia Extension patterns
-(include "iwmmxt.md")
 ;; Load the VFP co-processor patterns
 (include "vfp.md")
 ;; Thumb-1 patterns
diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md
deleted file mode 100644
index 0aa5dcd67093..
--- a/gcc/config/arm/iwmmxt.md
+++ /dev/null
@@ -1,1766 +0,0 @@
-;; Patterns for the Intel Wireless MMX technology architecture.
-;; Copyright (C) 2003-2025 Free Software Foundation, Inc.
-;; Contributed by Red Hat.
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify it under
-;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 3, or (at your option) any later
-;; version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-;; License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3.  If not see
-;; .
-
-;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h
-(define_constants
-  [(WCGR0   96)
-   (WCGR1   97)
-   (WCGR2   98)
-   (WCGR3   99)
-  ]
-)
-
-(define_insn "tbcstv8qi"
-  [(set (match_operand:V8QI   0 "register_operand" "=y")
-(vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
-  "TARGET_REALLY_IWMMXT"
-  "tbcstb%?\\t%0, %1"
-  [(set_attr "predicable" "yes")
-   (set_attr "type" "wmmx_tbcst")]
-)
-
-(define_insn "tbcstv4hi"
-  [(set (match_operand:V4HI   0 "register_operand" "=y")
-(vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
-  "TARGET_REALLY_IWMMXT"
-  "tbcsth%?\\t%0, %1"
-  [(set_attr "predicable" "yes")
-   (set_attr "type" "wmmx_tbcst")]
-)
-
-(define_insn "tbcstv2si"
-  [(set (match_operand:V2SI   0 "register_operand" "=y")
-(vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
-  "TARGET_REALLY_IWMMXT"
-  "tbcstw%?\\t%0, %1"
-  [(set_attr "predicable" "yes")
-   (set_attr "type" "wmmx_tbcst")]
-)
-
-(define_insn "iwmmxt_iordi3"
-  [(set (match_operand:DI 0 "register_operand" "=y")
-(ior:DI (match_operand:DI 1 "register_operand" "%y")
-   (match_operand:DI 2 "register_operand"  "y")))]
-  "TARGET_REALLY_IWMMXT"
-  "wor%?\\t%0, %1, %2"
-  [(set_attr "predicable" "yes")
-   (set_attr "length" "4")
-   (set_attr "type" "wmmx_wor")]
-)
-
-(define_insn "iwmmxt_xordi3"
-  [(set (match_operand:DI 0 "register_operand" "=y")
-(xor:DI (match_operand:DI 1 "register_operand" "%y")
-   (match_operand:DI 2 "register_operand"  "y")))]
-  "TARGET_REALLY_IWMMXT"
-  "wxor%?\\t%0, %1, %2"
-  [(set_attr "predicable" "yes")
-   (set_attr "length" "4")
-   (set_attr "type" "wmmx_wxor")]
-)
-
-(define_insn "iwmmxt_anddi3"
-  [(set (match_operand:DI 0 "register_operand" "=y")
-(and:DI (match_operand:DI 1 "register_operand" "%y")
-   (match_operand:DI 2 "register_operand"  "y")))]
-  "TARGET_REALLY_IWMMXT"
-  "wand%?\\t%0, %1, %2"
-  [(set_attr "predicable" "yes")
-   (set_attr "length" "4")
-   (set_attr "type" "wmmx_wand")]
-)
-
-(define_insn "iwmmxt_nanddi3"
-  [(set (match_operand:DI 0 "register_operand" "=y")
-(and:DI (match_operand:DI 1 "register_operan

[gcc r16-546] arm: remove IWMMXT checks from MD files.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:3212ddb58fcfed6424771510ec05b26b8dbff3ae

commit r16-546-g3212ddb58fcfed6424771510ec05b26b8dbff3ae
Author: Richard Earnshaw 
Date:   Mon Apr 28 14:17:41 2025 +0100

arm: remove IWMMXT checks from MD files.

Remove the various checks for TARGET_IWMMXT{,2} and
TARGET_REALLY_IWMMXT{,2} from the remaining machine description files.
These flags can never be true now.

gcc/ChangeLog:

* config/arm/arm.md(attr arch): Remove iwmmxt and iwmmxt2.
Remove checks based on TARGET_REALLY_IWMMXT2 from all split
patterns.
(arm_movdi): Likewise.
(*arm_movt): Likewise.
(arch_enabled): Remove test for iwmmxt2.
* config/arm/constraints.md (y, z): Remove register constraints.
(Uy): Remove memory constraint.
* config/arm/thumb2.md (thumb2_pop_single): Remove check for
IWMMXT.
* config/arm/vec-common.md (mov): Remove check for IWMMXT.
(mul3): Likewise.
(xor3): Likewise.
(2): Likewise.
(@movmisalign): Likewise.
(@mve_q_): Likewise.
(vashl3): Likewise.
(vashr3): Likewise.
(vlshr3): Likewise.
(uavg3_ceil): Likewise.

Diff:
---
 gcc/config/arm/arm.md | 15 ---
 gcc/config/arm/constraints.md | 18 +++---
 gcc/config/arm/thumb2.md  |  2 +-
 gcc/config/arm/vec-common.md  | 31 ---
 4 files changed, 20 insertions(+), 46 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index af0564c36a9b..ce1b987b2415 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -149,7 +149,7 @@
 ; This attribute is used to compute attribute "enabled",
 ; use type "any" to enable an alternative in all cases.
 (define_attr "arch" "any, a, t, 32, t1, t2, v6,nov6, v6t2, \
-v8mb, fix_vlldm, iwmmxt, iwmmxt2, armv6_or_vfpv3, \
+v8mb, fix_vlldm, armv6_or_vfpv3, \
 neon, mve"
   (const_string "any"))
 
@@ -197,10 +197,6 @@
  (match_test "fix_vlldm"))
 (const_string "yes")
 
-(and (eq_attr "arch" "iwmmxt2")
- (match_test "TARGET_REALLY_IWMMXT2"))
-(const_string "yes")
-
 (and (eq_attr "arch" "armv6_or_vfpv3")
  (match_test "arm_arch6 || TARGET_VFP3"))
 (const_string "yes")
@@ -2893,14 +2889,12 @@
 ;; Split DImode and, ior, xor operations.  Simply perform the logical
 ;; operation on the upper and lower halves of the registers.
 ;; This is needed for atomic operations in arm_split_atomic_op.
-;; Avoid splitting IWMMXT instructions.
 (define_split
   [(set (match_operand:DI 0 "s_register_operand" "")
(match_operator:DI 6 "logical_binary_operator"
  [(match_operand:DI 1 "s_register_operand" "")
   (match_operand:DI 2 "s_register_operand" "")]))]
-  "TARGET_32BIT && reload_completed
-   && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
(set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
   "
@@ -6345,7 +6339,6 @@
   "TARGET_32BIT
&& !(TARGET_HARD_FLOAT)
&& !(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT)
-   && !TARGET_IWMMXT
&& (   register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
   "*
@@ -6554,7 +6547,7 @@
 (define_insn "*arm_movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
(match_operand:SI 1 "general_operand"  "rk, I,K,j,mi,rk"))]
-  "TARGET_ARM && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
+  "TARGET_ARM && !TARGET_HARD_FLOAT
&& (   register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
   "@
@@ -13123,7 +13116,7 @@
   [(set_attr "conds" "unconditional")
(set_attr "type" "nop")])
 
-;; Vector bits common to IWMMXT, Neon and MVE
+;; Vector bits common to Neon and MVE
 (include "vec-common.md")
 ;; Load the VFP co-processor patterns
 (include "vfp.md")
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 9f1a37aa5d49..24743a82356b 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -19,11 +19,12 @@
 ;; .
 
 ;; The following register constraints have been used:
-;; - in ARM/Thumb-2 state: t, w, x, y, z
+;; - in ARM/Thumb-2 state: t, w, x
 ;; - in Thumb state: h, b
 ;; - in both states: l, c, k, q, Cs, Ts, US
 ;; In ARM state, 'l' is an alias for 'r'
 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
+;; 'y' and 'z' were previously used for iWMMX registers (removed after gcc-15)
 
 ;; The following normal constraints have been used:
 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
@@ -39,7 +40,7 @@
 ;; in all states: Pg
 
 ;; The following memory constraints have been used:
-;

[gcc r16-552] arm: remove most remaining iwmmxt code.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:f9d24c4d722e0f53e2e67ff5a42169b4de6dc88a

commit r16-552-gf9d24c4d722e0f53e2e67ff5a42169b4de6dc88a
Author: Richard Earnshaw 
Date:   Wed Apr 30 17:12:52 2025 +0100

arm: remove most remaining iwmmxt code.

Remove most of the remaining code for iWMMXT support, except for the
register allocation table entries.

gcc/ChangeLog:

* config/arm/arm-cpus.in (feature iwmmxt, feature iwmmxt2):  Delete.
* config/arm/arm-protos.h (arm_output_iwmmxt_shift_immediate): 
Delete.
(arm_output_iwmmxt_tinsr): Delete.
(arm_arch_iwmmxt): Delete.
(arm_arch_iwmmxt2): Delete.
* config/arm/arm.h (TARGET_IWMMXT): Delete.
(TARGET_IWMMXT2): Delete.
(TARGET_REALLY_IWMMXT): Delete.
(TARGET_REALLY_IWMMXT2): Delete.
(VALID_IWMMXT_REG_MODE): Delete.
(ARM_HAVE_V8QI_ARITH): Remove iWMMXT.
(ARM_HAVE_V4HI_ARITH): Likewise.
(ARM_HAVE_V2SI_ARITH): Likewise.
(ARM_HAVE_V8QI_LDST): Likewise.
(ARM_HAVE_V4HI_LDST): Likewise.
(ARM_HAVE_V2SI_LDST): Likewise.
(SECONDARY_OUTPUT_RELOAD_CLASS):  Remove iWMMXT cases.
(SECONDARY_INPUT_RELOAD_CLASS): Likewise.
* config/arm/arm.cc (arm_arch_iwmmxt): Delete.
(arm_arch_iwmmxt2): Delete.
(arm_option_reconfigure_globals): Don't initialize them.
(arm_register_move_cost): Remove costs for iwmmxt.
(struct minipool_node):  Update comment.
(output_move_double): Likewise
(output_return_instruction): Likewise.
(arm_print_operand, cases 'U' and 'w'): Report an error if
used.
(arm_regno_class): Remove iWMMXT cases.
(arm_debugger_regno): Remove iWMMXT cases.
(arm_output_iwmmxt_shift_immediate): Delete.
(arm_output_iwmmxt_tinsr): Delete.

Diff:
---
 gcc/config/arm/arm-cpus.in  |   6 --
 gcc/config/arm/arm-protos.h |   8 --
 gcc/config/arm/arm.cc   | 174 +++-
 gcc/config/arm/arm.h|  69 ++
 4 files changed, 32 insertions(+), 225 deletions(-)

diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index b34c441ec76d..7f5a8c670b63 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -102,12 +102,6 @@ define feature armv8
 # ARMv8 CRC32 instructions.
 define feature crc32
 
-# XScale v2 (Wireless MMX).
-define feature iwmmxt
-
-# XScale Wireless MMX2.
-define feature iwmmxt2
-
 # Architecture rel 8.1.
 define feature armv8_1
 
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 254c7310794b..ff7e7658f912 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -190,8 +190,6 @@ extern void arm_output_multireg_pop (rtx *, bool, rtx, 
bool, bool);
 extern void arm_set_return_address (rtx, rtx);
 extern int arm_eliminable_register (rtx);
 extern const char *arm_output_shift(rtx *, int);
-extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, 
bool);
-extern const char *arm_output_iwmmxt_tinsr (rtx *);
 extern unsigned int arm_sync_loop_insns (rtx , rtx *);
 extern int arm_attr_length_push_multi(rtx, rtx);
 extern int arm_attr_length_pop_multi(rtx *, bool, bool);
@@ -475,12 +473,6 @@ extern int arm_ld_sched;
 /* Nonzero if this chip is a StrongARM.  */
 extern int arm_tune_strongarm;
 
-/* Nonzero if this chip supports Intel Wireless MMX technology.  */
-extern int arm_arch_iwmmxt;
-
-/* Nonzero if this chip supports Intel Wireless MMX2 technology.  */
-extern int arm_arch_iwmmxt2;
-
 /* Nonzero if this chip is an XScale.  */
 extern int arm_arch_xscale;
 
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 78a1f744ec4e..8737c223391d 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -948,12 +948,6 @@ int arm_ld_sched = 0;
 /* Nonzero if this chip is a StrongARM.  */
 int arm_tune_strongarm = 0;
 
-/* Nonzero if this chip supports Intel Wireless MMX technology.  */
-int arm_arch_iwmmxt = 0;
-
-/* Nonzero if this chip supports Intel Wireless MMX2 technology.  */
-int arm_arch_iwmmxt2 = 0;
-
 /* Nonzero if this chip is an XScale.  */
 int arm_arch_xscale = 0;
 
@@ -3919,8 +3913,6 @@ arm_option_reconfigure_globals (void)
   arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
   arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
   arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
-  arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt);
-  arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2);
   arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv);
   arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv);
   arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32);
@@ -12378,11 +1237

[gcc r16-553] arm: remove iwmmxt registers from allocator tables

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:d0e86eba23d755fbd12c8ab35f827863b12131ea

commit r16-553-gd0e86eba23d755fbd12c8ab35f827863b12131ea
Author: Richard Earnshaw 
Date:   Wed Apr 30 18:13:43 2025 +0100

arm: remove iwmmxt registers from allocator tables

These registers can no-longer be allocated, so remove them from the
various tables.

gcc/ChangeLog:

* config/arm/aout.h (REGISTER_NAMES): Remove iwmmxt registers.
* config/arm/arm.h (FIRST_IWMMXT_REGNUM): Delete.
(LAST_IWMMXT_REGNUM): Delete.
(FIRST_IWMMXT_GR_REGNUM): Delete.
(LAST_IWMMXT_GR_REGNUM): Delete.
(IS_IWMMXT_REGNUM):  Delete.
(IS_IWMMXT_GR_REGNUM): Delete.
(FRAME_POINTER_REGNUM): Define relative to CC_REGNUM.
(ARG_POINTER_REGNUM): Define relative to FRAME_POINTER_REGNUM.
(FIRST_PSEUDO_REGISTER): Adjust.
(WREG): Delete.
(WGREG): Delete.
(REG_ALLOC_ORDER): Remove iWMMX registers.
(enum reg_class): Remove iWMMX register classes.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS):  Remove iWMMX registers.
* config/arm/arm.md (CC_REGNUM): Adjust value.
(VFPCC_RENGUM): Likewise.
(APSRQ_REGNUM): Likewise.
(APSRGE_REGNUM): Likewise.
(VPR_REGNUM): Likewise.
(RA_AUTH_CODE): Likewise.

Diff:
---
 gcc/config/arm/aout.h |  5 
 gcc/config/arm/arm.h  | 83 +++
 gcc/config/arm/arm.md | 12 
 3 files changed, 30 insertions(+), 70 deletions(-)

diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h
index cdce361e078d..a9b0dfaec383 100644
--- a/gcc/config/arm/aout.h
+++ b/gcc/config/arm/aout.h
@@ -69,11 +69,6 @@
   "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23",  \
   "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27",  \
   "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31",  \
-  "wr0",   "wr1",   "wr2",   "wr3",\
-  "wr4",   "wr5",   "wr6",   "wr7",\
-  "wr8",   "wr9",   "wr10",  "wr11",   \
-  "wr12",  "wr13",  "wr14",  "wr15",   \
-  "wcgr0", "wcgr1", "wcgr2", "wcgr3",  \
   "cc", "vfpcc", "sfp", "afp", "apsrq", "apsrge", "p0",\
   "ra_auth_code"   \
 }
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 1166171e5937..2e9d678d32a2 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -842,10 +842,6 @@ extern const int arm_arch_cde_coproc_bits[];
   1,1,1,1,1,1,1,1, \
   1,1,1,1,1,1,1,1, \
   1,1,1,1,1,1,1,1, \
-  /* IWMMXT regs.  */  \
-  1,1,1,1,1,1,1,1, \
-  1,1,1,1,1,1,1,1, \
-  1,1,1,1, \
   /* Specials.  */ \
   1,1,1,1,1,1,1,1  \
 }
@@ -872,10 +868,6 @@ extern const int arm_arch_cde_coproc_bits[];
   1,1,1,1,1,1,1,1, \
   1,1,1,1,1,1,1,1, \
   1,1,1,1,1,1,1,1, \
-  /* IWMMXT regs.  */  \
-  1,1,1,1,1,1,1,1, \
-  1,1,1,1,1,1,1,1, \
-  1,1,1,1, \
   /* Specials.  */ \
   1,1,1,1,1,1,1,1  \
 }
@@ -997,23 +989,11 @@ extern const int arm_arch_cde_coproc_bits[];
 /* Register to use for pushing function arguments.  */
 #define STACK_POINTER_REGNUM   SP_REGNUM
 
-#define FIRST_IWMMXT_REGNUM(LAST_HI_VFP_REGNUM + 1)
-#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
-
-/* Need to sync with WCGR in iwmmxt.md.  */
-#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
-#define LAST_IWMMXT_GR_REGNUM  (FIRST_IWMMXT_GR_REGNUM + 3)
-
-#define IS_IWMMXT_REGNUM(REGNUM) \
-  (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
-#define IS_IWMMXT_GR_REGNUM(REGNUM) \
-  (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
-
 /* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM   102
+#define FRAME_POINTER_REGNUM   (CC_REGNUM + 2)
 
 /* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 103
+#define ARG_POINTER_REGNUM (FRAME_POINTER_REGNUM + 1)
 
 #define FIRST_VFP_REGNUM   16
 #define D7_VFP_REGNUM  (FIRST_VFP_REGNUM + 15)
@@ -1054,9 +1034,8 @@ extern const int arm_arch_cde_coproc_bits[];
 
 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP
+ 1 APSRQ + 1 APSRGE + 1 VPR + 1 Pseudo register to save PAC.  */
-/* Intel Wireless MMX Technology registers add 16 + 4 more.  */
 /* VFP (VFP3) adds 32 (64) + 1 VFPCC.  */
-#define FIRST_PSEUDO_REGISTER   108
+#define FIRST_PSEUDO_REGISTER   88
 
 #define DWARF_PAC_REGNUM 143
 
@@ -1222,8 +1201,6 @@ extern int arm_regs_in_sequence[];
function.  */
 
 #define VREG(X)  (FIRST

[gcc r16-554] arm: doc: cleanup documentation references to iWMMXT extensions

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:9416969d795003c06714f7663bf670efd7efdd46

commit r16-554-g9416969d795003c06714f7663bf670efd7efdd46
Author: Richard Earnshaw 
Date:   Thu May 8 10:33:55 2025 +0100

arm: doc: cleanup documentation references to iWMMXT extensions

Now that the iwmmxt extensions have been removed, clean up the
references to it in the documentation.  We keep the
-mcpu/-mtune/-march references as these are still accepted by the
driver.

gcc/ChangeLog:

* doc/extend.texi: Remove the iwmmxt intrinsics.
* doc/md.texi: Remove the iwmmxt-related constraints.

Diff:
---
 gcc/doc/extend.texi | 155 
 gcc/doc/md.texi |   9 ---
 2 files changed, 164 deletions(-)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 212d24875584..40ccf22b29f4 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -17905,7 +17905,6 @@ instructions, but allow the compiler to schedule those 
calls.
 * Alpha Built-in Functions::
 * ARC Built-in Functions::
 * ARC SIMD Built-in Functions::
-* ARM iWMMXt Built-in Functions::
 * ARM C Language Extensions (ACLE)::
 * ARM Floating Point Status and Control Intrinsics::
 * ARM ARMv8-M Security Extensions::
@@ -18521,160 +18520,6 @@ _v4hi __builtin_arc_vaddsub4h (__v4hi, __v4hi);
 _v4hi __builtin_arc_vsubadd4h (__v4hi, __v4hi);
 @end example
 
-@node ARM iWMMXt Built-in Functions
-@subsection ARM iWMMXt Built-in Functions
-
-These built-in functions are available for the ARM family of
-processors when the @option{-mcpu=iwmmxt} switch is used:
-
-@smallexample
-typedef int v2si __attribute__ ((vector_size (8)));
-typedef short v4hi __attribute__ ((vector_size (8)));
-typedef char v8qi __attribute__ ((vector_size (8)));
-
-int __builtin_arm_getwcgr0 (void);
-void __builtin_arm_setwcgr0 (int);
-int __builtin_arm_getwcgr1 (void);
-void __builtin_arm_setwcgr1 (int);
-int __builtin_arm_getwcgr2 (void);
-void __builtin_arm_setwcgr2 (int);
-int __builtin_arm_getwcgr3 (void);
-void __builtin_arm_setwcgr3 (int);
-int __builtin_arm_textrmsb (v8qi, int);
-int __builtin_arm_textrmsh (v4hi, int);
-int __builtin_arm_textrmsw (v2si, int);
-int __builtin_arm_textrmub (v8qi, int);
-int __builtin_arm_textrmuh (v4hi, int);
-int __builtin_arm_textrmuw (v2si, int);
-v8qi __builtin_arm_tinsrb (v8qi, int, int);
-v4hi __builtin_arm_tinsrh (v4hi, int, int);
-v2si __builtin_arm_tinsrw (v2si, int, int);
-long long __builtin_arm_tmia (long long, int, int);
-long long __builtin_arm_tmiabb (long long, int, int);
-long long __builtin_arm_tmiabt (long long, int, int);
-long long __builtin_arm_tmiaph (long long, int, int);
-long long __builtin_arm_tmiatb (long long, int, int);
-long long __builtin_arm_tmiatt (long long, int, int);
-int __builtin_arm_tmovmskb (v8qi);
-int __builtin_arm_tmovmskh (v4hi);
-int __builtin_arm_tmovmskw (v2si);
-long long __builtin_arm_waccb (v8qi);
-long long __builtin_arm_wacch (v4hi);
-long long __builtin_arm_waccw (v2si);
-v8qi __builtin_arm_waddb (v8qi, v8qi);
-v8qi __builtin_arm_waddbss (v8qi, v8qi);
-v8qi __builtin_arm_waddbus (v8qi, v8qi);
-v4hi __builtin_arm_waddh (v4hi, v4hi);
-v4hi __builtin_arm_waddhss (v4hi, v4hi);
-v4hi __builtin_arm_waddhus (v4hi, v4hi);
-v2si __builtin_arm_waddw (v2si, v2si);
-v2si __builtin_arm_waddwss (v2si, v2si);
-v2si __builtin_arm_waddwus (v2si, v2si);
-v8qi __builtin_arm_walign (v8qi, v8qi, int);
-long long __builtin_arm_wand(long long, long long);
-long long __builtin_arm_wandn (long long, long long);
-v8qi __builtin_arm_wavg2b (v8qi, v8qi);
-v8qi __builtin_arm_wavg2br (v8qi, v8qi);
-v4hi __builtin_arm_wavg2h (v4hi, v4hi);
-v4hi __builtin_arm_wavg2hr (v4hi, v4hi);
-v8qi __builtin_arm_wcmpeqb (v8qi, v8qi);
-v4hi __builtin_arm_wcmpeqh (v4hi, v4hi);
-v2si __builtin_arm_wcmpeqw (v2si, v2si);
-v8qi __builtin_arm_wcmpgtsb (v8qi, v8qi);
-v4hi __builtin_arm_wcmpgtsh (v4hi, v4hi);
-v2si __builtin_arm_wcmpgtsw (v2si, v2si);
-v8qi __builtin_arm_wcmpgtub (v8qi, v8qi);
-v4hi __builtin_arm_wcmpgtuh (v4hi, v4hi);
-v2si __builtin_arm_wcmpgtuw (v2si, v2si);
-long long __builtin_arm_wmacs (long long, v4hi, v4hi);
-long long __builtin_arm_wmacsz (v4hi, v4hi);
-long long __builtin_arm_wmacu (long long, v4hi, v4hi);
-long long __builtin_arm_wmacuz (v4hi, v4hi);
-v4hi __builtin_arm_wmadds (v4hi, v4hi);
-v4hi __builtin_arm_wmaddu (v4hi, v4hi);
-v8qi __builtin_arm_wmaxsb (v8qi, v8qi);
-v4hi __builtin_arm_wmaxsh (v4hi, v4hi);
-v2si __builtin_arm_wmaxsw (v2si, v2si);
-v8qi __builtin_arm_wmaxub (v8qi, v8qi);
-v4hi __builtin_arm_wmaxuh (v4hi, v4hi);
-v2si __builtin_arm_wmaxuw (v2si, v2si);
-v8qi __builtin_arm_wminsb (v8qi, v8qi);
-v4hi __builtin_arm_wminsh (v4hi, v4hi);
-v2si __builtin_arm_wminsw (v2si, v2si);
-v8qi __builtin_arm_wminub (v8qi, v8qi);
-v4hi __builtin_arm_wminuh (v4hi, v4hi);
-v2si __builtin_arm_wminuw (v2si, v2si);
-v4hi __builtin_arm_wmulsm (v4hi, v4hi);
-v4hi __builtin_arm_wmulul (v4hi, v4hi);
-v4hi __builtin_arm_wmulum (v4hi, v4hi);
-long long

[gcc r16-548] arm: Remove iwmmxt support from arm.cc

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:dd15319be3a8de4e22dbd5475e52f44d149a69bb

commit r16-548-gdd15319be3a8de4e22dbd5475e52f44d149a69bb
Author: Richard Earnshaw 
Date:   Mon Apr 28 17:48:51 2025 +0100

arm: Remove iwmmxt support from arm.cc

TARGET_IWMMXT, TARGET_IWMMXT2 and their _REALLY_ equivalents are never
true now, so the code using them can be simplified.

gcc/ChangeLog:

* config/arm/arm.cc (arm_option_check_internal): Remove
IWMMXT check.
(arm_options_perform_arch_sanity_checks): Likewise.
(use_return_insn): Likewise.
(arm_init_cumulative_args): Likewise.
(arm_legitimate_index_p): Likewise.
(thumb2_legitimate_index_p): Likewise.
(arm_compute_save_core_reg_mask): Likewise.
(output_return_instruction): Likewise.
(arm_compute_frame_layout): Likewise.
(arm_save_coproc_regs): Likewise.
(arm_hard_regno_mode_ok): Likewise.
(arm_expand_epilogue_apcs_frame): Likewise.
(arm_expand_epilogue): Likewise.
(arm_vector_mode_supported_p): Likewise.
(arm_preferred_simd_mode): Likewise.
(arm_conditional_register_usage): Likewise.

Diff:
---
 gcc/config/arm/arm.cc | 183 +-
 1 file changed, 2 insertions(+), 181 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 663b58a58118..78a1f744ec4e 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -2970,11 +2970,6 @@ arm_option_check_internal (struct gcc_options *opts)
 {
   int flags = opts->x_target_flags;
 
-  /* iWMMXt and NEON are incompatible.  */
-  if (TARGET_IWMMXT
-  && bitmap_bit_p (arm_active_target.isa, isa_bit_neon))
-error ("iWMMXt and NEON are incompatible");
-
   /* Make sure that the processor choice does not conflict with any of the
  other command line choices.  */
   if (TARGET_ARM_P (flags)
@@ -2997,10 +2992,6 @@ arm_option_check_internal (struct gcc_options *opts)
 warning (0, "%<-g%> with %<-mno-apcs-frame%> may not give sensible "
 "debugging");
 
-  /* iWMMXt unsupported under Thumb mode.  */
-  if (TARGET_THUMB_P (flags) && TARGET_IWMMXT)
-error ("iWMMXt unsupported under Thumb mode");
-
   if (TARGET_HARD_TP && TARGET_THUMB1_P (flags))
 error ("cannot use %<-mtp=cp15%> with 16-bit Thumb");
 
@@ -3997,9 +3988,6 @@ arm_options_perform_arch_sanity_checks (void)
   if (arm_arch5t)
 target_flags &= ~MASK_INTERWORK;
 
-  if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
-error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
-
   /* BPABI targets use linker tricks to allow interworking on cores
  without thumb support.  */
   if (TARGET_INTERWORK
@@ -4550,11 +4538,6 @@ use_return_insn (int iscond, rtx sibling)
   if (reg_needs_saving_p (regno))
return 0;
 
-  if (TARGET_REALLY_IWMMXT)
-for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
-  if (reg_needs_saving_p (regno))
-   return 0;
-
   return 1;
 }
 
@@ -7188,19 +7171,6 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree 
fntype,
  named_count avoids having to change the way arm handles 'named' */
   pcum->named_count = 0;
   pcum->nargs = 0;
-
-  if (TARGET_REALLY_IWMMXT && fntype)
-{
-  tree fn_arg;
-
-  for (fn_arg = TYPE_ARG_TYPES (fntype);
-  fn_arg;
-  fn_arg = TREE_CHAIN (fn_arg))
-   pcum->named_count += 1;
-
-  if (! pcum->named_count)
-   pcum->named_count = INT_MAX;
-}
 }
 
 /* Return 2 if double word alignment is required for argument passing,
@@ -8868,12 +8838,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, 
RTX_CODE outer,
&& INTVAL (index) > -1024
&& (INTVAL (index) & 3) == 0);
 
-  if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
-return (code == CONST_INT
-   && INTVAL (index) < 1024
-   && INTVAL (index) > -1024
-   && (INTVAL (index) & 3) == 0);
-
   if (GET_MODE_SIZE (mode) <= 4
   && ! (arm_arch4
&& (mode == HImode
@@ -8953,17 +8917,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, 
int strict_p)
&& INTVAL (index) > -256
&& (INTVAL (index) & 3) == 0);
 
-  if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
-{
-  /* For DImode assume values will usually live in core regs
-and only allow LDRD addressing modes.  */
-  if (!TARGET_LDRD || mode != DImode)
-   return (code == CONST_INT
-   && INTVAL (index) < 1024
-   && INTVAL (index) > -1024
-   && (INTVAL (index) & 3) == 0);
-}
-
   /* For quad modes, we restrict the constant offset to be slightly less
  than what the instruction format permits.  We do this because for
  quad mode moves, we will actually decompose them into two separate
@@ -21414,34 +21367,6 @@ arm_compute_save_co

[gcc r16-549] arm: remove iwmmxt-related attributes from machine description

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:d88614d942264ade6a002c4e0a741341477dce34

commit r16-549-gd88614d942264ade6a002c4e0a741341477dce34
Author: Richard Earnshaw 
Date:   Wed Apr 30 11:45:28 2025 +0100

arm: remove iwmmxt-related attributes from machine description

Since we no-longer have any iwmxxt instructions, the iwmmxt-related
attributes can never be set.  Consequently, the marvel-f-iwmmxt
scheduler is redundant as none of the pipes are ever used now.

gcc/ChangeLog:

* config/arm/arm.md (core_cycles): Remove iwmmxt attributes.
* config/arm/types.md (autodetect_type): Likewise.
* config/arm/marvell-f-iwmmxt.md: Removed.
* config/arm/t-arm: Remove marvell-f-iwmmxt.md

Diff:
---
 gcc/config/arm/arm.md  |  14 +--
 gcc/config/arm/marvell-f-iwmmxt.md | 189 -
 gcc/config/arm/t-arm   |   1 -
 gcc/config/arm/types.md| 123 
 4 files changed, 1 insertion(+), 326 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index ce1b987b2415..7cbff8d3b603 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -358,18 +358,7 @@
 alus_ext, alus_imm, alus_sreg,\
 alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
 logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
-logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
-wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
-wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
-wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
-wmmx_wshufh, wmmx_wcmpeq, wmmx_wcmpgt, wmmx_wmax, wmmx_wmin, wmmx_wpack,\
-wmmx_wunpckih, wmmx_wunpckil, wmmx_wunpckeh, wmmx_wunpckel, wmmx_wror,\
-wmmx_wsra, wmmx_wsrl, wmmx_wsll, wmmx_wmadd, wmmx_tmia, wmmx_tmiaph,\
-wmmx_tmiaxy, wmmx_tbcst, wmmx_tmovmsk, wmmx_wacc, wmmx_waligni,\
-wmmx_walignr, wmmx_tandc, wmmx_textrc, wmmx_torc, wmmx_torvsc, wmmx_wsad,\
-wmmx_wabs, wmmx_wabsdiff, wmmx_waddsubhx, wmmx_wsubaddhx, wmmx_wavg4,\
-wmmx_wmulw, wmmx_wqmulm, wmmx_wqmulwm, wmmx_waddbhus, wmmx_wqmiaxy,\
-wmmx_wmiaxy, wmmx_wmiawxy, wmmx_wmerge")
+logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel")
(const_string "single")
(const_string "multi")))
 
@@ -431,7 +420,6 @@
  (const_string "yes")
  (const_string "no"
 
-(include "marvell-f-iwmmxt.md")
 (include "arm-generic.md")
 (include "arm926ejs.md")
 (include "arm1020e.md")
diff --git a/gcc/config/arm/marvell-f-iwmmxt.md 
b/gcc/config/arm/marvell-f-iwmmxt.md
deleted file mode 100644
index c9c7b00f6cbd..
--- a/gcc/config/arm/marvell-f-iwmmxt.md
+++ /dev/null
@@ -1,189 +0,0 @@
-;; Marvell WMMX2 pipeline description
-;; Copyright (C) 2011-2025 Free Software Foundation, Inc.
-;; Written by Marvell, Inc.
-
-;; This file is part of GCC.
-
-;; GCC is free software; you can redistribute it and/or modify it
-;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 3, or (at your
-;; option) any later version.
-
-;; GCC is distributed in the hope that it will be useful, but WITHOUT
-;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-;; License for more details.
-
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3.  If not see
-;; .
-
-
-(define_automaton "marvell_f_iwmmxt")
-
-
-;; Pipelines
-
-
-;; This is a 7-stage pipelines:
-;;
-;;MD | MI | ME1 | ME2 | ME3 | ME4 | MW
-;;
-;; There are various bypasses modelled to a greater or lesser extent.
-;;
-;; Latencies in this file correspond to the number of cycles after
-;; the issue stage that it takes for the result of the instruction to
-;; be computed, or for its side-effects to occur.
-
-(define_cpu_unit "mf_iwmmxt_MD" "marvell_f_iwmmxt")
-(define_cpu_unit "mf_iwmmxt_MI" "marvell_f_iwmmxt")
-(define_cpu_unit "mf_iwmmxt_ME1" "marvell_f_iwmmxt")
-(define_cpu_unit "mf_iwmmxt_ME2" "marvell_f_iwmmxt")
-(define_cpu_unit "mf_iwmmxt_ME3" "marvell_f_iwmmxt")
-(define_cpu_unit "mf_iwmmxt_ME4" "marvell_f_iwmmxt")
-(define_cpu_unit "mf_iwmmxt_MW" "marvell_f_iwmmxt")
-
-(define_reservation "mf_iwmmxt_ME"
-  "mf_iwmmxt_ME1,mf_iwmmxt_ME2,mf_iwmmxt_ME3,mf_iwmmxt_ME4"
-)
-
-(define_reservation "mf_iwmmxt_pipeline"
-  "mf_iwmmxt_MD, mf_iwmmxt_MI, mf_iwmmxt_ME, mf_iwmmxt_MW"
-)
-
-;; An attribute to indicate whether our reservations are applicable.
-(define_attr "marvell_f_iwmmxt" "yes,no"
-  (const (if_then_else (symbol_ref "arm_arch_iwmmxt")
-   (const_st

[gcc r16-547] arm: remove support for the iwmmxt ABI variant.

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:5314f159803e10987f12be2bd90a8c3d9e494999

commit r16-547-g5314f159803e10987f12be2bd90a8c3d9e494999
Author: Richard Earnshaw 
Date:   Mon Apr 28 17:15:45 2025 +0100

arm: remove support for the iwmmxt ABI variant.

The iwmmxt ABI is a variant of the ABI that supported passing certain
parameters and results in iwmmxt registers.  But since we no-longer
support the instructions that can read and write these registers, the
ABI variant can no-longer be used.

gcc/ChangeLog:

* config.gcc (arm, --with-abi): Remove iwmmxt abi option.
* config/arm/arm.opt (enum ARM_ABI_IWMMXT): Remove.
* config/arm/arm.h (TARGET_IWMMXT_ABI): Delete.
(enum arm_pcs): Remove ARM_PCS_AAPCS_IWMMXT.
(FUNCTION_ARG_REGNO_P): Remove IWMMXT ABI support.
(CUMULATIVE_ARGS): Remove iwmmxt_nregs.
* config/arm/arm.cc (arm_options_perform_arch_sanity_checks):
Remove IWMMXT ABI checks.
(arm_libcall_value_1): Likewise.
(arm_function_value_regno_p): Likewise.
(arm_apply_result_size): Remove adjustment for IWMMXT ABI.
(arm_function_arg): Remove IWMMXT ABI support.
(arm_arg_partial_bytes): Likewise.
(arm_function_arg_advance): Likewise.
(arm_init_cumulative_args): Don't initialize iwmmxt_nregs.
* doc/invoke.texi (arm -mabi): Remove mention of the iwmmxt
ABI option.
* config/arm/arm-opts.h (enum arm_abi_type): Remove ARM_ABI_IWMMXT.

Diff:
---
 gcc/config.gcc|  2 +-
 gcc/config/arm/arm-opts.h |  1 -
 gcc/config/arm/arm.cc | 44 +++-
 gcc/config/arm/arm.h  |  8 +---
 gcc/config/arm/arm.opt|  3 ---
 gcc/doc/invoke.texi   |  2 +-
 6 files changed, 6 insertions(+), 54 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index afbf82fd2b8f..c9fe996f2f7c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4459,7 +4459,7 @@ case "${target}" in
 
case "$with_abi" in
"" \
-   | apcs-gnu | atpcs | aapcs | iwmmxt | aapcs-linux )
+   | apcs-gnu | atpcs | aapcs | aapcs-linux )
#OK
;;
*)
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index 06a1939d087f..5c543bf52466 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -46,7 +46,6 @@ enum arm_abi_type
   ARM_ABI_APCS,
   ARM_ABI_ATPCS,
   ARM_ABI_AAPCS,
-  ARM_ABI_IWMMXT,
   ARM_ABI_AAPCS_LINUX
 };
 
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 6bdb68aa7881..663b58a58118 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -4000,9 +4000,6 @@ arm_options_perform_arch_sanity_checks (void)
   if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
 
-  if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
-error ("iwmmxt abi requires an iwmmxt capable cpu");
-
   /* BPABI targets use linker tricks to allow interworking on cores
  without thumb support.  */
   if (TARGET_INTERWORK
@@ -4043,9 +4040,7 @@ arm_options_perform_arch_sanity_checks (void)
 
   if (TARGET_AAPCS_BASED)
 {
-  if (arm_abi == ARM_ABI_IWMMXT)
-   arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
-  else if (TARGET_HARD_FLOAT_ABI)
+  if (TARGET_HARD_FLOAT_ABI)
{
  arm_pcs_default = ARM_PCS_AAPCS_VFP;
  if (!bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv2)
@@ -6048,9 +6043,6 @@ arm_libcall_value_1 (machine_mode mode)
 {
   if (TARGET_AAPCS_BASED)
 return aapcs_libcall_value (mode);
-  else if (TARGET_IWMMXT_ABI
-  && arm_vector_mode_supported_p (mode))
-return gen_rtx_REG (mode, FIRST_IWMMXT_REGNUM);
   else
 return gen_rtx_REG (mode, ARG_REGISTER (1));
 }
@@ -6083,9 +6075,7 @@ arm_function_value_regno_p (const unsigned int regno)
   || (TARGET_32BIT
  && TARGET_AAPCS_BASED
  && TARGET_HARD_FLOAT
- && regno == FIRST_VFP_REGNUM)
-  || (TARGET_IWMMXT_ABI
- && regno == FIRST_IWMMXT_REGNUM))
+ && regno == FIRST_VFP_REGNUM))
 return true;
 
   return false;
@@ -6102,8 +6092,6 @@ arm_apply_result_size (void)
 {
   if (TARGET_HARD_FLOAT_ABI)
size += 32;
-  if (TARGET_IWMMXT_ABI)
-   size += 8;
 }
 
   return size;
@@ -6265,7 +6253,6 @@ const struct pcs_attribute_arg
 #if 0
 /* We could recognize these, but changes would be needed elsewhere
  * to implement them.  */
-{"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT},
 {"atpcs", ARM_PCS_ATPCS},
 {"apcs", ARM_PCS_APCS},
 #endif
@@ -7195,7 +7182,6 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree 
fntype,
 
   /* On the ARM, the offset starts at 0.  */
   pcum->nregs = 0;
-  pcum->iwmmxt_nregs = 0;
   pcum->can_split = true;
 
   /* Varargs vectors are treated the same 

[gcc r16-550] arm: cleanup iterators.md after removing iwmmxt

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:f7ad5853c43729b9cd4d5570f0ed3f3553426c12

commit r16-550-gf7ad5853c43729b9cd4d5570f0ed3f3553426c12
Author: Richard Earnshaw 
Date:   Wed Apr 30 13:49:13 2025 +0100

arm: cleanup iterators.md after removing iwmmxt

Mostly this is just removing references to iWMMXT in comments, but also 
remove
some now unused iterators and attributes.

gcc/ChangeLog:

* config/arm/iterators.md (VMMX, VMMX2): Remove mode iterators.
(MMX_char): Remove mode iterator attribute.

Diff:
---
 gcc/config/arm/iterators.md | 20 ++--
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 743fe48e6ccc..0c163ed47820 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -59,30 +59,25 @@
 ;; A list of modes which the VFP unit can handle
 (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
 
-;; Integer element sizes implemented by IWMMXT.
-(define_mode_iterator VMMX [V2SI V4HI V8QI])
-
-(define_mode_iterator VMMX2 [V4HI V2SI])
-
 ;; Integer element sizes for shifts.
 (define_mode_iterator VSHFT [V4HI V2SI DI])
 
-;; Integer and float modes supported by Neon and IWMMXT.
+;; Integer and float modes supported by Neon.
 (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
 
-;; Integer and float modes supported by Neon, IWMMXT and MVE.
+;; Integer and float modes supported by Neon and MVE.
 (define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI])
 
-;; Integer and float modes supported by Neon and IWMMXT but not MVE.
+;; Integer and float modes supported by Neon but not MVE.
 (define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF])
 
-;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
+;; Integer and float modes supported by Neon, except V2DI.
 (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
 
-;; Integer modes supported by Neon and IWMMXT
+;; Integer modes supported by Neon
 (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
 
-;; Integer modes supported by Neon and IWMMXT, except V2DI
+;; Integer modes supported by Neon, except V2DI
 (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
 
 ;; Double-width vector modes, on which we support arithmetic (no HF!)
@@ -1644,9 +1639,6 @@
 ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM.
 (define_mode_attr arch [(CC_Z "32") (SI "t1")])
 
-;; Determine element size suffix from vector mode.
-(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
-
 ;; vtbl suffix for NEON vector modes.
 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])

[gcc r16-551] arm: remove dead predefines when using WMMX

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:31648852ad3f4b76e47dd468f88da5f4d36c134e

commit r16-551-g31648852ad3f4b76e47dd468f88da5f4d36c134e
Author: Richard Earnshaw 
Date:   Wed Apr 30 13:52:31 2025 +0100

arm: remove dead predefines when using WMMX

Since we no-longer enable iWMMXT, these predefines are no-longer enabled
when preprocessing C.  Remove them.

gcc/ChangeLog:

* config/arm/arm-c.cc (arm_cpu_builtins):  Remove predefines
for __IWWMXT__, __IWMMXT2__ and __ARM_WMMX.

Diff:
---
 gcc/config/arm/arm-c.cc | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc
index 15e4080904f3..d257e62b563b 100644
--- a/gcc/config/arm/arm-c.cc
+++ b/gcc/config/arm/arm-c.cc
@@ -373,13 +373,6 @@ arm_cpu_builtins (struct cpp_reader* pfile)
   builtin_define (arm_arch_name);
   if (arm_arch_xscale)
 builtin_define ("__XSCALE__");
-  if (arm_arch_iwmmxt)
-{
-  builtin_define ("__IWMMXT__");
-  builtin_define ("__ARM_WMMX");
-}
-  if (arm_arch_iwmmxt2)
-builtin_define ("__IWMMXT2__");
   /* ARMv6KZ was originally identified as the misspelled __ARM_ARCH_6ZK__.  To
  preserve the existing behavior, the misspelled feature macro must still be
  defined.  */

[gcc r16-454] arm: Only reverse FP inequalities when -ffinite-math-only [PR110796...]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:0a339746e7646bacf2c8aa5512268d23660f26f9

commit r16-454-g0a339746e7646bacf2c8aa5512268d23660f26f9
Author: Richard Earnshaw 
Date:   Fri Mar 28 12:59:03 2025 +

arm: Only reverse FP inequalities when -ffinite-math-only [PR110796...]

On Arm we have been failing to fully implement support for IEEE NaNs
in inequality comparisons because we have allowed reversing of
inequalities in a way that allows SELECT_CC_MODE to produce different
answers.  For example, the reverse of GT is UNLE, but if we pass these
two RTL codes to SELECT_CC_MODE, the former will return CCFPEmode,
while the latter CCFPmode.

It would be possible to allow fully reversible FPmodes, but to do so
would involve adding yet more RTL codes, something like NOT_GT and
NOT_UNLE, for the cases we cannot currently reverse.  NOT_GT would
then have the same condition code generation as UNLT, but the same
mode selection as GT.

In the mean time, we need to restrict REVERSIBLE_CC_MODE to
non-floating modes unless we are compiling with -ffinite-math-only.  In
that case we can continue to reverse the comparisons, but now we want
to always select CCFPmode as there's no need to consider the exception
raising cases.

PR target/110796
PR target/118446

gcc/ChangeLog:

* config/arm/arm.h (REVERSIBLE_CC_MODE): FP modes are only
reversible if flag_finite_math_only.
* config/arm/arm.cc (arm_select_cc_mode): Return CCFPmode for all
FP comparisons if flag_finite_math_only.

gcc/testsuite/ChangeLog:

* gcc.target/arm/armv8_2-fp16-arith-1.c: Adjust due to no-longer
emitting VCMPE when -ffast-math..

Diff:
---
 gcc/config/arm/arm.cc   | 4 +++-
 gcc/config/arm/arm.h| 6 +-
 gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c | 3 +--
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 670f487bcce3..fccddb0e7bc5 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -16218,7 +16218,9 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
case LE:
case GT:
case GE:
- return CCFPEmode;
+ return (flag_finite_math_only
+ ? CCFPmode
+ : CCFPEmode);
 
default:
  gcc_unreachable ();
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8472b7561272..08d3f0dae3da 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2257,7 +2257,11 @@ extern int making_const_table;
 
 #define SELECT_CC_MODE(OP, X, Y)  arm_select_cc_mode (OP, X, Y)
 
-#define REVERSIBLE_CC_MODE(MODE) 1
+/* Floating-point modes cannot be reversed unless we don't care about
+   NaNs.  */
+#define REVERSIBLE_CC_MODE(MODE)   \
+  (flag_finite_math_only   \
+   || !((MODE) == CCFPmode || (MODE) == CCFPEmode))
 
 #define REVERSE_CONDITION(CODE,MODE) \
   (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c 
b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c
index 52b87376dc78..f3fea524809e 100644
--- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c
+++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-arith-1.c
@@ -106,8 +106,7 @@ TEST_CMP (greaterthanqual, >=, int16x8_t, float16x8_t)
 /* { dg-final { scan-assembler-times {vdiv\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 13 
} }  */
 
 /* For float16_t.  */
-/* { dg-final { scan-assembler-times {vcmp\.f32\ts[0-9]+, s[0-9]+} 2 } }  */
-/* { dg-final { scan-assembler-times {vcmpe\.f32\ts[0-9]+, s[0-9]+} 4 } }  */
+/* { dg-final { scan-assembler-times {vcmp\.f32\ts[0-9]+, s[0-9]+} 6 } }  */
 
 /* For float16x4_t.  */
 /* { dg-final { scan-assembler-times {vceq\.f16\td[0-9]+, d[0-9]+} 2 } }  */

[gcc r16-455] arm: select CCFPEmode for LTGT [PR91323]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:fe10ca6e3cf583640155812b230a0153ce4dc7b7

commit r16-455-gfe10ca6e3cf583640155812b230a0153ce4dc7b7
Author: Richard Earnshaw 
Date:   Mon Mar 31 18:06:54 2025 +0100

arm: select CCFPEmode for LTGT [PR91323]

Besides Arm, there are three other ports that define both CCFPmode and
CCFPEmode.  AArch64 and Sparc return CCFPEmode for LTGT; the other,
Visium, doesn't support LTGT at all.

AArch64 was changed in r8-5286-g8332c5ee8c5f3b, and Sparc with
r10-2926-g000a5f8d23c04c.

I suspect this issue is latent on Arm because cbranch?f4 and cstore?f4
reject LTGT and UNEQ and we fall back to a generic expansion which
happens to work.  Nevertheless, this patch updates the relevant bits
of the Arm port to match the specification introduced in
r10-2926-g000a5f8d23c04c.

gcc/ChangeLog:

PR target/91323
* config/arm/arm.cc (arm_select_cc_mode): Use CCFPEmode for LTGT.

Diff:
---
 gcc/config/arm/arm.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index fccddb0e7bc5..6bdb68aa7881 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -16211,13 +16211,13 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
case UNGT:
case UNGE:
case UNEQ:
-   case LTGT:
  return CCFPmode;
 
case LT:
case LE:
case GT:
case GE:
+   case LTGT:
  return (flag_finite_math_only
  ? CCFPmode
  : CCFPEmode);

[gcc r16-475] gensupport: validate compact constraint modifiers

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:62dec5d9f60a0207c3c9147ceb8d4f7281e3fa80

commit r16-475-g62dec5d9f60a0207c3c9147ceb8d4f7281e3fa80
Author: Richard Earnshaw 
Date:   Mon Apr 14 15:46:54 2025 +0100

gensupport: validate compact constraint modifiers

For constraints there are operand modifiers and constraint qualifiers.
Operand modifiers apply to all alternatives and must appear, in
traditional syntax before the first alternative.  Constraint
qualifiers, on the other hand must appear in each alternative to which
they apply.

There's no easy way to validate the distinction in the traditional md
format, but when using the new compact format we can enforce some
semantic checking of these characters to avoid some potentially
surprising code generation.

gcc/

* gensupport.cc (conlist::conlist): Pass a location to the 
constructor.
Only allow skipping of non-alpha-numeric characters when parsing a
number and only allow '=', '+' or '%'.  Add some error checking when
parsing an operand number.
(parse_section_layout): Pass the location to the conlist 
constructor.
(parse_section): Allow an optional list of forbidden characters.
If specified, reject strings containing them.
(convert_syntax): Reject '=', '+' or '%' in an alternative.

Diff:
---
 gcc/gensupport.cc | 37 ++---
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/gcc/gensupport.cc b/gcc/gensupport.cc
index 80f1976faf1d..ac0132860a98 100644
--- a/gcc/gensupport.cc
+++ b/gcc/gensupport.cc
@@ -656,7 +656,7 @@ public:
  i.e. if rtx is the relevant match_operand or match_scratch then
  [ns..ns + len) should equal itoa (XINT (rtx, 0)), and if set_attr then
  [ns..ns + len) should equal XSTR (rtx, 0).  */
-  conlist (const char *ns, unsigned int len, bool numeric)
+  conlist (const char *ns, unsigned int len, bool numeric, file_location loc)
   {
 /* Trim leading whitespaces.  */
 while (len > 0 && ISBLANK (*ns))
@@ -670,16 +670,26 @@ public:
   if (!ISBLANK (ns[i]))
break;
 
-/* Parse off any modifiers.  */
-while (len > 0 && !ISALNUM (*ns))
-  {
-   con += *(ns++);
-   len--;
-  }
+/* Only numeric values can have modifiers.  */
+if (numeric)
+  /* Parse off any modifiers.  */
+  while (len > 0 && !ISALNUM (*ns))
+   {
+ if (*ns != '=' && *ns != '+' && *ns != '%')
+   error_at (loc, "`%c` is not a valid operand modifier", *ns);
+ con += *(ns++);
+ len--;
+   }
 
 name.assign (ns, len);
 if (numeric)
-  idx = strtol (name.c_str (), (char **)NULL, 10);
+  {
+   char *endstr;
+   /* There should only be a numeric value now... */
+   idx = strtol (name.c_str (), &endstr, 10);
+   if (*endstr != '\0')
+ error_at (loc, "operand number expected, found %s", name.c_str ());
+  }
   }
 
   /* Adds a character to the end of the string.  */
@@ -832,7 +842,7 @@ parse_section_layout (file_location loc, const char 
**templ, const char *label,
  *templ += len;
  if (val == ',')
(*templ)++;
- list.push_back (conlist (name_start, len, numeric));
+ list.push_back (conlist (name_start, len, numeric, loc));
}
 }
 }
@@ -845,7 +855,8 @@ parse_section_layout (file_location loc, const char 
**templ, const char *label,
 
 static void
 parse_section (const char **templ, unsigned int n_elems, unsigned int alt_no,
-  vec_conlist &list, file_location loc, const char *name)
+  vec_conlist &list, file_location loc, const char *name,
+  const char *invalid_chars = NULL)
 {
   unsigned int i;
 
@@ -856,6 +867,10 @@ parse_section (const char **templ, unsigned int n_elems, 
unsigned int alt_no,
   {
if (**templ == 0 || **templ == '\n')
  fatal_at (loc, "missing ']'");
+   if (invalid_chars
+   && strchr (invalid_chars, **templ))
+ error_at (loc, "'%c' is not permitted in an alternative for a %s",
+   **templ, name);
list[i].add (**templ);
if (**templ == ',')
  {
@@ -981,7 +996,7 @@ convert_syntax (rtx x, file_location loc)
  /* Parse the constraint list, then the attribute list.  */
  if (tconvec.size () > 0)
parse_section (&templ, tconvec.size (), alt_no, tconvec, loc,
-  "constraint");
+  "constraint", "=+%");
 
  if (attrvec.size () > 0)
{

[gcc r16-615] Remove Marcus Shawcroft

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:fb4952dddb5860acd8460568a51981b9261362f5

commit r16-615-gfb4952dddb5860acd8460568a51981b9261362f5
Author: Richard Earnshaw 
Date:   Wed May 14 11:28:42 2025 +0100

Remove Marcus Shawcroft

Marcus has stood down as a maintainer and we have no new email address.

ChangeLog:

* MAINTAINERS: Marcus Shawcroft has resigned from the project.

Diff:
---
 MAINTAINERS | 2 --
 1 file changed, 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b1e7fadf1b8e..a3e3f25d9d18 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -57,7 +57,6 @@ docs, and the testsuite related to that.
 aarch64 ldp/stp Alex Coplan 
 aarch64 portRichard Earnshaw
 aarch64 portRichard Sandiford   
-aarch64 portMarcus Shawcroft
 aarch64 portKyrylo Tkachov  
 alpha port  Richard Henderson   
 amdgcn port Julian Brown
@@ -792,7 +791,6 @@ Senthil Kumar Selvaraj  saaadhu 

 Kostya Serebryany   kcc 
 Thiemo Seufer   -   
 Bill Seurer seurer  
-Marcus Shawcroftmshawcroft  
 Nathaniel Shead nshead  
 Tim Shentimshen 
 Joel Sherrill   joel

[gcc r16-733] arm: fully validate mem_noofs_operand [PR120351]

[Richard Earnshaw via Gcc-cvs]

https://gcc.gnu.org/g:e5bb7a328eb71daa02d15b48d3a6c6b8cd24abc5

commit r16-733-ge5bb7a328eb71daa02d15b48d3a6c6b8cd24abc5
Author: Richard Earnshaw 
Date:   Mon May 19 16:19:39 2025 +0100

arm: fully validate mem_noofs_operand [PR120351]

It's not enough to just check that a memory operand is of the form
mem(reg); after RA we also need to validate the register being used.
The safest way to do this is to call memory_operand.

PR target/120351

gcc/ChangeLog:

* config/arm/predicates.md (mem_noofs_operand): Also check the op
is a valid memory_operand.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr120351.c: New test.

Diff:
---
 gcc/config/arm/predicates.md|  3 ++-
 gcc/testsuite/gcc.target/arm/pr120351.c | 47 +
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 57d4ec660886..c683ec2c607f 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -901,7 +901,8 @@
 
 (define_predicate "mem_noofs_operand"
   (and (match_code "mem")
-   (match_code "reg" "0")))
+   (match_code "reg" "0")
+   (match_operand 0 "memory_operand")))
 
 (define_predicate "call_insn_operand"
   (ior (and (match_code "symbol_ref")
diff --git a/gcc/testsuite/gcc.target/arm/pr120351.c 
b/gcc/testsuite/gcc.target/arm/pr120351.c
new file mode 100644
index ..d8e9d73275ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr120351.c
@@ -0,0 +1,47 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-add-options arm_neon } */
+/* { dg-additional-options "-O2" } */
+
+
+typedef struct A
+{
+  int f1;
+} A;
+
+__inline void ref (A* x)
+{
+  __atomic_fetch_add(&x->f1, 1, 0);
+}
+
+typedef struct B
+{
+  A *d;
+  int *ptr;
+} B;
+
+void insertOne (B*, B*);
+
+void init (B *);
+__inline void copy (B *p, B *q)
+{
+  p->d  = q->d;
+  p->ptr = q->ptr;
+  ref (p->d);
+}
+
+__inline void emplace(B* x)
+{
+  B dummy;
+  B _tmp;
+  init (&dummy);
+  copy (&_tmp, &dummy);
+  insertOne(x, &_tmp);
+}
+
+void testing ()
+{
+  B test;
+  init (&test);
+  emplace(&test);
+}