https://gcc.gnu.org/g:b47c7a5a3c8280ea64754a6c24582236eacef8a2
commit r15-7372-gb47c7a5a3c8280ea64754a6c24582236eacef8a2
Author: Richard Earnshaw <rearn...@arm.com>
Date: Thu Dec 19 15:54:16 2024 +0000
arm: remove constraints from *pop_multiple_with_writeback_and_return
This pattern is intended to be used only by the epilogue generation
code and will always use fixed hard registers. As such, it does not
need any register constraints, which might be misleading if a
post-reload pass wanted to try renumbering various registers. So
remove the constraints.
Futhermore, to permit this pattern to match when popping just the PC
(which is not a valid register_operand), remove the match on the first
transfer register: pop_multiple_return will validate everything it
needs to.
gcc/ChangeLog:
* config/arm/arm.md (*pop_multiple_with_writeback_and_return):
Remove
constraints. Don't validate the first transfer register here.
Diff:
---
gcc/config/arm/arm.md | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 842903e0bcdb..442d86b93292 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -11964,12 +11964,10 @@
(define_insn "*pop_multiple_with_writeback_and_return"
[(match_parallel 0 "pop_multiple_return"
[(return)
- (set (match_operand:SI 1 "s_register_operand" "+rk")
+ (set (match_operand:SI 1 "register_operand" "")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_I_operand" "I")))
- (set (match_operand:SI 3 "s_register_operand" "=rk")
- (mem:SI (match_dup 1)))
- ])]
+ (match_operand:SI 2 "const_int_I_operand" "")))
+ ])]
"TARGET_32BIT && (reload_in_progress || reload_completed)"
"*
{
