[gcc] Created branch 'majin/heads/master' in namespace 'refs/users'

2025-02-04 Thread Ma Jin via Gcc-cvs 
The branch 'majin/heads/master' was created in namespace 'refs/users' pointing 
to:

 d0acb7b2b26d... PR modula2/118010 m2 libc lseek procedure interface correct

[gcc] Created branch 'majin/heads/dev' in namespace 'refs/users'

2025-02-04 Thread Ma Jin via Gcc-cvs 
The branch 'majin/heads/dev' was created in namespace 'refs/users' pointing to:

 d0acb7b2b26d... PR modula2/118010 m2 libc lseek procedure interface correct

[gcc/majin/heads/master] (160 commits) Fortran: Fix PR 47485.

2025-02-04 Thread Ma Jin via Gcc-cvs 
The branch 'majin/heads/master' was updated to point to:

 e41a5a2a0832... Fortran: Fix PR 47485.

It previously pointed to:

 d0acb7b2b26d... PR modula2/118010 m2 libc lseek procedure interface correct

Diff:

Summary of changes (added commits):
---

  e41a5a2... Fortran: Fix PR 47485. (*)
  f2a8f3c... RTEMS: Add Cortex-M33 multilib (*)
  432f988... Daily bump. (*)
  4d0faaa... PR modula2/115112 Incorrect line debugging information occu (*)
  f176028... c++: add fixed test [PR94100] (*)
  a64d9c9... c++: Fix ICE with #embed/RAW_DATA_CST after list conversion (*)
  64c66f5... Ada: Fix assertion failure with iterator in container aggre (*)
  88c9c4a... testsuite: RISC-V: Ignore pr118170.c for E ABI (*)
  a506abf... Fix file cache tunables documentation (*)
  bcd3886... arm: testsuite: Adapt mve-vabs.c to improved codegen (*)
  e6e40cb... c++: auto in trailing-return-type in parameter [PR117778] (*)
  53d1f6c... c++: bogus -Wvexing-parse with trailing-return-type [PR1187 (*)
  adf1da7... testsuite: XFAIL test in pr109393.c for ilp32 targets [PR11 (*)
  4c8c9c9... c/118742 - gimple FE parsing of unary operators of C promot (*)
  a2e0a30... IBM zSystems: Do not use @PLT with larl (*)
  d346af2... c++: Fix overeager Woverloaded-virtual with conversion oper (*)
  0675eb1... tree-optimization/117113 - ICE with unroll-and-jam (*)
  887bdab... c++: Properly detect calls to digest_init in build_vec_init (*)
  4b2726a... c++: Fix up pedwarn for capturing structured bindings in la (*)
  4c98b38... optabs: Fix widening optabs for vec-mode -> scalar-mode [PR (*)
  c2a0ee5... Add modular exponentiation for UNSIGNED. (*)
  5b46c01... rtl-optimization/117611 - ICE in simplify_shift_const_1 (*)
  a55e14b... lto/113207 - fix free_lang_data_in_type (*)
  d3627c7... c++: Improve contracts support in modules [PR108205] (*)
  736e8ee... c++: Modularise start_cleanup_fn [PR98893] (*)
  a5b54be... Daily bump. (*)
  26d3424... c++: find A pack from B in ...B> [PR1 (*)
  4c74379... c++/coroutines: Fix awaiter var creation [PR116506] (*)
  ec716ad... c++: coroutines and range for [PR118491] (*)
  f3a41e6... Fortran: different character lengths in array constructor [ (*)
  214224c... i386: Fix and improve TARGET_INDIRECT_BRANCH_REGISTER handl (*)
  606527f... aarch64: Fix dupq_* testsuite failures (*)
  88bb18c... hppa: Revise various millicode insn patterns to use match_o (*)
  6ec1982... c++/79786 - bougs invocation of DATA_ABI_ALIGNMENT macro (*)
  fbcbbfe... tree-optimization/118717 - store commoning vs. abnormals (*)
  75ab30f... Add a unit test for random access in the file cache (*)
  baf26fc... Size input line cache based on file size (*)
  33acec6... Remove m_total_lines support from input cache (*)
  4a992ec... Rebalance file_cache input line cache dynamically (*)
  ae814af... Add tunables for input buffer (*)
  6fef385... Daily bump. (*)
  969c308... PR modula2/117411 Request for documentation to include exce (*)
  c0008df... options: Adjust cl_optimization_compare to avoid checking I (*)
  427b871... Daily bump. (*)
  e8262c9... x86: Add a test for PR rtl-optimization/111673 (*)
  dceec9e... x86: Change "if (TARGET_X32 ...)" back to "else if (TARGET_ (*)
  e2d32c8... PR modula2/118703 Abort compiling m2pim_NumberIO_BinToStr (*)
  dd6247c... x86: Handle TARGET_INDIRECT_BRANCH_REGISTER for -fno-plt (*)
  cf24c0f... sarif-replay: support "cached" logical locations [ยง3.33.3] (*)
  8ca6bbf... Ada: Fix segfault on uninitialized variable as operand of p (*)
  b38efaf... x86: Add a -mstack-protector-guard=global test (*)
  d3ba883... Daily bump. (*)
  2c0a9b7... [committed][PR tree-optimization/114277] Fix missed optimiz (*)
  ebd111a... icf: Compare call argument types in certain cases and asm o (*)
  6141fd5... c++: check_flexarray fixes [PR117516] (*)
  a9172b1... libstdc++: Fix flat_foo::insert_range for non-common ranges (*)
  ee79773... libstdc++: Fix return value of vector::insert_range (*)
  d6418fe... Fortran: host association issue with symbol in COMMON block (*)
  af51fe9... OpenMP/Fortran: Add missing pop_state in parse_omp_dispatch (*)
  0d97700... c++: wrong-code with consteval constructor [PR117501] (*)
  decc6c0... [PR116234][LRA]: Check debug insn when looking at one insn  (*)
  3b49727... Fix wrong elaboration for allocator at library level of dyn (*)
  9fc0683... testsuite: Add testcase for already fixed PR [PR117498] (*)
  5f34558... force-indirect-call-2.c: Allow indirect branch via GOT (*)
  319f1d0... debug/100530 - Revert QUAL_ADDR_SPACE handling from dwarf2o (*)
  85e1714... niter: Make build_cltz_expr more robust [PR118689] (*)
  9e3ceed... Do not rely on non-SLP analysis for SLP outer loop vectoriz (*)
  c8cc686... Daily bump. (*)
  5d43c3f... libbacktrace: add casts to avoid undefined shifts (*)
  dd5978b... [testsuite] require profiling support [PR113689] (*)
  2ca288d... [testsuite] require -Ofast for vect-ifcvt-18 even without a (*)
  1e819a9... AVR: Provide built-ins

[gcc] Deleted branch 'majin/heads/dev' in namespace 'refs/users'

2025-02-05 Thread Ma Jin via Gcc-cvs 
The branch 'majin/heads/dev' in namespace 'refs/users' was deleted.
It previously pointed to:

 d0acb7b2b26d... PR modula2/118010 m2 libc lseek procedure interface correct

[gcc r15-7367] MAINTAINERS: Add myself to write after approval

2025-02-05 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:884893ae87ae9a562c38f997d9b332c3591b

commit r15-7367-g884893ae87ae9a562c38f997d9b332c3591b
Author: Jin Ma 
Date:   Tue Dec 3 15:50:14 2024 +0800

MAINTAINERS: Add myself to write after approval

ChangeLog:

* MAINTAINERS: Add myself.

Diff:
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 44367b27b415..c423dd6e7874 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -641,6 +641,7 @@ H.J. Lu hjl 

 Xiong Hu Luo-   
 Bin Bin Lv  shlb
 Christophe Lyon clyon   
+Jin Ma  majin   
 Jun Ma  junma   
 Andrew MacLeod  -   
 Luis Machadoluisgpm

[gcc(refs/users/majin/heads/master)] MAINTAINERS: Add myself to write after approval

2025-02-05 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:8cae77a5be9c59aa511cd957ea6ea700605a5d97

commit 8cae77a5be9c59aa511cd957ea6ea700605a5d97
Author: Jin Ma 
Date:   Tue Dec 3 15:50:14 2024 +0800

MAINTAINERS: Add myself to write after approval

ChangeLog:

* MAINTAINERS: Add myself.

Diff:
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 44367b27b415..c423dd6e7874 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -641,6 +641,7 @@ H.J. Lu hjl 

 Xiong Hu Luo-   
 Bin Bin Lv  shlb
 Christophe Lyon clyon   
+Jin Ma  majin   
 Jun Ma  junma   
 Andrew MacLeod  -   
 Luis Machadoluisgpm

[gcc r15-7489] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

2025-02-11 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:580f571be6ce80aa71fb80e7b16e01824f088229

commit r15-7489-g580f571be6ce80aa71fb80e7b16e01824f088229
Author: Jin Ma 
Date:   Tue Feb 11 21:28:05 2025 +0800

RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

This is a follow-up to the patch below to avoid generating unrecognized
vsetivl instructions for XTheadVector.

https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html

PR target/118601

gcc/ChangeLog:

* config/riscv/riscv-string.cc (expand_block_move): Check with new
constraint 'vl' instead of 'K'.
(expand_vec_setmem): Likewise.
(expand_vec_cmpmem): Likewise.
* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
(expand_load_store): Likewise.
(expand_strided_load): Likewise.
(expand_strided_store): Likewise.
(expand_lanes_load_store): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Move to...
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: ...here.
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: New test.
* gcc.target/riscv/rvv/xtheadvector/pr118601.c: New test.

Reported-by: Edwin Lu 

Diff:
---
 gcc/config/riscv/riscv-string.cc   |  6 +--
 gcc/config/riscv/riscv-v.cc| 10 ++---
 .../riscv/rvv/xtheadvector/pr114194-rv32.c | 51 ++
 .../xtheadvector/{pr114194.c => pr114194-rv64.c}   |  5 +--
 .../gcc.target/riscv/rvv/xtheadvector/pr118601.c   | 18 
 5 files changed, 79 insertions(+), 11 deletions(-)

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 97e20bdb0026..408eb07e87f3 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1275,7 +1275,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in, 
bool movmem_p)
   machine_mode mask_mode = riscv_vector::get_vector_mode
(BImode, GET_MODE_NUNITS (info.vmode)).require ();
   rtx mask =  CONSTM1_RTX (mask_mode);
-  if (!satisfies_constraint_K (cnt))
+  if (!satisfies_constraint_vl (cnt))
cnt= force_reg (Pmode, cnt);
   rtx m_ops[] = {vec, mask, src};
   emit_nonvlmax_insn (code_for_pred_mov (info.vmode),
@@ -1626,7 +1626,7 @@ expand_vec_setmem (rtx dst_in, rtx length_in, rtx 
fill_value_in)
 }
   else
 {
-  if (!satisfies_constraint_K (info.avl))
+  if (!satisfies_constraint_vl (info.avl))
info.avl = force_reg (Pmode, info.avl);
   emit_nonvlmax_insn (code_for_pred_broadcast (info.vmode),
  riscv_vector::UNARY_OP, broadcast_ops, info.avl);
@@ -1694,7 +1694,7 @@ expand_vec_cmpmem (rtx result_out, rtx blk_a_in, rtx 
blk_b_in, rtx length_in)
 }
   else
 {
-  if (!satisfies_constraint_K (length_in))
+  if (!satisfies_constraint_vl (length_in))
  length_in = force_reg (Pmode, length_in);
 
   rtx memmask = CONSTM1_RTX (mask_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 9847439ca779..62456c7ef79d 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2103,7 +2103,7 @@ get_unknown_min_value (machine_mode mode)
 static rtx
 force_vector_length_operand (rtx vl)
 {
-  if (CONST_INT_P (vl) && !satisfies_constraint_K (vl))
+  if (CONST_INT_P (vl) && !satisfies_constraint_vl (vl))
 return force_reg (Pmode, vl);
   return vl;
 }
@@ -4130,7 +4130,7 @@ expand_load_store (rtx *ops, bool is_load)
 }
   else
 {
-  if (!satisfies_constraint_K (len))
+  if (!satisfies_constraint_vl (len))
len = force_reg (Pmode, len);
   if (is_load)
{
@@ -4165,7 +4165,7 @@ expand_strided_load (machine_mode mode, rtx *ops)
 emit_vlmax_insn (icode, BINARY_OP_TAMA, emit_ops);
   else
 {
-  len = satisfies_constraint_K (len) ? len : force_reg (Pmode, len);
+  len = satisfies_constraint_vl (len) ? len : force_reg (Pmode, len);
   emit_nonvlmax_insn (icode, BINARY_OP_TAMA, emit_ops, len);
 }
 }
@@ -4191,7 +4191,7 @@ expand_strided_store (machine_mode mode, rtx *ops)
 }
   else
 {
-  len = satisfies_constraint_K (len) ? len : force_reg (Pmode, len);
+  len = satisfies_constraint_vl (len) ? len : force_reg (Pmode, len);
   vl_type = get_avl_type_rtx (NONVLMAX);
 }
 
@@ -4642,7 +4642,7 @@ expand_lanes_load_store (rtx *ops, bool is_load)
 }
   else
 {
-  if (!satisfies_constraint_K (len))
+  if (!satisfies_constraint_vl (len))
len = force_reg (Pmode, len);
   if (is_load)
{
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
new file mode 100644
index ..f95e713ea246
--- /dev/null
+++ b/gcc/testsuite/gcc.t

[gcc r15-9266] RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.

2025-04-07 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:196b45caca0aae57a95bffcdd5c188994317de08

commit r15-9266-g196b45caca0aae57a95bffcdd5c188994317de08
Author: Jin Ma 
Date:   Mon Apr 7 14:21:50 2025 +0800

RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.

XThreadVector does not support the vsext/vzext instructions; however,
due to the reuse of RVV optimizations, it may generate these instructions
in certain cases. To prevent the error "Unknown opcode 'th.vsext.vf2',"
we should disable these patterns.

V2:
Change the value of dg-do in the test case from assemble to compile, and
remove the -save-temps option.

gcc/ChangeLog:

* config/riscv/vector.md: Disable vsext/vzext for XTheadVector.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vsext.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vzext.c: New test.

Diff:
---
 gcc/config/riscv/vector.md |  6 +++---
 .../gcc.target/riscv/rvv/xtheadvector/vsext.c  | 24 ++
 .../gcc.target/riscv/rvv/xtheadvector/vzext.c  | 24 ++
 3 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 8ee43cf0ce1c..51eb64fb1226 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3939,7 +3939,7 @@
  (any_extend:VWEXTI
(match_operand: 3 "register_operand" "   vr,   vr"))
  (match_operand:VWEXTI 2 "vector_merge_operand" "   vu,
0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "vext.vf2\t%0,%3%p1"
   [(set_attr "type" "vext")
(set_attr "mode" "")])
@@ -3959,7 +3959,7 @@
  (any_extend:VQEXTI
(match_operand: 3 "register_operand" "   vr,   vr"))
  (match_operand:VQEXTI 2 "vector_merge_operand"   "   vu,0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "vext.vf4\t%0,%3%p1"
   [(set_attr "type" "vext")
(set_attr "mode" "")])
@@ -3979,7 +3979,7 @@
  (any_extend:VOEXTI
(match_operand: 3 "register_operand" "   vr,   vr"))
  (match_operand:VOEXTI 2 "vector_merge_operand"  "   vu,0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "vext.vf8\t%0,%3%p1"
   [(set_attr "type" "vext")
(set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
new file mode 100644
index ..55db28304c7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */
+
+#include 
+
+struct a
+{
+  int b[];
+} c (vint32m4_t), d;
+
+char e;
+char *f;
+
+void g ()
+{
+  int h;
+  vint32m4_t i;
+  vint8m1_t j = __riscv_vlse8_v_i8m1 (&e, d.b[3], h);
+  vint16m2_t k = __riscv_vwadd_vx_i16m2 (j, 0, h);
+  i = __riscv_vwmacc_vx_i32m4 (i, f[0], k, h);
+  c (i);
+}
+
+/* { dg-final { scan-assembler-not {th\.vsext\.vf2} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
new file mode 100644
index ..fcb565991c6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */
+
+#include 
+
+struct a
+{
+  int b[];
+} c (vuint32m4_t), d;
+
+char e;
+char *f;
+
+void g ()
+{
+  int h;
+  vuint32m4_t i;
+  vuint8m1_t j = __riscv_vlse8_v_u8m1 (&e, d.b[3], h);
+  vuint16m2_t k = __riscv_vwaddu_vx_u16m2 (j, 0, h);
+  i = __riscv_vwmaccu_vx_u32m4 (i, f[0], k, h);
+  c (i);
+}
+
+/* { dg-final { scan-assembler-not {th\.vzext\.vf2} } } */

[gcc r14-11581] [PATCH] RISC-V: Bugfix for unrecognizable insn for XTheadVector

2025-04-10 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:07d4c264a000b6448d6b519110c05c3b8a64d23b

commit r14-11581-g07d4c264a000b6448d6b519110c05c3b8a64d23b
Author: Jin Ma 
Date:   Wed Nov 13 15:19:29 2024 -0700

[PATCH] RISC-V: Bugfix for unrecognizable insn for XTheadVector

error: unrecognizable insn:

(insn 35 34 36 2 (set (subreg:RVVM1SF (reg/v:RVVM1x4SF 142 [ _r ]) 0)
(unspec:RVVM1SF [
(const_vector:RVVM1SF repeat [
(const_double:SF 0.0 [0x0.0p+0])
])
(reg:DI 0 zero)
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_TH_VWLDST)) -1
 (nil))
during RTL pass: mode_sw

PR target/116591

gcc/ChangeLog:

* config/riscv/vector.md: Add restriction to call pred_th_whole_mov.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/pr116591.c: New test.

(cherry picked from commit 8564d0948c72df0a66d7eb47e15c6ab43e9b25ce)

Diff:
---
 gcc/config/riscv/vector.md |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c | 14 ++
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 913c09ffd856..327690a71f46 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1097,7 +1097,7 @@
- We can not leave it to TARGET_SECONDARY_RELOAD since it happens
 before spilling. The clobber scratch is used by spilling fractional
 registers in IRA/LRA so it's too early.  */
-  if (TARGET_XTHEADVECTOR)
+  if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], mode))
 {
   emit_insn (gen_pred_th_whole_mov (mode, operands[0], operands[1],
RVV_VLMAX, 
GEN_INT(riscv_vector::VLMAX)));
@@ -1197,7 +1197,7 @@
(match_operand:VB 1 "general_operand"))]
   "TARGET_VECTOR"
 {
-  if (TARGET_XTHEADVECTOR)
+  if (TARGET_XTHEADVECTOR && reg_or_mem_operand (operands[1], mode))
 {
   emit_insn (gen_pred_th_whole_mov (mode, operands[0], operands[1],
RVV_VLMAX, 
GEN_INT(riscv_vector::VLMAX)));
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c
new file mode 100644
index ..dfaf82ce1ca8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116591.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32d -O2 -save-temps" { 
target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2 -save-temps" { 
target { rv64 } } } */
+
+#include 
+
+void
+foo (float *a, int b)
+{
+  vfloat32m1x4_t c;
+  __riscv_vsseg4e32_v_f32m1x4(a, c, b);
+}
+
+/* { dg-final { scan-assembler-times {th\.vmv\.v\.i\tv[0-9]+,0} 4 } } */

[gcc r14-11583] RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero immediate

2025-04-10 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:2631ac38d9b2a9def13a04c1e1fefb3871e420ab

commit r14-11583-g2631ac38d9b2a9def13a04c1e1fefb3871e420ab
Author: Jin Ma 
Date:   Tue Jan 21 10:46:37 2025 -0700

RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not 
get a non-zero immediate

Although we have handled the vl of XTheadVector correctly in the
expand phase and predicates, the results show that the work is
still insufficient.

In the curr_insn_transform function, the insn is transformed from:
(insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0  S[128, 128] 
A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(reg:DI 209)
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 143 [ _xx ])
(mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0  S[128, 128] A32])))
 (expr_list:REG_DEAD (reg/v:RVVM8SF 143 [ _xx ])
(nil)))
to
(insn 69 284 225 11 (set (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] 
[218]) [0  S[128, 128] A32])
(if_then_else:RVVM8SF (unspec:RVVMF4BI [
(const_vector:RVVMF4BI repeat [
(const_int 1 [0x1])
])
(const_int 1 [0x1])
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(reg/v:RVVM8SF 104 v8 [orig:143 _xx ] [143])
(mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0  S[128, 
128] A32])))
 (nil))

Looking at the log for the reload pass, it is found that "Changing pseudo 
209 in
operand 3 of insn 69 on equiv 0x1".
It converts the vl operand in insn from the expected register(reg:DI 209) 
to the
constant 1(const_int 1 [0x1]).

This conversion occurs because, although the predicate for the vl operand is
restricted by "vector_length_operand" in the pattern, the constraint is 
still
"rK", which allows the transformation.

The issue is that changing the "rK" constraint to "rJ" for the constraint 
of vl
operand in the pattern would prevent this conversion, But unfortunately 
this will
conflict with RVV (RISC-V Vector Extension).

Based on the review's recommendations, the best solution for now is to 
create
a new constraint to distinguish between RVV and XTheadVector, which is 
exactly
what this patch does.

PR target/116593

gcc/ChangeLog:

* config/riscv/constraints.md (vl): New.
* config/riscv/thead-vector.md: Replacing rK with rvl.
* config/riscv/vector.md: Likewise.

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/rvv.exp: Enable testsuite of XTheadVector.
* g++.target/riscv/rvv/xtheadvector/pr116593.C: New test.

(cherry picked from commit 3024b12f2cde5db3bf52b49b07e32ef3065929fb)

Diff:
---
 gcc/config/riscv/constraints.md|   6 +
 gcc/config/riscv/thead-vector.md   |  18 +-
 gcc/config/riscv/vector.md | 500 ++---
 gcc/testsuite/g++.target/riscv/rvv/rvv.exp |   3 +
 .../g++.target/riscv/rvv/xtheadvector/pr116593.C   |  47 ++
 5 files changed, 315 insertions(+), 259 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index a590df545d7d..a03a1d755051 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -188,6 +188,12 @@
   (and (match_code "const_vector")
(match_test "riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)")))
 
+(define_constraint "vl"
+  "A uimm5 for Vector or zero for XTheadVector."
+  (and (match_code "const_int")
+   (ior (match_test "!TARGET_XTHEADVECTOR && satisfies_constraint_K (op)")
+   (match_test "TARGET_XTHEADVECTOR && satisfies_constraint_J (op)"
+
 (define_constraint "Wc0"
   "@internal
  A constraint that matches a vector of immediate all zeros."
diff --git a/gcc/config/riscv/thead-vector.md b/gcc/config/riscv/thead-vector.md
index 5fe9ba08c4eb..5a02debdd207 100644
--- a/gcc/config/riscv/thead-vector.md
+++ b/gcc/config/riscv/thead-vector.md
@@ -108,7 +108,7 @@
   [(set (match_operand:V_VLS_VT 0 "reg_or_mem_operand"  "=vr,vr, m")
(unspec:V_VLS_VT
  [(match_operand:V_VLS_VT 1 "reg_or_mem_operand" " vr, m,vr")
-  (match_operand 2 "vector_length_operand"   " rK, rK, rK")
+  (match_operand 2 "vector_length_operand"   "rvl,rvl,rvl")
   (match_operand 3 "const_1_operand" "  i, i, i")
   (reg:SI VL_REGNUM)
   (reg

[gcc r14-11582] RISC-V: Enable and adjust the testsuite for XTheadVector.

2025-04-10 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:319b9a385d42f529da49d2b90a98ea92bab54b39

commit r14-11582-g319b9a385d42f529da49d2b90a98ea92bab54b39
Author: Jin Ma 
Date:   Tue Jan 21 10:43:47 2025 -0700

RISC-V: Enable and adjust the testsuite for XTheadVector.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Enable testsuite of
XTheadVector.
* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Adjust correctly.
* gcc.target/riscv/rvv/xtheadvector/prefix.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: Likewise.

(cherry picked from commit ab24171d237a9138714f0e6d2bb38fd357ccaed9)

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp |  2 ++
 .../gcc.target/riscv/rvv/xtheadvector/pr114194.c   | 32 +++---
 .../gcc.target/riscv/rvv/xtheadvector/prefix.c |  2 +-
 .../gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c| 17 +++-
 .../gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c   | 17 +++-
 .../gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c| 17 +++-
 .../gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c   | 17 +++-
 .../gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c| 17 +++-
 .../gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c   | 17 +++-
 9 files changed, 79 insertions(+), 59 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp 
b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 8c4e916d5b1f..b407ebfb017f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -37,6 +37,8 @@ dg-init
 set CFLAGS "$DEFAULT_CFLAGS -O3"
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
"" $CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xtheadvector/*.\[cS\]]] \
+   "" $CFLAGS
 gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
"" $CFLAGS
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
index fc2d13494256..2e53a7ecc3e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
@@ -1,11 +1,11 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*
 ** foo0_1:
-** sb\tzero,0([a-x0-9]+)
+** sb\tzero,0\([a-x0-9]+\)
 ** ret
 */
 void foo0_1 (void *p)
@@ -15,13 +15,13 @@ void foo0_1 (void *p)
 
 /*
 ** foo0_7:
-** sb\tzero,0([a-x0-9]+)
-** sb\tzero,1([a-x0-9]+)
-** sb\tzero,2([a-x0-9]+)
-** sb\tzero,3([a-x0-9]+)
-** sb\tzero,4([a-x0-9]+)
-** sb\tzero,5([a-x0-9]+)
-** sb\tzero,6([a-x0-9]+)
+** sb\tzero,0\([a-x0-9]+\)
+** sb\tzero,1\([a-x0-9]+\)
+** sb\tzero,2\([a-x0-9]+\)
+** sb\tzero,3\([a-x0-9]+\)
+** sb\tzero,4\([a-x0-9]+\)
+** sb\tzero,5\([a-x0-9]+\)
+** sb\tzero,6\([a-x0-9]+\)
 ** ret
 */
 void foo0_7 (void *p)
@@ -32,7 +32,7 @@ void foo0_7 (void *p)
 /*
 ** foo1_1:
 ** li\t[a-x0-9]+,1
-** sb\t[a-x0-9]+,0([a-x0-9]+)
+** sb\t[a-x0-9]+,0\([a-x0-9]+\)
 ** ret
 */
 void foo1_1 (void *p)
@@ -43,11 +43,11 @@ void foo1_1 (void *p)
 /*
 ** foo1_5:
 ** li\t[a-x0-9]+,1
-** sb\t[a-x0-9]+,0([a-x0-9]+)
-** sb\t[a-x0-9]+,1([a-x0-9]+)
-** sb\t[a-x0-9]+,2([a-x0-9]+)
-** sb\t[a-x0-9]+,3([a-x0-9]+)
-** sb\t[a-x0-9]+,4([a-x0-9]+)
+** sb\t[a-x0-9]+,0\([a-x0-9]+\)
+** sb\t[a-x0-9]+,1\([a-x0-9]+\)
+** sb\t[a-x0-9]+,2\([a-x0-9]+\)
+** sb\t[a-x0-9]+,3\([a-x0-9]+\)
+** sb\t[a-x0-9]+,4\([a-x0-9]+\)
 ** ret
 */
 void foo1_5 (void *p)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
index eee727ef6b42..0a18e697830c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -9,4 +9,4 @@ prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
   return __riscv_vadd_vv_i32m1 (vx, vy, vl);
 }
 
-/* { dg-final { scan-assembler {\mth\.v\M} } } */
+/* { dg-final { scan-assembler {\mth\.vadd\.vv\M} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c 
b/gcc/testsuite/gcc.target/riscv/rvv

[gcc r14-11585] RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.

2025-04-10 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:51e041a9db714215d310bf69969de7b6f1c7c2bf

commit r14-11585-g51e041a9db714215d310bf69969de7b6f1c7c2bf
Author: Jin Ma 
Date:   Mon Apr 7 14:21:50 2025 +0800

RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.

XThreadVector does not support the vsext/vzext instructions; however,
due to the reuse of RVV optimizations, it may generate these instructions
in certain cases. To prevent the error "Unknown opcode 'th.vsext.vf2',"
we should disable these patterns.

V2:
Change the value of dg-do in the test case from assemble to compile, and
remove the -save-temps option.

gcc/ChangeLog:

* config/riscv/vector.md: Disable vsext/vzext for XTheadVector.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/vsext.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vzext.c: New test.

(cherry picked from commit 196b45caca0aae57a95bffcdd5c188994317de08)

Diff:
---
 gcc/config/riscv/vector.md |  6 +++---
 .../gcc.target/riscv/rvv/xtheadvector/vsext.c  | 24 ++
 .../gcc.target/riscv/rvv/xtheadvector/vzext.c  | 24 ++
 3 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 6fd169746934..80d810fbca77 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3839,7 +3839,7 @@
  (any_extend:VWEXTI
(match_operand: 3 "register_operand" "   vr,   vr"))
  (match_operand:VWEXTI 2 "vector_merge_operand" "   vu,
0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "vext.vf2\t%0,%3%p1"
   [(set_attr "type" "vext")
(set_attr "mode" "")])
@@ -3859,7 +3859,7 @@
  (any_extend:VQEXTI
(match_operand: 3 "register_operand" "   vr,   vr"))
  (match_operand:VQEXTI 2 "vector_merge_operand"   "   vu,0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "vext.vf4\t%0,%3%p1"
   [(set_attr "type" "vext")
(set_attr "mode" "")])
@@ -3879,7 +3879,7 @@
  (any_extend:VOEXTI
(match_operand: 3 "register_operand" "   vr,   vr"))
  (match_operand:VOEXTI 2 "vector_merge_operand"  "   vu,0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "vext.vf8\t%0,%3%p1"
   [(set_attr "type" "vext")
(set_attr "mode" "")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
new file mode 100644
index ..ecf338db5ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */
+
+#include 
+
+struct a
+{
+  int b[10];
+} c (vint32m4_t), d;
+
+char e;
+char *f;
+
+void g ()
+{
+  int h;
+  vint32m4_t i;
+  vint8m1_t j = __riscv_vlse8_v_i8m1 (&e, d.b[3], h);
+  vint16m2_t k = __riscv_vwadd_vx_i16m2 (j, 0, h);
+  i = __riscv_vwmacc_vx_i32m4 (i, f[0], k, h);
+  c (i);
+}
+
+/* { dg-final { scan-assembler-not {th\.vsext\.vf2} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
new file mode 100644
index ..753f65309147
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */
+
+#include 
+
+struct a
+{
+  int b[10];
+} c (vuint32m4_t), d;
+
+char e;
+char *f;
+
+void g ()
+{
+  int h;
+  vuint32m4_t i;
+  vuint8m1_t j = __riscv_vlse8_v_u8m1 (&e, d.b[3], h);
+  vuint16m2_t k = __riscv_vwaddu_vx_u16m2 (j, 0, h);
+  i = __riscv_vwmaccu_vx_u32m4 (i, f[0], k, h);
+  c (i);
+}
+
+/* { dg-final { scan-assembler-not {th\.vzext\.vf2} } } */

[gcc r14-11584] RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

2025-04-10 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:f2e2e255004dc35beef9d8b5800d69d228f7eec1

commit r14-11584-gf2e2e255004dc35beef9d8b5800d69d228f7eec1
Author: Jin Ma 
Date:   Tue Feb 11 21:28:05 2025 +0800

RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

This is a follow-up to the patch below to avoid generating unrecognized
vsetivl instructions for XTheadVector.

https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html

PR target/118601

gcc/ChangeLog:

* config/riscv/riscv-string.cc (expand_block_move): Check with new
constraint 'vl' instead of 'K'.
(expand_vec_setmem): Likewise.
(expand_vec_cmpmem): Likewise.
* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
(expand_load_store): Likewise.
(expand_strided_load): Likewise.
(expand_strided_store): Likewise.
(expand_lanes_load_store): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Move to...
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: ...here.
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: New test.
* gcc.target/riscv/rvv/xtheadvector/pr118601.c: New test.

Reported-by: Edwin Lu 
(cherry picked from commit 580f571be6ce80aa71fb80e7b16e01824f088229)

Diff:
---
 gcc/config/riscv/riscv-string.cc   |  2 +-
 gcc/config/riscv/riscv-v.cc|  8 ++--
 .../riscv/rvv/xtheadvector/pr114194-rv32.c | 51 ++
 .../xtheadvector/{pr114194.c => pr114194-rv64.c}   |  5 +--
 .../gcc.target/riscv/rvv/xtheadvector/pr118601.c   |  9 
 5 files changed, 67 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index b09b51d7526b..1cb9f832bb54 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -969,7 +969,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in)
   machine_mode mask_mode = riscv_vector::get_vector_mode
(BImode, GET_MODE_NUNITS (vmode)).require ();
   rtx mask =  CONSTM1_RTX (mask_mode);
-  if (!satisfies_constraint_K (cnt))
+  if (!satisfies_constraint_vl (cnt))
cnt= force_reg (Pmode, cnt);
   rtx m_ops[] = {vec, mask, src};
   emit_nonvlmax_insn (code_for_pred_mov (vmode),
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index fe51e2fe9b83..bb38d8b42c70 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2075,7 +2075,7 @@ get_unknown_min_value (machine_mode mode)
 static rtx
 force_vector_length_operand (rtx vl)
 {
-  if (CONST_INT_P (vl) && !satisfies_constraint_K (vl))
+  if (CONST_INT_P (vl) && !satisfies_constraint_vl (vl))
 return force_reg (Pmode, vl);
   return vl;
 }
@@ -3864,7 +3864,7 @@ expand_load_store (rtx *ops, bool is_load)
 }
   else
 {
-  if (!satisfies_constraint_K (len))
+  if (!satisfies_constraint_vl (len))
len = force_reg (Pmode, len);
   if (is_load)
{
@@ -4309,7 +4309,7 @@ expand_lanes_load_store (rtx *ops, bool is_load)
 }
   else
 {
-  if (!satisfies_constraint_K (len))
+  if (!satisfies_constraint_vl (len))
len = force_reg (Pmode, len);
   if (is_load)
{
@@ -5108,7 +5108,7 @@ can_be_broadcasted_p (rtx op)
   && !satisfies_constraint_Wdm (op))
 return false;
 
-  if (satisfies_constraint_K (op) || register_operand (op, mode)
+  if (satisfies_constraint_vl (op) || register_operand (op, mode)
   || satisfies_constraint_Wdm (op) || rtx_equal_p (op, CONST0_RTX (mode)))
 return true;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
new file mode 100644
index ..0bee5ec33de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target rv32 } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo0_1:
+** sb\tzero,0\([a-x0-9]+\)
+** ret
+*/
+void foo0_1 (void *p)
+{
+  __builtin_memset (p, 0, 1);
+}
+
+/*
+** foo0_7:
+** li\t[a-x0-9]+,7
+** th.vsetvli\tzero,[a-x0-9]+,e8,m1
+** th\.vmv\.v\.i\tv[0-9],0
+** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void foo0_7 (void *p)
+{
+  __builtin_memset (p, 0, 7);
+}
+
+/*
+** foo1_1:
+** li\t[a-x0-9]+,1
+** sb\t[a-x0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void foo1_1 (void *p)
+{
+  __builtin_memset (p, 1, 1);
+}
+
+/*
+** foo1_5:
+** li\t[a-x0-9]+,5
+** th.vsetvli\tzero,[a-x0-9]+,e8,m1
+** th\.vmv\.v\.i\tv[0-9],1
+** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+
+void foo1_5 (void *p)
+{
+  __builtin_memset (p, 1, 5);
+}
diff --git a/gcc/testsuite/gcc.targ

[gcc r14-11595] [PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w

2025-04-10 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:889e40576fec9938bdc52fee7ccebe2e97ed28f5

commit r14-11595-g889e40576fec9938bdc52fee7ccebe2e97ed28f5
Author: Jin Ma 
Date:   Wed Apr 2 13:37:07 2025 -0600

[PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w

Assuming we have the following variables:

unsigned long long a0, a1;
unsigned int a2;

For the expression:

a0 = (a0 << 50) >> 49;  // slli a0, a0, 50 + srli a0, a0, 49
a2 = a1 + a0;   // addw a2, a1, a0 + slli a2, a2, 32 + srli a2, a2, 
32

In the optimization process of ZBA (combine pass), it would be optimized to:

a2 = a0 << 1 + a1;  // sh1add a2, a0, a1 + zext.w a2, a2

This is clearly incorrect, as it overlooks the fact that a0=a0&0x7ffe, 
meaning
that the bits a0[32:14] are set to zero.

gcc/ChangeLog:

* config/riscv/bitmanip.md: The optimization can only be applied if
the high bit of operands[3] is set to 1.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zba-shNadd-09.c: New test.
* gcc.target/riscv/zba-shNadd-10.c: New test.

(cherry picked from commit dd6ebc0a3473a830115995bdcaf8f797ebd085a3)

Diff:
---
 gcc/config/riscv/bitmanip.md   |  4 +++-
 gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c | 12 
 gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c | 21 +
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 0612e69fcb3b..f2d256f44198 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -80,7 +80,9 @@
(match_operand:DI 3 
"consecutive_bits_operand")) 0)
 (subreg:SI (match_operand:DI 4 
"register_operand") 0]
   "TARGET_64BIT && TARGET_ZBA
-   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))"
+   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
+   /* Ensure the mask includes all the bits in SImode.  */
+   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0)"
   [(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) 
(match_dup 4)))
(set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 0) 0)))])
 
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c 
b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c
new file mode 100644
index ..303f3cbb8630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+long long sub (unsigned long long a, unsigned long long b)
+{
+  b = (b << 50) >> 49;
+  unsigned int x = a + b;
+  return x;
+}
+
+/* { dg-final { scan-assembler-not {\msh1add} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c 
b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c
new file mode 100644
index ..883cce271ca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */
+
+struct {
+  unsigned a : 14;
+  unsigned b : 3;
+} c;
+
+unsigned long long d;
+void e (unsigned long long *f, long p2) { *f = p2; }
+signed g;
+long i;
+
+int main () {
+  c.b = 4;
+  i = -(-c.a - (3023282U + c.a + g));
+  e (&d, i);
+  if (d != 3023282)
+__builtin_abort ();
+  __builtin_exit (0);
+}

[gcc r13-9504] [PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w

2025-04-11 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:372415181e4c6ab5bd1e32d60e7c2c96824e0cc8

commit r13-9504-g372415181e4c6ab5bd1e32d60e7c2c96824e0cc8
Author: Jin Ma 
Date:   Wed Apr 2 13:37:07 2025 -0600

[PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w

Assuming we have the following variables:

unsigned long long a0, a1;
unsigned int a2;

For the expression:

a0 = (a0 << 50) >> 49;  // slli a0, a0, 50 + srli a0, a0, 49
a2 = a1 + a0;   // addw a2, a1, a0 + slli a2, a2, 32 + srli a2, a2, 
32

In the optimization process of ZBA (combine pass), it would be optimized to:

a2 = a0 << 1 + a1;  // sh1add a2, a0, a1 + zext.w a2, a2

This is clearly incorrect, as it overlooks the fact that a0=a0&0x7ffe, 
meaning
that the bits a0[32:14] are set to zero.

gcc/ChangeLog:

* config/riscv/bitmanip.md: The optimization can only be applied if
the high bit of operands[3] is set to 1.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zba-shNadd-09.c: New test.
* gcc.target/riscv/zba-shNadd-10.c: New test.

(cherry picked from commit dd6ebc0a3473a830115995bdcaf8f797ebd085a3)

Diff:
---
 gcc/config/riscv/bitmanip.md   |  4 +++-
 gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c | 12 
 gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c | 21 +
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 7aa591689ba8..92f4261ba1a3 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -80,7 +80,9 @@
(match_operand:DI 3 
"consecutive_bits_operand")) 0)
 (subreg:SI (match_operand:DI 4 
"register_operand") 0]
   "TARGET_64BIT && TARGET_ZBA
-   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))"
+   && riscv_shamt_matches_mask_p (INTVAL (operands[2]), INTVAL (operands[3]))
+   /* Ensure the mask includes all the bits in SImode.  */
+   && ((INTVAL (operands[3]) & (HOST_WIDE_INT_1U << 31)) != 0)"
   [(set (match_dup 0) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) 
(match_dup 4)))
(set (match_dup 0) (zero_extend:DI (subreg:SI (match_dup 0) 0)))])
 
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c 
b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c
new file mode 100644
index ..303f3cbb8630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-09.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+long long sub (unsigned long long a, unsigned long long b)
+{
+  b = (b << 50) >> 49;
+  unsigned int x = a + b;
+  return x;
+}
+
+/* { dg-final { scan-assembler-not {\msh1add} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c 
b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c
new file mode 100644
index ..883cce271ca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-10.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_zba -mabi=lp64d -O2" } */
+
+struct {
+  unsigned a : 14;
+  unsigned b : 3;
+} c;
+
+unsigned long long d;
+void e (unsigned long long *f, long p2) { *f = p2; }
+signed g;
+long i;
+
+int main () {
+  c.b = 4;
+  i = -(-c.a - (3023282U + c.a + g));
+  e (&d, i);
+  if (d != 3023282)
+__builtin_abort ();
+  __builtin_exit (0);
+}

[gcc r15-7601] RISC-V: Fix failed tests for regression due to fix ICE patch

2025-02-17 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:b22f191b7c594b33fb4b4a07769dbf0ca45bc9e9

commit r15-7601-gb22f191b7c594b33fb4b4a07769dbf0ca45bc9e9
Author: Jin Ma 
Date:   Mon Feb 17 10:43:22 2025 +0800

RISC-V: Fix failed tests for regression due to fix ICE patch

Ref:
https://github.com/ewlu/gcc-precommit-ci/issues/3096#issue-2854419069

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/bug-9.c: Added new failure check.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: 
Likewise.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: 
Likewise.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c  | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c | 1 +
 .../gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c  | 1 +
 15 files changed, 15 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
index 20ae9ebf6f22..8cfe96588751 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c
@@ -11,3 +11,4 @@ vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t 
vl)
 }
 
 /* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA 
extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA 
extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
 
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
index a064417169d8..ebe31f5c961b 100644
--- 
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
+++ 
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
@@ -11,3 +11,4 @@ test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f, zve64d or 
v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vint64m1_t' requires the zve64x, zve64f, zve64d 
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
 
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
index 61d3fb25dc2d..7e9a101795dc 100644
--- 
a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
+++ 
b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
@@ -11,3 +11,4 @@ test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
 }
 
 /* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f, zve64d 
or v ISA extension" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-error "argument type 'vfloat32m1_t' requires the zve32f, zve64f, 
zve64d or v ISA extension

[gcc r15-7550] RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters

2025-02-15 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:25a103feb3056bc483a1558af315be452060035b

commit r15-7550-g25a103feb3056bc483a1558af315be452060035b
Author: Jin Ma 
Date:   Fri Feb 14 14:58:49 2025 +0800

RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters

When using riscv_v_abi, the return and arguments of the function should
be adequately checked to avoid ICE.

PR target/118872

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_fntype_abi): Strengthen the logic
of the check to avoid missing the error report.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr118872.c: New test.

Reviewed-by: Palmer Dabbelt 
Signed-off-by: Jin Ma 

Diff:
---
 gcc/config/riscv/riscv.cc  | 10 +++---
 gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c | 13 +
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6e14126e3a4a..9bf7713139f6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6479,9 +6479,13 @@ riscv_fntype_abi (const_tree fntype)
   /* Implement the vector calling convention.  For more details please
  reference the below link.
  https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389  */
-  if (riscv_return_value_is_vector_type_p (fntype)
- || riscv_arguments_is_vector_type_p (fntype)
- || riscv_vector_cc_function_p (fntype))
+  bool validate_v_abi_p = false;
+
+  validate_v_abi_p |= riscv_return_value_is_vector_type_p (fntype);
+  validate_v_abi_p |= riscv_arguments_is_vector_type_p (fntype);
+  validate_v_abi_p |= riscv_vector_cc_function_p (fntype);
+
+  if (validate_v_abi_p)
 return riscv_v_abi ();
 
   return default_function_abi;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c
new file mode 100644
index ..adb54d648a52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118872.c
@@ -0,0 +1,13 @@
+/* Test that we do not have ice when compile */
+/* { dg-do assemble } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2"  { target { rv64 } } } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2"  { target { rv32 } } } */
+
+#include 
+
+vfloat32m2_t foo (vfloat16m1_t a, size_t vl)
+{
+  return __riscv_vfwcvt_f_f_v_f32m2(a, vl);
+}
+
+/* { dg-error "argument type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA 
extension" "" { target { "riscv*-*-*" } } 0 } */

[gcc r16-708] RISC-V: Since the loop increment i++ is unreachable, the loop body will never execute more than once

2025-05-16 Thread Ma Jin via Gcc-cvs 
https://gcc.gnu.org/g:55cfd1c8fa2ad2c5d91eadd14daa35f695779a2b

commit r16-708-g55cfd1c8fa2ad2c5d91eadd14daa35f695779a2b
Author: Jin Ma 
Date:   Fri May 16 15:27:13 2025 +0800

RISC-V: Since the loop increment i++ is unreachable, the loop body will 
never execute more than once

Reported-by: huangcunjian 

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
break and fixbug for elt index.

Diff:
---
 gcc/config/riscv/riscv.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fd51472dbeaa..b2794252291e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11580,11 +11580,10 @@ riscv_gpr_save_operation_p (rtx op)
  /* Two CLOBBER and USEs, must check the order.  */
  unsigned expect_code = i < 3 ? CLOBBER : USE;
  if (GET_CODE (elt) != expect_code
- || !REG_P (XEXP (elt, 1))
- || (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i]))
+ || !REG_P (XEXP (elt, 0))
+ || (REGNO (XEXP (elt, 0)) != gpr_save_reg_order[i]))
return false;
}
-   break;
 }
   return true;
 }