https://gcc.gnu.org/g:196b45caca0aae57a95bffcdd5c188994317de08
commit r15-9266-g196b45caca0aae57a95bffcdd5c188994317de08
Author: Jin Ma <ji...@linux.alibaba.com>
Date: Mon Apr 7 14:21:50 2025 +0800
RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector.
XThreadVector does not support the vsext/vzext instructions; however,
due to the reuse of RVV optimizations, it may generate these instructions
in certain cases. To prevent the error "Unknown opcode 'th.vsext.vf2',"
we should disable these patterns.
V2:
Change the value of dg-do in the test case from assemble to compile, and
remove the -save-temps option.
gcc/ChangeLog:
* config/riscv/vector.md: Disable vsext/vzext for XTheadVector.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/vsext.c: New test.
* gcc.target/riscv/rvv/xtheadvector/vzext.c: New test.
Diff:
---
gcc/config/riscv/vector.md | 6 +++---
.../gcc.target/riscv/rvv/xtheadvector/vsext.c | 24 ++++++++++++++++++++++
.../gcc.target/riscv/rvv/xtheadvector/vzext.c | 24 ++++++++++++++++++++++
3 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 8ee43cf0ce1c..51eb64fb1226 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3939,7 +3939,7 @@
(any_extend:VWEXTI
(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VWEXTI 2 "vector_merge_operand" " vu,
0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
"v<sz>ext.vf2\t%0,%3%p1"
[(set_attr "type" "vext")
(set_attr "mode" "<MODE>")])
@@ -3959,7 +3959,7 @@
(any_extend:VQEXTI
(match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
"v<sz>ext.vf4\t%0,%3%p1"
[(set_attr "type" "vext")
(set_attr "mode" "<MODE>")])
@@ -3979,7 +3979,7 @@
(any_extend:VOEXTI
(match_operand:<V_OCT_TRUNC> 3 "register_operand" " vr, vr"))
(match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
"v<sz>ext.vf8\t%0,%3%p1"
[(set_attr "type" "vext")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
new file mode 100644
index 000000000000..55db28304c7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vsext.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */
+
+#include <riscv_vector.h>
+
+struct a
+{
+ int b[];
+} c (vint32m4_t), d;
+
+char e;
+char *f;
+
+void g ()
+{
+ int h;
+ vint32m4_t i;
+ vint8m1_t j = __riscv_vlse8_v_i8m1 (&e, d.b[3], h);
+ vint16m2_t k = __riscv_vwadd_vx_i16m2 (j, 0, h);
+ i = __riscv_vwmacc_vx_i32m4 (i, f[0], k, h);
+ c (i);
+}
+
+/* { dg-final { scan-assembler-not {th\.vsext\.vf2} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
new file mode 100644
index 000000000000..fcb565991c6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vzext.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O3" } */
+
+#include <riscv_vector.h>
+
+struct a
+{
+ int b[];
+} c (vuint32m4_t), d;
+
+char e;
+char *f;
+
+void g ()
+{
+ int h;
+ vuint32m4_t i;
+ vuint8m1_t j = __riscv_vlse8_v_u8m1 (&e, d.b[3], h);
+ vuint16m2_t k = __riscv_vwaddu_vx_u16m2 (j, 0, h);
+ i = __riscv_vwmaccu_vx_u32m4 (i, f[0], k, h);
+ c (i);
+}
+
+/* { dg-final { scan-assembler-not {th\.vzext\.vf2} } } */
