https://gcc.gnu.org/g:f2e2e255004dc35beef9d8b5800d69d228f7eec1
commit r14-11584-gf2e2e255004dc35beef9d8b5800d69d228f7eec1
Author: Jin Ma <ji...@linux.alibaba.com>
Date: Tue Feb 11 21:28:05 2025 +0800
RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets
This is a follow-up to the patch below to avoid generating unrecognized
vsetivl instructions for XTheadVector.
https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html
PR target/118601
gcc/ChangeLog:
* config/riscv/riscv-string.cc (expand_block_move): Check with new
constraint 'vl' instead of 'K'.
(expand_vec_setmem): Likewise.
(expand_vec_cmpmem): Likewise.
* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
(expand_load_store): Likewise.
(expand_strided_load): Likewise.
(expand_strided_store): Likewise.
(expand_lanes_load_store): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Move to...
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: ...here.
* gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: New test.
* gcc.target/riscv/rvv/xtheadvector/pr118601.c: New test.
Reported-by: Edwin Lu <e...@rivosinc.com>
(cherry picked from commit 580f571be6ce80aa71fb80e7b16e01824f088229)
Diff:
---
gcc/config/riscv/riscv-string.cc | 2 +-
gcc/config/riscv/riscv-v.cc | 8 ++--
.../riscv/rvv/xtheadvector/pr114194-rv32.c | 51 ++++++++++++++++++++++
.../xtheadvector/{pr114194.c => pr114194-rv64.c} | 5 +--
.../gcc.target/riscv/rvv/xtheadvector/pr118601.c | 9 ++++
5 files changed, 67 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index b09b51d7526b..1cb9f832bb54 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -969,7 +969,7 @@ expand_block_move (rtx dst_in, rtx src_in, rtx length_in)
machine_mode mask_mode = riscv_vector::get_vector_mode
(BImode, GET_MODE_NUNITS (vmode)).require ();
rtx mask = CONSTM1_RTX (mask_mode);
- if (!satisfies_constraint_K (cnt))
+ if (!satisfies_constraint_vl (cnt))
cnt= force_reg (Pmode, cnt);
rtx m_ops[] = {vec, mask, src};
emit_nonvlmax_insn (code_for_pred_mov (vmode),
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index fe51e2fe9b83..bb38d8b42c70 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2075,7 +2075,7 @@ get_unknown_min_value (machine_mode mode)
static rtx
force_vector_length_operand (rtx vl)
{
- if (CONST_INT_P (vl) && !satisfies_constraint_K (vl))
+ if (CONST_INT_P (vl) && !satisfies_constraint_vl (vl))
return force_reg (Pmode, vl);
return vl;
}
@@ -3864,7 +3864,7 @@ expand_load_store (rtx *ops, bool is_load)
}
else
{
- if (!satisfies_constraint_K (len))
+ if (!satisfies_constraint_vl (len))
len = force_reg (Pmode, len);
if (is_load)
{
@@ -4309,7 +4309,7 @@ expand_lanes_load_store (rtx *ops, bool is_load)
}
else
{
- if (!satisfies_constraint_K (len))
+ if (!satisfies_constraint_vl (len))
len = force_reg (Pmode, len);
if (is_load)
{
@@ -5108,7 +5108,7 @@ can_be_broadcasted_p (rtx op)
&& !satisfies_constraint_Wdm (op))
return false;
- if (satisfies_constraint_K (op) || register_operand (op, mode)
+ if (satisfies_constraint_vl (op) || register_operand (op, mode)
|| satisfies_constraint_Wdm (op) || rtx_equal_p (op, CONST0_RTX (mode)))
return true;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
new file mode 100644
index 000000000000..0bee5ec33de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target rv32 } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** foo0_1:
+** sb\tzero,0\([a-x0-9]+\)
+** ret
+*/
+void foo0_1 (void *p)
+{
+ __builtin_memset (p, 0, 1);
+}
+
+/*
+** foo0_7:
+** li\t[a-x0-9]+,7
+** th.vsetvli\tzero,[a-x0-9]+,e8,m1
+** th\.vmv\.v\.i\tv[0-9],0
+** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void foo0_7 (void *p)
+{
+ __builtin_memset (p, 0, 7);
+}
+
+/*
+** foo1_1:
+** li\t[a-x0-9]+,1
+** sb\t[a-x0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+void foo1_1 (void *p)
+{
+ __builtin_memset (p, 1, 1);
+}
+
+/*
+** foo1_5:
+** li\t[a-x0-9]+,5
+** th.vsetvli\tzero,[a-x0-9]+,e8,m1
+** th\.vmv\.v\.i\tv[0-9],1
+** th\.vse\.v\tv[0-9]+,0\([a-x0-9]+\)
+** ret
+*/
+
+void foo1_5 (void *p)
+{
+ __builtin_memset (p, 1, 5);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
similarity index 82%
rename from gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
rename to gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
index 2e53a7ecc3e7..84333c1cf5a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c
@@ -1,6 +1,5 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
+/* { dg-do compile { target rv64 } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" } */
/* { dg-final { check-function-bodies "**" "" } } */
/*
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118601.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118601.c
new file mode 100644
index 000000000000..c8acfcfea0ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118601.c
@@ -0,0 +1,9 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
+
+void foo1_16 (void *p)
+{
+ __builtin_memset (p, 1, 16);
+}
