Re: Progress notes on hacking on RPi2 with new firmware
Hello everybody, I have managed HYP boot to run on RPi2 even when application is loaded by U-boot. Code is functional on RPi1 in SVC boot mode and U-boot load with cache enabled and should work even with direct boots from (hopefully) all versions of firmware. Graphic works on RPi1 and on RPi2 under QEMU but on real board there is no screen output on RPi2 U-boot loaded application even that mailbox operations report correct values for modes, memory size and initialization result. May be cache/setup problems? May be U-boot misconfiguring something. Anyway, even when graphic console is requested and HDMI not detected serial output is selected. Default is serial port anyway. I have started on cache manager extensions and corrections. The RPi boot and cache manager work is available from GitHub for testing https://github.com/ppisa/rtems/tree/rtems-rpi-devel I consider at least patches listed at the end of this e-mail as mainline quality material. Comments review welcome. I expect to send them as e-mail series this evening. Current version includes proposal for new cave manager operations but no real cache manager correction for ARM BSPs where it is missing. Proposed new operations /** + * @brief Returns the maximal cache line size of all cache kinds in bytes. + * + * Returns computed or obtained maximal cache line size of all + * all caches in the system. + * + * @retval 0 No cache is present + * @retval positive The maximal cache line size in bytes. + */ +size_t rtems_cache_get_maximal_line_size( void ); + +/** + +/** + * @brief Ensure necessary synchronization required after code changes + * + * When code is loaded or modified then many Harvard cache equipped + * systems require synchronization of main memory and or updated + * code in data cache to ensure visibility of change in all + * connected CPUs instruction memory view. This operation + * should be used by run time loader for example. + * + * @param[in] addr The start address of the area to invalidate. + * @param[in] size The size in bytes of the area to invalidate. + */ +void rtems_cache_instruction_sync_after_code_change( + const void * code_addr, + size_t n_bytes +); + They are implemented naive way for now but should be clean interface to build on in future. Cache manager is compiled only for initial set of RAM BSPs still which means that it is missing for most of the targets. I plan to take some journey to refres the body and mind from Monday evening until next Sunday without net access. I would be happy if patches at least up to arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2. could be pushed to mainline to correct RPi2 situation. Best wishes, Pavel commit 28e36bba4ad343877aeac1fa0de9d0471c1c505c Author: Pavel Pisa Date: Fri Jul 1 00:05:33 2016 +0200 arm/score and shared: define ARM hypervisor mode and alternate vector table base access. The main reason for inclusion of minimum hypervisor related defines is that current ARM boards firmware and loaders (U-boot for example) start loaded operating system kernel in HYP mode to allow it take control of virtualization (Linux/KVM for example). commit e6dc617b27bc2ddd67f4eff9b0eb6a43438fcca8 Author: Pavel Pisa Date: Sat Jul 2 17:02:57 2016 +0200 bsps/arm: Support recent bootloaders starting kernel in HYP mode When HYP mode is detected at startup then setup HYP mode vectors table (for future extensions) clean exceptions switching to HYP mode and switch CPU to ARM SVC mode. BSPs which want to use this support need to include next option in their configure.ac RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") and need to include next lines in corresponding Makefile.am if BSP_START_IN_HYP_SUPPORT libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S endif commit 7428e3300dcbf83567335c8e1dbd56a54e3c34b1 Author: Pavel Pisa Date: Sat Jul 2 13:15:02 2016 +0200 arm/raspberrypi: Enable HYP to SVC switch for this BSP. This support is required when newer firmware is used on Raspberry Pi 2 boards. commit 1f89edd41f84d14cafc1ddeda6f815ba20298197 Author: Pavel Pisa Date: Sat Jul 2 14:33:11 2016 +0200 score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib. Some/many Cortex-A cores have data cache line length 64 bytes and maximum value has to be used for system structures alignment. commit 2422dce40537b97f471625a680344281737c6bcb Author: Pavel Pisa Date: Sat Jul 2 18:52:44 2016 +0200 arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2. The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2, clean by individual lines works on RPi1 and RPi2.
[PATCH 07/10] bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.
From: Pavel Pisa
---
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4
1 file changed, 4 insertions(+)
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 35c8002..e83b55c 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
@@ -72,6 +72,10 @@ extern "C" {
/* These two defines also ensure that the rtems_cache_* functions have bodies
*/
#define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
+#if defined(__ARM_ARCH_7A__)
+/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
+#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
--
1.9.1
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[PATCH 08/10] bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs.
From: Pavel Pisa The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support --- c/src/lib/libbsp/arm/beagle/Makefile.am| 5 +- c/src/lib/libbsp/arm/csb336/Makefile.am| 6 +- c/src/lib/libbsp/arm/csb337/Makefile.am| 6 +- c/src/lib/libbsp/arm/lpc32xx/Makefile.am | 6 +- c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 8 +- c/src/lib/libbsp/arm/raspberrypi/preinstall.am | 4 - c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 5 +- .../arm/shared/armv467ar-basic-cache/cache_.h | 134 + c/src/lib/libbsp/arm/smdk2410/Makefile.am | 6 +- c/src/lib/libcpu/arm/shared/include/cache_.h | 134 + 10 files changed, 190 insertions(+), 124 deletions(-) create mode 100644 c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h diff --git a/c/src/lib/libbsp/arm/beagle/Makefile.am b/c/src/lib/libbsp/arm/beagle/Makefile.am index 20d3092..904cb84 100644 --- a/c/src/lib/libbsp/arm/beagle/Makefile.am +++ b/c/src/lib/libbsp/arm/beagle/Makefile.am @@ -126,8 +126,9 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h -libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include +libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h +libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h +libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache ### # Special Rules # diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am b/c/src/lib/libbsp/arm/csb336/Makefile.am index e2687b8..27d159f 100644 --- a/c/src/lib/libbsp/arm/csb336/Makefile.am +++ b/c/src/lib/libbsp/arm/csb336/Makefile.am @@ -10,6 +10,7 @@ include_HEADERS = include/bsp.h include_HEADERS += ../../shared/include/tm27.h include_bsp_HEADERS = +libbsp_a_CPPFLAGS = nodist_include_HEADERS = include/bspopts.h nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h @@ -51,8 +52,9 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += ../../shared/include/cache_.h -libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include +libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h +libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h +libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache if HAS_NETWORKING network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ diff --git a/c/src/lib/libbsp/arm/csb337/Makefile.am b/c/src/lib/libbsp/arm/csb337/Makefile.am index 598a67f..018bf67 100644 --- a/c/src/lib/libbsp/arm/csb337/Makefile.am +++ b/c/src/lib/libbsp/arm/csb337/Makefile.am @@ -13,6 +13,7 @@ include_HEADERS += include/sed1356.h endif include_bsp_HEADERS = +libbsp_a_CPPFLAGS = if ENABLE_UMON include_umondir = $(includedir)/umon @@ -88,8 +89,9 @@ endif # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += ../../shared/include/cache_.h -libbsp_a_CPPFLAGS = -I$(srcdir)/../../shared/include +libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h +libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h +libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache if HAS_NETWORKING network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am index 5426323..e87c6a0 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am @@ -142,8 +142,10 @@ libbsp_a_SOURCES += misc/idle-thread.c # Cache libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c -libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h -libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include +libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h +libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h +libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache + # Start hooks libbsp_a_SOURCES += startup/bspstarthooks.c diff --git a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am index c9208d4..4b111ad 100644 --- a/c/src/lib/libbsp/arm/ra
[PATCH 00/10] HYP mode boot and cache manager updates for ARM and RaspberryPi specially.
From: Pavel Pisa These changes allows to boot Raspberry Pi 2 with recent firmware which start system in ARM hypervisor (HYP) mode. There are more changes to correct/make compile cache manager functions for more boards (till now only Zynq, Altera Cyclone and LPC32xx have non empty implementation included). Cache maintenance is required for communication with VideoCore on RPi2. Actual series leaves local workaround solution in that place but mailbox code has been tested to work even with proposed deeper change in cache manager. I am not sure about last three patches but at least series including arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2. should be in shape for mainline and should help other projects working on RPi. Pavel Pisa (10): arm/score and shared: define ARM hypervisor mode and alternate vector table base access. bsps/arm: Support recent bootloaders starting kernel in HYP mode arm/raspberrypi: Enable HYP to SVC switch for this BSP. score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib. arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2. rtems+bsps/cache: Define cache manager operations for code synchronization and maximal alignment. bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310. bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs. libdl/rtl-obj.c: ensure that loaded code is synchronized through caches. bsps/arm: basic on core cache support changed to use l1 functions. c/src/lib/libbsp/arm/beagle/Makefile.am| 5 +- c/src/lib/libbsp/arm/csb336/Makefile.am| 6 +- c/src/lib/libbsp/arm/csb337/Makefile.am| 6 +- c/src/lib/libbsp/arm/lpc32xx/Makefile.am | 6 +- c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 11 +- c/src/lib/libbsp/arm/raspberrypi/configure.ac | 4 + c/src/lib/libbsp/arm/raspberrypi/misc/vc.c | 15 +- c/src/lib/libbsp/arm/raspberrypi/preinstall.am | 4 - c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am | 5 +- c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4 + .../arm/shared/armv467ar-basic-cache/cache_.h | 171 + c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 71 - .../lib/libbsp/arm/shared/include/linker-symbols.h | 4 + c/src/lib/libbsp/arm/shared/include/start.h| 13 +- c/src/lib/libbsp/arm/shared/start/start.S | 73 - .../arm/shared/startup/bsp-start-in-hyp-support.S | 77 ++ c/src/lib/libbsp/arm/shared/startup/linkcmds.base | 9 +- c/src/lib/libbsp/arm/smdk2410/Makefile.am | 6 +- c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 61 +++- c/src/lib/libcpu/arm/shared/include/cache_.h | 134 c/src/lib/libcpu/shared/src/cache_manager.c| 42 + cpukit/libcsupport/src/cachealignedalloc.c | 2 +- cpukit/libdl/rtl-obj.c | 2 + cpukit/rtems/include/rtems/rtems/cache.h | 29 cpukit/score/cpu/arm/rtems/score/arm.h | 4 + cpukit/score/cpu/arm/rtems/score/cpu.h | 8 +- 26 files changed, 592 insertions(+), 180 deletions(-) create mode 100644 c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h create mode 100644 c/src/lib/libbsp/arm/shared/startup/bsp-start-in-hyp-support.S -- 1.9.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 04/10] score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.
From: Pavel Pisa
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
---
cpukit/score/cpu/arm/rtems/score/arm.h | 4
cpukit/score/cpu/arm/rtems/score/cpu.h | 7 +--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h
b/cpukit/score/cpu/arm/rtems/score/arm.h
index 334e73a..9ae7830 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -54,6 +54,10 @@ extern "C" {
#define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
#endif
+#if defined(__ARM_ARCH_7A__)
+ #define ARM_MULTILIB_CACHE_LINE_MAX_64B
+#endif
+
#if !defined(__SOFTFP__)
#if defined(__ARM_NEON__)
#define ARM_MULTILIB_VFP_D32
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 91e4ec6..68ea178 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -145,8 +145,11 @@
#define CPU_STACK_GROWS_UP FALSE
-/* FIXME: Is this the right value? */
-#define CPU_CACHE_LINE_BYTES 32
+#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64B)
+ #define CPU_CACHE_LINE_BYTES 32
+#else
+ #define CPU_CACHE_LINE_BYTES 64
+#endif
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
--
1.9.1
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[PATCH 06/10] rtems+bsps/cache: Define cache manager operations for code synchronization and maximal alignment.
From: Pavel Pisa
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
---
c/src/lib/libcpu/shared/src/cache_manager.c | 42 +
cpukit/libcsupport/src/cachealignedalloc.c | 2 +-
cpukit/rtems/include/rtems/rtems/cache.h| 29
3 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c
b/c/src/lib/libcpu/shared/src/cache_manager.c
index 255f621..3201c31 100644
--- a/c/src/lib/libcpu/shared/src/cache_manager.c
+++ b/c/src/lib/libcpu/shared/src/cache_manager.c
@@ -477,3 +477,45 @@ rtems_cache_disable_instruction( void )
_CPU_cache_disable_instruction();
#endif
}
+
+/* Returns the maximal cache line size of all cache kinds in bytes. */
+size_t rtems_cache_get_maximal_line_size( void )
+{
+#if defined(CPU_MAXIMAL_CACHE_ALIGNMENT)
+ return CPU_MAXIMAL_CACHE_ALIGNMENT;
+#endif
+ size_t max_line_size = 0;
+#if defined(CPU_DATA_CACHE_ALIGNMENT)
+ {
+size_t data_line_size = CPU_DATA_CACHE_ALIGNMENT;
+if ( max_line_size < data_line_size )
+ max_line_size = data_line_size;
+ }
+#endif
+#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
+ {
+size_t instruction_line_size = CPU_INSTRUCTION_CACHE_ALIGNMENT;
+if ( max_line_size < instruction_line_size )
+ max_line_size = instruction_line_size;
+ }
+#endif
+ return max_line_size;
+}
+
+/*
+ * Purpose is to synchronize caches after code has been loaded
+ * or self modified. Actual implementation is simple only
+ * but it can and should be repaced by optimized version
+ * which does not need flush and invalidate all cache levels
+ * when code is changed.
+ */
+void
+rtems_cache_instruction_sync_after_code_change( const void * code_addr, size_t
n_bytes )
+{
+#if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION)
+ _CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes );
+#else
+ rtems_cache_flush_multiple_data_lines( code_addr, n_bytes );
+ rtems_cache_invalidate_multiple_instruction_lines( code_addr, n_bytes );
+#endif
+}
diff --git a/cpukit/libcsupport/src/cachealignedalloc.c
b/cpukit/libcsupport/src/cachealignedalloc.c
index a704859..764fdfb 100644
--- a/cpukit/libcsupport/src/cachealignedalloc.c
+++ b/cpukit/libcsupport/src/cachealignedalloc.c
@@ -15,7 +15,7 @@
void *rtems_cache_aligned_malloc( size_t nbytes )
{
- size_t line_size = rtems_cache_get_data_line_size();
+ size_t line_size = rtems_cache_get_maximal_line_size();
if ( line_size > 0 ) {
/* Assume that the cache line size is a power of two */
diff --git a/cpukit/rtems/include/rtems/rtems/cache.h
b/cpukit/rtems/include/rtems/rtems/cache.h
index a7dcaa6..f1dc9bf 100644
--- a/cpukit/rtems/include/rtems/rtems/cache.h
+++ b/cpukit/rtems/include/rtems/rtems/cache.h
@@ -61,6 +61,17 @@ size_t rtems_cache_get_data_line_size( void );
size_t rtems_cache_get_instruction_line_size( void );
/**
+ * @brief Returns the maximal cache line size of all cache kinds in bytes.
+ *
+ * Returns computed or obtained maximal cache line size of all
+ * all caches in the system.
+ *
+ * @retval 0 No cache is present
+ * @retval positive The maximal cache line size in bytes.
+ */
+size_t rtems_cache_get_maximal_line_size( void );
+
+/**
* @brief Returns the data cache size in bytes.
*
* @param[in] level The cache level of interest. The cache level zero
@@ -125,6 +136,24 @@ void rtems_cache_invalidate_multiple_instruction_lines(
size_t size
);
+
+/**
+ * @brief Ensure necessary synchronization required after code changes
+ *
+ * When code is loaded or modified then many Harvard cache equipped
+ * systems require synchronization of main memory and or updated
+ * code in data cache to ensure visibility of change in all
+ * connected CPUs instruction memory view. This operation
+ * should be used by run time loader for example.
+ *
+ * @param[in] addr The start address of the area to invalidate.
+ * @param[in] size The size in bytes of the area to invalidate.
+ */
+void rtems_cache_instruction_sync_after_code_change(
+ const void * code_addr,
+ size_t n_bytes
+);
+
/**
* @brief Flushes the entire data cache.
*
--
1.9.1
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[PATCH 03/10] arm/raspberrypi: Enable HYP to SVC switch for this BSP.
From: Pavel Pisa This support is required when newer firmware is used on Raspberry Pi 2 boards. --- c/src/lib/libbsp/arm/raspberrypi/Makefile.am | 3 +++ c/src/lib/libbsp/arm/raspberrypi/configure.ac | 4 2 files changed, 7 insertions(+) diff --git a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am index abb6865..c9208d4 100644 --- a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am +++ b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am @@ -94,6 +94,9 @@ libbsp_a_SOURCES += ../../shared/sbrk.c libbsp_a_SOURCES += ../../shared/src/stackalloc.c libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c +if BSP_START_IN_HYP_SUPPORT +libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S +endif # Startup libbsp_a_SOURCES += ../../shared/bspreset_loop.c diff --git a/c/src/lib/libbsp/arm/raspberrypi/configure.ac b/c/src/lib/libbsp/arm/raspberrypi/configure.ac index 2676bef..ecaee3d 100644 --- a/c/src/lib/libbsp/arm/raspberrypi/configure.ac +++ b/c/src/lib/libbsp/arm/raspberrypi/configure.ac @@ -24,6 +24,10 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) +RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode]) +AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" = "1") + RTEMS_BSPOPTS_SET([I2C_IO_MODE],[*],[1]) RTEMS_BSPOPTS_HELP([I2C_IO_MODE],[Define to 1 to use interrupt-driven I/O with the Raspberry Pi I2C bus. If defined to other value the access will be polled-driven.]) -- 1.9.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 01/10] arm/score and shared: define ARM hypervisor mode and alternate vector table base access.
From: Pavel Pisa
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
---
c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 30 ++
cpukit/score/cpu/arm/rtems/score/cpu.h | 1 +
2 files changed, 31 insertions(+)
diff --git a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
index 4c1966d..8357656 100644
--- a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
+++ b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h
@@ -1324,6 +1324,36 @@ arm_cp15_set_vector_base_address(void *base)
);
}
+ARM_CP15_TEXT_SECTION static inline void
+*arm_cp15_get_hyp_vector_base_address(void)
+{
+ ARM_SWITCH_REGISTERS;
+ void *base;
+
+ __asm__ volatile (
+ARM_SWITCH_TO_ARM
+"mrc p15, 4, %[base], c12, c0, 0\n"
+ARM_SWITCH_BACK
+: [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT
+ );
+
+ return base;
+}
+
+ARM_CP15_TEXT_SECTION static inline void
+arm_cp15_set_hyp_vector_base_address(void *base)
+{
+ ARM_SWITCH_REGISTERS;
+
+ __asm__ volatile (
+ARM_SWITCH_TO_ARM
+"mcr p15, 4, %[base], c12, c0, 0\n"
+ARM_SWITCH_BACK
+: ARM_SWITCH_OUTPUT
+: [base] "r" (base)
+ );
+}
+
/**
* @brief Sets the @a section_flags for the address range [@a begin, @a end).
*
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h
b/cpukit/score/cpu/arm/rtems/score/cpu.h
index 815cd95..91e4ec6 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -82,6 +82,7 @@
#define ARM_PSR_M_IRQ 0x12
#define ARM_PSR_M_SVC 0x13
#define ARM_PSR_M_ABT 0x17
+#define ARM_PSR_M_HYP 0x1a
#define ARM_PSR_M_UND 0x1b
#define ARM_PSR_M_SYS 0x1f
--
1.9.1
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[PATCH 05/10] arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2.
From: Pavel Pisa
The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2,
clean by individual lines works on RPi1 and RPi2.
---
c/src/lib/libbsp/arm/raspberrypi/misc/vc.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
b/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
index 7bc17ba..0bec0c2 100644
--- a/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
+++ b/c/src/lib/libbsp/arm/raspberrypi/misc/vc.c
@@ -73,9 +73,20 @@ static inline void
bcm2835_mailbox_buffer_flush_and_invalidate(
*/
rtems_cache_flush_multiple_data_lines( buf, size );
rtems_cache_invalidate_multiple_data_lines( buf, size );
-#else
-/* Flush complete data cache */
+#elif 0
+/* Flush complete data cache, does not work on RPi2 for some reason */
arm_cp15_data_cache_clean_and_invalidate();
+#else
+/*
+ * This is temporal workaround for missing cache meanager
+ * which works on RPi2
+ */
+size += (uintptr_t)buf & ~63;
+size = (size + 63) & ~63;
+while ( size ) {
+ size -= 32;
+ arm_cp15_data_cache_clean_and_invalidate_line(buf);
+}
#endif
}
}
--
1.9.1
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[PATCH 09/10] libdl/rtl-obj.c: ensure that loaded code is synchronized through caches.
From: Pavel Pisa Synchronize each cluster of sections of the same type separately to support even cases where text and data are allocated from different areas (for example due allocation from different MPU protection regions). rtems_cache_instruction_sync_after_code_change is called even to data sections. Propagation of data only changes should not require cache maintenance operation on sane SMP mutithread capable systems if barrier instruction is added but be on safe side even for case where self modifying code uses data sections initial values etc. --- cpukit/libdl/rtl-obj.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpukit/libdl/rtl-obj.c b/cpukit/libdl/rtl-obj.c index 5c89990..00a1c6e 100644 --- a/cpukit/libdl/rtl-obj.c +++ b/cpukit/libdl/rtl-obj.c @@ -618,6 +618,8 @@ rtems_rtl_obj_sections_loader (uint32_t mask, first = false; } +rtems_cache_instruction_sync_after_code_change(base, base_offset); + node = rtems_chain_next (node); } -- 1.9.1 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
[PATCH 10/10] bsps/arm: basic on core cache support changed to use l1 functions.
From: Pavel Pisa
The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.
Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.
---
.../arm/shared/armv467ar-basic-cache/cache_.h | 43 -
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 71 +-
c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 31 +-
3 files changed, 97 insertions(+), 48 deletions(-)
diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
index bc19cb7..de5fddb 100644
--- a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
@@ -24,6 +24,7 @@
#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
#include
+#include "../include/arm-cache-l1.h"
#define CPU_DATA_CACHE_ALIGNMENT 32
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
@@ -32,14 +33,44 @@
#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
#endif
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
+ ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+
+
static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
{
- arm_cp15_data_cache_clean_line(d_addr);
+ arm_cache_l1_flush_1_data_line(d_addr);
+}
+
+static inline void
+_CPU_cache_flush_data_range(
+ const void *d_addr,
+ size_t n_bytes
+)
+{
+ _ARM_Data_synchronization_barrier();
+ arm_cp15_drain_write_buffer();
+ arm_cache_l1_flush_data_range(
+d_addr,
+n_bytes
+ );
}
static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
- arm_cp15_data_cache_invalidate_line(d_addr);
+ arm_cache_l1_invalidate_1_data_line(d_addr);
+}
+
+static inline void
+_CPU_cache_invalidate_data_range(
+ const void *addr_first,
+ size_t n_bytes
+)
+{
+ arm_cache_l1_invalidate_data_range(
+addr_first,
+n_bytes
+ );
}
static inline void _CPU_cache_freeze_data(void)
@@ -54,7 +85,13 @@ static inline void _CPU_cache_unfreeze_data(void)
static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
- arm_cp15_instruction_cache_invalidate_line(d_addr);
+ arm_cache_l1_invalidate_1_instruction_line(d_addr);
+}
+
+static inline void
+_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
+{
+ arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
}
static inline void _CPU_cache_freeze_instruction(void)
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
index 1c3d9cf..74a65c5 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
@@ -37,8 +37,10 @@ extern "C" {
#define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32
#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
-#define ARM_CACHE_L1_CSS_ID_DATA 0
-#define ARM_CACHE_L1_CSS_ID_INSTRUCTION 1
+#define ARM_CACHE_L1_CSS_ID_DATA \
+ (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
+#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
+ (ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
#define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
#define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \
@@ -52,15 +54,6 @@ static void arm_cache_l1_errata_764369_handler( void )
#endif
}
-static void arm_cache_l1_select( const uint32_t selection )
-{
- /* select current cache level in cssr */
- arm_cp15_set_cache_size_selection( selection );
-
- /* isb to sych the new cssr&csidr */
- _ARM_Instruction_synchronization_barrier();
-}
-
/*
* @param l1LineSize Number of bytes in cache line expressed as power of
*2 value
@@ -69,22 +62,23 @@ static void arm_cache_l1_select( const uint32_t selection )
* qparam liNumSets Number of sets in cache
* */
-static inline void arm_cache_l1_properties(
+static inline void arm_cache_l1_properties_for_level(
uint32_t *l1LineSize,
uint32_t *l1Associativity,
- uint32_t *l1NumSets )
+ uint32_t *l1NumSets,
+ uint32_t level_and_inst_dat
+)
{
- uint32_t id;
+ uint32_t ccsidr;
- _ARM_Instruction_synchronization_barrier();
- id = arm_cp15_get_cache_size_id();
+ ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
/* Cache line size in words + 2 -> bytes) */
- *l1LineSize = ( id & 0x0007U ) + 2 + 2;
+ *l1LineSize = arm_ccsidr_get_line_power(ccsidr);
/* Number of Ways */
- *l1Associativity = ( ( id >> 3 ) & 0x03ffU ) + 1;
+ *l1As
[PATCH 02/10] bsps/arm: Support recent bootloaders starting kernel in HYP mode
From: Pavel Pisa
When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1])
RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM
HYP mode])
AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" =
"1")
and need to include next lines in corresponding Makefile.am
if BSP_START_IN_HYP_SUPPORT
libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S
endif
---
.../lib/libbsp/arm/shared/include/linker-symbols.h | 4 ++
c/src/lib/libbsp/arm/shared/include/start.h| 13 +++-
c/src/lib/libbsp/arm/shared/start/start.S | 73 +++-
.../arm/shared/startup/bsp-start-in-hyp-support.S | 77 ++
c/src/lib/libbsp/arm/shared/startup/linkcmds.base | 9 ++-
5 files changed, 170 insertions(+), 6 deletions(-)
create mode 100644
c/src/lib/libbsp/arm/shared/startup/bsp-start-in-hyp-support.S
diff --git a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
index 7446259..1a996f5 100644
--- a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
+++ b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
@@ -59,6 +59,10 @@ LINKER_SYMBOL(bsp_stack_und_begin)
LINKER_SYMBOL(bsp_stack_und_end)
LINKER_SYMBOL(bsp_stack_und_size)
+LINKER_SYMBOL(bsp_stack_hyp_begin)
+LINKER_SYMBOL(bsp_stack_hyp_end)
+LINKER_SYMBOL(bsp_stack_hyp_size)
+
LINKER_SYMBOL(bsp_stack_svc_begin)
LINKER_SYMBOL(bsp_stack_svc_end)
LINKER_SYMBOL(bsp_stack_svc_size)
diff --git a/c/src/lib/libbsp/arm/shared/include/start.h
b/c/src/lib/libbsp/arm/shared/include/start.h
index f61eed3..bf8eed4 100644
--- a/c/src/lib/libbsp/arm/shared/include/start.h
+++ b/c/src/lib/libbsp/arm/shared/include/start.h
@@ -45,6 +45,15 @@ extern "C" {
#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
+/*
+* Many ARM boot loaders pass arguments to loaded OS kernel
+*/
+#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS
+#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int
saved_dtb_adr
+#else
+#define BSP_START_HOOKS_LOADER_ARGS void
+#endif
+
/**
* @brief System start entry.
*/
@@ -57,7 +66,7 @@ void _start(void);
* stack pointers are initialized but before the copying of the exception
* vectors.
*/
-void bsp_start_hook_0(void);
+void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS);
/**
* @brief Start entry hook 1.
@@ -65,7 +74,7 @@ void bsp_start_hook_0(void);
* This hook will be called from the start entry code after copying of the
* exception vectors but before the call to boot_card().
*/
-void bsp_start_hook_1(void);
+void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS);
/**
* @brief Similar to standard memcpy().
diff --git a/c/src/lib/libbsp/arm/shared/start/start.S
b/c/src/lib/libbsp/arm/shared/start/start.S
index 4050deb..0848fff 100644
--- a/c/src/lib/libbsp/arm/shared/start/start.S
+++ b/c/src/lib/libbsp/arm/shared/start/start.S
@@ -54,6 +54,11 @@
.extern bsp_start_init_registers_vfp
#endif
+#ifdef BSP_START_IN_HYP_SUPPORT
+ .extern bsp_start_arm_drop_hyp_mode
+ .globl bsp_start_hyp_vector_table_begin
+#endif
+
/* Global symbols */
.globl _start
.globl bsp_start_vector_table_begin
@@ -124,16 +129,56 @@ handler_addr_fiq:
bsp_start_vector_table_end:
+#ifdef BSP_START_IN_HYP_SUPPORT
+bsp_start_hyp_vector_table_begin:
+ ldr pc, handler_addr_hyp_reset
+ ldr pc, handler_addr_hyp_undef
+ ldr pc, handler_addr_hyp_swi
+ ldr pc, handler_addr_hyp_prefetch
+ ldr pc, handler_addr_hyp_abort
+ ldr pc, handler_addr_hyp_hyp
+ ldr pc, handler_addr_hyp_irq
+ ldr pc, handler_addr_hyp_fiq
+
+handler_addr_hyp_reset:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_undef:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_swi:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_prefetch:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_abort:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_hyp:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_irq:
+ .word _ARMV4_Exception_reserved_default
+
+handler_addr_hyp_fiq:
+ .word _ARMV4_Exception_reserved_default
+
+bsp_start_hyp_vector_table_end:
+#endif
+
/* Start entry */
_start:
/*
* We do not save the context since we do not return to the boot
-* loader.
+* loader but preserve r1 and r2 to allow access to bootloader
parameters
*/
-
-#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
+#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
+ mov r5, r1 /* machi
Re: [PATCH 07/10] bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310.
Does it make sense to use the new
ARM_MULTILIB_CACHE_LINE_MAX_64B
here?
On 04/07/16 01:52, pp...@cmp.felk.cvut.cz wrote:
From: Pavel Pisa
---
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4
1 file changed, 4 insertions(+)
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index 35c8002..e83b55c 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
@@ -72,6 +72,10 @@ extern "C" {
/* These two defines also ensure that the rtems_cache_* functions have bodies
*/
#define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
+#if defined(__ARM_ARCH_7A__)
+/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */
+#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
+#endif
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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Re: [PATCH 04/10] score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.
On 04/07/16 01:52, pp...@cmp.felk.cvut.cz wrote: +#if defined(__ARM_ARCH_7A__) + #define ARM_MULTILIB_CACHE_LINE_MAX_64B +#endif Is 'B' bytes or bits? I think in the cache line context its pretty clear that these are bytes, so I would use ARM_MULTILIB_CACHE_LINE_MAX_64 or ARM_MULTILIB_CACHE_LINE_MAX_64_BYTES -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: [PATCH 02/10] bsps/arm: Support recent bootloaders starting kernel in HYP mode
On 04/07/16 01:52, pp...@cmp.felk.cvut.cz wrote:
From: Pavel Pisa
When HYP mode is detected at startup then setup HYP mode
vectors table (for future extensions) clean exceptions
switching to HYP mode and switch CPU to ARM SVC mode.
BSPs which want to use this support need to include next option
in their configure.ac
RTEMS_BSPOPTS_SET([BSP_START_IN_HYP_SUPPORT],[*],[1])
RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM
HYP mode])
AM_CONDITIONAL(BSP_START_IN_HYP_SUPPORT,test "$BSP_START_IN_HYP_SUPPORT" =
"1")
and need to include next lines in corresponding Makefile.am
if BSP_START_IN_HYP_SUPPORT
libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S
endif
---
.../lib/libbsp/arm/shared/include/linker-symbols.h | 4 ++
c/src/lib/libbsp/arm/shared/include/start.h| 13 +++-
c/src/lib/libbsp/arm/shared/start/start.S | 73 +++-
.../arm/shared/startup/bsp-start-in-hyp-support.S | 77 ++
c/src/lib/libbsp/arm/shared/startup/linkcmds.base | 9 ++-
5 files changed, 170 insertions(+), 6 deletions(-)
create mode 100644
c/src/lib/libbsp/arm/shared/startup/bsp-start-in-hyp-support.S
diff --git a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
index 7446259..1a996f5 100644
--- a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
+++ b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h
@@ -59,6 +59,10 @@ LINKER_SYMBOL(bsp_stack_und_begin)
LINKER_SYMBOL(bsp_stack_und_end)
LINKER_SYMBOL(bsp_stack_und_size)
+LINKER_SYMBOL(bsp_stack_hyp_begin)
+LINKER_SYMBOL(bsp_stack_hyp_end)
+LINKER_SYMBOL(bsp_stack_hyp_size)
+
LINKER_SYMBOL(bsp_stack_svc_begin)
LINKER_SYMBOL(bsp_stack_svc_end)
LINKER_SYMBOL(bsp_stack_svc_size)
diff --git a/c/src/lib/libbsp/arm/shared/include/start.h
b/c/src/lib/libbsp/arm/shared/include/start.h
index f61eed3..bf8eed4 100644
--- a/c/src/lib/libbsp/arm/shared/include/start.h
+++ b/c/src/lib/libbsp/arm/shared/include/start.h
@@ -45,6 +45,15 @@ extern "C" {
#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
+/*
+* Many ARM boot loaders pass arguments to loaded OS kernel
+*/
+#ifdef BSP_START_HOOKS_WITH_LOADER_ARGS
+#define BSP_START_HOOKS_LOADER_ARGS int saved_psr, int saved_machid, int
saved_dtb_adr
+#else
+#define BSP_START_HOOKS_LOADER_ARGS void
+#endif
+
/**
* @brief System start entry.
*/
@@ -57,7 +66,7 @@ void _start(void);
* stack pointers are initialized but before the copying of the exception
* vectors.
*/
-void bsp_start_hook_0(void);
+void bsp_start_hook_0(BSP_START_HOOKS_LOADER_ARGS);
Do we really need the saved_psr and saved_machid? I think it is
sufficient to pass the DTB address or NULL to bsp_start_hook_0() for all
BSPs. We should avoid this conditional parameter list.
/**
* @brief Start entry hook 1.
@@ -65,7 +74,7 @@ void bsp_start_hook_0(void);
* This hook will be called from the start entry code after copying of the
* exception vectors but before the call to boot_card().
*/
-void bsp_start_hook_1(void);
+void bsp_start_hook_1(BSP_START_HOOKS_LOADER_ARGS);
These parameters are not set up in start.S in this patch.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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Re: Error while adding usb ethernet driver
On 03/07/16 06:56, Chris Johns wrote: On 30/06/2016 20:22, Deval Shah wrote: On Tue, Jun 28, 2016 at 3:12 AM, Chris Johns mailto:chr...@rtems.org>> wrote: It might pay for us to add these to an RTEMS header to make porting simpler. Can't we update our sys/net/if.c and sys/net/if_var.h files accourding to new FreeBSD ? I don't think its a good idea to selectively update random files of the network stack core. I do not know. Currently we have a policy of keeping as much at the snapshot point as we can. Sebastian has looked at moving to FreeBSD 10 and backed off doing so because it was more work than he could handle due to changes in FreeBSD 10. I am not against something like this being merged if the change is localised to just those files, it works, and the existing drivers work. If the change ripples out across the code base then it would be a problem. Partial updates make it harder and harder to do a major update. I did this for complete subsystems like SDCard/MMC/USB, however, doing this for individual files is really a problem if want to update. The blocking point for an easy update to FreeBSD 10 or 11 are the user space command line programs like ifconfig and route. We need a better general approach to deal with user space programs. We may have time to do an update later this year. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Error while adding usb ethernet driver
On 04/07/2016 15:46, Sebastian Huber wrote: On 03/07/16 06:56, Chris Johns wrote: On 30/06/2016 20:22, Deval Shah wrote: On Tue, Jun 28, 2016 at 3:12 AM, Chris Johns mailto:chr...@rtems.org>> wrote: It might pay for us to add these to an RTEMS header to make porting simpler. Can't we update our sys/net/if.c and sys/net/if_var.h files accourding to new FreeBSD ? I don't think its a good idea to selectively update random files of the network stack core. I am fine with this and understand the reasons. I do not know. Currently we have a policy of keeping as much at the snapshot point as we can. Sebastian has looked at moving to FreeBSD 10 and backed off doing so because it was more work than he could handle due to changes in FreeBSD 10. I am not against something like this being merged if the change is localised to just those files, it works, and the existing drivers work. If the change ripples out across the code base then it would be a problem. Partial updates make it harder and harder to do a major update. I did this for complete subsystems like SDCard/MMC/USB, however, doing this for individual files is really a problem if want to update. The blocking point for an easy update to FreeBSD 10 or 11 are the user space command line programs like ifconfig and route. We need a better general approach to deal with user space programs. It would be good to see if dynamic loading can be used to help here. I would need some time to sort through the issues but in theory we should be able to do this. We may have time to do an update later this year. This would be good. Chris ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
