[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

@craig.topper Thanks!
@asb Hi Alex, I'd like to get another approval from you. Are there any more 
concerns?


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[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D70401#4657101 , @jrtc27 wrote:

> In D70401#4657098 , @jrtc27 wrote:
>
>> GCC only ever defines __riscv_32e
>
> Hm, seems the comments about __riscv_32e were from months ago, ignore them if 
> they aren't correct or have become outdated...

FYI: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/52


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[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D70401#4655408 , @asb wrote:

> First of all, thank you to everyone who has been trying to nudge this forward 
> and apologies it must have been a frustrating experience.
>
> I appreciate there are users who want to see this and I don't like that LLVM 
> doesn't serve them right now - I think it's unfortunate that this need for 
> the ABI hasn't translated into effort to finalise the ABI definition in the 
> psABI doc and to at least get it to match what GCC actually implements (spec. 
> That said, I've not really vocalised that concern clearly up to now - so 
> that's my bad.
>
> Matching what GCC does by setting stack alignment to 4 bytes for 2xlen types 
> seems fine - except this doesn't seem to be documented explicitly in the 
> current ABI doc (it notes the stack if 4 byte aligned, but you could have 
> that be the case and still require it to be realigned when storing objects 
> with a greater alignment requirement, surely?).
>
> Having different alignment requirements _only_ on the stack does seem ugly, 
> but I can't think of something off hand that would realistically break with 
> this.
>
> @wangpc do you want to update this with the suggested documentation in the 
> release notes and RISCVUsage on the support being "experimental"?

Thanks! I added a note to the RISCVUsage. There won't be `experimental-e` like 
other experimental extensions as it is already ratified and adds no 
instruction, it is experimental just because the support is experimental.

For ABI part, I don't know if @kito-cheng has some updates/comments.


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[PATCH] D122629: [RISCV] Add index check for vset/vget

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead created this revision.
pcwang-thead added reviewers: luismarques, asb, craig.topper, khchen.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
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jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, 
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Index of vset/vget must be a constant integer and be
located in right range.


Repository:
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https://reviews.llvm.org/D122629

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/vget-index-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vset-index-out-of-range.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset-index-out-of-range.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset-index-out-of-range.c
@@ -0,0 +1,341 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -fsyntax-only -verify %s
+
+#include 
+
+vint8m1_t test_vset_v_index_not_constant(vint8m2_t dest, vint8m1_t val, int index) {
+  // expected-error@+1 {{argument to 'vset_v_i8m1_i8m2' must be a constant integer}}
+  return vset_v_i8m1_i8m2(dest, index, val);
+}
+
+vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i8m1_i8m2(dest, 2, val);
+}
+
+vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i8m1_i8m4(dest, 4, val);
+}
+
+vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i8m2_i8m4(dest, 2, val);
+}
+
+vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  return vset_v_i8m1_i8m8(dest, 8, val);
+}
+
+vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i8m2_i8m8(dest, 4, val);
+}
+
+vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i8m4_i8m8(dest, 2, val);
+}
+
+vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i16m1_i16m2(dest, 2, val);
+}
+
+vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i16m1_i16m4(dest, 4, val);
+}
+
+vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i16m2_i16m4(dest, 2, val);
+}
+
+vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) {
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  return vset_v_i16m1_i16m8(dest, 8, val);
+}
+
+vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, vint16m2_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i16m2_i16m8(dest, 4, val);
+}
+
+vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, vint16m4_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i16m4_i16m8(dest, 2, val);
+}
+
+vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, vint32m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i32m1_i32m2(dest, 2, val);
+}
+
+vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, vint32m1_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i32m1_i32m4(dest, 4, val);
+}
+
+vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, vint32m2_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i32m2_i32m4(dest, 2, val);
+}
+
+vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, vint32m1_t val) {
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  return vset_v_i32m1_i32m8(dest, 8, val);
+}
+
+vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, vint32m2_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i32m2_i32m8(dest, 4, val);
+}
+
+vint32m8_t t

[PATCH] D122629: [RISCV] Add index check for vset/vget

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcebbfd3d2555: [RISCV] Add index check for vset/vget 
(authored by pcwang-thead).

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Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/vget-index-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vset-index-out-of-range.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vset-index-out-of-range.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vset-index-out-of-range.c
@@ -0,0 +1,341 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN:   -fsyntax-only -verify %s
+
+#include 
+
+vint8m1_t test_vset_v_index_not_constant(vint8m2_t dest, vint8m1_t val, int index) {
+  // expected-error@+1 {{argument to 'vset_v_i8m1_i8m2' must be a constant integer}}
+  return vset_v_i8m1_i8m2(dest, index, val);
+}
+
+vint8m2_t test_vset_v_i8m1_i8m2(vint8m2_t dest, vint8m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i8m1_i8m2(dest, 2, val);
+}
+
+vint8m4_t test_vset_v_i8m1_i8m4(vint8m4_t dest, vint8m1_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i8m1_i8m4(dest, 4, val);
+}
+
+vint8m4_t test_vset_v_i8m2_i8m4(vint8m4_t dest, vint8m2_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i8m2_i8m4(dest, 2, val);
+}
+
+vint8m8_t test_vset_v_i8m1_i8m8(vint8m8_t dest, vint8m1_t val) {
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  return vset_v_i8m1_i8m8(dest, 8, val);
+}
+
+vint8m8_t test_vset_v_i8m2_i8m8(vint8m8_t dest, vint8m2_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i8m2_i8m8(dest, 4, val);
+}
+
+vint8m8_t test_vset_v_i8m4_i8m8(vint8m8_t dest, vint8m4_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i8m4_i8m8(dest, 2, val);
+}
+
+vint16m2_t test_vset_v_i16m1_i16m2(vint16m2_t dest, vint16m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i16m1_i16m2(dest, 2, val);
+}
+
+vint16m4_t test_vset_v_i16m1_i16m4(vint16m4_t dest, vint16m1_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i16m1_i16m4(dest, 4, val);
+}
+
+vint16m4_t test_vset_v_i16m2_i16m4(vint16m4_t dest, vint16m2_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i16m2_i16m4(dest, 2, val);
+}
+
+vint16m8_t test_vset_v_i16m1_i16m8(vint16m8_t dest, vint16m1_t val) {
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  return vset_v_i16m1_i16m8(dest, 8, val);
+}
+
+vint16m8_t test_vset_v_i16m2_i16m8(vint16m8_t dest, vint16m2_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i16m2_i16m8(dest, 4, val);
+}
+
+vint16m8_t test_vset_v_i16m4_i16m8(vint16m8_t dest, vint16m4_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i16m4_i16m8(dest, 2, val);
+}
+
+vint32m2_t test_vset_v_i32m1_i32m2(vint32m2_t dest, vint32m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i32m1_i32m2(dest, 2, val);
+}
+
+vint32m4_t test_vset_v_i32m1_i32m4(vint32m4_t dest, vint32m1_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i32m1_i32m4(dest, 4, val);
+}
+
+vint32m4_t test_vset_v_i32m2_i32m4(vint32m4_t dest, vint32m2_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i32m2_i32m4(dest, 2, val);
+}
+
+vint32m8_t test_vset_v_i32m1_i32m8(vint32m8_t dest, vint32m1_t val) {
+  // expected-error@+1 {{argument value 8 is outside the valid range [0, 7]}}
+  return vset_v_i32m1_i32m8(dest, 8, val);
+}
+
+vint32m8_t test_vset_v_i32m2_i32m8(vint32m8_t dest, vint32m2_t val) {
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return vset_v_i32m2_i32m8(dest, 4, val);
+}
+
+vint32m8_t test_vset_v_i32m4_i32m8(vint32m8_t dest, vint32m4_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i32m4_i32m8(dest, 2, val);
+}
+
+vint64m2_t test_vset_v_i64m1_i64m2(vint64m2_t dest, vint64m1_t val) {
+  // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+  return vset_v_i64m1_i64m2(dest, 2, val

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D129824#3699911 , @kito-cheng 
wrote:

> Just realized the problem is trying to fixed the default value of `-mabi=`, 
> currently `clang -target riscv32-elf -march=rv64gc 
> -mabi=lp64d`/`riscv32-elf-clang -march=rv64gc -mabi=lp64d` is work, and match 
> the behavior of GCC did, `riscv32-elf-gcc -march=rv64gc -mabi=lp64d`.
>
> And this patch is trying to make following two command work: `clang -target 
> riscv32-elf -march=rv64gc`/`riscv32-elf-clang -march=rv64gc`, specify 
> `-march` and `-target` but no `-mabi`.
>
> That is different story now, GCC isn't deduce the default abi from either 
> target triple or abi, so if you invoke gcc with `riscv32-elf-gcc 
> -march=rv64gc` or `riscv64-elf-gcc -march=rv32gc`, you will got error message 
> like that: `cc1: error: ABI requires '-march=rv32'` or `cc1: error: ABI 
> requires '-march=rv64'`.



> So that's not compatible issue with GCC, that's sort of clang driver specify 
> issue, and I don't have strong opinion on this.
>
> ---
>
> As a GNU toolchain developer, I would say, we are not intend to change the 
> behavior of default value of `-mabi` or `-march`, the consensus among RISC-V 
> GNU toolchain maintainer is user should explicitly specify the `-march` and 
> `-mabi` if you are not using default `-march` and `-mabi`.

@kito-cheng Thanks! We have noticed these differences between GNU and LLVM, and 
we have done some efforts to make both compatible.
I think we can discuss here: 
https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/20


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead commandeered this revision.
pcwang-thead edited reviewers, added: zixuan-wu; removed: pcwang-thead.
pcwang-thead added a comment.
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Herald added a project: All.

In D70401#3250049 , @khchen wrote:

> 1. please add a check here 
> 
>  and a clang cc1 test for it.
> 2. Have you try to run llvm-test-suite with rv32e config on qemu?



1. Thanks, I may do it later. And here is a question: the comment 

 says `It is illegal to specify 'e' extensions with 'f' and 'd'`.

While ilp32e 

 says:

> The ILP32E calling convention is not compatible with ISAs that have registers 
> that require load and store alignments of more than 32 bits. In particular, 
> this calling convention must not be used with the D ISA extension.

And, the RV32E 
 chapter 
in RISCV ISA manual says:

> RV32E can be combined with all current standard extensions.

If I understand correctly, E can't be combined with D in current specification 
since E must use ILP32E calling convention.

2. I have run llvm-test-suite with rv32e on qemu, and found no major fault for 
current implementation. Some tests are disabled because they can't run on bare 
mental (sees Disabled llvm-test-suite cases ).

There are some failed tests due to floating-point precision, but I saw the same 
result when run with  rv32gc on bare mental. I haven't taken the time to find 
out the reason, but I guess it may be soft-float issues.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D70401#3395340 , @kito-cheng wrote:

> Last LLVM sync-up call @asb has raise the discussion about the ILP32E issue, 
> so here is note from my site:
>
> RISC-V psABI doc still say "we don't  guarantee the stability of `ILP32E`", 
> the reason is RV32E still not a ratified extension, but as psABI chair, what 
> I can say is we intend to do NOT change as possible.
>
> As I know rv32e*/ilp32e are already used by many vendors (include SiFive), so 
> I support ilp32e should be supported on LLVM upstream.

Thanks! I will spend some time to make this patch compatible with GCC 
implementation, please feel free to give some comments and suggestions!


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.
Herald added a subscriber: StephenFan.

In D70401#3391561 , @khchen wrote:

> I found 
> https://github.com/llvm/llvm-test-suite/blob/main/SingleSource/UnitTests/2003-05-26-Shorts.c
>  result is mismatched with gcc's (-march=rv32e -mabi=ilp32e).
> Did you have same issue?

I got the same issue, but it may be not this patch's problem.
Here is the reduced case:

  #include 
  
  unsigned long long getL() { return 0xafafafafc5c5b8a3ull; }
  int main(int argc, char **argv) {
unsigned long long UL = getL(); /* 0xafafafafc5c5b8a3 */
unsigned int ui = (unsigned int)UL; /* 0xc5c5b8a3 =  3318069411 */
printf("ui = %u (0x%x)\t\tUL-ui = %lld (0x%llx)\n", ui, ui, UL - ui, UL - 
ui);
  }

GCC output is:

  ui = 3318069411 (0xc5c5b8a3)UL-ui = -5787213829993660416 
(0xafafafaf)

LLVM output is:

  ui = 3318069411 (0xc5c5b8a3)UL-ui = 0 (0xafafafaf)

The problem is the way to pass arguments to `printf`.
GCC asm:

li  a4,-1347440640
addisp,sp,-24
addia4,a4,-81
sw  a4,8(sp)
lw  a5,8(sp)
li  a2,-976896000
addia2,a2,-1885
lui a0,%hi(.LC1)
sw  a5,0(sp)
li  a3,0
li  a5,0
mv  a1,a2
addia0,a0,%lo(.LC1)
sw  ra,20(sp)
sw  a3,4(sp)
callprintf

LLVM asm:

addisp, sp, -16
sw  ra, 12(sp)  # 4-byte Folded Spill
sw  s0, 8(sp)   # 4-byte Folded Spill
addis0, sp, 16
andisp, sp, -8
lui a0, 719611
addia5, a0, -81
sw  a5, 4(sp)
lui a0, %hi(.L.str)
addia0, a0, %lo(.L.str)
lui a1, 810076
addia1, a1, -1885
sw  zero, 0(sp)
mv  a2, a1
mv  a4, zero
callprintf

Both GCC and LLVM pass format string and two `ui` by `a0, a1, a2`, the 
difference is how they pass rest variadic arguments.
`UL-ui` is with 2*XLEN size, so it will be spilt to two part (low and high 
32-bits). Low part is 0x, high part is 0xafafafaf.
For GCC:

  First UL-ui  : low -> a3, high -> a4
  Second UL-ui : low -> a5, high -> stack.0

For LLVM:

  First UL-ui  : low -> a4, high -> a5
  Second UL-ui : low -> stack.0, high -> stack.1

Because we use GLIBC compiled by GCC  while linking with LLVM's output, so in 
`printf`'s view:

  a3 -> undefined, so it is zero.
  a4 -> low part, 0x
  a5 -> high part, 0xafafafaf
  stack.0 -> low part, 0x
  stack.1 -> not used

It get `0x` and `0xafafafaf` for two `UL-ui` (seen as 
the output).

In the ABI specification, it says (Integer Calling Convention 
):

  In the base integer calling convention, variadic arguments are passed in the 
same manner as named arguments, with one exception. Variadic arguments with 
2×XLEN-bit alignment and size at most 2×XLEN bits are passed in an aligned 
register pair (i.e., the first register in the pair is even-numbered), or on 
the stack by value if none is available. After a variadic argument has been 
passed on the stack, all future arguments will also be passed on the stack 
(i.e. the last argument register may be left unused due to the aligned register 
pair rule).

And this is what LLVM do for ILP32E currently.

I saw the same issue on Github(Inconsistent variadic argument passing behavior 
between ilp32 and ilp32e for long long/double 
), so shall LLVM be 
compatible with GCC's behavior?
@kito-cheng @khchen


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 423555.
pcwang-thead added a comment.

- Disable sized deallocation for Apple targets.
- Update tests and don't use `-fno-sized-deallocation` any more.
  - With one exception: `clang/test/SemaCXX/builtin-operator-new-delete.cpp`, 
which will generate two notes without line infos if using default settings.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc-new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-alloc-exp-namespace.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup-exp-namespace.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-gro-exp-namespace.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -10,9 +10,10 @@
 
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// XFAIL: apple-clang
+
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: clang/www/cxx_status.html
===
--- clang/www/cxx_status.html
+++ clang/www/cxx_status.html
@@ -578,12 +578,11 @@
 
 
 
-(7): In Clang 3.7 and later, sized deallocation is only enabled
-if the user passes the -fsized-deallocation flag. The user must
-supply definitions of the sized deallocation functions, either by providing them
-explicitly or by using a C++ standard library that does. libstdc++
-added these functions in version 5.0, and libc++ added them in
-version 3.7.
+(7): The user must supply definitions of the sized deallocation
+functions, either by providing them explicitly or by using a C++ standard library
+that does. libstdc++ added these functions in version 5.0, and
+libc++ added them in version 3.7. The user can also use the
+-fno-sized-deallocation option to disable sized deallocation.
 
 
 
Index: clang/unittests/StaticAnalyzer/CallEventTest.cpp
===
--- clang/unittests/StaticAnalyzer/CallEventTest.cpp
+++ clang/unittests/StaticAnalyzer/CallEventTest.cpp
@@ -81,7 +81,7 @@
 }
   )",
  Diags));
-  EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 1\n");
+  EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 2\n");
 }
 
 } // namespace
Index: clang/test/SemaCXX/unavailable_aligned_allocation.cpp
===
--- clang/test/SemaCXX/unavailable_aligned_allocation.cpp
+++ clang/test/SemaCXX/unavailable_aligned_allocation.cpp
@@ -74,32 +74,35 @@
 // expected-note@-21 {{if you supply your own aligned allocation functions}}
 // expected-error-re@-22 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is {{only|not}} available on}}
 // expected-note@-23 {{if you supply your own aligned allocation functions}}
-
+#if !defined(ZOS)
 // expected-error-re@-24 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is {{only|not}} available on}}
 // expected-note@-25 {{if you supply your own aligned allocation functions}}
-
-// expected-error-re@-26 {{aligned allocation function of type 'void *(std::size_t, std::align_val_t, const std::nothrow_t &) noexcept' is {{only|not}} available on}}
-// expected-note@-27 {{if you supply your o

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D112921#3453114 , @MaskRay wrote:

> Beside the concern raised by platform maintainers: the cc1 default switch 
> part should be made separately from the patch.
> This makes revert easy and leaves fewer churn to the test suite.
>
> If -fno-sized-deallocation is a better cc1 default (but not Driver's), I can 
> make such a change.

That will be helpful, thanks!


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D112921#3462592 , @Mordante wrote:

> I didn't look at the code, but I have some hints how we can test libc++.

Thanks! I ran tests with no error occurred on my local machine and I really 
want to know how to test it!


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: 
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp:17
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 

Mordante wrote:
> This `// XFAIL: clang-12, clang-13` is still needed but should be `// XFAIL: 
> clang-13, clang-14`. (Since the LLVM 14 release we only support these two 
> versions.)
> 
> For testing it's the easiest to remove line 147 of 
> `libcxx/utils/ci/buildkite-pipeline.yml`
> https://github.com/llvm/llvm-project/blob/afcc6baac52fcc91d1636f6803f5c230e7018016/libcxx/utils/ci/buildkite-pipeline.yml#L147
> 
> That way all builds run. The `Bootstrapping build` builds clang and uses that 
> clang to test libc++. That way we can validate which builds fail and which 
> succeed. Maybe some more builds need to be (temporary) disabled.
> 
> Once we verify that works we need to:
> - undo the buildkite changes
> - disable this test temporary (`UNSUPPORTED: clang-15`)
> - create a followup patch to reenable the test
> After the change has landed it will take some time before the change is 
> propagated to the CI. Once it's propagated the followup patch can be landed. 
> I'm willing to create the followup patch and land it at the proper time.
> 
Thanks! I will have a try later. :)


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D112921#3473022 , @ldionne wrote:

> (BTW I strongly support this patch, I just think we should do it properly on 
> all platforms from the start :-)

I couldn't agree with you more, but I have no idea how to implement it. :-(

In D112921#3473080 , @rjmccall wrote:

> Ideally, I think, we would set this up to work something like `ObjCRuntime`, 
> where we're making queries to a common place that contains all the 
> information necessary to decide what runtime features are available.  In 
> particular, we shouldn't treat Apple platforms as forever unique in providing 
> a stable runtime interface with availability gating.
>
> Now, we don't necessarily need the same complexity that `ObjCRuntime` 
> supports, where the user can tell us to use a different runtime and runtime 
> version from the default for the platform.  On the other hand, maybe we want 
> that, because it's a good way to deal with the compatibility problem that we 
> have on non-Apple platforms.  Users could tell us that they're targeting e.g. 
> libsupc++ v4.8, and we could tell them in response that sized allocation 
> isn't supported.  And if we get them to tell us that, rather than "I have 
> sized allocation support" specifically, it sets us up well to solve similar 
> problems in the future.

You mean that we may provide a option `-fc++-runtime` likes `-fobjc-runtime`, 
or extend `-stdlib` to specify version number in the form of  
`-stdlib=libsupc++-v4.8`?


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D112921#3474964 , @rjmccall wrote:

> Hmm.  Allowing a version on `-stdlib` is intuitively appealing, but I'm not 
> sure it actually gives us the information we need.  As I recall, `-stdlib` 
> selects the high-level stdlib and not the low-level one, and those are 
> related in code but not necessarily at runtime; for example, you can (or at 
> least could, historically) use libstdc++ on macOS, but the underlying 
> low-level stdlib is going to be libc++abi, not libsupc++.  And the low-level 
> runtime is the one that actually provides global `operator new` functions.  
> Is there a way to bridge that gap?

Hmm, that's really a tough nut. We have high-level standard libraries like 
`libc++` and `libstdc++`, and low-level runtimes like `libc++abi`, `libsupc++` 
and libcxxrt . There could be a lot of 
situations and we haven't think about MSVC yet.
I don't know if adding an option `-cxxabilib=libsupc++-v4.8` or something like 
this would make sense, but I think we should make another revision to do it. I 
will appy @ldionne 's solution first.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 425443.
pcwang-thead added a comment.
Herald added subscribers: dexonsmith, arichardson.

- Add handling of Apple targets.
- Update libc++ tests.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc-new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-alloc-exp-namespace.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup-exp-namespace.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-gro-exp-namespace.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  libcxx/utils/ci/buildkite-pipeline.yml

Index: libcxx/utils/ci/buildkite-pipeline.yml
===
--- libcxx/utils/ci/buildkite-pipeline.yml
+++ libcxx/utils/ci/buildkite-pipeline.yml
@@ -1,4 +1,5 @@
 #===--===##
+#===--===##
 #
 # Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 # See https://llvm.org/LICENSE.txt for license information.
@@ -144,7 +145,7 @@
   #
   # All other supported configurations of libc++.
   #
-  - wait
+  # - wait
 
   - label: "C++20"
 command: "libcxx/utils/ci/run-buildbot generic-cxx20"
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -9,10 +9,11 @@
 // test sized operator delete[] replacement.
 
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-13, clang-14
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: clang/www/cxx_status.html
===
--- clang/www/cxx_status.html
+++ clang/www/cxx_status.html
@@ -578,12 +578,11 @@
 
 
 
-(7): In Clang 3.7 and later, sized deallocation is only enabled
-if the user passes the -fsized-deallocation flag. The user must
-supply definitions of the sized deallocation functions, either by providing them
-explicitly or by using a C++ standard library that does. libstdc++
-added these functions in version 5.0, and libc++ added them in
-version 3.7.
+(7): The user must supply definitions of the sized deallocation
+functions, either by providing them explicitly or by using a C++ standard library
+that does. libstdc++ added these functions in version 5.0, and
+libc++ added them in version 3.7. The user can also use the
+-fno-sized-deallocation option to disable sized deallocation.
 
 
 
Index: clang/unittests/StaticAnalyzer/CallEventTest.cpp
===
--- clang/unittests/StaticAnalyzer/CallEventTest.cpp
+++ clang/unittests/StaticAnalyzer/CallEventTest.cpp
@@ -81,7 +81,7 @@
 }
   )",
  Diags));
-  EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 1\n");
+  EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 2\n");
 }
 
 } // namespace
Index: clang/test/SemaCXX/unavailable_aligned_allocation.cpp
===
--- clang/test/SemaCXX/unavailable_aligned_allocation.cpp
+++ clang/test/SemaCXX/unavailable_aligned_allocation.c

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead created this revision.
pcwang-thead added reviewers: asb, luismarques, kito-cheng, craig.topper.
Herald added subscribers: sunshaoce, VincentWu, luke957, jeroen.dobbelaere, 
StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, 
johnrusso, rbar, arichardson.
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pcwang-thead requested review of this revision.
Herald added subscribers: cfe-commits, eopXD.
Herald added a project: clang.

We use them in RVV intrinsics doc but there is no definition
in riscv_vector.h, which is confusing for users. This matches
what GCC does too.

There are too many tests using the raw types, so we keep them
untouched.


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Files:
  clang/include/clang/Basic/riscv_vector.td


Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1504,6 +1504,16 @@
 // and LMUL.
 let HeaderCode =
 [{
+#if defined(__riscv_zvfh)
+typedef _Float16 float16_t;
+#endif
+#if defined(__riscv_f)
+typedef float float32_t;
+#endif
+#if defined(__riscv_d)
+typedef double float64_t;
+#endif
+
 #define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
 #define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
 #define vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)


Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1504,6 +1504,16 @@
 // and LMUL.
 let HeaderCode =
 [{
+#if defined(__riscv_zvfh)
+typedef _Float16 float16_t;
+#endif
+#if defined(__riscv_f)
+typedef float float32_t;
+#endif
+#if defined(__riscv_d)
+typedef double float64_t;
+#endif
+
 #define vsetvl_e8mf8(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 5)
 #define vsetvl_e8mf4(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 6)
 #define vsetvl_e8mf2(avl) __builtin_rvv_vsetvli((size_t)(avl), 0, 7)
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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 430246.
pcwang-thead added a comment.
Herald added a subscriber: MaskRay.

Add a test to check RVV type aliases.


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  clang/test/CodeGen/RISCV/rvv-type-aliases.c

Index: clang/test/CodeGen/RISCV/rvv-type-aliases.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-type-aliases.c
@@ -0,0 +1,155 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
+// RUN: -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN: -fsyntax-only -verify -ast-dump %s | FileCheck %s
+
+#include 
+
+// expected-no-diagnostics
+void bar(void) {
+  // CHECK: f16 'float16_t':'_Float16'
+  float16_t f16;
+  // CHECK: f32 'float32_t':'float'
+  float32_t f32;
+  // CHECK: f64 'float64_t':'double'
+  float64_t f64;
+
+  // CHECK: b1 'vbool1_t':'__rvv_bool1_t'
+  vbool1_t b1;
+  // CHECK: b2 'vbool2_t':'__rvv_bool2_t'
+  vbool2_t b2;
+  // CHECK: b4 'vbool4_t':'__rvv_bool4_t'
+  vbool4_t b4;
+  // CHECK: b8 'vbool8_t':'__rvv_bool8_t'
+  vbool8_t b8;
+  // CHECK: b16 'vbool16_t':'__rvv_bool16_t'
+  vbool16_t b16;
+  // CHECK: b32 'vbool32_t':'__rvv_bool32_t'
+  vbool32_t b32;
+  // CHECK: b64 'vbool64_t':'__rvv_bool64_t'
+  vbool64_t b64;
+
+  // CHECK: i8mf8 'vint8mf8_t':'__rvv_int8mf8_t'
+  vint8mf8_t i8mf8;
+  // CHECK: u8mf8 'vuint8mf8_t':'__rvv_uint8mf8_t'
+  vuint8mf8_t u8mf8;
+  // CHECK: i8mf4 'vint8mf4_t':'__rvv_int8mf4_t'
+  vint8mf4_t i8mf4;
+  // CHECK: u8mf4 'vuint8mf4_t':'__rvv_uint8mf4_t'
+  vuint8mf4_t u8mf4;
+  // CHECK: i8mf2 'vint8mf2_t':'__rvv_int8mf2_t'
+  vint8mf2_t i8mf2;
+  // CHECK: u8mf2 'vuint8mf2_t':'__rvv_uint8mf2_t'
+  vuint8mf2_t u8mf2;
+  // CHECK: i8m1 'vint8m1_t':'__rvv_int8m1_t'
+  vint8m1_t i8m1;
+  // CHECK: u8m1 'vuint8m1_t':'__rvv_uint8m1_t'
+  vuint8m1_t u8m1;
+  // CHECK: i8m2 'vint8m2_t':'__rvv_int8m2_t'
+  vint8m2_t i8m2;
+  // CHECK: u8m2 'vuint8m2_t':'__rvv_uint8m2_t'
+  vuint8m2_t u8m2;
+  // CHECK: i8m4 'vint8m4_t':'__rvv_int8m4_t'
+  vint8m4_t i8m4;
+  // CHECK: u8m4 'vuint8m4_t':'__rvv_uint8m4_t'
+  vuint8m4_t u8m4;
+  // CHECK: i8m8 'vint8m8_t':'__rvv_int8m8_t'
+  vint8m8_t i8m8;
+  // CHECK: u8m8 'vuint8m8_t':'__rvv_uint8m8_t'
+  vuint8m8_t u8m8;
+
+  // CHECK: i16mf4 'vint16mf4_t':'__rvv_int16mf4_t'
+  vint16mf4_t i16mf4;
+  // CHECK: u16mf4 'vuint16mf4_t':'__rvv_uint16mf4_t'
+  vuint16mf4_t u16mf4;
+  // CHECK: i16mf2 'vint16mf2_t':'__rvv_int16mf2_t'
+  vint16mf2_t i16mf2;
+  // CHECK: u16mf2 'vuint16mf2_t':'__rvv_uint16mf2_t'
+  vuint16mf2_t u16mf2;
+  // CHECK: i16m1 'vint16m1_t':'__rvv_int16m1_t'
+  vint16m1_t i16m1;
+  // CHECK: u16m1 'vuint16m1_t':'__rvv_uint16m1_t'
+  vuint16m1_t u16m1;
+  // CHECK: i16m2 'vint16m2_t':'__rvv_int16m2_t'
+  vint16m2_t i16m2;
+  // CHECK: u16m2 'vuint16m2_t':'__rvv_uint16m2_t'
+  vuint16m2_t u16m2;
+  // CHECK: i16m4 'vint16m4_t':'__rvv_int16m4_t'
+  vint16m4_t i16m4;
+  // CHECK: u16m4 'vuint16m4_t':'__rvv_uint16m4_t'
+  vuint16m4_t u16m4;
+  // CHECK: i16m8 'vint16m8_t':'__rvv_int16m8_t'
+  vint16m8_t i16m8;
+  // CHECK: u16m8 'vuint16m8_t':'__rvv_uint16m8_t'
+  vuint16m8_t u16m8;
+
+  // CHECK: i32mf2 'vint32mf2_t':'__rvv_int32mf2_t'
+  vint32mf2_t i32mf2;
+  // CHECK: u32mf2 'vuint32mf2_t':'__rvv_uint32mf2_t'
+  vuint32mf2_t u32mf2;
+  // CHECK: i32m1 'vint32m1_t':'__rvv_int32m1_t'
+  vint32m1_t i32m1;
+  // CHECK: u32m1 'vuint32m1_t':'__rvv_uint32m1_t'
+  vuint32m1_t u32m1;
+  // CHECK: i32m2 'vint32m2_t':'__rvv_int32m2_t'
+  vint32m2_t i32m2;
+  // CHECK: u32m2 'vuint32m2_t':'__rvv_uint32m2_t'
+  vuint32m2_t u32m2;
+  // CHECK: i32m4 'vint32m4_t':'__rvv_int32m4_t'
+  vint32m4_t i32m4;
+  // CHECK: u32m4 'vuint32m4_t':'__rvv_uint32m4_t'
+  vuint32m4_t u32m4;
+  // CHECK: i32m8 'vint32m8_t':'__rvv_int32m8_t'
+  vint32m8_t i32m8;
+  // CHECK: u32m8 'vuint32m8_t':'__rvv_uint32m8_t'
+  vuint32m8_t u32m8;
+
+  // CHECK: i64m1 'vint64m1_t':'__rvv_int64m1_t'
+  vint64m1_t i64m1;
+  // CHECK: u64m1 'vuint64m1_t':'__rvv_uint64m1_t'
+  vuint64m1_t u64m1;
+  // CHECK: i64m2 'vint64m2_t':'__rvv_int64m2_t'
+  vint64m2_t i64m2;
+  // CHECK: u64m2 'vuint64m2_t':'__rvv_uint64m2_t'
+  vuint64m2_t u64m2;
+  // CHECK: i64m4 'vint64m4_t':'__rvv_int64m4_t'
+  vint64m4_t i64m4;
+  // CHECK: u64m4 'vuint64m4_t':'__rvv_uint64m4_t'
+  vuint64m4_t u64m4;
+  // CHECK: i64m8 'vint64m8_t':'__rvv_int64m8_t'
+  vint64m8_t i64m8;
+  // CHECK: u64m8 'vuint64m8_t':'__rvv_uint64m8_t'
+  vuint64m8_t u64m8;
+
+  // CHECK: f16mf4 'vfloat16mf4_t':'__rvv_float16mf4_t'
+  vfloat16mf4_t f16mf4;
+  // CHECK: f16mf2 'vfloat16mf2_t':'__rvv_float16mf2_t'
+  vfloat16mf2_t f16mf2;
+  // CHECK: f16m1 'vfloat16m1_t':'__rvv_float16m1_t'
+  vfloat16m1_t f16m1;
+  // CHECK: f16m2 'vfloat16m2_t':'__rvv_float16m2_t'
+  vfloat16m2_t f16m2;
+  // C

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Besides, should we add `vread_csr` and `vwrite_csr` like what in GCC 
?
These two functions doesn't exist in RVV intrinsics doc, is it a historical 
problem?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125765/new/

https://reviews.llvm.org/D125765

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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 430285.
pcwang-thead added a comment.

Move to separate RVVHeader.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125765/new/

https://reviews.llvm.org/D125765

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-type-aliases.c

Index: clang/test/CodeGen/RISCV/rvv-type-aliases.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-type-aliases.c
@@ -0,0 +1,155 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +v \
+// RUN: -target-feature +zfh -target-feature +experimental-zvfh \
+// RUN: -fsyntax-only -verify -ast-dump %s | FileCheck %s
+
+#include 
+
+// expected-no-diagnostics
+void bar(void) {
+  // CHECK: f16 'float16_t':'_Float16'
+  float16_t f16;
+  // CHECK: f32 'float32_t':'float'
+  float32_t f32;
+  // CHECK: f64 'float64_t':'double'
+  float64_t f64;
+
+  // CHECK: b1 'vbool1_t':'__rvv_bool1_t'
+  vbool1_t b1;
+  // CHECK: b2 'vbool2_t':'__rvv_bool2_t'
+  vbool2_t b2;
+  // CHECK: b4 'vbool4_t':'__rvv_bool4_t'
+  vbool4_t b4;
+  // CHECK: b8 'vbool8_t':'__rvv_bool8_t'
+  vbool8_t b8;
+  // CHECK: b16 'vbool16_t':'__rvv_bool16_t'
+  vbool16_t b16;
+  // CHECK: b32 'vbool32_t':'__rvv_bool32_t'
+  vbool32_t b32;
+  // CHECK: b64 'vbool64_t':'__rvv_bool64_t'
+  vbool64_t b64;
+
+  // CHECK: i8mf8 'vint8mf8_t':'__rvv_int8mf8_t'
+  vint8mf8_t i8mf8;
+  // CHECK: u8mf8 'vuint8mf8_t':'__rvv_uint8mf8_t'
+  vuint8mf8_t u8mf8;
+  // CHECK: i8mf4 'vint8mf4_t':'__rvv_int8mf4_t'
+  vint8mf4_t i8mf4;
+  // CHECK: u8mf4 'vuint8mf4_t':'__rvv_uint8mf4_t'
+  vuint8mf4_t u8mf4;
+  // CHECK: i8mf2 'vint8mf2_t':'__rvv_int8mf2_t'
+  vint8mf2_t i8mf2;
+  // CHECK: u8mf2 'vuint8mf2_t':'__rvv_uint8mf2_t'
+  vuint8mf2_t u8mf2;
+  // CHECK: i8m1 'vint8m1_t':'__rvv_int8m1_t'
+  vint8m1_t i8m1;
+  // CHECK: u8m1 'vuint8m1_t':'__rvv_uint8m1_t'
+  vuint8m1_t u8m1;
+  // CHECK: i8m2 'vint8m2_t':'__rvv_int8m2_t'
+  vint8m2_t i8m2;
+  // CHECK: u8m2 'vuint8m2_t':'__rvv_uint8m2_t'
+  vuint8m2_t u8m2;
+  // CHECK: i8m4 'vint8m4_t':'__rvv_int8m4_t'
+  vint8m4_t i8m4;
+  // CHECK: u8m4 'vuint8m4_t':'__rvv_uint8m4_t'
+  vuint8m4_t u8m4;
+  // CHECK: i8m8 'vint8m8_t':'__rvv_int8m8_t'
+  vint8m8_t i8m8;
+  // CHECK: u8m8 'vuint8m8_t':'__rvv_uint8m8_t'
+  vuint8m8_t u8m8;
+
+  // CHECK: i16mf4 'vint16mf4_t':'__rvv_int16mf4_t'
+  vint16mf4_t i16mf4;
+  // CHECK: u16mf4 'vuint16mf4_t':'__rvv_uint16mf4_t'
+  vuint16mf4_t u16mf4;
+  // CHECK: i16mf2 'vint16mf2_t':'__rvv_int16mf2_t'
+  vint16mf2_t i16mf2;
+  // CHECK: u16mf2 'vuint16mf2_t':'__rvv_uint16mf2_t'
+  vuint16mf2_t u16mf2;
+  // CHECK: i16m1 'vint16m1_t':'__rvv_int16m1_t'
+  vint16m1_t i16m1;
+  // CHECK: u16m1 'vuint16m1_t':'__rvv_uint16m1_t'
+  vuint16m1_t u16m1;
+  // CHECK: i16m2 'vint16m2_t':'__rvv_int16m2_t'
+  vint16m2_t i16m2;
+  // CHECK: u16m2 'vuint16m2_t':'__rvv_uint16m2_t'
+  vuint16m2_t u16m2;
+  // CHECK: i16m4 'vint16m4_t':'__rvv_int16m4_t'
+  vint16m4_t i16m4;
+  // CHECK: u16m4 'vuint16m4_t':'__rvv_uint16m4_t'
+  vuint16m4_t u16m4;
+  // CHECK: i16m8 'vint16m8_t':'__rvv_int16m8_t'
+  vint16m8_t i16m8;
+  // CHECK: u16m8 'vuint16m8_t':'__rvv_uint16m8_t'
+  vuint16m8_t u16m8;
+
+  // CHECK: i32mf2 'vint32mf2_t':'__rvv_int32mf2_t'
+  vint32mf2_t i32mf2;
+  // CHECK: u32mf2 'vuint32mf2_t':'__rvv_uint32mf2_t'
+  vuint32mf2_t u32mf2;
+  // CHECK: i32m1 'vint32m1_t':'__rvv_int32m1_t'
+  vint32m1_t i32m1;
+  // CHECK: u32m1 'vuint32m1_t':'__rvv_uint32m1_t'
+  vuint32m1_t u32m1;
+  // CHECK: i32m2 'vint32m2_t':'__rvv_int32m2_t'
+  vint32m2_t i32m2;
+  // CHECK: u32m2 'vuint32m2_t':'__rvv_uint32m2_t'
+  vuint32m2_t u32m2;
+  // CHECK: i32m4 'vint32m4_t':'__rvv_int32m4_t'
+  vint32m4_t i32m4;
+  // CHECK: u32m4 'vuint32m4_t':'__rvv_uint32m4_t'
+  vuint32m4_t u32m4;
+  // CHECK: i32m8 'vint32m8_t':'__rvv_int32m8_t'
+  vint32m8_t i32m8;
+  // CHECK: u32m8 'vuint32m8_t':'__rvv_uint32m8_t'
+  vuint32m8_t u32m8;
+
+  // CHECK: i64m1 'vint64m1_t':'__rvv_int64m1_t'
+  vint64m1_t i64m1;
+  // CHECK: u64m1 'vuint64m1_t':'__rvv_uint64m1_t'
+  vuint64m1_t u64m1;
+  // CHECK: i64m2 'vint64m2_t':'__rvv_int64m2_t'
+  vint64m2_t i64m2;
+  // CHECK: u64m2 'vuint64m2_t':'__rvv_uint64m2_t'
+  vuint64m2_t u64m2;
+  // CHECK: i64m4 'vint64m4_t':'__rvv_int64m4_t'
+  vint64m4_t i64m4;
+  // CHECK: u64m4 'vuint64m4_t':'__rvv_uint64m4_t'
+  vuint64m4_t u64m4;
+  // CHECK: i64m8 'vint64m8_t':'__rvv_int64m8_t'
+  vint64m8_t i64m8;
+  // CHECK: u64m8 'vuint64m8_t':'__rvv_uint64m8_t'
+  vuint64m8_t u64m8;
+
+  // CHECK: f16mf4 'vfloat16mf4_t':'__rvv_float16mf4_t'
+  vfloat16mf4_t f16mf4;
+  // CHECK: f16mf2 'vfloat16mf2_t':'__rvv_float16mf2_t'
+  vfloat16mf2_t f16mf2;
+  // CHECK: f16m1 'vfloat16m1_t':'__rvv_float16m1_t'
+  vfloat16m1_t f16m1;
+  // CHECK: f16m2 'vfloat16m2_t':'__rvv_float16m2_t'
+  vfloat16m2_t f16m2;
+  // CHECK: f16m4 'vfloat16m4_t':'__rvv_float16m4_t'

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead created this revision.
pcwang-thead added reviewers: asb, luismarques, kito-cheng, craig.topper.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, 
frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, 
arichardson.
Herald added a project: All.
pcwang-thead requested review of this revision.
Herald added subscribers: cfe-commits, eopXD, MaskRay.
Herald added a project: clang.

These two functions are described in RVV intrinsics doc
to read/write RVV CSRs. This matches what GCC does.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125875

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-vread-csr.c
  clang/test/CodeGen/RISCV/rvv-vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-vwrite-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-vwrite-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}
Index: clang/test/CodeGen/RISCV/rvv-vread-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-vread-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1497,6 +1497,58 @@
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {
+  unsigned long rv = 0;
+  switch (csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(rv) : : "memory");
+  break;
+case RVV_VXSAT:
+  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(rv) : : "memory");
+  break;
+   

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1511
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {

craig.topper wrote:
> Do we need __gnu_inline__ and __artificial__? The only intrinsics headers 
> that have them in clang are in ppc_wrappers. X86 uses 
> `__attribute__((__always_inline__, __nodebug__`
I just made it the same as GCC.



Comment at: clang/include/clang/Basic/riscv_vector.td:1512
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {
+  unsigned long rv = 0;

craig.topper wrote:
> X86 and arm_neon.h uses double underscore prefixes on all variables in 
> intrinsic headers to reduce the chance of a collision with a user having a 
> macro with the same name.
The function prototypes have already been defined in RVV intrinsics doc 
(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-api.md#readwrite-urw-vector-csrs).


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1512
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR csr) {
+  unsigned long rv = 0;

craig.topper wrote:
> pcwang-thead wrote:
> > craig.topper wrote:
> > > X86 and arm_neon.h uses double underscore prefixes on all variables in 
> > > intrinsic headers to reduce the chance of a collision with a user having 
> > > a macro with the same name.
> > The function prototypes have already been defined in RVV intrinsics doc 
> > (https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-api.md#readwrite-urw-vector-csrs).
> I'm only refering to `csr`, `rv` and `value`. Those don't need to match the 
> intrinsics doc. They aren't visible to code using the header.
Oh I get it.


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 430567.
pcwang-thead added a comment.

Add double underscore to all variables.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-vread-csr.c
  clang/test/CodeGen/RISCV/rvv-vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-vwrite-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-vwrite-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}
Index: clang/test/CodeGen/RISCV/rvv-vread-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-vread-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1497,6 +1497,58 @@
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+unsigned long vread_csr(enum RVV_CSR __csr) {
+  unsigned long __rv = 0;
+  switch (__csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXSAT:
+  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXRM:
+  __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VCSR:
+  __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
+  break;
+  }
+  return __rv;
+}
+
+__extension__ extern __inline
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
+  switch (__csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ

[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead created this revision.
pcwang-thead added reviewers: asb, craig.topper, benshi001, luismarques, jrtc27.
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frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
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It seems that we use ilp32/lp64 ABI for these archs with
only single-precision floating-point extension. I believe
that users would like to pass arguments by floating-point
registers if they provide F extension in -march. So here
we use ilp32f and lp64f for these cases.

For some existed tests, we set `-target-abi` explicitly
to keep consistent.

@benshi001 has proposed this before and I think it is
necessary.

Links:

- https://reviews.llvm.org/D103878
- https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13


Repository:
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Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/Driver/riscv-abi.c
  clang/test/Driver/riscv-cpus.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
  llvm/test/CodeGen/RISCV/calling-conv-half.ll
  llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
  llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
  llvm/test/CodeGen/RISCV/rv64f-float-convert.ll

Index: llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
===
--- llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
+++ llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
@@ -10,8 +10,7 @@
 define i32 @aext_fptosi(float %a) nounwind {
 ; RV64IF-LABEL: aext_fptosi:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a0
-; RV64IF-NEXT:fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT:fcvt.w.s a0, fa0, rtz
 ; RV64IF-NEXT:ret
   %1 = fptosi float %a to i32
   ret i32 %1
@@ -20,8 +19,7 @@
 define signext i32 @sext_fptosi(float %a) nounwind {
 ; RV64IF-LABEL: sext_fptosi:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a0
-; RV64IF-NEXT:fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT:fcvt.w.s a0, fa0, rtz
 ; RV64IF-NEXT:ret
   %1 = fptosi float %a to i32
   ret i32 %1
@@ -30,8 +28,7 @@
 define zeroext i32 @zext_fptosi(float %a) nounwind {
 ; RV64IF-LABEL: zext_fptosi:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a0
-; RV64IF-NEXT:fcvt.w.s a0, ft0, rtz
+; RV64IF-NEXT:fcvt.w.s a0, fa0, rtz
 ; RV64IF-NEXT:slli a0, a0, 32
 ; RV64IF-NEXT:srli a0, a0, 32
 ; RV64IF-NEXT:ret
@@ -42,8 +39,7 @@
 define i32 @aext_fptoui(float %a) nounwind {
 ; RV64IF-LABEL: aext_fptoui:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a0
-; RV64IF-NEXT:fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT:fcvt.wu.s a0, fa0, rtz
 ; RV64IF-NEXT:ret
   %1 = fptoui float %a to i32
   ret i32 %1
@@ -52,8 +48,7 @@
 define signext i32 @sext_fptoui(float %a) nounwind {
 ; RV64IF-LABEL: sext_fptoui:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a0
-; RV64IF-NEXT:fcvt.wu.s a0, ft0, rtz
+; RV64IF-NEXT:fcvt.wu.s a0, fa0, rtz
 ; RV64IF-NEXT:ret
   %1 = fptoui float %a to i32
   ret i32 %1
@@ -62,8 +57,7 @@
 define zeroext i32 @zext_fptoui(float %a) nounwind {
 ; RV64IF-LABEL: zext_fptoui:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a0
-; RV64IF-NEXT:fcvt.lu.s a0, ft0, rtz
+; RV64IF-NEXT:fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:ret
   %1 = fptoui float %a to i32
   ret i32 %1
@@ -72,9 +66,7 @@
 define i32 @bcvt_f32_to_aext_i32(float %a, float %b) nounwind {
 ; RV64IF-LABEL: bcvt_f32_to_aext_i32:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a1
-; RV64IF-NEXT:fmv.w.x ft1, a0
-; RV64IF-NEXT:fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:fadd.s ft0, fa0, fa1
 ; RV64IF-NEXT:fmv.x.w a0, ft0
 ; RV64IF-NEXT:ret
   %1 = fadd float %a, %b
@@ -85,9 +77,7 @@
 define signext i32 @bcvt_f32_to_sext_i32(float %a, float %b) nounwind {
 ; RV64IF-LABEL: bcvt_f32_to_sext_i32:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a1
-; RV64IF-NEXT:fmv.w.x ft1, a0
-; RV64IF-NEXT:fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:fadd.s ft0, fa0, fa1
 ; RV64IF-NEXT:fmv.x.w a0, ft0
 ; RV64IF-NEXT:ret
   %1 = fadd float %a, %b
@@ -98,9 +88,7 @@
 define zeroext i32 @bcvt_f32_to_zext_i32(float %a, float %b) nounwind {
 ; RV64IF-LABEL: bcvt_f32_to_zext_i32:
 ; RV64IF:   # %bb.0:
-; RV64IF-NEXT:fmv.w.x ft0, a1
-; RV64IF-NEXT:fmv

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D125765#3524456 , @khchen wrote:

> I think we have no consensus in 
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/18#issuecomment-817890161,
>  and most people disagree the current naming,
> maybe we need to have more followup discussion before landing this patch.

Thanks for your reminding of previous discussion!
Should we put this in next sync-up discussion agenda and settle it down? There 
are already some large code bases based GCC implementation, we should make it 
stable before it becomes too hard to change.

> For example, maybe `_Float16` should be supported when enable zvh, not zvfh?

You mean `zfh`? `float16_t` is only used in RVV intrinsics, so I think it is OK 
to me. And it is the same as generated type aliases in riscv_vector.h(at about 
line 130):

  #if defined(__riscv_zvfh)
  typedef __rvv_float16mf4_t vfloat16mf4_t;
  typedef __rvv_float16mf2_t vfloat16mf2_t;
  typedef __rvv_float16m1_t vfloat16m1_t;
  typedef __rvv_float16m2_t vfloat16m2_t;
  typedef __rvv_float16m4_t vfloat16m4_t;
  typedef __rvv_float16m8_t vfloat16m8_t;
  #endif


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[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D125947#3525537 , @jrtc27 wrote:

> It's currently this way in order to be compatible with GCC. Changing this 
> requires consensus from both toolchains to ensure compatibility is preserved. 
> See https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13 
> for some discussion on this.

Thanks! I may send a GCC patch later.


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[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D125947#3525539 , @jrtc27 wrote:

> Also, the tests where you have codegen changes rather than preserving a 
> soft-float ABI should probably be put up for review separately by adding an 
> explicit hard single-float ABI, as those seem worthwhile for reducing noise

Will do.


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 431654.
pcwang-thead added a comment.

- Rebase.
- move tests to `test/CodeGen/RISCV/rvv-intrinsics`.
- Update functions' attrs.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1497,6 +1497,56 @@
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vread_csr(enum RVV_CSR __csr) {
+  unsigned long __rv = 0;
+  switch (__csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXSAT:
+  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXRM:
+  __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VCSR:
+  __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
+  break;
+  }
+  return __rv;
+}
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
+  switch (__csr) {
+case RVV_VSTART:
+ 

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

@asb @kito-cheng @jrtc27 @craig.topper 
Can I commit this since the support of RVE is really of great importance for 
some downstreams? If there are some problems, I will be there to fix them.
If we all agree with this, I will mark RVE as exprimental and commit it then.


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[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead marked an inline comment as done.
pcwang-thead added a comment.

In D70401#3873347 , @luojia wrote:

> Hello! Any further updates to this patch? It seems like all the inline 
> comments have been resolved.

We have done some works in this patch to make it compatible with GCC, it can be 
combined with GNU toolchain now.

But as what have been discussed[1, 2], we may proceed with this patch when 
RV32E/ilp32e is ratified.

1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257


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[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead created this revision.
pcwang-thead added reviewers: kito-cheng, craig.topper, asb.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, 
arichardson.
Herald added a project: All.
pcwang-thead requested review of this revision.
Herald added subscribers: cfe-commits, eopXD, MaskRay.
Herald added a project: clang.

We may need hosted Clang/LLVM to compile.

I don't know how to test it, but all that this patch rely on
is `getHostCpuName`, so pacthes like D123978  
may have covered it?


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Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Clang.cpp


Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2187,7 +2187,10 @@
 
   if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) {
 CmdArgs.push_back("-tune-cpu");
-CmdArgs.push_back(A->getValue());
+if (strcmp(A->getValue(), "native") == 0)
+  CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUName()));
+else
+  CmdArgs.push_back(A->getValue());
   }
 }
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Optional.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/Error.h"
+#include "llvm/Support/Host.h"
 #include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
@@ -70,8 +71,12 @@
 
   // If users give march and mcpu, get std extension feature from MArch
   // and other features (ex. mirco architecture feature) from mcpu
-  if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
-getRISCFeaturesFromMcpu(D, Triple, Args, A, A->getValue(), Features);
+  if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
+StringRef CPU = A->getValue();
+if (CPU == "native")
+  CPU = llvm::sys::getHostCPUName();
+getRISCFeaturesFromMcpu(D, Triple, Args, A, CPU, Features);
+  }
 
   // Handle features corresponding to "-ffixed-X" options
   if (Args.hasArg(options::OPT_ffixed_x1))
@@ -260,7 +265,10 @@
 
   // 2. Get march (isa string) based on `-mcpu=`
   if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
-StringRef MArch = llvm::RISCV::getMArchFromMcpu(A->getValue());
+StringRef CPU = A->getValue();
+if (CPU == "native")
+  CPU = llvm::sys::getHostCPUName();
+StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
 // Bypass if target cpu's default march is empty.
 if (MArch != "")
   return MArch;


Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2187,7 +2187,10 @@
 
   if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) {
 CmdArgs.push_back("-tune-cpu");
-CmdArgs.push_back(A->getValue());
+if (strcmp(A->getValue(), "native") == 0)
+  CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUName()));
+else
+  CmdArgs.push_back(A->getValue());
   }
 }
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Optional.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/Error.h"
+#include "llvm/Support/Host.h"
 #include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
@@ -70,8 +71,12 @@
 
   // If users give march and mcpu, get std extension feature from MArch
   // and other features (ex. mirco architecture feature) from mcpu
-  if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
-getRISCFeaturesFromMcpu(D, Triple, Args, A, A->getValue(), Features);
+  if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
+StringRef CPU = A->getValue();
+if (CPU == "native")
+  CPU = llvm::sys::getHostCPUName();
+getRISCFeaturesFromMcpu(D, Triple, Args, A, CPU, Features);
+  }
 
   // Handle features corresponding to "-ffixed-X" options
   if (Args.hasArg(options::OPT_ffixed_x1))
@@ -260,7 +265,10 @@
 
   // 2. Get march (isa string) based on `-mcpu=`
   if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
-StringRef MArch = llvm::RISCV::getMArchFromMcpu(A->getValue());
+StringRef CPU = A->getValue();
+if (CPU == "native")
+  

[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2190
 CmdArgs.push_back("-tune-cpu");
-CmdArgs.push_back(A->getValue());
+if (strcmp(A->getValue(), "native") == 0)
+  CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUName()));

craig.topper wrote:
> Why can't we use A->getValue() == "native" here?
Because newly-changed support of other targets (like PowerPC) are in this form, 
so I think this may benefit from simplification?


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[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 472228.
pcwang-thead added a comment.

- Add release note.
- Add tests to `riscv-cpus.c`.
- Add `getRISCVTargetCPU`.
- Make diagnostic more exact for `native`.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/riscv-cpus.c

Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -7,6 +7,10 @@
 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
 // MCPU-ROCKET64: "-target-feature" "+64bit"
 
+// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=native | FileCheck -check-prefix=MCPU-NATIVE %s
+// MCPU-NATIVE-NOT: "-target-cpu" "native"
+
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
 // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"
 
@@ -26,6 +30,10 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s
 // MTUNE-ROCKET-64: "-tune-cpu" "rocket"
 
+// We cannot check much for -mtune=native, but it should be replaced by a valid CPU string.
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=native | FileCheck -check-prefix=MTUNE-NATIVE %s
+// MTUNE-NATIVE-NOT: "-tune-cpu" "native"
+
 // mcpu with default march
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s
 // MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20"
@@ -130,10 +138,10 @@
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
-// FAIL-MCPU-NAME: error: the clang compiler does not support '-mcpu=generic-rv321'
+// FAIL-MCPU-NAME: error: unsupported argument 'generic-rv321' to option '-mcpu='
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
-// MISMATCH-ARCH: error: the clang compiler does not support '-mcpu=generic-rv32'
+// MISMATCH-ARCH: error: unsupported argument 'generic-rv32' to option '-mcpu='
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv64 | FileCheck -check-prefix=MISMATCH-MCPU %s
-// MISMATCH-MCPU: error: the clang compiler does not support '-mcpu=generic-rv64'
+// MISMATCH-MCPU: error: unsupported argument 'generic-rv64' to option '-mcpu='
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -12,6 +12,7 @@
 #include "Arch/M68k.h"
 #include "Arch/Mips.h"
 #include "Arch/PPC.h"
+#include "Arch/RISCV.h"
 #include "Arch/Sparc.h"
 #include "Arch/SystemZ.h"
 #include "Arch/VE.h"
@@ -432,9 +433,7 @@
   return "ck810";
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
-if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
-  return A->getValue();
-return "";
+return riscv::getRISCVTargetCPU(Args, T);
 
   case llvm::Triple::bpfel:
   case llvm::Triple::bpfeb:
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2187,7 +2187,10 @@
 
   if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) {
 CmdArgs.push_back("-tune-cpu");
-CmdArgs.push_back(A->getValue());
+if (strcmp(A->getValue(), "native") == 0)
+  CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUName()));
+else
+  CmdArgs.push_back(A->getValue());
   }
 }
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.h
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.h
+++ clang/lib/Driver/ToolChains/Arch/RISCV.h
@@ -26,6 +26,8 @@
   const llvm::Triple &Triple);
 StringRef getRISCVArch(const llvm::opt::ArgList &Args,
const llvm::Triple &Triple);
+std::string getRISCVTargetCPU(const llvm::opt::ArgList &Args,
+  const llvm::Triple &Triple);
 } // end namespace riscv
 } // namespace tools
 } // end namespace driver
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Optional.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/Error.h"
+#include "l

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead marked an inline comment as done.
pcwang-thead added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411
 // implemented such that the stack will always be 16 byte aligned.
 unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
 RVFI->setLibCallStackSize(LibCallFrameSize);

zixuan-wu wrote:
> I think this 16 should be adjusted as above logic for rv32e
Thanks. :-)


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D112921#4003939 , 
@Romain-Geissler-1A wrote:

> Hi,
>
> Is there any update about this ?

Currently, no.
If someone is interesting in this, please feel free to commandeer. :-)


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[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D137517#4009175 , @fpetrogalli 
wrote:

> @pcwang-thead, I addressed some of your comments.
>
> The value of `EnumFeatures` is now computed dynamicaly from the
> `Features` field of the `Processor` class.

Thanks! That sounds great to me!

> As for generating `MArch` out of the `Features` field, @craig.topper
> pointed me at
> https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11. From
> the reading of it, it seems that the alphabetical order is enough to
> build the string that carries `MArch`. Am I missing something?

Currently, I think the alphabetical order is OK. If we relax the checking of 
arch string someday, there is no doubt that we should change the implementation 
here too.


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[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D137517#4012307 , @craig.topper 
wrote:

> In D137517#4012298 , @pcwang-thead 
> wrote:
>
>> In D137517#4009175 , @fpetrogalli 
>> wrote:
>>
>>> @pcwang-thead, I addressed some of your comments.
>>>
>>> The value of `EnumFeatures` is now computed dynamicaly from the
>>> `Features` field of the `Processor` class.
>>
>> Thanks! That sounds great to me!
>>
>>> As for generating `MArch` out of the `Features` field, @craig.topper
>>> pointed me at
>>> https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11. From
>>> the reading of it, it seems that the alphabetical order is enough to
>>> build the string that carries `MArch`. Am I missing something?
>>
>> Currently, I think the alphabetical order is OK. If we relax the checking of 
>> arch string someday, there is no doubt that we should change the 
>> implementation here too.
>
> The currently accepted order isn’t alphabetical. The single letter extensions 
> have a specific order. The z extensions are ordered by looking up the second 
> letter in the single letter order. If we alphabetize here i don’t think it 
> will be accepted by the frontend.

Oops, my mistake.

Here is my PoC to generate march from Features:

  diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
  index d1d0356179f5..b2520f25bfea 100644
  --- a/llvm/lib/Target/RISCV/RISCV.td
  +++ b/llvm/lib/Target/RISCV/RISCV.td
  @@ -556,8 +556,8 @@ include "RISCVSchedSyntacoreSCR1.td"
   class RISCVProcessorModelPROC f,
  -  string default_march = "",
  -  list tunef = []> :  
ProcessorModel {
  +  list tunef = [],
  +  string default_march = ""> :  
ProcessorModel {
 string DefaultMarch = default_march;
   }
  diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp 
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  index b216e82cef6c..eea31e6ddea8 100644
  --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  @@ -13,17 +13,33 @@
   
   #include "TableGenBackends.h"
   #include "llvm/TableGen/Record.h"
  +#include "llvm/Support/RISCVISAInfo.h"
   
   using namespace llvm;
   
  -static std::string getEnumFeatures(const Record &Rec) {
  +static int getXLen(const Record &Rec) {
 std::vector Features = Rec.getValueAsListOfDefs("Features");
 if (find_if(Features, [](const Record *R) {
   return R->getName() == "Feature64Bit";
 }) != Features.end())
  -return "FK_64BIT";
  +return 64;
   
  -  return "FK_NONE";
  +  return 32;
  +}
  +
  +static std::string getMArch(int XLen, const Record &Rec) {
  +  std::vector Features = Rec.getValueAsListOfDefs("Features");
  +  std::vector FeatureVector;
  +  // Convert Features to FeatureVector.
  +  for (auto *Feature : Features) {
  +StringRef FeatureName = Feature->getValueAsString("Name");
  +if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
  +  FeatureVector.push_back(std::string("+") + FeatureName.str());
  +  }
  +  auto ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
  +  if (!ISAInfo)
  +report_fatal_error("Invalid features: ");
  +  return (*ISAInfo)->toString();
   }
   
   void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
  @@ -39,11 +55,17 @@ void llvm::EmitRISCVTargetDef(const RecordKeeper &RK, 
raw_ostream &OS) {
 // Iterate on all definition records.
 for (const MapTy &Def : Map) {
   const Record &Rec = *(Def.second);
  -if (Rec.isSubClassOf("RISCVProcessorModelPROC"))
  +if (Rec.isSubClassOf("RISCVProcessorModelPROC")) {
  +  int XLen = getXLen(Rec);
  +  std::string EnumFeatures = XLen == 64 ? "FK_64BIT" : "FK_NONE";
  +  std::string MArch = Rec.getValueAsString("DefaultMarch").str();
  +  if (MArch == "")
  +MArch = getMArch(XLen, Rec);
 OS << "PROC(" << Rec.getName() << ", "
  - << "{\"" << Rec.getValueAsString("Name") << "\"},"
  - << getEnumFeatures(Rec) << ", "
  - << "{\"" << Rec.getValueAsString("DefaultMarch") << "\"})\n";
  + << "{\"" << Rec.getValueAsString("Name") << "\"}," << EnumFeatures
  + << ", "
  + << "{\"" << MArch << "\"})\n";
  +}
 }
 OS << "\n#undef PROC\n";
 OS << "\n";

The generated file would be like below (the march strings are tedious but I 
think that would be OK):

  #ifndef PROC
  #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
  #endif
  
  PROC(INVALID, {"invalid"}, FK_INVALID, {""})
  PROC(GENERIC_RV32, {"generic-rv32"},FK_NONE, {"rv32i2p0"})
  PROC(GENERIC_RV64, {"generic-rv64"},FK_64BIT, {"rv64i2p0"})
  PROC(ROCKET_RV32, {"rocket-rv32"},FK_NONE, {"rv32i2p0"})
  PROC(ROCKET_RV64, {"rocket-rv64"},FK_64BIT, {"rv64i2p0"})
  PROC(SI

[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

> @pcwang-thead, may I ask you to own these further optimisations of the 
> generative process, and submit a patch for it after the current patch lands? 
> I'd happily review it!
>
> The reason I am asking this is because the current patch is mostly dealing 
> with making sure we can build clang/llvm after removing the def file.  People 
> are discussing dependencies and modules (for example, last update I did was 
> to make the patch work for modules with `-DLLVM_ENABLE_MODULES=On`), and this 
> is already taking quite a number of comments.
> There is value in the discussion on how to build march out of the features, 
> I'd rather keep it in a separate submission so that the threads do not get 
> lost among the other comments for this patch.
>
> Francesco

Yes, I am happy to do it. :-)


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[PATCH] D137838: [Support] Move TargetParsers to new component

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:10
+/// \file
+/// This header is deprecated in favour of `llvm/Support/RISCVISAInfo.h`.
+///

zixuan-wu wrote:
> I think there is a typo that should be 'in favour of 
> `llvm/TargetParser/RISCVISAInfo.h` '
I may move `RISCVISAInfo` back to `Support` and fix this in D140529.


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[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:568
 
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROCRISCVProcessorModel?
RISCVProcessorModelTUNE_PROC->RISCVTuneProcessorModel?
I think it is a little weird that we mixed naming styles here.





Comment at: llvm/lib/Target/RISCV/RISCV.td:576
+
+class RISCVProcessorModelTUNE_PROC f,
+  list tunef = []> : 
ProcessorModel;

As for ProcessorModels for tuning, `list f` is always empty 
in both upstream and our downstream, and it is unlikely that we will specify 
target features for tune models. So it can be a default argument with value 
`[]` and swap the position of `f` and `tunef`(we are more likely to specify 
tune features). It becomes:
```
class RISCVTuneProcessorModel tunef = [],
list f = []> : ProcessorModel;
```
@craig.topper Any thoughts on this?


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[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1559
   __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
   break;
   }

Should we report errors if `vwrite_csr(RVV_VLENB, some_value)`?


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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1565
+  unsigned long __rv = 0;
+  __asm__ __volatile__ ("csrr\t%0, vlenb" : "=r"(__rv) : : "memory");
+  return __rv;

Inline assembly may not be elegant since it can't be optimized in many ways. We 
can eliminate some redundant reads of vlenb currently(done in D125564). So I 
think we may add a builtin function and lower it to `llvm.read_register`?


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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead accepted this revision.
pcwang-thead added a comment.
This revision is now accepted and ready to land.

The code is OK to me, except that a few small comments.




Comment at: clang/include/clang/Basic/riscv_vector.td:1579
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+  return Builder.CreateCall(F, Metadata);

The value type of `read_register` is `i32` in 
`llvm/test/CodeGen/RISCV/vlenb.ll`, but I don't insist on it.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c:1
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target

Add `--check-globals` or `--global-value-regex` to check if the metadata is 
`vlenb` exactly?


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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:1579
+  llvm::Function *F =
+CGM.getIntrinsic(llvm::Intrinsic::read_register, {Int64Ty});
+  return Builder.CreateCall(F, Metadata);

craig.topper wrote:
> pcwang-thead wrote:
> > The value type of `read_register` is `i32` in 
> > `llvm/test/CodeGen/RISCV/vlenb.ll`, but I don't insist on it.
> Doesn't this need to match the size of long?
So what about `i32` for rv32 and `i64` for rv64?


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[PATCH] D141032: [Clang][RISCV] Expose vlenb to user

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics/vlenb.c:33
+// RV32: !2 = !{i32 1, !"SmallDataLimit", i32 0}
+// RV32: !3 = !{!"clang version 16.0.0 (g...@github.com:llvm/llvm-project.git 
e80f0cc0a318fe8473ba460d6a16166d81b303b1)"}
+// RV32: !4 = !{!"vlenb"}

Hmm, why would we emit version info here? I think we should avoid this.
I find a clang option `-Qn` that can disable emitting this by setting 
`EmitVersionIdentMetadata` to `false`.


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[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Thanks! I think it's a great improvement!




Comment at: llvm/lib/Target/RISCV/RISCV.td:509
 
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROC {
+  string Enum = enum;

Can `EnumFeatures/DefaultMarch` string be inferred from ProcessorModel's 
SubtargetFeature if not specified and `Enum` just be the uppercase of the name 
of ProcessorModel? The implementation could be more complicated but I think 
it's worthy.


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[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Thanks!


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[PATCH] D136930: [RISCV] Support -mcpu/mtune=native

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7c50bcb44170: [RISCV] Support -mcpu/mtune=native (authored 
by pcwang-thead).

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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/riscv-cpus.c

Index: clang/test/Driver/riscv-cpus.c
===
--- clang/test/Driver/riscv-cpus.c
+++ clang/test/Driver/riscv-cpus.c
@@ -7,6 +7,10 @@
 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
 // MCPU-ROCKET64: "-target-feature" "+64bit"
 
+// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=native | FileCheck -check-prefix=MCPU-NATIVE %s
+// MCPU-NATIVE-NOT: "-target-cpu" "native"
+
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s
 // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32"
 
@@ -26,6 +30,10 @@
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s
 // MTUNE-ROCKET-64: "-tune-cpu" "rocket"
 
+// We cannot check much for -mtune=native, but it should be replaced by a valid CPU string.
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=native | FileCheck -check-prefix=MTUNE-NATIVE %s
+// MTUNE-NATIVE-NOT: "-tune-cpu" "native"
+
 // mcpu with default march
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s
 // MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20"
@@ -130,10 +138,10 @@
 // Check failed cases
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
-// FAIL-MCPU-NAME: error: the clang compiler does not support '-mcpu=generic-rv321'
+// FAIL-MCPU-NAME: error: unsupported argument 'generic-rv321' to option '-mcpu='
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
-// MISMATCH-ARCH: error: the clang compiler does not support '-mcpu=generic-rv32'
+// MISMATCH-ARCH: error: unsupported argument 'generic-rv32' to option '-mcpu='
 
 // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv64 | FileCheck -check-prefix=MISMATCH-MCPU %s
-// MISMATCH-MCPU: error: the clang compiler does not support '-mcpu=generic-rv64'
+// MISMATCH-MCPU: error: unsupported argument 'generic-rv64' to option '-mcpu='
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -12,6 +12,7 @@
 #include "Arch/M68k.h"
 #include "Arch/Mips.h"
 #include "Arch/PPC.h"
+#include "Arch/RISCV.h"
 #include "Arch/Sparc.h"
 #include "Arch/SystemZ.h"
 #include "Arch/VE.h"
@@ -432,9 +433,7 @@
   return "ck810";
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64:
-if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
-  return A->getValue();
-return "";
+return riscv::getRISCVTargetCPU(Args, T);
 
   case llvm::Triple::bpfel:
   case llvm::Triple::bpfeb:
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -2187,7 +2187,10 @@
 
   if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) {
 CmdArgs.push_back("-tune-cpu");
-CmdArgs.push_back(A->getValue());
+if (strcmp(A->getValue(), "native") == 0)
+  CmdArgs.push_back(Args.MakeArgString(llvm::sys::getHostCPUName()));
+else
+  CmdArgs.push_back(A->getValue());
   }
 }
 
Index: clang/lib/Driver/ToolChains/Arch/RISCV.h
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.h
+++ clang/lib/Driver/ToolChains/Arch/RISCV.h
@@ -26,6 +26,8 @@
   const llvm::Triple &Triple);
 StringRef getRISCVArch(const llvm::opt::ArgList &Args,
const llvm::Triple &Triple);
+std::string getRISCVTargetCPU(const llvm::opt::ArgList &Args,
+  const llvm::Triple &Triple);
 } // end namespace riscv
 } // namespace tools
 } // end namespace driver
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -16,6 +16,7 @@
 #include "llvm/ADT/Optional.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/Error.h"
+#include "llvm/Support/Host.h"
 #include "ll

[PATCH] D137517: [TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

A rough implementation just for your reference:

  diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp 
b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  index 47e11b9a1eab..f91f969c2b17 100644
  --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
  @@ -14,6 +14,32 @@
   #include "llvm/TableGen/Record.h"
   
   namespace llvm {
  +struct CPUInfo {
  +  std::string EnumName;
  +  std::string MArch;
  +  std::string Features;
  +};
  +
  +static CPUInfo getCPUInfoFromFeatures(const Record &Record) {
  +  std::string EnumName = Record.getValueAsString("Name").upper();
  +  EnumName = EnumName.replace(EnumName.find_first_of('-'), 1, "_");
  +  std::string MArch;
  +  // FIXME: MArch should be in alphabetical order.
  +  std::string Features;
  +  for (auto *Feature : Record.getValueAsListOfDefs("Features")) {
  +StringRef FeatureName = Feature->getValueAsString("Name");
  +if (FeatureName == "32bit") {
  +  MArch += "rv32i";
  +  Features = "FK_NONE";
  +} else if (FeatureName == "64bit") {
  +  MArch += "rv64i";
  +  Features = "FK_64BIT";
  +} else
  +  MArch += FeatureName;
  +  }
  +  return {EnumName, MArch, Features};
  +}
  +
   void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
 const auto &Map = RK.getDefs();
   
  @@ -26,11 +52,17 @@ void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream 
&OS) {
 for (auto &Def : Map) {
   const auto &Record = Def.second;
   if (Record->isSubClassOf("RISCVProcessorModelPROC") &&
  -Record->isSubClassOf("ProcessorModel"))
  +Record->isSubClassOf("ProcessorModel")) {
 OS << "PROC(" << Record->getValueAsString("Enum") << ", "
<< "{\"" << Record->getValueAsString("Name") << "\"}, "
<< Record->getValueAsString("EnumFeatures") << ", "
<< "{\"" << Record->getValueAsString("DefaultMarch") << "\"})\n";
  +  const CPUInfo &Info = getCPUInfoFromFeatures(*Record);
  +  OS << "// PROC(" << Info.EnumName << ", "
  + << "{\"" << Record->getValueAsString("Name") << "\"}, "
  + << Info.Features << ", "
  + << "{\"" << Info.MArch << "\"})\n";
  +}
 }
 OS << "\n#undef PROC\n";
 OS << "\n";

The generated header would be like:

  #ifndef PROC
  #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
  #endif
  
  PROC(INVALID, {"invalid"}, FK_INVALID, {""})
  PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
  // PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {"rv32i"})
  PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
  // PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {"rv64i"})
  PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
  // PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {"rv32i"})
  PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
  // PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {"rv64i"})
  PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
  // PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
  PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
  // PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
  PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
  // PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
  PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
  // PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
  PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"})
  // PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"})
  PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
  // PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
  PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"})
  // PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"})
  PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
  // PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
  PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
  // PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64imafdc"})
  PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
  // PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64imafdc"})
  PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
  // PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64imafdc"})
  PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
  // PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64imafdc"})
  
  #undef PROC
  
  #ifndef TUNE_PROC
  #define TUNE_PROC(ENUM, NAME)
  #endif
  
  TUNE_PROC(GENERIC, "generic")
  TUNE_PROC(ROCKET, "rocket")
  TUNE_PROC(SIFIVE_7, "sifive-7-series")
  
  #undef TUNE_PROC

---

> My preference would be to keep the Enum explicit as it would help using those 
> enums in the code. Also, sometimes the enum cannot be derived from the Name 
> (see for example "sifive-7-series" vs "SIFIVE_7").

I believe that we can change it to "SIFIVE-7-SERIES" since this enum name 
haven't been used in anywhere and it's just an enum name. :-)


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

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pcwang-thead added a comment.

Ping.


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGaebe24a856d2: [RISCV] Add vread_csr and vwrite_csr to 
riscv_vector.h (authored by pcwang-thead).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125875/new/

https://reviews.llvm.org/D125875

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1497,6 +1497,56 @@
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vread_csr(enum RVV_CSR __csr) {
+  unsigned long __rv = 0;
+  switch (__csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXSAT:
+  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXRM:
+  __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VCSR:
+  __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
+  break;
+  }
+  return __rv;
+}
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
+  switch (__csr) {
+case 

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 436344.
pcwang-thead added a comment.

Add `REQUIRES` to tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125875/new/

https://reviews.llvm.org/D125875

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1497,6 +1497,56 @@
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vread_csr(enum RVV_CSR __csr) {
+  unsigned long __rv = 0;
+  switch (__csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXSAT:
+  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXRM:
+  __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VCSR:
+  __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
+  break;
+  }
+  return __rv;
+}
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
+  switch (__csr) {
+case RVV_VST

[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG93b4a41b5510: [RISCV] Add vread_csr and vwrite_csr to 
riscv_vector.h (authored by pcwang-thead).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125875/new/

https://reviews.llvm.org/D125875

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vwrite_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vstart(unsigned long value) {
+  vwrite_csr(RVV_VSTART, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxsat(unsigned long value) {
+  vwrite_csr(RVV_VXSAT, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vxrm(unsigned long value) {
+  vwrite_csr(RVV_VXRM, value);
+}
+
+// CHECK-LABEL: @vwrite_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret void
+//
+void vwrite_csr_vcsr(unsigned long value) {
+  vwrite_csr(RVV_VCSR, value);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
@@ -0,0 +1,42 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
+// RUN: | opt -S -O2 | FileCheck  %s
+
+#include 
+
+// CHECK-LABEL: @vread_csr_vstart(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vstart(void) {
+  return vread_csr(RVV_VSTART);
+}
+
+// CHECK-LABEL: @vread_csr_vxsat(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxsat(void) {
+  return vread_csr(RVV_VXSAT);
+}
+
+// CHECK-LABEL: @vread_csr_vxrm(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vxrm(void) {
+  return vread_csr(RVV_VXRM);
+}
+
+// CHECK-LABEL: @vread_csr_vcsr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+unsigned long vread_csr_vcsr(void) {
+  return vread_csr(RVV_VCSR);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1497,6 +1497,56 @@
   }
 }
 
+// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
+let HeaderCode =
+[{
+enum RVV_CSR {
+  RVV_VSTART = 0,
+  RVV_VXSAT,
+  RVV_VXRM,
+  RVV_VCSR,
+};
+
+static __inline__ __attribute__((__always_inline__, __nodebug__))
+unsigned long vread_csr(enum RVV_CSR __csr) {
+  unsigned long __rv = 0;
+  switch (__csr) {
+case RVV_VSTART:
+  __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXSAT:
+  __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VXRM:
+  __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
+  break;
+case RVV_VCSR:
+  __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
+  break;
+  }
+  return __rv;
+}
+
+static __inline__ __attrib

[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Ping. Any comments?


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D126461#3596769 , @khchen wrote:

> Could you please purpose this implement in rvv-intrinsc-doc first?
> I think this feature need to have discussion because store to nullptr is UB 
> but we are making it as defined behavior only for these intrinsics.
> Personally I like they have consistent behavior and in document side we just 
> make a note for users that vl should not be a null pointer.

https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/153


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D126461#3597862 , @craig.topper 
wrote:

> In D126461#3596761 , @reames wrote:
>
>> Despite the comments above, the purpose of this patch remains unclear.
>>
>> Per the draft spec, the relevant wording is:
>> "These instructions execute as a regular load except that they will only 
>> take a trap caused by a synchronous exception
>> on element 0. If element 0 raises an exception, vl is not modied, and the 
>> trap is taken. If an element > 0 raises an
>> exception, the corresponding trap is not taken, and the vector length vl is 
>> reduced to the index of the element that would
>> have raised an exception."
>>
>> Working through the scenario in this patch with the destination being null, 
>> the expected result is for a trap to be generated (provided null is unmapped 
>> of course), and VL not to be modified.  In order for this change to make any 
>> difference in runtime behavior, the value passed must be null (or otherwise 
>> guaranteed to fault).  It seems very odd to me that we are modifying code 
>> which only runs after an instruction which is guaranteed to fault.  Is there 
>> an assumed runtime here which is e.g. restarting execution?
>
> `dst` in the patch description is not the pointer being loaded, it's the 
> pointer of where to store the new_vl. That is only thing being checked for 
> null in this patch.

Thanks for your kind explanation! @craig.topper
I did this change just because previous GCC implementation have done null 
pointer checking. Some of our codebases crashed when we switched to LLVM 
because new_vl is set to NULL to ignore output new vl. : ) @reames


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff new_vl output pointer isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead abandoned this revision.
pcwang-thead added a comment.

After discussion, we decide to not change anything right now.


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead created this revision.
pcwang-thead added reviewers: khchen, kito-cheng, craig.topper, asb.
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Store to null will be changed to unreachable, so all instructions
after vleff intrinsic call will be deleted and it causes runtime
errors. If destination to store is null, we won't extract and store
the new vl.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
@@ -6,6 +6,17 @@
 
 #include 
 
+// CHECK-RV64-LABEL: @test_vleff_save_new_vl_to_nullptr(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call { , i64 } 
@llvm.riscv.vleff.nxv1i8.i64( undef, * 
[[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { , i64 } 
[[TMP1]], 0
+// CHECK-RV64-NEXT:ret  [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_nullptr (const int8_t *base, size_t vl) {
+  return vle8ff_v_i8mf8(base, NULL, vl);
+}
+
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -643,10 +643,12 @@
 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
 llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
 // Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+if (!isa(NewVL)) {
+  clang::CharUnits Align =
+  CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
+  llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
+  Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+}
 return V;
   }
   }],
@@ -663,10 +665,12 @@
 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
 llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
 // Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(3)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+if (!isa(NewVL)) {
+  clang::CharUnits Align =
+  CGM.getNaturalPointeeTypeAlignment(E->getArg(3)->getType());
+  llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
+  Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
+}
 return V;
   }
   }] in {


Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
@@ -6,6 +6,17 @@
 
 #include 
 
+// CHECK-RV64-LABEL: @test_vleff_save_new_vl_to_nullptr(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv1i8.i64( undef, * [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { , i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT:ret  [[TMP2]]
+//
+vint8mf8_t test_vleff_save_new_vl_to_nullptr (const int8_t *base, size_t vl) {
+  return vle8ff_v_i8mf8(base, NULL, vl);
+}
+
 // CHECK-RV64-LABEL: @test_vle8ff_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:[[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to *
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -643,10 +643,12 @@
 llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
 llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
 // Store new_vl.
-   

[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D126461#3541577 , @craig.topper 
wrote:

> What if it isn't known to be null at compile time but gets optimized to it.

Thanks, I haven't thought it clearly and I just wanted to solve found bugs. :-)
I changed it to generate IRs to do the check. It is the same as GCC 
implementation now I think.
https://github.com/riscv-collab/riscv-gcc/blob/riscv-gcc-10.1-rvv-dev/gcc/config/riscv/riscv_vector.h#L289

  if (new_vl)   \
  { \
  if (__riscv_xlen == 32)   \
*new_vl = __builtin_riscv_vreadvlsi (); \
  else  \
*new_vl = __builtin_riscv_vreadvldi (); \
  } 



> Are we trying to make passing a null pointer defined behavior for these 
> intrinsics?

Yes, but only for vleff instructions, since it has two outputs actually. And 
this behavior is compatible with GCC.
If necessary, I will propose it to rvv-intrinsic-doc.


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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Is there an easy way to update tests? Or we need to add passthru operands 
manually? I will appreciate it if you can tell me. :-)


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[PATCH] D125323: [RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D125323#3550307 , @khchen wrote:

> In D125323#3549794 , @pcwang-thead 
> wrote:
>
>> Is there an easy way to update tests? Or we need to add passthru operands 
>> manually? I will appreciate it if you can tell me. :-)
>
> use sed to do replacement.
> ex.
>
>   #!/bin/bash
>   set -x
>   
>   for var in "$@"
>   do
> sed -i 's/declare {\([^,]\+\),[^,]\+} \(.*\)(\([0-9a-z*]\+\)/declare 
> {\1,\1} \2(\1,\1, \3/g' $var
> sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1} \2(\1,\1,\1, \3/g' $var
> sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1} \2(\1,\1,\1,\1, \3/g' $var
> sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1} \2(\1,\1,\1,\1,\1, \3/g' $var
> sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1,\1} \2(\1,\1,\1,\1,\1,\1, 
> \3/g' $var
> sed -i 's/declare {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1,\1,\1} 
> \2(\1,\1,\1,\1,\1,\1,\1, \3/g' $var
> sed -i 's/declare 
> {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/declare {\1,\1,\1,\1,\1,\1,\1,\1} 
> \2(\1,\1,\1,\1,\1,\1,\1,\1, \3/g' $var
> sed -i 's/call {\([^,]\+\),[^,]\+} \(.*\)(\([0-9a-z*]\+\)/call {\1,\1} 
> \2(\1 undef, \1 undef, \3/g' $var
> sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+} \(.*\)(\([0-9a-z*]\+\)/call 
> {\1,\1,\1} \2(\1 undef, \1 undef, \1 undef, \3/g' $var
> sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 undef, \1 
> undef, \3/g' $var
> sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 undef, 
> \1 undef, \1 undef, \3/g' $var
> sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 
> undef, \1 undef, \1 undef, \1 undef, \3/g' $var
> sed -i 's/call {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1,\1,\1} \2(\1 undef, \1 undef, \1 
> undef, \1 undef, \1 undef, \1 undef, \1 undef, \3/g' $var
> sed -i 's/call 
> {\([^,]\+\),[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+,[^,]\+} 
> \(.*\)(\([0-9a-z*]\+\)/call {\1,\1,\1,\1,\1,\1,\1,\1} \2(\1 undef, \1 undef 
> ,\1 undef ,\1 undef, \1 undef ,\1 undef, \1 undef, \1 undef, \
>   3/g' $var
>   done

Thanks!


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[PATCH] D125875: [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Gentle ping.


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

Ping. :-)


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D126461#3565305 , @khchen wrote:

>> Store to null will be changed to unreachable, so all instructions after 
>> vleff intrinsic call will be deleted and it causes runtime errors. If 
>> destination to store is null, we won't extract and store the new vl.
>
>
>
>> Yes, but only for vleff instructions, since it has two outputs actually. And 
>> this behavior is compatible with GCC. If necessary, I will propose it to 
>> rvv-intrinsic-doc.
>
> Compiling with -O0, I didn't see this behavior, so are you trying to make the 
> optimized code behavior is compatible with GCC?
> In addition, it seems this behavior also exist in scalar code, do we also 
> need to make the scalar result is compatible with GCC?

Store to nullptr is UB and it seems that LLVM and GCC have different behavior. 
As shown in 
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Transforms/Utils/Local.cpp#L2317,
 LLVM (`simplifycfg` in particular) will turn stores to nullptr into 
unreachable. When compiling with -O0, no optimization is done, so we can't see 
this behavior.
What I am doing in this patch is not making store to nullptr a defined 
behavior, but changing the way to store the new vl in vleff intrinsics (only do 
it if destination to store is not null).
Before:

  new_vl = vleff(...)
  *dst = new_vl;

Now:

  new_vl = vleff(...)
  if (dst) {
*dst = new_vl;
  }

So that we won't generate store to nullptr if we pass a nullptr to vleff 
intrinsics. This behavior is compatible with GCC.

As for the difference when compiling with -O3, it is because GCC handles this 
UB (store to nullptr) in other way. But as you can see, `sw zero,0(zero)` will 
cause interruption (runtime errors). I don't know if we should make LLVM and 
GCC with the same behavior to  handle stores to null, which is beyond this 
patch.

> ex.
>
>   int foo (int j){
>   int *k = nullptr;
>   *k = 10;
>   return 100;
>   }
>
> compiling with `-O3`, llvm generates empty function but gcc generates
>
>   foo(int):
>   sw  zero,0(zero)
>   ebreak
>
> https://godbolt.org/z/46vGrzs49
>
> Please correct me if I misunderstand something, thanks.




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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added a comment.

In D126461#3566626 , @khchen wrote:

> IMO, if I'm an user, I would not expected intrinsic function will generate 
> the condition code to impact the performance, maybe we need to raise a issue 
> in rvv-intrinsic-doc.
> maybe another way is adding a note in intrinsic document to address that the 
> vl could not be a null pointer.

I understand your concern about impact on performance and I added a test to 
show that the comparison and branch instruction can be optimized if destination 
is known to be not null (which is common in most scenarios using vleff).
For example:

  size_t new_vl;
  v=vleff(..., &new_vl, vl);
  //usage of new_vl.

When doing `instsimplify`, LLVM knows `new_vl` won't be null. Comparison is 
evaluated to be true and branch instruction will be changed to unconditional 
branch (which will be simplified by `simplifycfg`).
So I think there is no impact on performance for most scenarios. For some cases 
that we don't know whether destination is null or not (like using destination 
passed by argument in `vleff.c`, but I think it is not normal usage and IPO may 
help), it is a potential risk that we may end in program crashing if we don't 
do null pointer checking.

> How about the segment load? Does it make sense to add null pointer checking 
> for all argument v0~vN?

That's a good point and I have thought it before. Here is my point but we can 
have more discussion.
I think we don't need null pointer checking for non-tuple segment loads. One of 
the reason is that we have said (but not documented?) that pointers can't be 
null in https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/95. Besides, 
I think we should treat the output of segment loads as whole structure though 
we have non-tuple intrinsics for now. The reason why we add null pointer 
checking for vleff is because the outputs of vleff are of two different types 
and we just want to ignore the output new vl.


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[PATCH] D126461: [RISCV] Extract and store new vl of vleff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 435454.
pcwang-thead edited the summary of this revision.
pcwang-thead added a comment.

Add null pointer checking for vlsegff.


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  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff-optimized.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff-optimized.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c

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[PATCH] D126461: [RISCV] Extract and store new vl of vleff/vlsegff iff destination isn't null

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead updated this revision to Diff 435466.
pcwang-thead added a comment.

Update test `rvv-intrinsics-overloaded/vlsegff.c`.


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  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff-optimized.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff-optimized.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c

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[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:52
 // Same as CSR_Interrupt, but including all 64-bit FP registers.
 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
  (sequence "F%u_D", 0, 31))>;

Should we add CSRs for interrupt functions? And Should we save `vtype`, 
`vstart`, `vxrm`, `vxsat`, etc. registers?


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[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 541374.
wangpc added a comment.

Update ReleaseNotes.


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  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-default-features.c
  clang/test/Driver/riscv-features.c


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -24,6 +24,22 @@
 // DEFAULT: "-target-feature" "-save-restore"
 // DEFAULT-NOT: "-target-feature" "+save-restore"
 
+// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | 
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 
| FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | 
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | 
FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
+
+// UNALIGNED-SCALAR-MEM: "-target-feature" "+unaligned-scalar-mem"
+// NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
+// UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
+// NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
+// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
+// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
+
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
 // RUN: %clang --target=riscv64-linux -### %s -fsyntax-only 2>&1 \
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,8 +3,10 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
+// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
+// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -167,6 +167,19 @@
   else
 Features.push_back("-save-restore");
 
+  // -mno-unaligned-access is default, unless -munaligned-access is specified.
+  bool HasV = llvm::is_contained(Features, "+zve32x");
+  if (Args.hasFlag(options::OPT_munaligned_access,
+   options::OPT_mno_unaligned_access, false)) {
+Features.push_back("+unaligned-scalar-mem");
+if (HasV)
+  Features.push_back("+unaligned-vector-mem");
+  } else {
+Features.push_back("-unaligned-scalar-mem");
+if (HasV)
+  Features.push_back("-unaligned-vector-mem");
+  }
+
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3811,9 +3811,9 @@
"in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch 
only)">;
+  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch 
only)">;
+  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
 } // let Flags = [TargetSpecific]
 def mstrict_align : Flag<["-"], "mstrict-align">, Alias, 
Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (same as 
mno-unaligned-access)">;
Index: clang/docs/ReleaseNotes.rst
==

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 541415.
wangpc added a comment.

Rebase and fix libcxx tests.


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  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
===
--- clang/www/cxx_status.html
+++ clang/www/cxx_status.html
@@ -1208,12 +1208,11 @@
 
 
 
-(7): In Clang 3.7 and later, sized deallocation is only enabled
-if the user passes the -fsized-deallocation flag. The user must
-supply definitions of the sized deallocation functions, either by providing them
-explicitly or by using a C++ standard library that does. libstdc++
-added these functions in version 5.0, and libc++ added th

[PATCH] D155647: [RISCV] Add C intrinsics for scalar crypto

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

Can we run mem2reg pass in RUNs just like RVV tests (maybe another cleanup 
patch)? I think there are a lot of noises in CHECKS.


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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc planned changes to this revision.
wangpc added a comment.

I don't have any thoughts on this patch now.

In D125765#4511637 , @eopXD wrote:

> Sorry for the late reply, I missed this in may mails.
>
> I see that the motivation start from where you spotted this type alias. 
> However it was essentially just an act for convenience so we don't have to 
> map a more irregular pattern of ( _Float16, float, double) when generating 
> the test cases by code. Is it necessary that we have them in the header? On 
> the other hand, these are scalar floating-point types, and if we want them to 
> be defined, I agree with Zakk that starting a discussion in riscv-c-api will 
> be helpful.

Yeah, I agree. But I won't continue this now.


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[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.



Comment at: clang/test/Driver/riscv-features.c:41
+// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
+// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
+

arichardson wrote:
> This looks a bit fragile, can we just check all -target-feature flags instead 
> and add --implicit-check-not='-target-feature" to Filecheck?
I'm so sorry that I may not get what you mean, can you tell me what kind of 
change I need to make?


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

Ping.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 543828.
wangpc added a comment.

Rebase.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
===
--- clang/www/cxx_status.html
+++ clang/www/cxx_status.html
@@ -1208,12 +1208,11 @@
 
 
 
-(7): In Clang 3.7 and later, sized deallocation is only enabled
-if the user passes the -fsized-deallocation flag. The user must
-supply definitions of the sized deallocation functions, either by providing them
-explicitly or by using a C++ standard library that does. libstdc++
-added these functions in version 5.0, and libc++ added them in
-version 3.7.
+

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D112921#4529182 , @Mordante wrote:

> I noticed some of the CI jobs are still failing with the patch, I didn't look 
> into them.

I don't think they are related to this patch, so I rebased again. If still 
failed, I will try to fix them later.


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 

I think the comment is outdated here. `E` can be combined with all other 
extensions according to spec:
> Unless otherwise stated, standard extensions compatible with RV32I and RV64I 
> are also compatible with RV32E and RV64E, respectively.
And, please see also D70401 for more context.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D112921#4532378 , @Mordante wrote:

> In D112921#4530916 , @wangpc wrote:
>
>> In D112921#4529182 , @Mordante 
>> wrote:
>>
>>> I noticed some of the CI jobs are still failing with the patch, I didn't 
>>> look into them.
>>
>> I don't think they are related to this patch, so I rebased again. If still 
>> failed, I will try to fix them later.
>
> I see changes in the libc++ ABI list output
>
>   Symbol added: _ZdlPvmSt11align_val_t
>   {'name': '_ZdlPvmSt11align_val_t', 'type': 'FUNC', 'is_defined': False}
>   
>   Symbol added: _ZdlPvm
>   {'name': '_ZdlPvm', 'type': 'FUNC', 'is_defined': False}
>   
>   SYMBOL REMOVED: _ZdlPvSt11align_val_t
>   {'is_defined': False, 'name': '_ZdlPvSt11align_val_t', 'type': 'FUNC'}
>   
>   Summary
>   Added:   2
>   Removed: 1
>   Changed: 0
>
> There seems to be small change in the symbol name. What does the `m` in the 
> added symbol mean?
>
>   _ZdlPvmSt11align_val_t - added
>   _ZdlPvSt11align_val_t  - remove
>
> There is also a new symbol `_ZdlPvm` added.

`m` means `unsigned long` in mangled name (5.1.5.2 Builtin types 
), which 
is the `size` of sized deallocation.

  $ c++filt _ZdlPvmSt11align_val_t _ZdlPvm
  operator delete(void*, unsigned long, std::align_val_t)
  operator delete(void*, unsigned long)

I am not familiar  with libcxx, can you please help me to fix these tests? I 
hope we can catch up with the release of LLVM 17.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 544640.
wangpc added a comment.

- Remove usages of `-fsized-deallocation` in some tests.
- Rebase.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
==

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D112921#4536088 , @Mordante wrote:

> In D112921#4535716 , @wangpc wrote:
>
>> In D112921#4532378 , @Mordante 
>> wrote:
>>
>>> In D112921#4530916 , @wangpc 
>>> wrote:
>>>
 In D112921#4529182 , @Mordante 
 wrote:

> I noticed some of the CI jobs are still failing with the patch, I didn't 
> look into them.

 I don't think they are related to this patch, so I rebased again. If still 
 failed, I will try to fix them later.
>>>
>>> I see changes in the libc++ ABI list output
>>>
>>>   Symbol added: _ZdlPvmSt11align_val_t
>>>   {'name': '_ZdlPvmSt11align_val_t', 'type': 'FUNC', 'is_defined': 
>>> False}
>>>   
>>>   Symbol added: _ZdlPvm
>>>   {'name': '_ZdlPvm', 'type': 'FUNC', 'is_defined': False}
>>>   
>>>   SYMBOL REMOVED: _ZdlPvSt11align_val_t
>>>   {'is_defined': False, 'name': '_ZdlPvSt11align_val_t', 'type': 'FUNC'}
>>>   
>>>   Summary
>>>   Added:   2
>>>   Removed: 1
>>>   Changed: 0
>>>
>>> There seems to be small change in the symbol name. What does the `m` in the 
>>> added symbol mean?
>>>
>>>   _ZdlPvmSt11align_val_t - added
>>>   _ZdlPvSt11align_val_t  - remove
>>>
>>> There is also a new symbol `_ZdlPvm` added.
>>
>> `m` means `unsigned long` in mangled name (5.1.5.2 Builtin types 
>> ), 
>> which is the `size` of sized deallocation.
>>
>>   $ c++filt _ZdlPvmSt11align_val_t _ZdlPvm
>>   operator delete(void*, unsigned long, std::align_val_t)
>>   operator delete(void*, unsigned long)
>>
>> I am not familiar  with libcxx, can you please help me to fix these tests? I 
>> hope we can catch up with the release of LLVM 17.
>
> Looking at the ABI list we currently have
>
>   _ZdlPv -> operator delete(void*)   // this 
> one is kept
>   _ZdlPvSt11align_val_t -> operator delete(void*, std::align_val_t)  // this 
> one is removed
>
> You add the overloads
>
>   operator delete(void*, unsigned long, std::align_val_t)
>   operator delete(void*, unsigned long)
>
> Looking in the current WP 
> http://eel.is/c++draft/replacement.functions#lib:new,operator the removed 
> overload is still listed there.
>
> Do you know why `operator delete(void*)` and `operator delete(void*, unsigned 
> long)` are both available?

I don't know the details about C++ spec, but I think they should be available 
for runtimes with/without sized deallocations.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 545006.
wangpc added a comment.

- Rebase.
- Unsupport clang-18.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17, clang-18
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
===

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D149017#4579179 , @zixuan-wu wrote:

> Is it going to commit?

This patch is stuck since the patch to support function/lambda is WIP (I may 
not work on it recently).


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[PATCH] D157680: [X86]Support options -mno-gather -mno-scatter

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:7527
+  // -mno-gather, -mno-scatter support
+  if (Args.hasArg(options::OPT_mno_gather)) {
+CmdArgs.push_back("-target-feature");

Put these in `clang/lib/Driver/ToolChains/Arch/X86.cpp:getX86TargetFeatures`? 
They are target-specific.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 550983.
wangpc marked 10 inline comments as done.
wangpc added a comment.

- Rebase.
- Update tests, remove clang-17.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-18
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
===
--- clan

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

In D112921#4595918 , @Mordante wrote:

> In D112921#4594092 , @wangpc wrote:
>
>> - Rebase.
>> - Update tests, remove clang-17.
>
> The removal of the markers in the libc++ tests breaks these test. FYI the 
> tests are using a Clang build of apt.llvm.org and are not using this patch 
> for testing.

Thanks! I didn't know this. I will add it back before I commit this patch.


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[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 551367.
wangpc added a comment.

Rebase and fix failed tests.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  
libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.nonew.abilist
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: libcxx/lib

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 551702.
wangpc added a comment.

- Rebase.
- Remove abilist changes.
- Add clang-18.


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
===

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 551890.
wangpc added a comment.

Rebase


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Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,13 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

@ldionne Sorry for bothering, what do you think about landing this patch?


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[PATCH] D155647: [RISCV] Add C intrinsics for scalar bitmanip and crypto

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc accepted this revision.
wangpc added a comment.
This revision is now accepted and ready to land.
Herald added a subscriber: sunshaoce.

LGTM if the proposal is merged.


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[PATCH] D142144: [RISCV][Driver] Add -mrvv-vector-bits= option similar to -msve-vector-bits=

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.
Herald added subscribers: jobnoorman, sunshaoce.



Comment at: clang/test/Driver/riscv-rvv-vector-bits.c:43
+// RUN: %clang -c %s -### --target=riscv64-linux-gnu -march=rv64gcv \
+// RUN:  -mrvv-vector-bits=64 2>&1 | FileCheck 
--check-prefix=CHECK-BAD-VALUE-ERROR %s
+

Why isn't 64 an valid value?


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[PATCH] D151730: [RISCV] Support target attribute for function

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:376
+
+  if (AttrString.startswith("+") || AttrString.startswith("-")) {
+// EXTENSION like arch=+v,+zbb,-c

`-` is removed in 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35/commits/fc690d6caf71c80500d2572dd04d87773946451a.


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[PATCH] D156693: [clang][ASTImporter]Skip check depth of friend template parameter

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG07ab5140080e: [clang][ASTImporter]Skip check depth of friend 
template parameter (authored by jcsxky, committed by wangpc).

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D156693

Files:
  clang/include/clang/AST/ASTStructuralEquivalence.h
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/ASTStructuralEquivalence.cpp
  clang/unittests/AST/ASTImporterTest.cpp
  clang/unittests/AST/StructuralEquivalenceTest.cpp

Index: clang/unittests/AST/StructuralEquivalenceTest.cpp
===
--- clang/unittests/AST/StructuralEquivalenceTest.cpp
+++ clang/unittests/AST/StructuralEquivalenceTest.cpp
@@ -1,5 +1,6 @@
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/ASTStructuralEquivalence.h"
+#include "clang/AST/DeclTemplate.h"
 #include "clang/ASTMatchers/ASTMatchers.h"
 #include "clang/Frontend/ASTUnit.h"
 #include "clang/Testing/CommandLineArgs.h"
@@ -130,15 +131,20 @@
 return makeStmts(Wrap(SrcCode0), Wrap(SrcCode1), Lang, AMatcher);
   }
 
-  bool testStructuralMatch(Decl *D0, Decl *D1) {
+  bool testStructuralMatch(Decl *D0, Decl *D1,
+   bool IgnoreTemplateParmDepth = false) {
 llvm::DenseSet> NonEquivalentDecls01;
 llvm::DenseSet> NonEquivalentDecls10;
 StructuralEquivalenceContext Ctx01(
-D0->getASTContext(), D1->getASTContext(),
-NonEquivalentDecls01, StructuralEquivalenceKind::Default, false, false);
+D0->getASTContext(), D1->getASTContext(), NonEquivalentDecls01,
+StructuralEquivalenceKind::Default, /*StrictTypeSpelling=*/false,
+/*Complain=*/false, /*ErrorOnTagTypeMismatch=*/false,
+IgnoreTemplateParmDepth);
 StructuralEquivalenceContext Ctx10(
-D1->getASTContext(), D0->getASTContext(),
-NonEquivalentDecls10, StructuralEquivalenceKind::Default, false, false);
+D1->getASTContext(), D0->getASTContext(), NonEquivalentDecls10,
+StructuralEquivalenceKind::Default, /*StrictTypeSpelling=*/false,
+/*Complain=*/false, /*ErrorOnTagTypeMismatch=*/false,
+IgnoreTemplateParmDepth);
 bool Eq01 = Ctx01.IsEquivalent(D0, D1);
 bool Eq10 = Ctx10.IsEquivalent(D1, D0);
 EXPECT_EQ(Eq01, Eq10);
@@ -165,8 +171,9 @@
 return testStructuralMatch(get<0>(t), get<1>(t));
   }
 
-  bool testStructuralMatch(std::tuple t) {
-return testStructuralMatch(get<0>(t), get<1>(t));
+  bool testStructuralMatch(std::tuple t,
+   bool IgnoreTemplateParmDepth = false) {
+return testStructuralMatch(get<0>(t), get<1>(t), IgnoreTemplateParmDepth);
   }
 };
 
@@ -1689,6 +1696,40 @@
   EXPECT_FALSE(testStructuralMatch(t));
 }
 
+TEST_F(StructuralEquivalenceTemplateTest,
+   IgnoreTemplateParmDepthAtTemplateTypeParmDecl) {
+  auto Decls = makeDecls(
+  R"(
+template struct A;
+  )",
+  R"(
+template struct S {
+  template friend struct A;
+};
+  )",
+  Lang_CXX03, classTemplateDecl(hasName("A")),
+  classTemplateDecl(hasName("A")));
+  EXPECT_TRUE(testStructuralMatch(Decls));
+  EXPECT_TRUE(testStructuralMatch(Decls, true));
+}
+
+TEST_F(StructuralEquivalenceTemplateTest,
+   IgnoreTemplateParmDepthAtNonTypeTemplateParmDecl) {
+  auto Decls = makeDecls(
+  R"(
+template struct A;
+  )",
+  R"(
+template struct S {
+  template friend struct A;
+};
+  )",
+  Lang_CXX03, classTemplateDecl(hasName("A")),
+  classTemplateDecl(hasName("A")));
+  EXPECT_FALSE(testStructuralMatch(Decls));
+  EXPECT_TRUE(testStructuralMatch(Decls, /*IgnoreTemplateParmDepth=*/true));
+}
+
 TEST_F(
 StructuralEquivalenceTemplateTest,
 ClassTemplSpecWithInequivalentShadowedTemplArg) {
Index: clang/unittests/AST/ASTImporterTest.cpp
===
--- clang/unittests/AST/ASTImporterTest.cpp
+++ clang/unittests/AST/ASTImporterTest.cpp
@@ -4246,6 +4246,58 @@
   EXPECT_TRUE(Imported->getPreviousDecl());
 }
 
+TEST_P(ImportFriendClasses, SkipComparingFriendTemplateDepth) {
+  Decl *ToTU = getToTuDecl(
+  R"(
+  template 
+  class A;
+
+  template 
+  class A {
+  public:
+template 
+friend class A;
+
+A(T x)  :x(x) {}
+
+  private:
+T x;
+  };
+  )",
+  Lang_CXX11);
+
+  auto *Fwd = FirstDeclMatcher().match(
+  ToTU,
+  classTemplateDecl(has(cxxRecordDecl(hasDefinition(), hasName("A");
+  Decl *FromTU = getTuDecl(
+  R"(
+  template 
+  class A;
+
+  template 
+  class A {
+  public:
+template 
+friend class A;
+
+A(T x) : x(x) {}
+
+  private:
+T x;
+  };
+
+  A a1(0);
+  )",
+  Lang_

[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc created this revision.
wangpc added a reviewer: craig.topper.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
wangpc requested review of this revision.
Herald added subscribers: cfe-commits, eopXD, MaskRay.
Herald added a project: clang.

We used to convert them to M1  types in arguments 
and return
value, which causes failures in CodeGen since it is not legal
to insert subvectors with LMUL>1 to M1  vectors.

Fixes 64266


Repository:
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https://reviews.llvm.org/D156779

Files:
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c

Index: clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
===
--- clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
+++ clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
@@ -42,8 +42,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <8 x i32>, ptr [[TMP0]], align 8
 // CHECK-NEXT:store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m1_t test_ptr_to_global() {
   fixed_int32m1_t *global_vec_ptr;
@@ -63,8 +63,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 8
 // CHECK-NEXT:store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m1_t array_arg(fixed_int32m1_t arr[]) {
   return arr[0];
@@ -76,14 +76,14 @@
 // CHECK-NEXT:[[VEC_ADDR:%.*]] = alloca , align 4
 // CHECK-NEXT:store  [[VEC:%.*]], ptr [[VEC_ADDR]], align 4
 // CHECK-NEXT:[[TMP0:%.*]] = load <8 x i32>, ptr @global_vec, align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], i64 0)
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], i64 0)
 // CHECK-NEXT:[[TMP1:%.*]] = load , ptr [[VEC_ADDR]], align 4
-// CHECK-NEXT:[[TMP2:%.*]] = call  @llvm.riscv.vadd.nxv2i32.nxv2i32.i64( poison,  [[CASTSCALABLESVE]],  [[TMP1]], i64 8)
-// CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TMP2]], i64 0)
-// CHECK-NEXT:store <8 x i32> [[CASTFIXEDSVE]], ptr [[RETVAL]], align 8
+// CHECK-NEXT:[[TMP2:%.*]] = call  @llvm.riscv.vadd.nxv2i32.nxv2i32.i64( poison,  [[CAST_SCALABLE]],  [[TMP1]], i64 8)
+// CHECK-NEXT:[[CAST_FIXED:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TMP2]], i64 0)
+// CHECK-NEXT:store <8 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP3:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE1:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP3]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE1]]
+// CHECK-NEXT:[[CAST_SCALABLE1:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP3]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE1]]
 //
 fixed_int32m1_t test_cast(vint32m1_t vec) {
   return __riscv_vadd(global_vec, vec, __riscv_v_fixed_vlen/32);
@@ -98,8 +98,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[TMP0]], align 8
 // CHECK-NEXT:store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m2_t test_ptr_to_global_m2() {
   fixed_int32m2_t *global_vec_ptr;
@@ -119,8 +119,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[ARRAYIDX]], align 8
 // CHECK-NEXT:store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] =

[PATCH] D156779: [RISCV] Use correct LMUL!=1 types for __attribute__((riscv_rvv_vector_bits(N)))

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGedb5056300bb: [RISCV] Use correct LMUL!=1 types for 
__attribute__((riscv_rvv_vector_bits(N))) (authored by wangpc).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156779/new/

https://reviews.llvm.org/D156779

Files:
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c

Index: clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
===
--- clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
+++ clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
@@ -42,8 +42,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <8 x i32>, ptr [[TMP0]], align 8
 // CHECK-NEXT:store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m1_t test_ptr_to_global() {
   fixed_int32m1_t *global_vec_ptr;
@@ -63,8 +63,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <8 x i32>, ptr [[ARRAYIDX]], align 8
 // CHECK-NEXT:store <8 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m1_t array_arg(fixed_int32m1_t arr[]) {
   return arr[0];
@@ -76,14 +76,14 @@
 // CHECK-NEXT:[[VEC_ADDR:%.*]] = alloca , align 4
 // CHECK-NEXT:store  [[VEC:%.*]], ptr [[VEC_ADDR]], align 4
 // CHECK-NEXT:[[TMP0:%.*]] = load <8 x i32>, ptr @global_vec, align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], i64 0)
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP0]], i64 0)
 // CHECK-NEXT:[[TMP1:%.*]] = load , ptr [[VEC_ADDR]], align 4
-// CHECK-NEXT:[[TMP2:%.*]] = call  @llvm.riscv.vadd.nxv2i32.nxv2i32.i64( poison,  [[CASTSCALABLESVE]],  [[TMP1]], i64 8)
-// CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TMP2]], i64 0)
-// CHECK-NEXT:store <8 x i32> [[CASTFIXEDSVE]], ptr [[RETVAL]], align 8
+// CHECK-NEXT:[[TMP2:%.*]] = call  @llvm.riscv.vadd.nxv2i32.nxv2i32.i64( poison,  [[CAST_SCALABLE]],  [[TMP1]], i64 8)
+// CHECK-NEXT:[[CAST_FIXED:%.*]] = call <8 x i32> @llvm.vector.extract.v8i32.nxv2i32( [[TMP2]], i64 0)
+// CHECK-NEXT:store <8 x i32> [[CAST_FIXED]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP3:%.*]] = load <8 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE1:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP3]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE1]]
+// CHECK-NEXT:[[CAST_SCALABLE1:%.*]] = call  @llvm.vector.insert.nxv2i32.v8i32( undef, <8 x i32> [[TMP3]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE1]]
 //
 fixed_int32m1_t test_cast(vint32m1_t vec) {
   return __riscv_vadd(global_vec, vec, __riscv_v_fixed_vlen/32);
@@ -98,8 +98,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[TMP0]], align 8
 // CHECK-NEXT:store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m2_t test_ptr_to_global_m2() {
   fixed_int32m2_t *global_vec_ptr;
@@ -119,8 +119,8 @@
 // CHECK-NEXT:[[TMP1:%.*]] = load <16 x i32>, ptr [[ARRAYIDX]], align 8
 // CHECK-NEXT:store <16 x i32> [[TMP1]], ptr [[RETVAL]], align 8
 // CHECK-NEXT:[[TMP2:%.*]] = load <16 x i32>, ptr [[RETVAL]], align 8
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call  @llvm.vector.insert.nxv2i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
-// CHECK-NEXT:ret  [[CASTSCALABLESVE]]
+// CHECK-NEXT:[[CAST_SCALABLE:%.*]] = call  @llvm.vector.insert.nxv4i32.v16i32( undef, <16 x i32> [[TMP2]], i64 0)
+// CHECK-NEXT:ret  [[CAST_SCALABLE]]
 //
 fixed_int32m2_t array_arg_m2(fixed_int32m2_t arr[]) {
   return arr[0];
@@ -132,14 +132,14 @@
 // CHECK-NEXT:[[VEC_ADDR:%.*]] = alloca , a

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 546760.
wangpc added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112921/new/

https://reviews.llvm.org/D112921

Files:
  clang-tools-extra/clangd/unittests/FindTargetTests.cpp
  clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/SizedDeallocation.h
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Darwin.cpp
  clang/lib/Driver/ToolChains/Darwin.h
  clang/lib/Driver/ToolChains/ZOS.cpp
  clang/test/AST/ast-dump-expr-json.cpp
  clang/test/AST/ast-dump-expr.cpp
  clang/test/AST/ast-dump-stmt-json.cpp
  clang/test/Analysis/cxxnewexpr-callback.cpp
  
clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp
  clang/test/CXX/expr/expr.unary/expr.new/p14.cpp
  clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp
  clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp
  clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp
  clang/test/CodeGenCXX/delete-two-arg.cpp
  clang/test/CodeGenCXX/delete.cpp
  clang/test/CodeGenCXX/dllimport.cpp
  clang/test/CodeGenCXX/new.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp
  clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp
  clang/test/CodeGenCoroutines/coro-alloc.cpp
  clang/test/CodeGenCoroutines/coro-cleanup.cpp
  clang/test/CodeGenCoroutines/coro-dealloc.cpp
  clang/test/CodeGenCoroutines/coro-gro.cpp
  clang/test/CodeGenCoroutines/pr56919.cpp
  clang/test/Lexer/cxx-features.cpp
  clang/test/PCH/cxx1z-aligned-alloc.cpp
  clang/test/SemaCXX/MicrosoftExtensions.cpp
  clang/test/SemaCXX/builtin-operator-new-delete.cpp
  clang/test/SemaCXX/cxx1y-sized-deallocation.cpp
  clang/test/SemaCXX/unavailable_aligned_allocation.cpp
  clang/unittests/StaticAnalyzer/CallEventTest.cpp
  clang/www/cxx_status.html
  libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
  
libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp

Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
===
--- libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
+++ libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp
@@ -8,11 +8,14 @@
 
 // test sized operator delete[] replacement.
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17, clang-18
 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11
+// XFAIL: clang-15, clang-16
+// XFAIL: apple-clang
 
-// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by
-// default. It is only enabled when -fsized-deallocation is given.
-// XFAIL: clang, apple-clang
+// Sized deallocation was added in macOS 10.12 and aligned OSes.
+// XFAIL: use_system_cxx_lib && target={{.+}}-apple-macosx10.{{9|10|11}}
 
 #include 
 #include 
Index: libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
===
--- libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
+++ libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp
@@ -25,6 +25,9 @@
 // GCC doesn't support the aligned-allocation flags.
 // XFAIL: gcc
 
+// TODO(mordante) fix this test after updating clang in Docker
+// UNSUPPORTED: clang-17, clang-18
+
 // RUN: %{build} -faligned-allocation -fsized-deallocation
 // RUN: %{run}
 // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE
Index: clang/www/cxx_status.html
===

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc added a comment.

Thanks!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

[Wang Pengcheng via Phabricator via cfe-commits]

wangpc updated this revision to Diff 546772.
wangpc added a comment.

Rebase since `ReleaseNotes.rst` is changed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155456/new/

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Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-default-features.c
  clang/test/Driver/riscv-features.c


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -26,6 +26,22 @@
 // DEFAULT: "-target-feature" "-save-restore"
 // DEFAULT-NOT: "-target-feature" "+save-restore"
 
+// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | 
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 
| FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | 
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | 
FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
+
+// UNALIGNED-SCALAR-MEM: "-target-feature" "+unaligned-scalar-mem"
+// NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
+// UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
+// NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
+// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
+// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
+
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
 // RUN: %clang --target=riscv64-linux -### %s -fsyntax-only 2>&1 \
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,8 +3,10 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
+// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
+// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -167,6 +167,19 @@
   else
 Features.push_back("-save-restore");
 
+  // -mno-unaligned-access is default, unless -munaligned-access is specified.
+  bool HasV = llvm::is_contained(Features, "+zve32x");
+  if (Args.hasFlag(options::OPT_munaligned_access,
+   options::OPT_mno_unaligned_access, false)) {
+Features.push_back("+unaligned-scalar-mem");
+if (HasV)
+  Features.push_back("+unaligned-vector-mem");
+  } else {
+Features.push_back("-unaligned-scalar-mem");
+if (HasV)
+  Features.push_back("-unaligned-vector-mem");
+  }
+
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3834,9 +3834,9 @@
"in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch 
only)">;
+  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch 
only)">;
+  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
 } // let Flags = [TargetSpecific]
 def mstrict_align : Flag<["-"], "mstrict-align">, Alias, 
Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (same as 
mno-unaligned-access)">;
Index: clang/docs/ReleaseNotes.rst
===

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

[Wang Pengcheng via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG23ce5368409c: [RISCV] Support -m[no-]strict-align options 
(authored by wangpc).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155456/new/

https://reviews.llvm.org/D155456

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-default-features.c
  clang/test/Driver/riscv-features.c


Index: clang/test/Driver/riscv-features.c
===
--- clang/test/Driver/riscv-features.c
+++ clang/test/Driver/riscv-features.c
@@ -26,6 +26,22 @@
 // DEFAULT: "-target-feature" "-save-restore"
 // DEFAULT-NOT: "-target-feature" "+save-restore"
 
+// RUN: %clang --target=riscv32-unknown-elf -### %s -munaligned-access 2>&1 | 
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-unaligned-access 2>&1 
| FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mno-strict-align 2>&1 | 
FileCheck %s -check-prefix=UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -mstrict-align 2>&1 | 
FileCheck %s -check-prefix=NO-UNALIGNED-SCALAR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-munaligned-access 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mno-unaligned-access 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mno-strict-align 2>&1 | FileCheck %s -check-prefix=UNALIGNED-VECTOR-MEM
+// RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv32gv 
-mstrict-align 2>&1 | FileCheck %s -check-prefix=NO-UNALIGNED-VECTOR-MEM
+
+// UNALIGNED-SCALAR-MEM: "-target-feature" "+unaligned-scalar-mem"
+// NO-UNALIGNED-SCALAR-MEM: "-target-feature" "-unaligned-scalar-mem"
+// UNALIGNED-VECTOR-MEM: "-target-feature" "+unaligned-vector-mem"
+// NO-UNALIGNED-VECTOR-MEM: "-target-feature" "-unaligned-vector-mem"
+// DEFAULT: "-target-feature" "-unaligned-scalar-mem"
+// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-mem"
+
 // RUN: %clang --target=riscv32-linux -### %s -fsyntax-only 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=DEFAULT-LINUX
 // RUN: %clang --target=riscv64-linux -### %s -fsyntax-only 2>&1 \
Index: clang/test/Driver/riscv-default-features.c
===
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -3,8 +3,10 @@
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
+// RV32-SAME: -unaligned-scalar-mem
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 // RV64-SAME: -save-restore
+// RV64-SAME: -unaligned-scalar-mem
 
 // Dummy function
 int foo(void){
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -167,6 +167,19 @@
   else
 Features.push_back("-save-restore");
 
+  // -mno-unaligned-access is default, unless -munaligned-access is specified.
+  bool HasV = llvm::is_contained(Features, "+zve32x");
+  if (Args.hasFlag(options::OPT_munaligned_access,
+   options::OPT_mno_unaligned_access, false)) {
+Features.push_back("+unaligned-scalar-mem");
+if (HasV)
+  Features.push_back("+unaligned-vector-mem");
+  } else {
+Features.push_back("-unaligned-scalar-mem");
+if (HasV)
+  Features.push_back("-unaligned-vector-mem");
+  }
+
   // Now add any that the user explicitly requested on the command line,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,
Index: clang/include/clang/Driver/Options.td
===
--- clang/include/clang/Driver/Options.td
+++ clang/include/clang/Driver/Options.td
@@ -3834,9 +3834,9 @@
"in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group,
-  HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch 
only)">;
+  HelpText<"Allow memory accesses to be unaligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group,
-  HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch 
only)">;
+  HelpText<"Force all memory accesses to be aligned 
(AArch32/AArch64/LoongArch/RISC-V only)">;
 } // let Flags = [TargetSpecific]
 def mstrict_align : Flag<["-"], "mstrict-align">, Alias, 
Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be al