[PATCH] D141032: [Clang][RISCV] Expose vlenb to vread_csr

[Wang Pengcheng via Phabricator via cfe-commits]

pcwang-thead added inline comments.


================
Comment at: clang/include/clang/Basic/riscv_vector.td:1559
       __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
       break;
   }
----------------
Should we report errors if `vwrite_csr(RVV_VLENB, some_value)`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141032/new/

https://reviews.llvm.org/D141032

_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits