[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

2022-09-13 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 updated this revision to Diff 459803.
sagarkulkarni19 added a comment.

- Support Opaque pointers
- Correct predicate types for the intrinsics.
- Decorate intrinsics with SME attributes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,8 @@
 void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveRangeChecks(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
+void EmitSmeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,7 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +220,8 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +441,9 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -169,6 +169,11 @@
 
   SmallVector ImmChecks;
 
+  /// True if this is an SME intrinsic.
+  bool IsSMEIntrinsic;
+  /// Attributes for SME intrinsics.
+  std::string SMEAttributes;
+
 public:
   Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
 StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
@@ -194,6 +199,10 @@
   uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
+  bool isSMEIntrinsic() const { return IsSMEIntrinsic; }
+  // Return a comma seperated string of SME attributes.
+  std::string getSMEAttributes() const { return SMEAttributes; }
+
   ArrayRef getImmChecks() const { return ImmChecks; }
 
   /// Return the type string for a BUILTIN() macro in Builtins.def.
@@ -334,6 +343,9 @@
   /// Emit arm_sve.h.
   void createHeader(raw_ostream &o);
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream &o);
+
   /// Emit all the __builtin prototypes and code needed by Sema.
   void createBuiltins(raw_ostream &o);
 
@@ -347,7 +359,9 @@
   void createTypeFlags(raw_ostream &o);
 
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> &Out);
+  void createIntrinsic(Record *R,
+   SmallVectorImpl> &Out,
+   bool IsSME = false);
 };
 
 } // end anonymous namespace
@@ -757,6 +771,11 @@
 NumVectors = 0;
 Signed = true;
 break;
+  case '%':
+Pointer = true;
+Void = true;
+NumVectors = 0;
+break;
   case 'A':
 Pointer = true;
 ElementBitwidth = Bitwidth = 8;
@@ -840,6 +859,16 @@
   this->Flags |= Emitter.encodeMergeType(MergeTy);
   if (hasSplat())
 this->Flags |= Emitter.encodeSplatOperand(getSplatIdx());
+
+  // Set attributes for SME intrinsics.
+  if (this->Flags & Emitter.getEnumValueForFlag("IsSME")) {
+this->IsSMEIntrinsic = true;
+if (this->Flags & Emitter.getEnumValueForFlag("IsSMELd1"))
+  this->SMEAttributes = "arm_streaming, arm_shared_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMESt1"))
+

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

2022-09-26 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 updated this revision to Diff 463023.
sagarkulkarni19 added a comment.

Update testcases by adding "arm_streaming" attribute to the callee.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,8 @@
 void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveRangeChecks(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
+void EmitSmeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -81,6 +81,7 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -219,6 +220,8 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -438,6 +441,9 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -169,6 +169,11 @@
 
   SmallVector ImmChecks;
 
+  /// True if this is an SME intrinsic.
+  bool IsSMEIntrinsic;
+  /// Attributes for SME intrinsics.
+  std::string SMEAttributes;
+
 public:
   Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
 StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
@@ -194,6 +199,10 @@
   uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
+  bool isSMEIntrinsic() const { return IsSMEIntrinsic; }
+  // Return a comma seperated string of SME attributes.
+  std::string getSMEAttributes() const { return SMEAttributes; }
+
   ArrayRef getImmChecks() const { return ImmChecks; }
 
   /// Return the type string for a BUILTIN() macro in Builtins.def.
@@ -334,6 +343,9 @@
   /// Emit arm_sve.h.
   void createHeader(raw_ostream &o);
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream &o);
+
   /// Emit all the __builtin prototypes and code needed by Sema.
   void createBuiltins(raw_ostream &o);
 
@@ -347,7 +359,9 @@
   void createTypeFlags(raw_ostream &o);
 
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> &Out);
+  void createIntrinsic(Record *R,
+   SmallVectorImpl> &Out,
+   bool IsSME = false);
 };
 
 } // end anonymous namespace
@@ -757,6 +771,11 @@
 NumVectors = 0;
 Signed = true;
 break;
+  case '%':
+Pointer = true;
+Void = true;
+NumVectors = 0;
+break;
   case 'A':
 Pointer = true;
 ElementBitwidth = Bitwidth = 8;
@@ -840,6 +859,18 @@
   this->Flags |= Emitter.encodeMergeType(MergeTy);
   if (hasSplat())
 this->Flags |= Emitter.encodeSplatOperand(getSplatIdx());
+
+  // Set attributes for SME intrinsics.
+  if (this->Flags & Emitter.getEnumValueForFlag("IsSME")) {
+this->IsSMEIntrinsic = true;
+if (this->Flags & Emitter.getEnumValueForFlag("IsSMELd1"))
+  this->SMEAttributes = "arm_streaming, arm_shared_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMESt1"))
+  this->SMEAttributes = "arm_streaming, arm_share

[PATCH] D134677: [Clang][AArch64] Add SME zero intrinsic

2022-09-26 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 created this revision.
sagarkulkarni19 added reviewers: sdesmalen, rsandifo-arm, david-arm.
sagarkulkarni19 added a project: clang.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
sagarkulkarni19 requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch adds support for the following SME ACLE intrinsics:

- svzero_mask_za
- svzero_za


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134677

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -871,6 +871,8 @@
   this->SMEAttributes = "arm_streaming, arm_shared_za, arm_preserves_za";
 else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEWrite"))
   this->SMEAttributes = "arm_streaming, arm_shared_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEZero"))
+  this->SMEAttributes = "arm_streaming_compatible, arm_shared_za";
 else
   llvm_unreachable("Unknown SME instruction");
   } else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,63 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-LABEL: @test_svzero_mask_za(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 0)
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z19test_svzero_mask_zav(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 0)
+// CPP-CHECK-NEXT:ret void
+//
+void test_svzero_mask_za() {
+  svzero_mask_za(0);
+}
+
+// CHECK-LABEL: @test_svzero_mask_za_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 176)
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z21test_svzero_mask_za_1v(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 176)
+// CPP-CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_1() {
+  svzero_mask_za(176);
+}
+
+// CHECK-LABEL: @test_svzero_mask_za_2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 255)
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z21test_svzero_mask_za_2v(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 255)
+// CPP-CHECK-NEXT:ret void
+//
+void test_svzero_mask_za_2() {
+  svzero_mask_za(255);
+}
+
+// CHECK-LABEL: @test_svzero_za(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 255)
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z14test_svzero_zav(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.zero(i64 255)
+// CPP-CHECK-NEXT:ret void
+//
+void test_svzero_za() {
+  svzero_za();
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4240,6 +4240,9 @@
   llvm::Value *EmitSMEWrite(SVETypeFlags TypeFlags,
 llvm::SmallVectorImpl &Ops,
 unsigned IntID);
+  llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+   llvm::SmallVectorImpl &Ops,
+   unsigned IntID);
   llvm::Value *EmitSVEPrefetchLoad(const SVETypeFlags &TypeFlags,
SmallVectorImpl &Ops,
unsigned BuiltinID);
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9122,6 +9122,18 @@
   return Builder.CreateCall(F, Ops);
 }
 
+Value *CodeGenFunction::EmitSMEZero(SVETypeFlags TypeFlags,
+SmallVectorImpl &Ops,

[PATCH] D134678: [Clang][AArch64] Add SME ldr and str intrinsic

2022-09-26 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 created this revision.
sagarkulkarni19 added reviewers: sdesmalen, rsandifo-arm, david-arm.
sagarkulkarni19 added a project: clang.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
sagarkulkarni19 requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch adds support for the following SME ACLE intrinsics:

  svldr_vnum_za
  svstr_vnum_za


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134678

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -873,6 +873,10 @@
   this->SMEAttributes = "arm_streaming, arm_shared_za";
 else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEZero"))
   this->SMEAttributes = "arm_streaming_compatible, arm_shared_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMELdr"))
+  this->SMEAttributes = "arm_streaming_compatible, arm_shared_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEStr"))
+  this->SMEAttributes = "arm_streaming_compatible, arm_shared_za, arm_preserves_za";
 else
   llvm_unreachable("Unknown SME instruction");
   } else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,62 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+
+// CHECK-LABEL: @test_svstr_vnum_za(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CPP-CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-LABEL: @test_svstr_vnum_za_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CPP-CHECK-NEXT:[[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CPP-CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 15, ptr);
+}
+
+// CHECK-LABEL: @test_svstr_vnum_za_2(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT:[[MULVL:%.*]] = shl nuw nsw i64 [[VSCALE]], 8
+// CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z20test_svstr_vnum_za_2jPv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CPP-CHECK-NEXT:[[MULVL:%.*]] = shl nuw nsw i64 [[VSCALE]], 8
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CPP-CHECK-NEXT:ret void
+//
+void test_svstr_vnum_za_2(uint32_t slice_base, void *ptr) {
+  svstr_vnum_za(slice_base, 16, ptr);
+}
Index: clang/test/CodeGen/aar

[PATCH] D134679: [Clang][AArch64] Add SME svcntsb/h/w/d C intrinsics

2022-09-26 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 created this revision.
sagarkulkarni19 added reviewers: sdesmalen, rsandifo-arm, david-arm.
sagarkulkarni19 added a project: clang.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
sagarkulkarni19 requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch adds support for the following SME ACLE intrinsics:

  svcntsb
  svcntsh
  svcntsw
  svcntsd


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134679

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -877,6 +877,8 @@
   this->SMEAttributes = "arm_streaming_compatible, arm_shared_za";
 else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEStr"))
   this->SMEAttributes = "arm_streaming_compatible, arm_shared_za, arm_preserves_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMECnt"))
+  this->SMEAttributes = "arm_streaming_compatible, arm_preserves_za";
 else
   llvm_unreachable("Unknown SME instruction");
   } else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,63 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+// CHECK-LABEL: @test_svcntsb(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntsbv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CPP-CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-LABEL: @test_svcntsh(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntshv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CPP-CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-LABEL: @test_svcntsw(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntswv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CPP-CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-LABEL: @test_svcntsd(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntsdv(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CPP-CHECK-NEXT:ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -214,6 +214,7 @@
 def IsSMEZero : FlagType<0x100>;
 def IsSMELdr  : FlagType<0x200>;
 def IsSMEStr  : FlagType<0x400>;
+def IsSMECnt  : FlagType<0x800>;
 
 // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
 class ImmCheckType {
@@ -2173,3 +2174,11 @@
 
 def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", [IsOverloadNone, IsSME, IsSMEZero]>;
 def SVZERO_ZA  : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero", [IsOverloadNone, IsSME, IsSMEZero]>;
+
+
+// SME - Counting elements in a streaming vector
+
+def SVCNTSB : SInst<"svcntsb", "n", "", MergeNone, "aarch64_sme_cntsb", [IsOverloadNone, IsSME, IsSMECnt]>;
+def SVCNTSH : SInst<"s

[PATCH] D134680: [Clang][AArch64] Add SME svaddha and svaddva intrinsics

2022-09-26 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 created this revision.
sagarkulkarni19 added reviewers: sdesmalen, david-arm, rsandifo-arm.
sagarkulkarni19 added a project: clang.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
sagarkulkarni19 requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch adds support for the following SME ACLE intrinsics:

- svaddha_za32[_u32] // Also for s32
- svaddva_za32[_u32] // Also for s32
- svaddha_za64[_u64] // Also for s64
- svaddva_za64[_u64] // Also for s64


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134680

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -879,6 +879,8 @@
   this->SMEAttributes = "arm_streaming_compatible, arm_shared_za, arm_preserves_za";
 else if (this->Flags & Emitter.getEnumValueForFlag("IsSMECnt"))
   this->SMEAttributes = "arm_streaming_compatible, arm_preserves_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEAdd"))
+  this->SMEAttributes = "arm_streaming, arm_shared_za";
 else
   llvm_unreachable("Unknown SME instruction");
   } else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
@@ -0,0 +1,159 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-LABEL: @test_svaddha_za64_u64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i64 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z21test_svaddha_za64_u64u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i64 0,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CPP-CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svaddha_za64_u64(svbool_t pn, svbool_t pm, svuint64_t zn) {
+  SME_ACLE_FUNC(svaddha_za64, _u64,)(0, pn, pm, zn);
+}
+
+// CHECK-LABEL: @test_svaddha_za64_u64_1(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.addha.nxv2i64(i64 7,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z23test_svaddha_za64_u64_1u10__SVBool_tu10__SVBool_tu12__SVUint64_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PN:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch6

[PATCH] D134681: [Clang][AArch64] Add SME outer product intrinsics

2022-09-26 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 created this revision.
sagarkulkarni19 added reviewers: sdesmalen, rsandifo-arm, david-arm.
sagarkulkarni19 added a project: clang.
Herald added a subscriber: kristof.beyls.
Herald added a project: All.
sagarkulkarni19 requested review of this revision.
Herald added a subscriber: cfe-commits.

This patch adds support for the following SME ACLE intrinsics:

- svmopa_za32[_bf16] // Also for f16, u8, s8, f32
- svmopa_za64[_u16] // Also for s16, f64
- svmops_za32[_bf16] // Also for f16, u8, s8, f32
- svmops_za64[_u16] // Also for s16, f64
- svsumopa_za32[_s8]
- svsumopa_za64[_s16]
- svusmopa_za32[_u8]
- svusmopa_za64[_u16]
- svsumops_za32[_s8]
- svsumops_za64[_s16]
- svusmops_za32[_u8]
- svusmops_za64[_u16]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D134681

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -881,6 +881,8 @@
   this->SMEAttributes = "arm_streaming_compatible, arm_preserves_za";
 else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEAdd"))
   this->SMEAttributes = "arm_streaming, arm_shared_za";
+else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEMop"))
+  this->SMEAttributes = "arm_streaming, arm_shared_za";
 else
   llvm_unreachable("Unknown SME instruction");
   } else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
@@ -0,0 +1,105 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-f64 -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-f64 -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64 -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64 -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme-f64 -target-feature +sme-i64 -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include 
+
+#ifdef SME_OVERLOADED_FORMS
+#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3
+#else
+#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3
+#endif
+
+// CHECK-LABEL: @test_svmops_za64_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM:%.*]])
+// CHECK-NEXT:tail call void @llvm.aarch64.sme.smops.wide.nxv8i16(i64 1,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CHECK-NEXT:ret void
+//
+// CPP-CHECK-LABEL: @_Z20test_svmops_za64_s16u10__SVBool_tu10__SVBool_tu11__SVInt16_tu11__SVInt16_t(
+// CPP-CHECK-NEXT:  entry:
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN:%.*]])
+// CPP-CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM:%.*]])
+// CPP-CHECK-NEXT:tail call void @llvm.aarch64.sme.smops.wide.nxv8i16(i64 1,  [[TMP0]],  [[TMP1]],  [[ZN:%.*]],  [[ZM:%.*]])
+// CPP-CHECK-NEXT:ret void
+//
+__attribute__((arm_streaming)) void test_svmops_za64_s16(svbool_t pn, svbool_t pm, svint16_t zn, svint16_t zm) {
+  SME_ACLE_FUNC(svmops_za64, _s16,)(1, pn, pm, zn, zm);
+}
+
+// CHECK-LABEL: @test_svmops_za64_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = tail call  @llvm.aarch64.sve.convert.from.s

[PATCH] D134681: [Clang][AArch64] Add SME outer product intrinsics

2022-10-17 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 added a comment.

In D134681#3858849 , @rsandifo-arm 
wrote:

> Thanks for the patch.  This is going to be inconvenient, sorry, but: while 
> implementing the specification in GCC, I noticed that the ZA functions 
> weren't consistent about whether they had an `_m` suffix.  `svwrite` (MOVA) 
> had one, but the MOP intrinsics that you're implementing here didn't.  Since 
> SME2 does have some unpredicated instructions, it seems like it would be 
> better to make the MOP intrinsics consistent with `svwrite`, with an `_m` 
> suffix.
>
> I've created https://github.com/ARM-software/acle/pull/218 for that change.  
> Please let me know if it looks reasonable to you.

Thanks for letting me know. I can make the changes to MOP and ADD intrinsics 
and add a `_m` suffix. 
Yes, this looks reasonable to me.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134681/new/

https://reviews.llvm.org/D134681

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

2022-06-16 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 added a comment.

In D127910#3589068 , @sdesmalen wrote:

> Hi @sagarkulkarni19, this patch will have to wait until the ABI is 
> implemented so that the builtins can be decorated with the attributes. A 
> first patch proposing these attributes is in D127762 
> . LLVM patches that use these attributes to 
> implement the ABI will follow soon. We could add you as reviewer to these 
> patches if you'd like to help us with that?

Hi @sdesmalen, sounds good. I can update this patch accordingly when the 
attributes patches are in. Sure, please add me as a reviewer to those patches. 
We are porting much of our downstream C intrinsics implementation to support 
the ACLE instead and can contribute this effort upstream. I have also created 
an article on discourse 
(https://discourse.llvm.org/t/clang-sme-acle-intrinsics/63223) for further 
discussion on this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

2022-06-16 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:209
 def IsTupleSet: FlagType<0x4>;
+def IsSME : FlagType<0x8>;
+def IsSMELoadStore: FlagType<0x10>;

sdesmalen wrote:
> Is there value in having both `IsSME` and `IsSMELoadStore`?
`IsSME` flag is checked in the SveEmitter.cpp : createSMEHeader(...) to 
generate arm_sme.h with only the SME intrinsics, whereas `IsSMELoadStore` is 
used to correctly CodeGen (CGBuiltins.cpp) load and store intrinsics. 



Comment at: clang/lib/Basic/Targets/AArch64.cpp:342
+  if (HasSME)
+Builder.defineMacro("__ARM_FEATURE_SME", "1");
+

sdesmalen wrote:
> When this macro is non-zero, it suggests that the compiler implements the 
> full SME ACLE. That is currently not yet the case, so until then we should 
> leave this macro undefined.
Okay makes sense. But until all SME ACLE is implemented, do we need some sort 
of guard in the meantime while the SME intrinsics that are implemented 
incrementally? 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

2022-06-24 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 updated this revision to Diff 439919.
sagarkulkarni19 edited the summary of this revision.
sagarkulkarni19 added a comment.

Updated testcases and also added the `vnum` variant of the ld1 and st1 
intrinsics.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
  clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -101,6 +101,8 @@
 void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveRangeChecks(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
+void EmitSmeHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -80,6 +80,7 @@
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
   GenArmSveRangeChecks,
+  GenArmSmeHeader,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -217,6 +218,8 @@
"Generate arm_sve_typeflags.inc for clang"),
 clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
"Generate arm_sve_sema_rangechecks.inc for clang"),
+clEnumValN(GenArmSmeHeader, "gen-arm-sme-header",
+   "Generate arm_sme.h for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -434,6 +437,9 @@
   case GenArmSveRangeChecks:
 EmitSveRangeChecks(Records, OS);
 break;
+  case GenArmSmeHeader:
+EmitSmeHeader(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -334,6 +334,9 @@
   /// Emit arm_sve.h.
   void createHeader(raw_ostream &o);
 
+  /// Emit arm_sme.h.
+  void createSMEHeader(raw_ostream &o);
+
   /// Emit all the __builtin prototypes and code needed by Sema.
   void createBuiltins(raw_ostream &o);
 
@@ -347,7 +350,9 @@
   void createTypeFlags(raw_ostream &o);
 
   /// Create intrinsic and add it to \p Out
-  void createIntrinsic(Record *R, SmallVectorImpl> &Out);
+  void createIntrinsic(Record *R,
+   SmallVectorImpl> &Out,
+   bool IsSME = false);
 };
 
 } // end anonymous namespace
@@ -757,6 +762,11 @@
 NumVectors = 0;
 Signed = true;
 break;
+  case '%':
+Pointer = true;
+Void = true;
+NumVectors = 0;
+break;
   case 'A':
 Pointer = true;
 ElementBitwidth = Bitwidth = 8;
@@ -989,7 +999,7 @@
 }
 
 void SVEEmitter::createIntrinsic(
-Record *R, SmallVectorImpl> &Out) {
+Record *R, SmallVectorImpl> &Out, bool IsSME) {
   StringRef Name = R->getValueAsString("Name");
   StringRef Proto = R->getValueAsString("Prototype");
   StringRef Types = R->getValueAsString("Types");
@@ -1005,6 +1015,9 @@
   for (auto FlagRec : FlagsList)
 Flags |= FlagRec->getValueAsInt("Value");
 
+  bool SMEFlag = Flags & getEnumValueForFlag("IsSME");
+  if (SMEFlag != IsSME)
+return;
   // Create a dummy TypeSpec for non-overloaded builtins.
   if (Types.empty()) {
 assert((Flags & getEnumValueForFlag("IsOverloadNone")) &&
@@ -1286,11 +1299,85 @@
   OS << "#endif /* __ARM_SVE_H */\n";
 }
 
+void SVEEmitter::createSMEHeader(raw_ostream &OS) {
+  OS << "/*=== arm_sme.h - ARM SME intrinsics "
+"---===\n"
+" *\n"
+" *\n"
+" * Part of the LLVM Project, under the Apache License v2.0 with LLVM "
+"Exceptions.\n"
+" * See https://llvm.org/LICENSE.txt for license information.\n"
+" * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception\n"
+" *\n"
+

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

2022-06-24 Thread Sagar Kulkarni via Phabricator via cfe-commits 
sagarkulkarni19 marked 2 inline comments as done.
sagarkulkarni19 added inline comments.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:342
+  if (HasSME)
+Builder.defineMacro("__ARM_FEATURE_SME", "1");
+

sdesmalen wrote:
> sagarkulkarni19 wrote:
> > sdesmalen wrote:
> > > When this macro is non-zero, it suggests that the compiler implements the 
> > > full SME ACLE. That is currently not yet the case, so until then we 
> > > should leave this macro undefined.
> > Okay makes sense. But until all SME ACLE is implemented, do we need some 
> > sort of guard in the meantime while the SME intrinsics that are implemented 
> > incrementally? 
> The tests need to have manual `-D__ARM_FEATURE_SME` in the RUN lines. Once 
> the feature is implemented and we add the definition automatically when +sme 
> is specified, we update the tests. See for example D81725 where we did this 
> for SVE.
Thanks. That makes sense, now the macro is undefined and I have updated the 
testcases accordingly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127910/new/

https://reviews.llvm.org/D127910

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits