sagarkulkarni19 created this revision.
sagarkulkarni19 added reviewers: sdesmalen, rsandifo-arm, david-arm.
sagarkulkarni19 added a project: clang.
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Herald added a project: All.
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This patch adds support for the following SME ACLE intrinsics:
- svzero_mask_za
- svzero_za
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D134677
Files:
clang/include/clang/Basic/TargetBuiltins.h
clang/include/clang/Basic/arm_sve.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
clang/utils/TableGen/SveEmitter.cpp
Index: clang/utils/TableGen/SveEmitter.cpp
===================================================================
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -871,6 +871,8 @@
this->SMEAttributes = "arm_streaming, arm_shared_za, arm_preserves_za";
else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEWrite"))
this->SMEAttributes = "arm_streaming, arm_shared_za";
+ else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEZero"))
+ this->SMEAttributes = "arm_streaming_compatible, arm_shared_za";
else
llvm_unreachable("Unknown SME instruction");
} else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
@@ -0,0 +1,63 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include <arm_sme.h>
+
+// CHECK-LABEL: @test_svzero_mask_za(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 0)
+// CHECK-NEXT: ret void
+//
+// CPP-CHECK-LABEL: @_Z19test_svzero_mask_zav(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 0)
+// CPP-CHECK-NEXT: ret void
+//
+void test_svzero_mask_za() {
+ svzero_mask_za(0);
+}
+
+// CHECK-LABEL: @test_svzero_mask_za_1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 176)
+// CHECK-NEXT: ret void
+//
+// CPP-CHECK-LABEL: @_Z21test_svzero_mask_za_1v(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 176)
+// CPP-CHECK-NEXT: ret void
+//
+void test_svzero_mask_za_1() {
+ svzero_mask_za(176);
+}
+
+// CHECK-LABEL: @test_svzero_mask_za_2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 255)
+// CHECK-NEXT: ret void
+//
+// CPP-CHECK-LABEL: @_Z21test_svzero_mask_za_2v(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 255)
+// CPP-CHECK-NEXT: ret void
+//
+void test_svzero_mask_za_2() {
+ svzero_mask_za(255);
+}
+
+// CHECK-LABEL: @test_svzero_za(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 255)
+// CHECK-NEXT: ret void
+//
+// CPP-CHECK-LABEL: @_Z14test_svzero_zav(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.zero(i64 255)
+// CPP-CHECK-NEXT: ret void
+//
+void test_svzero_za() {
+ svzero_za();
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===================================================================
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4240,6 +4240,9 @@
llvm::Value *EmitSMEWrite(SVETypeFlags TypeFlags,
llvm::SmallVectorImpl<llvm::Value *> &Ops,
unsigned IntID);
+ llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
+ llvm::SmallVectorImpl<llvm::Value *> &Ops,
+ unsigned IntID);
llvm::Value *EmitSVEPrefetchLoad(const SVETypeFlags &TypeFlags,
SmallVectorImpl<llvm::Value *> &Ops,
unsigned BuiltinID);
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9122,6 +9122,18 @@
return Builder.CreateCall(F, Ops);
}
+Value *CodeGenFunction::EmitSMEZero(SVETypeFlags TypeFlags,
+ SmallVectorImpl<Value *> &Ops,
+ unsigned IntID) {
+ // svzero_za() intrinsic zeros the entire za tile and has no paramters.
+ if (Ops.size() == 0)
+ Ops.push_back(llvm::ConstantInt::get(Int64Ty, 255));
+ else
+ Ops[0] = Builder.CreateIntCast(Ops[0], Int64Ty, false);
+ Function *F = CGM.getIntrinsic(IntID, {});
+ return Builder.CreateCall(F, Ops);
+}
+
// Limit the usage of scalable llvm IR generated by the ACLE by using the
// sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat.
Value *CodeGenFunction::EmitSVEDupX(Value *Scalar, llvm::Type *Ty) {
@@ -9258,6 +9270,8 @@
return EmitSMERead(TypeFlags, Ops, Builtin->LLVMIntrinsic);
else if (TypeFlags.isSMEWrite())
return EmitSMEWrite(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+ else if (TypeFlags.isSMEZero())
+ return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
else if (TypeFlags.isGatherLoad())
return EmitSVEGatherLoad(TypeFlags, Ops, Builtin->LLVMIntrinsic);
else if (TypeFlags.isScatterStore())
Index: clang/include/clang/Basic/arm_sve.td
===================================================================
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -211,6 +211,7 @@
def IsSMESt1 : FlagType<0x2000000000>;
def IsSMERead : FlagType<0x4000000000>;
def IsSMEWrite : FlagType<0x8000000000>;
+def IsSMEZero : FlagType<0x10000000000>;
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
class ImmCheckType<int val> {
@@ -2159,3 +2160,10 @@
def SVWRITE_VER_ZA32 : SInst<"svwrite_ver_za32[_{d}]", "vimiPd", "iUif", MergeOp1, "aarch64_sme_write_vert", [IsSME, IsSMEWrite]>;
def SVWRITE_VER_ZA64 : SInst<"svwrite_ver_za64[_{d}]", "vimiPd", "lUld", MergeOp1, "aarch64_sme_write_vert", [IsSME, IsSMEWrite]>;
def SVWRITE_VER_ZA128 : SInst<"svwrite_ver_za128[_{d}]", "vimiPd", "csilUcUsUiUlhbfd", MergeOp1, "aarch64_sme_writeq_vert", [IsSME, IsSMEWrite]>;
+
+
+////////////////////////////////////////////////////////////////////////////////
+// SME - Zero
+
+def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", [IsOverloadNone, IsSME, IsSMEZero]>;
+def SVZERO_ZA : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero", [IsOverloadNone, IsSME, IsSMEZero]>;
Index: clang/include/clang/Basic/TargetBuiltins.h
===================================================================
--- clang/include/clang/Basic/TargetBuiltins.h
+++ clang/include/clang/Basic/TargetBuiltins.h
@@ -286,6 +286,7 @@
bool isSMESt1() const { return Flags & IsSMESt1; }
bool isSMERead() const { return Flags & IsSMERead; }
bool isSMEWrite() const { return Flags & IsSMEWrite; }
+ bool isSMEZero() const { return Flags & IsSMEZero; }
uint64_t getBits() const { return Flags; }
bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
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