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This patch adds support for the following SME ACLE intrinsics:
svcntsb
svcntsh
svcntsw
svcntsd
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D134679
Files:
clang/include/clang/Basic/arm_sve.td
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
clang/utils/TableGen/SveEmitter.cpp
Index: clang/utils/TableGen/SveEmitter.cpp
===================================================================
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -877,6 +877,8 @@
this->SMEAttributes = "arm_streaming_compatible, arm_shared_za";
else if (this->Flags & Emitter.getEnumValueForFlag("IsSMEStr"))
this->SMEAttributes = "arm_streaming_compatible, arm_shared_za, arm_preserves_za";
+ else if (this->Flags & Emitter.getEnumValueForFlag("IsSMECnt"))
+ this->SMEAttributes = "arm_streaming_compatible, arm_preserves_za";
else
llvm_unreachable("Unknown SME instruction");
} else
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,63 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s
+
+#include <arm_sme.h>
+
+// CHECK-LABEL: @test_svcntsb(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntsbv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+ return svcntsb();
+}
+
+// CHECK-LABEL: @test_svcntsh(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntshv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+ return svcntsh();
+}
+
+// CHECK-LABEL: @test_svcntsw(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntswv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+ return svcntsw();
+}
+
+// CHECK-LABEL: @test_svcntsd(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT: ret i64 [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z12test_svcntsdv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CPP-CHECK-NEXT: ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+ return svcntsd();
+}
Index: clang/include/clang/Basic/arm_sve.td
===================================================================
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -214,6 +214,7 @@
def IsSMEZero : FlagType<0x10000000000>;
def IsSMELdr : FlagType<0x20000000000>;
def IsSMEStr : FlagType<0x40000000000>;
+def IsSMECnt : FlagType<0x80000000000>;
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
class ImmCheckType<int val> {
@@ -2173,3 +2174,11 @@
def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", [IsOverloadNone, IsSME, IsSMEZero]>;
def SVZERO_ZA : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero", [IsOverloadNone, IsSME, IsSMEZero]>;
+
+////////////////////////////////////////////////////////////////////////////////
+// SME - Counting elements in a streaming vector
+
+def SVCNTSB : SInst<"svcntsb", "n", "", MergeNone, "aarch64_sme_cntsb", [IsOverloadNone, IsSME, IsSMECnt]>;
+def SVCNTSH : SInst<"svcntsh", "n", "", MergeNone, "aarch64_sme_cntsh", [IsOverloadNone, IsSME, IsSMECnt]>;
+def SVCNTSW : SInst<"svcntsw", "n", "", MergeNone, "aarch64_sme_cntsw", [IsOverloadNone, IsSME, IsSMECnt]>;
+def SVCNTSD : SInst<"svcntsd", "n", "", MergeNone, "aarch64_sme_cntsd", [IsOverloadNone, IsSME, IsSMECnt]>;
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