[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)
https://github.com/BeMg approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/74889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Enable target attribute when invoked through clang driver (PR #74889)
BeMg wrote: > LGTM > > Related question. If there is an -mcpu on the command line and target > attribute changes the march, do we keep the original CPU in the -target-cpu > attribute or drop it. The reason for all those negative features from the > driver was to make the backend not infer any features from the CPU that > weren't in the provided march. So I'm wondering if we have that issue with > the target attribute now. Compiler will keep target-cpu from command line when target attribute doesn't assign new cpu option. https://github.com/llvm/llvm-project/pull/74889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/75804
Address question from https://github.com/llvm/llvm-project/pull/74889
---
The target-cpu will infer its target-feature during backend codegen, it will
make TargetAttr doesn't work.
This patch implement the following override rule
by
1. When implying Full-Arch-String in target attribute, replace target-cpu with
baseline cpu to make sure backend doesn't infer other target feature.
2. Keep mcpu in tune-cpu during Attr-cpu,Attr-tune not present.
## Driver with march, mcpu
|No. | Attr-arch| Attr-cpu | Attr-tune |
target-cpu | target-feature | tune-cpu |
|---| --| |
--|-- |---| -|
|1| No |No| No | mcpu | march | No |
|2| Full-Arch-String |No| No| generic-rv32/rv64 | attr-arch
| mcpu |
|3| Full-Arch-String |Yes| No| generic-rv32/rv64 |
attr-arch | attr-cpu |
|4| Full-Arch-String |No| Yes| generic-rv32/rv64 |
attr-arch | attr-tune |
|5| Full-Arch-String |Yes| Yes| generic-rv32/rv64 |
attr-arch | attr-tune |
|6| Adding-Extension |No| No | mcpu | march + attr-arch | No |
|7| Adding-Extension |Yes| No | mcpu | march + attr-arch |
attr-cpu |
|8| Adding-Extension |No | Yes | mcpu | march + attr-arch |
attr-tune |
|9| Adding-Extension |Yes | Yes | mcpu | march + attr-arch |
attr-tune |
|10| No |Yes | No | attr-cpu | attr-cpu | No |
|11| No |Yes | Yes | attr-cpu | attr-cpu | attr-tune |
|12| No |No | Yes | mcpu | march | attr-tune |
## Note
This patch assumes that target-cpu is only used to infer target-feature and
tune-cpu in the backend. If there are other purposes for target-cpu, then this
patch need to find the alternative solution.
>From 139ab4d26badc0d43c14fc94fe73db32342cfc1e Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 17 Dec 2023 23:12:12 -0800
Subject: [PATCH] Make target-cpu override rule correct
---
clang/lib/CodeGen/CodeGenModule.cpp | 25
.../RISCV/riscv-func-attr-target-mcpu-rv32.c | 63 +++
.../RISCV/riscv-func-attr-target-mcpu-rv64.c | 63 +++
.../CodeGen/RISCV/riscv-func-attr-target.c| 10 +--
...riscv-func-target-feature-mcpu-override.ll | 36 +++
5 files changed, 192 insertions(+), 5 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
create mode 100644 clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv64.c
create mode 100644
llvm/test/CodeGen/RISCV/riscv-func-target-feature-mcpu-override.ll
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 7ad26ace328ab2..83a530f1fee45d 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2571,6 +2571,31 @@ bool
CodeGenModule::GetCPUAndFeaturesAttributes(GlobalDecl GD,
if (!ParsedAttr.Tune.empty() &&
getTarget().isValidCPUName(ParsedAttr.Tune))
TuneCPU = ParsedAttr.Tune;
+
+ if (getTarget().getTriple().isRISCV()) {
+// attr-cpu override march only if arch isn't present.
+if (TD->getFeaturesStr().contains("arch=")) {
+ // Before drop attr-cpu, keep it in tune-cpu
+ if (!TargetCPU.empty() && TuneCPU.empty())
+TuneCPU = TargetCPU;
+
+ // Reassign mcpu due to attr-arch= need
+ // target-feature from mcpu/march.
+ // Use attr-cpu will affect target-feature.
+ TargetCPU = getTarget().getTargetOpts().CPU;
+
+ // arch= need keep target feature clean,
+ // use the baseline cpu.
+ if (llvm::find(ParsedAttr.Features,
+ "__RISCV_TargetAttrNeedOverride") !=
+ ParsedAttr.Features.end())
+TargetCPU = (getTarget().getTriple().isRISCV32()) ? "generic-rv32"
+ : "generic-rv64";
+
+ if (TargetCPU == TuneCPU)
+TuneCPU = "";
+}
+ }
}
if (SD) {
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
new file mode 100644
index 00..abbeb57f54faa3
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
@@ -0,0 +1,63 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-cpu sifive-e76 -target-feature
+zifencei -target-feature +m \
+// RUN: -target-feature +a -target-feature +save-restore -target-feature -zbb
\
+// RUN: -target-feature -relax -target-feature -zfa \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define dso_local void @testDefault() #0
+void testDefault() {}
+
+// CHECK: define dso_local voi
[clang] d80e46d - [RISCV] Support target attribute for function
Author: Piyou Chen
Date: 2023-11-23T23:05:21-08:00
New Revision: d80e46da7d20645afd7b751a4e6cba9837addcb4
URL:
https://github.com/llvm/llvm-project/commit/d80e46da7d20645afd7b751a4e6cba9837addcb4
DIFF:
https://github.com/llvm/llvm-project/commit/d80e46da7d20645afd7b751a4e6cba9837addcb4.diff
LOG: [RISCV] Support target attribute for function
The proposal of target attribute is
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35
This patch implements it by emitting .option arch during codegen.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D151730
Added:
clang/test/CodeGen/RISCV/riscv-func-attr-target-err.c
clang/test/CodeGen/RISCV/riscv-func-attr-target.c
Modified:
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/Sema/SemaDeclAttr.cpp
Removed:
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 990692c06d7d3a8..6894e22da34e0c7 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -3177,6 +3177,10 @@ def warn_unsupported_target_attribute
def err_attribute_unsupported
: Error<"%0 attribute is not supported on targets missing %1;"
" specify an appropriate -march= or -mcpu=">;
+def err_duplicate_target_attribute
+: Error<"%select{unsupported|duplicate|unknown}0%select{| CPU|"
+ " tune CPU}1 '%2' in the
'%select{target|target_clones|target_version}3' "
+ "attribute string; ">;
// The err_*_attribute_argument_not_int are separate because they're used by
// VerifyIntegerConstantExpression.
def err_aligned_attribute_argument_not_int : Error<
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 0b9ebeaf5e75bbd..0ecc35f3a332a9b 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,6 +235,47 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+static std::vector
+collectNonISAExtFeature(const std::vector &FeaturesNeedOverride,
+int XLen) {
+ auto ParseResult =
+ llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride);
+
+ if (!ParseResult) {
+consumeError(ParseResult.takeError());
+return std::vector();
+ }
+
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+
+ std::vector NonISAExtFeatureVec;
+
+ llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
+[&](const std::string &Feat) {
+ return !llvm::is_contained(ImpliedFeatures, Feat);
+});
+
+ return NonISAExtFeatureVec;
+}
+
+static std::vector
+resolveTargetAttrOverride(const std::vector &FeaturesVec,
+ int XLen) {
+ auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I == FeaturesVec.end())
+return FeaturesVec;
+
+ const std::vector FeaturesNeedOverride(FeaturesVec.begin(), I);
+ std::vector NonISAExtFeature =
+ collectNonISAExtFeature(FeaturesNeedOverride, XLen);
+
+ auto ResolvedFeature = std::vector(++I, FeaturesVec.end());
+ ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
+ NonISAExtFeature.end());
+
+ return ResolvedFeature;
+}
+
bool RISCVTargetInfo::initFeatureMap(
llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector &FeaturesVec) const {
@@ -248,7 +289,10 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+ std::vector NewFeaturesVec =
+ resolveTargetAttrOverride(FeaturesVec, XLen);
+
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
if (!ParseResult) {
std::string Buffer;
llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -262,7 +306,7 @@ bool RISCVTargetInfo::initFeatureMap(
// RISCVISAInfo makes implications for ISA features
std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
// Add non-ISA features like `relax` and `save-restore` back
- for (const std::string &Feature : FeaturesVec)
+ for (const std::string &Feature : NewFeaturesVec)
if (!llvm::is_contained(ImpliedFeatures, Feature))
ImpliedFeatures.push_back(Feature);
@@ -359,3 +403,82 @@ void RISCVTargetInfo::fillValidTuneCPUList(
bool Is64Bit = getTriple().isArch64Bit();
llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
}
+
+static void handleFullArchString(StringRef FullArchStr,
+ std::vector &Features) {
+ Features.push_back("__RISCV_TargetAttrNeedOverride");
+ auto RII = llvm::RISCVISAInfo::pa
[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/75804
>From 139ab4d26badc0d43c14fc94fe73db32342cfc1e Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 17 Dec 2023 23:12:12 -0800
Subject: [PATCH 1/2] Make target-cpu override rule correct
---
clang/lib/CodeGen/CodeGenModule.cpp | 25
.../RISCV/riscv-func-attr-target-mcpu-rv32.c | 63 +++
.../RISCV/riscv-func-attr-target-mcpu-rv64.c | 63 +++
.../CodeGen/RISCV/riscv-func-attr-target.c| 10 +--
...riscv-func-target-feature-mcpu-override.ll | 36 +++
5 files changed, 192 insertions(+), 5 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
create mode 100644 clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv64.c
create mode 100644
llvm/test/CodeGen/RISCV/riscv-func-target-feature-mcpu-override.ll
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 7ad26ace328ab2..83a530f1fee45d 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -2571,6 +2571,31 @@ bool
CodeGenModule::GetCPUAndFeaturesAttributes(GlobalDecl GD,
if (!ParsedAttr.Tune.empty() &&
getTarget().isValidCPUName(ParsedAttr.Tune))
TuneCPU = ParsedAttr.Tune;
+
+ if (getTarget().getTriple().isRISCV()) {
+// attr-cpu override march only if arch isn't present.
+if (TD->getFeaturesStr().contains("arch=")) {
+ // Before drop attr-cpu, keep it in tune-cpu
+ if (!TargetCPU.empty() && TuneCPU.empty())
+TuneCPU = TargetCPU;
+
+ // Reassign mcpu due to attr-arch= need
+ // target-feature from mcpu/march.
+ // Use attr-cpu will affect target-feature.
+ TargetCPU = getTarget().getTargetOpts().CPU;
+
+ // arch= need keep target feature clean,
+ // use the baseline cpu.
+ if (llvm::find(ParsedAttr.Features,
+ "__RISCV_TargetAttrNeedOverride") !=
+ ParsedAttr.Features.end())
+TargetCPU = (getTarget().getTriple().isRISCV32()) ? "generic-rv32"
+ : "generic-rv64";
+
+ if (TargetCPU == TuneCPU)
+TuneCPU = "";
+}
+ }
}
if (SD) {
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
new file mode 100644
index 00..abbeb57f54faa3
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target-mcpu-rv32.c
@@ -0,0 +1,63 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-cpu sifive-e76 -target-feature
+zifencei -target-feature +m \
+// RUN: -target-feature +a -target-feature +save-restore -target-feature -zbb
\
+// RUN: -target-feature -relax -target-feature -zfa \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: define dso_local void @testDefault() #0
+void testDefault() {}
+
+// CHECK: define dso_local void @testFullArchOnly() #1
+__attribute__((target("arch=rv32imac"))) void
+testFullArchOnly() {}
+
+// CHECK: define dso_local void @testFullArchAndCpu() #2
+__attribute__((target("arch=rv32imac;cpu=sifive-e34"))) void
+testFullArchAndCpu() {}
+
+// CHECK: define dso_local void @testFullArchAndTune() #2
+__attribute__((target("arch=rv32imac;tune=sifive-e34"))) void
+testFullArchAndTune() {}
+
+// CHECK: define dso_local void @testFullArchAndCpuAndTune() #2
+__attribute__((target("arch=rv32imac;cpu=sifive-e31;tune=sifive-e34"))) void
+testFullArchAndCpuAndTune() {}
+
+// CHECK: define dso_local void @testAddExtOnly() #3
+__attribute__((target("arch=+v"))) void
+testAddExtOnly() {}
+
+// CHECK: define dso_local void @testAddExtAndCpu() #4
+__attribute__((target("arch=+v;cpu=sifive-e31"))) void
+testAddExtAndCpu() {}
+
+// CHECK: define dso_local void @testAddExtAndTune() #4
+__attribute__((target("arch=+v;tune=sifive-e31"))) void
+testAddExtAndTune() {}
+
+// CHECK: define dso_local void @testAddExtAndCpuAndTune() #5
+__attribute__((target("arch=+v;cpu=sifive-e31;tune=sifive-e34"))) void
+testAddExtAndCpuAndTune() {}
+
+// CHECK: define dso_local void @testCpuOnly() #6
+__attribute__((target("cpu=sifive-e31"))) void
+testCpuOnly() {}
+
+// CHECK: define dso_local void @testCpuAndTune() #7
+__attribute__((target("cpu=sifive-e31;tune=sifive-e34"))) void
+testCpuAndTune() {}
+
+// CHECK: define dso_local void @testTuneOnly() #8
+__attribute__((target("tune=sifive-e34"))) void
+testTuneOnly() {}
+
+// .
+// CHECK: attributes #0 = { {{.*}}"target-cpu"="sifive-e76"
"target-features"="+32bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="generic-rv32"
"target-features"="+32bit,+a,+c,+m,+save-restore,-relax,-zbb,-zfa"
"tune-cpu"="sifive-e76" }
+// CHECK: attributes #2 = { {{.*}}"target-cpu"="generic-rv32"
"target-features"="+
[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
https://github.com/BeMg approved this pull request. https://github.com/llvm/llvm-project/pull/76962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/85786
This patch enable the function multiversion(FMV) and `target_clones` attribute
for RISC-V target.
It will emit the IFUNC resolver function to select appropriate function during
runtime.
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/lib/AST/ASTContext.cpp | 9 ++
clang/lib/Basic/Targets/RISCV.cpp | 10 +-
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 23 +++
clang/lib/Sema/SemaDeclAttr.cpp | 22 +++
clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
.../CodeGenCXX/attr-target-clones-riscv.cpp | 136 ++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 19 +++
12 files changed, 462 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
} else {
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
if (I != FeaturesVec.end()) {
std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
@@ -366,6 +366,12 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
return true;
}
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+ if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+ Features.push_back("+__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -10
[clang] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: Inside the resolver function, a function named `__riscv_ifunc_select` is used to ensure that all additional extension requirements are met. It is temporary interface until proposal be ratified. ``` bool __riscv_ifunc_select(char *FeatureStr); ``` https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: The candidate function priority order is undefined. Currently, it base on declaration order. https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote:
The warning occurs because the RISC-V target_clones syntax
`__attribute__((target_clones("default", "arch=+zba,+v,+c,+zicond",
"arch=+zbb,+c,+v")))` contains a comma inside double quotes.
```
warning: mixing 'target_clones' specifier mechanisms is permitted for GCC
compatibility;
use a comma separated sequence of string literals, or a string literal
containing a comma-separated list of versions
```
Should we suppress this warning for RISC-V target? Or change the target_clones
syntax?
https://github.com/llvm/llvm-project/pull/85786
___
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[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/85899
For RISC-V target only `target_clones` and `target_version` can enable function
multiversion(FMV).
This patch make target attribute trigger redefinition instead of emit FMV.
>From 0bbffb92e7f36957c042cab9a67a483571d9b3f9 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH] [RISCV] Disallow target attribute use in multiversioning
---
clang/lib/Sema/SemaDecl.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 5850cd0ab6b9aa..e543aff77e67ea 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11853,6 +11853,10 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
return false;
+ // Target attribute on RISCV is not used for multiversioning
+ if (NewTA && S.getASTContext().getTargetInfo().getTriple().isRISCV())
+return false;
+
if (!OldDecl || !OldDecl->getAsFunction() ||
OldDecl->getDeclContext()->getRedeclContext() !=
NewFD->getDeclContext()->getRedeclContext()) {
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[clang] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/2] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/lib/AST/ASTContext.cpp | 9 ++
clang/lib/Basic/Targets/RISCV.cpp | 10 +-
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 23 +++
clang/lib/Sema/SemaDeclAttr.cpp | 22 +++
clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
.../CodeGenCXX/attr-target-clones-riscv.cpp | 136 ++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 19 +++
12 files changed, 462 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
} else {
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
if (I != FeaturesVec.end()) {
std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
@@ -366,6 +366,12 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
return true;
}
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+ if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+ Features.push_back("+__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
bool handleTargetFeatures(std::vector &Features,
DiagnosticsEngine &Diags) override;
+ bool is
[clang] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg ready_for_review https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: The proposal can be found at the https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48. https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg ready_for_review https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
BeMg wrote: The proposal could be found here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48. https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/4] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/lib/AST/ASTContext.cpp | 9 ++
clang/lib/Basic/Targets/RISCV.cpp | 10 +-
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 23 +++
clang/lib/Sema/SemaDeclAttr.cpp | 22 +++
clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
.../CodeGenCXX/attr-target-clones-riscv.cpp | 136 ++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 19 +++
12 files changed, 462 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
} else {
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
if (I != FeaturesVec.end()) {
std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
@@ -366,6 +366,12 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
return true;
}
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+ if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+ Features.push_back("+__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
bool handleTargetFeatures(std::vector &Features,
DiagnosticsEngine &Diags) override;
+ bool is
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: 1. Suppress the warning `warn_target_clone_mixed_values` for RISC-V 2. Update `__riscv_ifunc_select`. From `__riscv_ifunc_select(char *)` into `__riscv_ifunc_select(unsigned long long, unsigned long long )`. 3. Add one more error messenge when there are +extension that hwprobe can't detect. https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85899
>From 0bbffb92e7f36957c042cab9a67a483571d9b3f9 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH 1/2] [RISCV] Disallow target attribute use in multiversioning
---
clang/lib/Sema/SemaDecl.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 5850cd0ab6b9aa..e543aff77e67ea 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11853,6 +11853,10 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
return false;
+ // Target attribute on RISCV is not used for multiversioning
+ if (NewTA && S.getASTContext().getTargetInfo().getTriple().isRISCV())
+return false;
+
if (!OldDecl || !OldDecl->getAsFunction() ||
OldDecl->getDeclContext()->getRedeclContext() !=
NewFD->getDeclContext()->getRedeclContext()) {
>From f0057a2c65a030fc5afa30dee4b08c71cf3451bd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 1 Apr 2024 23:21:25 -0700
Subject: [PATCH 2/2] Add testcase
---
clang/test/Sema/attr-target-riscv.c | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 clang/test/Sema/attr-target-riscv.c
diff --git a/clang/test/Sema/attr-target-riscv.c
b/clang/test/Sema/attr-target-riscv.c
new file mode 100644
index 00..ed4e2915d6c6ef
--- /dev/null
+++ b/clang/test/Sema/attr-target-riscv.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -fsyntax-only
-verify -std=c2x %s
+
+//expected-note@+1 {{previous definition is here}}
+int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
+//expected-error@+1 {{redefinition of 'foo'}}
+int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
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[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
BeMg wrote:
This code section will make clang violate target attribute syntax specification.
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#__attribute__targetattr-string
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include
+
+void test_builtin() {
+ __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_rvv_vsetvli' needs
target feature zve32x}}
+}
+
+__attribute__((target("+zve32x")))
BeMg wrote:
Base on
[spec](https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#__attribute__targetattr-string),
this target attribute should update as
`__attribute__((target("arch=+zve32x")))`
https://github.com/llvm/llvm-project/pull/83674
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[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/7] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..38de95e4fbf7aa4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a7956..865ca48aeb90d1a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if du
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt,
+MapVector> &SeenExtMap,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if duplicated extension.
+ if (!IgnoreUnknown && (SeenExtMap.find(Name.str()) != SeenExtMap.end()))
BeMg wrote:
Done
https://github.com/llvm/llvm-project/pull/78120
___
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cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
@@ -695,6 +696,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt,
+MapVector> &SeenExtMap,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if duplicated extension.
+ if (!IgnoreUnknown && (SeenExtMap.find(Name.str()) != SeenExtMap.end()))
+return createStringError(errc::invalid_argument, "duplicated %s '%s'",
+ Desc.str().c_str(), Name.str().c_str());
+
+ if (IgnoreUnknown && !RISCVISAInfo::isSupportedExtension(Name))
+return Error::success();
+
+ SeenExtMap[Name.str()] = {Major, Minor};
+ return Error::success();
+}
+
+static Error processSingleLetterExtension(
+StringRef &RawExt,
+MapVector> &SeenExtMap,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ unsigned Major, Minor, ConsumeLength;
+ StringRef Name = RawExt.take_front(1);
+ RawExt.consume_front(Name);
+ if (auto E = getExtensionVersion(Name, RawExt, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ RawExt = RawExt.substr(ConsumeLength);
+ return Error::success();
+}
+return E;
+ }
+
+ RawExt = RawExt.substr(ConsumeLength);
+
+ // Check if duplicated extension.
+ if (!IgnoreUnknown && (SeenExtMap.find(Name.str()) != SeenExtMap.end()))
BeMg wrote:
Done
https://github.com/llvm/llvm-project/pull/78120
___
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cfe-commits@lists.llvm.org
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[clang] [clang-tools-extra] [llvm] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/7] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..38de95e4fbf7aa4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a7956..865ca48aeb90d1a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if du
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 7ad5726d93e957050723a7df7a8384bc9ff694b3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/8] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..38de95e4fbf7aa4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 3c02492e99f1db4..06579c20b2637a2 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -703,6 +703,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if du
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 7ad5726d93e957050723a7df7a8384bc9ff694b3 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b6..38de95e4fbf7aa 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 3c02492e99f1db..06579c20b2637a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -703,6 +703,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if duplic
[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From aaee7cfdea325459d68bc4e7205d7e25ca045d1a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..38de95e4fbf7aa4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a359e6eefa8f1d1..fa2a9ae283b45d1 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -707,6 +707,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if du
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 8f7b429d2f7fe791a2a469e3d232d33abba1bef8 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 295 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 174 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..38de95e4fbf7aa4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 9a716f7aff1cc94..5674de804f6bb58 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -704,6 +704,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if du
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From f3444e9f434a5084b16ad25981428549c5b2e151 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/9] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 295 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 174 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b..38de95e4fbf7a 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index c46d76da962c6..61ac5769b5d33 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -703,6 +703,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if duplicated
[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/78120
Address the https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14
This patch relax the `-march` string for accept any order.
1. single-letter extension can be arbitrary order
- march=rv32iamdf
2. single-letter extension and multi-letter extension can be mixed
- march=rv32i_zihintntl_m_a_f_d_svinval
3. multi-letter extension need seperate the following extension by underscore,
otherwise it will be intreprete as one extension.
- march=rv32i_zbam -> i,zbam
- march=rv32i_zba_m -> i,zba,m
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b6..38de95e4fbf7aa 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a795..865ca48aeb90d1 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/4] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b6..38de95e4fbf7aa 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a795..865ca48aeb90d1 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if duplic
[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
@@ -785,153 +878,61 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
Minor = Version->Minor;
}
-ISAInfo->addExtension(StringRef(&Baseline, 1), {Major, Minor});
+// Postpone AddExtension until end of this function
+SeenExts.push_back(StringRef(&Baseline, 1).str());
+ExtsVersion.push_back({Major, Minor});
}
// Consume the base ISA version number and any '_' between rvxxx and the
// first extension
Exts = Exts.drop_front(ConsumeLength);
Exts.consume_front("_");
- auto StdExtsItr = StdExts.begin();
- auto StdExtsEnd = StdExts.end();
- auto GoToNextExt = [](StringRef::iterator &I, unsigned ConsumeLength,
-StringRef::iterator E) {
-I += 1 + ConsumeLength;
-if (I != E && *I == '_')
- ++I;
- };
- for (auto I = Exts.begin(), E = Exts.end(); I != E;) {
-char C = *I;
-
-// Check ISA extensions are specified in the canonical order.
-while (StdExtsItr != StdExtsEnd && *StdExtsItr != C)
- ++StdExtsItr;
-
-if (StdExtsItr == StdExtsEnd) {
- // Either c contains a valid extension but it was not given in
- // canonical order or it is an invalid extension.
- if (StdExts.contains(C)) {
-return createStringError(
-errc::invalid_argument,
-"standard user-level extension not given in canonical order '%c'",
-C);
- }
-
- return createStringError(errc::invalid_argument,
- "invalid standard user-level extension '%c'",
C);
-}
-
-// Move to next char to prevent repeated letter.
-++StdExtsItr;
-
-StringRef Next;
-unsigned Major, Minor, ConsumeLength;
-if (std::next(I) != E)
- Next = StringRef(std::next(I), E - std::next(I));
-if (auto E = getExtensionVersion(StringRef(&C, 1), Next, Major, Minor,
- ConsumeLength,
EnableExperimentalExtension,
- ExperimentalExtensionVersionCheck)) {
- if (IgnoreUnknown) {
-consumeError(std::move(E));
-GoToNextExt(I, ConsumeLength, Exts.end());
-continue;
- }
- return std::move(E);
-}
-
-// The order is OK, then push it into features.
-// Currently LLVM supports only "mafdcvh".
-if (!isSupportedExtension(StringRef(&C, 1))) {
- if (IgnoreUnknown) {
-GoToNextExt(I, ConsumeLength, Exts.end());
-continue;
- }
- return createStringError(errc::invalid_argument,
- "unsupported standard user-level extension
'%c'",
- C);
-}
-ISAInfo->addExtension(StringRef(&C, 1), {Major, Minor});
-
-// Consume full extension name and version, including any optional '_'
-// between this extension and the next
-GoToNextExt(I, ConsumeLength, Exts.end());
- }
-
- // Handle other types of extensions other than the standard
- // general purpose and standard user-level extensions.
- // Parse the ISA string containing non-standard user-level
- // extensions, standard supervisor-level extensions and
- // non-standard supervisor-level extensions.
- // These extensions start with 'z', 's', 'x' prefixes, might have a version
BeMg wrote:
Comment has been restored.
https://github.com/llvm/llvm-project/pull/78120
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[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
@@ -156,9 +156,8 @@ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s // RV32L: error: invalid arch name 'rv32l' -// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \ -// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s -// RV32IMADF: error: invalid arch name 'rv32imadf' +// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \ +// RUN: -fsyntax-only 2>&1 | FileCheck %s BeMg wrote: Add two more space for some RUN LINE. https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
@@ -337,10 +319,79 @@ TEST(ParseArchString,
AcceptsUnderscoreSplittingExtensions) {
}
}
+TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) {
+ for (StringRef Input :
+ {"rv32imfad", "rv32im_fa_d", "rv32im2p0fad", "rv32i2p1m2p0fad"}) {
+auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
+ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
+RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
+EXPECT_EQ(Exts.size(), 6UL);
+EXPECT_EQ(Exts.count("i"), 1U);
+EXPECT_EQ(Exts.count("m"), 1U);
+EXPECT_EQ(Exts.count("f"), 1U);
+EXPECT_EQ(Exts.count("a"), 1U);
+EXPECT_EQ(Exts.count("d"), 1U);
+EXPECT_EQ(Exts.count("zicsr"), 1U);
+ }
+}
+
+TEST(ParseArchString, AcceptsRelaxMixedLetterExtensions) {
+ for (StringRef Input :
+ {"rv32i_zihintntl_m_a_f_d_svinval", "rv32izihintntl_mafdsvinval",
+"rv32i_zihintntl_mafd_svinval"}) {
+auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);
+ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
+RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
+EXPECT_EQ(Exts.size(), 8UL);
+EXPECT_EQ(Exts.count("i"), 1U);
+EXPECT_EQ(Exts.count("m"), 1U);
+EXPECT_EQ(Exts.count("a"), 1U);
+EXPECT_EQ(Exts.count("f"), 1U);
+EXPECT_EQ(Exts.count("d"), 1U);
+EXPECT_EQ(Exts.count("zihintntl"), 1U);
+EXPECT_EQ(Exts.count("svinval"), 1U);
+EXPECT_EQ(Exts.count("zicsr"), 1U);
+ }
+}
+
+TEST(ParseArchString, AcceptsAmbiguousFromRelaxExtensions) {
+ for (StringRef Input : {"rv32i_zba_m", "rv32izba_m", "rv32izba1p0_m2p0"}) {
BeMg wrote:
Add three testcases
```
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv32zba_im", true).takeError()),
"first letter should be 'e', 'i' or 'g'");
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv32izbai_m", true).takeError()),
"unsupported standard user-level extension 'zbai'");
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv32izbaim", true).takeError()),
"unsupported standard user-level extension 'zbaim'");
```
https://github.com/llvm/llvm-project/pull/78120
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[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/78120
>From 88eef23588b545f29f3fe62a702ed2121b53c7cd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 14 Jan 2024 19:41:59 -0800
Subject: [PATCH 1/6] [RISCV] Relax march string order constraint
---
clang/test/Driver/riscv-arch.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 297 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 91 --
3 files changed, 226 insertions(+), 176 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index 0ac81ea982f1b61..38de95e4fbf7aa4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -156,9 +156,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32L %s
// RV32L: error: invalid arch name 'rv32l'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMADF %s
-// RV32IMADF: error: invalid arch name 'rv32imadf'
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32IMM %s
@@ -184,9 +183,8 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64L %s
// RV64L: error: invalid arch name 'rv64l'
-// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMADF %s
-// RV64IMADF: error: invalid arch name 'rv64imadf'
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64imadf -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck %s
// RUN: not %clang --target=riscv64-unknown-elf -march=rv64imm -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64IMM %s
@@ -216,7 +214,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
// RV32-ORDER: error: invalid arch name 'rv32imcq',
-// RV32-ORDER: standard user-level extension not given in canonical order 'q'
+// RV32-ORDER: unsupported standard user-level extension 'q'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
@@ -318,7 +316,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_a -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-PREFIX %s
// RV32-PREFIX: error: invalid arch name 'rv32ixabc_a',
-// RV32-PREFIX: invalid extension prefix 'a'
+// RV32-PREFIX: unsupported non-standard user-level extension 'xabc'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a7956..865ca48aeb90d1a 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
+ SmallVector Split;
+ if (Exts.empty())
+return Error::success();
+
+ Exts.split(Split, "_");
+
+ for (auto Ext : Split) {
+if (Ext.empty())
+ return createStringError(errc::invalid_argument,
+ "extension name missing after separator '_'");
+
+SplitedExts.push_back(Ext.str());
+ }
+ return Error::success();
+}
+
+static Error processMultiLetterExtension(
+StringRef RawExt, SmallVector &SeenExts,
+SmallVector &ExtsVersion,
+bool IgnoreUnknown, bool EnableExperimentalExtension,
+bool ExperimentalExtensionVersionCheck) {
+ StringRef Type = getExtensionType(RawExt);
+ StringRef Desc = getExtensionTypeDesc(RawExt);
+ auto Pos = findLastNonVersionCharacter(RawExt) + 1;
+ StringRef Name(RawExt.substr(0, Pos));
+ StringRef Vers(RawExt.substr(Pos));
+
+ if (Type.empty()) {
+if (IgnoreUnknown)
+ return Error::success();
+return createStringError(errc::invalid_argument,
+ "invalid extension prefix '" + RawExt + "'");
+ }
+
+ if (!IgnoreUnknown && Name.size() == Type.size())
+return createStringError(errc::invalid_argument,
+ "%s name missing after '%s'", Desc.str().c_str(),
+ Type.str().c_str());
+
+ unsigned Major, Minor, ConsumeLength;
+ if (auto E = getExtensionVersion(Name, Vers, Major, Minor, ConsumeLength,
+ EnableExperimentalExtension,
+ ExperimentalExtensionVersionCheck)) {
+if (IgnoreUnknown) {
+ consumeError(std::move(E));
+ return Error::success();
+}
+return E;
+ }
+
+ // Check if du
[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
@@ -695,6 +695,106 @@ RISCVISAInfo::parseNormalizedArchString(StringRef Arch) {
return std::move(ISAInfo);
}
+static Error splitExtsByUnderscore(StringRef Exts,
+ std::vector &SplitedExts) {
BeMg wrote:
Done
https://github.com/llvm/llvm-project/pull/78120
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[clang] [llvm] [RISCV] Relax march string order constraint (PR #78120)
@@ -715,6 +815,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, unsigned XLen = HasRV64 ? 64 : 32; std::unique_ptr ISAInfo(new RISCVISAInfo(XLen)); + SmallVector SeenExts; BeMg wrote: Use MapVector instead of SmallVector https://github.com/llvm/llvm-project/pull/78120 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/75804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Update TargetAttr target-cpu override rule (PR #75804)
BeMg wrote: Close due to land https://github.com/llvm/llvm-project/pull/77426 https://github.com/llvm/llvm-project/pull/75804 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] f8b8426 - [RISCV] Add Svnapot extension
Author: Piyou Chen
Date: 2022-10-24T01:27:04-07:00
New Revision: f8b8426861a7a26ff60fe085800cc338591bee41
URL:
https://github.com/llvm/llvm-project/commit/f8b8426861a7a26ff60fe085800cc338591bee41
DIFF:
https://github.com/llvm/llvm-project/commit/f8b8426861a7a26ff60fe085800cc338591bee41.diff
LOG: [RISCV] Add Svnapot extension
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D136570
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index c1c29da5e18b0..725d722bfc952 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -39,6 +39,7 @@
// CHECK-NOT: __riscv_zk
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
+// CHECK-NOT: __riscv_svnapot
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -418,3 +419,9 @@
// RUN: -march=rv64iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32isvnapot -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
+// RUN: %clang -target riscv64 -march=rv64isvnapot -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
+// CHECK-SVNAPOT-EXT: __riscv_svnapot 100{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 9cf7e04713655..ff5f1d7475189 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -101,6 +101,8 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
+
+{"svnapot", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 822b2c44c2309..a5c9f97d68a34 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -388,6 +388,10 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of
FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch
Instructions)">;
+def FeatureStdExtSvnapot
+: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+ "'Svnapot' (NAPOT Translation Contiguity)">;
+
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h
b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 89fb7cb212a87..f0980ea08e081 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZicbom = false;
bool HasStdExtZicboz = false;
bool HasStdExtZicbop = false;
+ bool HasStdExtSvnapot = false;
bool HasStdExtZmmul = false;
bool HasStdExtZawrs = false;
bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZicbom() const { return HasStdExtZicbom; }
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+ bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
bool hasStdExtZawrs() const { return HasStdExtZawrs; }
bool hasStdExtZmmul() const { return HasStdExtZmmul; }
bool hasStdExtZtso() const { return HasStdExtZtso; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 4136c6f37a16e..45dd8679292d5 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck
--check-prefix=RV32ZICBOM %s
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck
--check-prefix=RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck
--check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck
--check-prefix=RV32SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M
%s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck
--check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck
--check-prefix=R
[clang] 7d7940f - [RISCV] add svinval extension
Author: Piyou Chen
Date: 2022-10-26T09:45:30-07:00
New Revision: 7d7940fd7761e21b68f915e948389b87835d1304
URL:
https://github.com/llvm/llvm-project/commit/7d7940fd7761e21b68f915e948389b87835d1304
DIFF:
https://github.com/llvm/llvm-project/commit/7d7940fd7761e21b68f915e948389b87835d1304.diff
LOG: [RISCV] add svinval extension
1. Add the svinval extension support
2. Add the svinval Predicates for its instruction
Note: the svinval instructions defined in https://reviews.llvm.org/D117654
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D136571
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/priv-valid.s
Removed:
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 725d722bfc952..2d4aed24002e0 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -40,6 +40,7 @@
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svinval
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -425,3 +426,9 @@
// RUN: %clang -target riscv64 -march=rv64isvnapot -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
// CHECK-SVNAPOT-EXT: __riscv_svnapot 100{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32isvinval -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
+// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
+// CHECK-SVINVAL-EXT: __riscv_svinval 100{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index f5234ec0fcb30..387f2c29d26dc 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -52,6 +52,7 @@ on support follow.
``D``Supported
``F``Supported
``M``Supported
+ ``Svinval`` Assembly Support
``V``Supported
``Zba`` Supported
``Zbb`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index ff5f1d7475189..1a899616ade94 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zicbop", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}},
+{"svinval", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index a5c9f97d68a34..3813769a73dc7 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -392,6 +392,13 @@ def FeatureStdExtSvnapot
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
+def FeatureStdExtSvinval
+: SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
+ "'Svinval' (Fine-Grained Address-Translation Cache
Invalidation)">;
+def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
+AssemblerPredicate<(all_of
FeatureStdExtSvinval),
+"'Svinval' (Fine-Grained Address-Translation
Cache Invalidation)">;
+
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index fb3bcf429d9a0..12bd105053e7a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,6 +796,7 @@ def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
let rs2 = 0b00101;
}
+let Predicates = [HasStdExtSvinval] in {
def SFENCE_W_INVAL : Priv<"sfence.w.inval", 0b0001100>, Sched<[]> {
let rd = 0;
let rs1 = 0;
@@ -807,13 +808,14 @@ def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>,
Sched<[]> {
let rs1 = 0;
let rs2 = 0b1;
}
+def SINVAL_VMA : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
+def HINVAL_VVMA : Priv_rr<"hinval.vvma", 0b0010011>, Sched<[]>;
+def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
+} // Predicates = [HasStdExtSvinval]
def SFENCE_VMA : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>;
-def SINVAL_VMA : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
def HFENCE_VVMA :
[clang] 0d4c650 - [RISCV] Refactor RVV Policy by structure
Author: Piyou Chen
Date: 2022-12-20T01:13:13-08:00
New Revision: 0d4c6506100b339311283c10d841d7693287666a
URL:
https://github.com/llvm/llvm-project/commit/0d4c6506100b339311283c10d841d7693287666a
DIFF:
https://github.com/llvm/llvm-project/commit/0d4c6506100b339311283c10d841d7693287666a.diff
LOG: [RISCV] Refactor RVV Policy by structure
RVV intrinsic function has several policy variants.
Include TU, TA, TAMU, TAMA, TUMU, TUMA, MU, MA, TUM, TAM
Currently, the clang side enumerates these policies, but it's hard to add a new
policy.
This patch use structure to replace the origin policy enumeration, and enhance
some policy transform logic.
This is a clean-up job that will not affect the RVV intrinsic functionality and
make sure riscv_vector_builtin_cg.inc is the same as the original one.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D139995
Added:
Modified:
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/lib/Support/RISCVVIntrinsicUtils.cpp
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index a3a2a3c068604..8f37aa783aca3 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -92,19 +92,80 @@ enum class TypeModifier : uint8_t {
LLVM_MARK_AS_BITMASK_ENUM(LMUL1),
};
-// The Lowerest two bit equal to policy value.
-enum Policy : uint8_t {
- TU = 0, // For unmasked TU, last two bit is TUMU
- TA = 1, // // For unmasked TA, last two bit is TAMU
- TUMA = 2,
- TAMA = 3,
- TUMU = 4,
- TAMU = 5,
- MU = 6, // For masked MU, last two bit is TAMU
- MA = 7, // For masked MA, last two bit is TAMA
- TUM = 10, // For masked MA, last two bit is TUMA
- TAM = 11, // For masked MA, last two bit is TAMA
- PolicyNone,
+struct Policy {
+ bool PolicyNone = false;
+ enum PolicyType {
+Undisturbed,
+Agnostic,
+Omit, // No policy required.
+ };
+ PolicyType TailPolicy = Omit;
+ PolicyType MaskPolicy = Omit;
+ bool IntrinsicWithoutMU = false;
+ Policy() : PolicyNone(true) {}
+ Policy(PolicyType _TailPolicy, PolicyType _MaskPolicy,
+ bool _IntrinsicWithoutMU = false)
+ : TailPolicy(_TailPolicy), MaskPolicy(_MaskPolicy),
+IntrinsicWithoutMU(_IntrinsicWithoutMU) {}
+
+ bool isTAMAPolicy() const {
+return TailPolicy == Agnostic && MaskPolicy == Agnostic;
+ }
+
+ bool isTAMUPolicy() const {
+return TailPolicy == Agnostic && MaskPolicy == Undisturbed;
+ }
+
+ bool isTUMAPolicy() const {
+return TailPolicy == Undisturbed && MaskPolicy == Agnostic;
+ }
+
+ bool isTUMUPolicy() const {
+return TailPolicy == Undisturbed && MaskPolicy == Undisturbed;
+ }
+
+ bool isTUMPolicy() const {
+return TailPolicy == Undisturbed && MaskPolicy == Agnostic &&
+ IntrinsicWithoutMU;
+ }
+
+ bool isTAMPolicy() const {
+return TailPolicy == Agnostic && MaskPolicy == Agnostic &&
+ IntrinsicWithoutMU;
+ }
+
+ bool isTAPolicy() const {
+return TailPolicy == Agnostic && MaskPolicy == Omit;
+ }
+
+ bool isTUPolicy() const {
+return TailPolicy == Undisturbed && MaskPolicy == Omit;
+ }
+
+ bool isMAPolicy() const {
+return MaskPolicy == Agnostic && TailPolicy == Omit;
+ }
+
+ bool isMUPolicy() const {
+return MaskPolicy == Undisturbed && TailPolicy == Omit;
+ }
+
+ bool isPolicyNonePolicy() const { return PolicyNone; }
+
+ bool operator==(const Policy &Other) const {
+return PolicyNone == Other.PolicyNone && TailPolicy == Other.TailPolicy &&
+ MaskPolicy == Other.MaskPolicy &&
+ IntrinsicWithoutMU == Other.IntrinsicWithoutMU;
+ }
+
+ bool operator!=(const Policy &Other) const { return !(*this == Other); }
+
+ bool operator<(const Policy &Other) const {
+// Just for maintain the old order for quick test.
+if (MaskPolicy != Other.MaskPolicy)
+ return Other.MaskPolicy < MaskPolicy;
+return TailPolicy < Other.TailPolicy;
+ }
};
// PrototypeDescriptor is used to compute type info of arguments or return
@@ -333,7 +394,7 @@ class RVVIntrinsic {
// InputTypes. -1 means the return type.
std::vector IntrinsicTypes;
unsigned NF = 1;
- Policy DefaultPolicy = Policy::PolicyNone;
+ Policy DefaultPolicy;
public:
RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix,
@@ -373,12 +434,33 @@ class RVVIntrinsic {
return IntrinsicTypes;
}
Policy getDefaultPolicy() const {
-assert(DefaultPolicy != Policy::PolicyNone);
+assert(DefaultPolicy.PolicyNone == false);
return DefaultPolicy;
}
unsigned getDefaultPolicyBits() const {
-assert(DefaultPolicy != Policy::PolicyNone);
-return static_cast(DefaultPolicy) & 3;
+// Return following value.
+// constexpr unsig
[clang] 5370255 - [RISCV] Merge Masked and unMasked RVV manual codegen
Author: Piyou Chen
Date: 2022-12-21T20:28:12-08:00
New Revision: 5370255ff18ac101a73685b77615148142ee7552
URL:
https://github.com/llvm/llvm-project/commit/5370255ff18ac101a73685b77615148142ee7552
DIFF:
https://github.com/llvm/llvm-project/commit/5370255ff18ac101a73685b77615148142ee7552.diff
LOG: [RISCV] Merge Masked and unMasked RVV manual codegen
RVV intrinsic function will generate riscv_vector_builtin_cg.inc for
CGBuiltin.cpp to produce the corresponding RVV intrinsic LLVM IR.
In this stage, riscv_vector.td will describe the bunch of manual codegen C++
code to tell CGBuiltin how to handle these instructions.
In this patch, we merge the masked RVV manual codegen and unmasked RVV manual
codegen to reduce the number of manual codegen, and make more policy addition
easier in the future.
This is a clean-up job that will not affect the RVV intrinsic functionality.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D140361
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 90e18df0403e0..7dbd331b2c5ec 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -217,7 +217,6 @@ class RVVBuiltin types> {
UnMaskedPolicyScheme = HasPassthruOperand,
ManualCodegen = [{
{
-if (DefaultPolicy == TAIL_AGNOSTIC)
- Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-IntrinsicTypes = {ResultType, Ops[3]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-Value *NewVL = Ops[2];
-Ops.erase(Ops.begin() + 2);
-llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
-llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
-llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
-// Store new_vl.
-clang::CharUnits Align =
-CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
-llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
-Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
-return V;
- }
- }],
- MaskedManualCodegen = [{
- {
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
- Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
+if (IsMasked) {
+ // Move mask to right before vl.
+ std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+ if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+ Ops.push_back(ConstantInt::get(Ops.back()->getType(),
DefaultPolicy));
+ IntrinsicTypes = {ResultType, Ops[4]->getType()};
+} else {
+ if (DefaultPolicy == TAIL_AGNOSTIC)
+Ops.insert(Ops.begin(), llvm::PoisonValue::get(ResultType));
+ IntrinsicTypes = {ResultType, Ops[3]->getType()};
+}
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
Value *NewVL = Ops[2];
Ops.erase(Ops.begin() + 2);
@@ -659,8 +645,11 @@ multiclass RVVVLEFFBuiltin types> {
llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
// Store new_vl.
-clang::CharUnits Align = CGM.getNaturalPointeeTypeAlignment(
-E->getArg(E->getNumArgs()-2)->getType());
+clang::CharUnits Align;
+if (IsMasked)
+ Align =
CGM.getNaturalPointeeTypeAlignment(E->getArg(E->getNumArgs()-2)->getType());
+else
+ Align = CGM.getNaturalPointeeTypeAlignment(E->getArg(1)->getType());
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
return V;
@@ -720,16 +709,18 @@ multiclass RVVIndexedLoad {
let HasMaskedOffOperand = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
- // Builtin: (ptr, value, vl). Intrinsic: (value, ptr, vl)
- std::swap(Ops[0], Ops[1]);
- Ops[1] = Builder.CreateBitCast(Ops[1],
Ops[0]->getType()->getPointerTo());
- IntrinsicTypes = {Ops[0]->getType(), Ops[2]->getType()};
-}],
-MaskedManualCodegen= [{
- // Builtin: (mask, ptr, value, vl). Intrinsic: (value, ptr, mask, vl)
- std::swap(Ops[0], Ops[2]);
+ if (IsMasked) {
+// Builtin: (mask, ptr, value, vl). Intrins
[clang] 2df05cd - [RISCV] Support overloaded version ntlh intrinsic function
Author: Piyou Chen
Date: 2023-08-04T00:39:25-07:00
New Revision: 2df05cd01c17f3ef720e554dc7cde43df27e5224
URL:
https://github.com/llvm/llvm-project/commit/2df05cd01c17f3ef720e554dc7cde43df27e5224
DIFF:
https://github.com/llvm/llvm-project/commit/2df05cd01c17f3ef720e554dc7cde43df27e5224.diff
LOG: [RISCV] Support overloaded version ntlh intrinsic function
Here is the proposal https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47.
The version that omit the domain argument imply domain=__RISCV_NTLH_ALL.
```
type __riscv_ntl_load (type *ptr);
void __riscv_ntl_store (type *ptr, type val);
```
Reviewed By: kito-cheng, craig.topper
Differential Revision: https://reviews.llvm.org/D156221
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Headers/riscv_ntlh.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 45fbbbed1275df..36d3aa987bb49a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -20298,11 +20298,13 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
// Zihintntl
case RISCV::BI__builtin_riscv_ntl_load: {
llvm::Type *ResTy = ConvertType(E->getType());
-ConstantInt *Mode = cast(Ops[1]);
+unsigned DomainVal = 5; // Default __RISCV_NTLH_ALL
+if (Ops.size() == 2)
+ DomainVal = cast(Ops[1])->getZExtValue();
llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
getLLVMContext(),
-llvm::ConstantAsMetadata::get(Builder.getInt32(Mode->getZExtValue(;
+llvm::ConstantAsMetadata::get(Builder.getInt32(DomainVal)));
llvm::MDNode *NontemporalNode = llvm::MDNode::get(
getLLVMContext(), llvm::ConstantAsMetadata::get(Builder.getInt32(1)));
@@ -20324,11 +20326,13 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
return Load;
}
case RISCV::BI__builtin_riscv_ntl_store: {
-ConstantInt *Mode = cast(Ops[2]);
+unsigned DomainVal = 5; // Default __RISCV_NTLH_ALL
+if (Ops.size() == 3)
+ DomainVal = cast(Ops[2])->getZExtValue();
llvm::MDNode *RISCVDomainNode = llvm::MDNode::get(
getLLVMContext(),
-llvm::ConstantAsMetadata::get(Builder.getInt32(Mode->getZExtValue(;
+llvm::ConstantAsMetadata::get(Builder.getInt32(DomainVal)));
llvm::MDNode *NontemporalNode = llvm::MDNode::get(
getLLVMContext(), llvm::ConstantAsMetadata::get(Builder.getInt32(1)));
diff --git a/clang/lib/Headers/riscv_ntlh.h b/clang/lib/Headers/riscv_ntlh.h
index 9ce17092058353..c92e580a0a6317 100644
--- a/clang/lib/Headers/riscv_ntlh.h
+++ b/clang/lib/Headers/riscv_ntlh.h
@@ -21,8 +21,6 @@ enum {
__RISCV_NTLH_ALL
};
-#define __riscv_ntl_load(PTR, DOMAIN) __builtin_riscv_ntl_load((PTR), (DOMAIN))
-#define __riscv_ntl_store(PTR, VAL, DOMAIN)
\
- __builtin_riscv_ntl_store((PTR), (VAL), (DOMAIN))
-
-#endif
\ No newline at end of file
+#define __riscv_ntl_load __builtin_riscv_ntl_load
+#define __riscv_ntl_store __builtin_riscv_ntl_store
+#endif
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 502c583a48d6df..dd08d755b5cd05 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5287,12 +5287,16 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const
TargetInfo &TI,
bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store;
unsigned NumArgs = IsStore ? 3 : 2;
-if (checkArgCount(*this, TheCall, NumArgs))
+if (checkArgCountAtLeast(*this, TheCall, NumArgs - 1))
+ return true;
+
+if (checkArgCountAtMost(*this, TheCall, NumArgs))
return true;
// Domain value should be compile-time constant.
// 2 <= domain <= 5
-if (SemaBuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5))
+if (TheCall->getNumArgs() == NumArgs &&
+SemaBuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5))
return true;
Expr *PointerArg = TheCall->getArg(0);
diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index 5276e486604dee..f27f89df704858 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -100,6 +100,24 @@ void ntl_all_sizes() {
// CHECK-LABEL: ntl
*scvs1 = __riscv_ntl_load(scvs2, __RISCV_NTLH_ALL); // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
*scvc1 = __riscv_ntl_load(scvc2, __RISCV_NTLH_ALL); // CHECK: load {{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !8
+ uc = __riscv_ntl_load(&sc); // CHECK: load i8{{.*}}align 1, !nontemporal
!4, !riscv-nontemporal-domain !
[clang] [RISCV] Support target attribute for function (PR #65948)
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/65948:
The spec of RISC-V target feature is
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/35.
---
This patch implements target attribute for RISC-V.
>From 4e661a7cc4775e569bd648b0a119ece51ec031f7 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 14 Aug 2023 05:23:20 -0700
Subject: [PATCH] [RISCV] Support target attribute for function
This patch implements target attribute for RISC-V.
---
clang/lib/Basic/Targets/RISCV.cpp | 97 ++-
clang/lib/Basic/Targets/RISCV.h | 2 +
.../CodeGen/RISCV/riscv-func-attr-target.c| 55 +++
3 files changed, 152 insertions(+), 2 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-func-attr-target.c
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index d55ab76395c8271..e132e3bfc9f5b75 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -224,6 +224,21 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
+static std::vector
+resolveTargetAttrOverride(const std::vector &FeaturesVec) {
+ if (!llvm::is_contained(FeaturesVec, "__RISCV_TargetAttrNeedOverride"))
+return FeaturesVec;
+
+ auto VecPtr = FeaturesVec.begin();
+
+ while (*VecPtr != "__RISCV_TargetAttrNeedOverride")
+VecPtr++;
+
+ VecPtr++;
+
+ return std::vector(VecPtr, FeaturesVec.end());
+}
+
bool RISCVTargetInfo::initFeatureMap(
llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector &FeaturesVec) const {
@@ -237,7 +252,10 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
+ std::vector NewFeaturesVec =
+ resolveTargetAttrOverride(FeaturesVec);
+
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
if (!ParseResult) {
std::string Buffer;
llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -251,7 +269,7 @@ bool RISCVTargetInfo::initFeatureMap(
// RISCVISAInfo makes implications for ISA features
std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
// Add non-ISA features like `relax` and `save-restore` back
- for (const std::string &Feature : FeaturesVec)
+ for (const std::string &Feature : NewFeaturesVec)
if (!llvm::is_contained(ImpliedFeatures, Feature))
ImpliedFeatures.push_back(Feature);
@@ -346,3 +364,78 @@ void RISCVTargetInfo::fillValidTuneCPUList(
bool Is64Bit = getTriple().isArch64Bit();
llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
}
+
+static void handleFullArchString(StringRef FullArchStr,
+ std::vector &Features) {
+ Features.push_back("__RISCV_TargetAttrNeedOverride");
+ auto RII = llvm::RISCVISAInfo::parseArchString(
+ FullArchStr, /* EnableExperimentalExtension */ true);
+ if (!RII) {
+consumeError(RII.takeError());
+// Forward the invalid FullArchStr.
+Features.push_back("+" + FullArchStr.str());
+ } else {
+std::vector FeatStrings = (*RII)->toFeatureVector();
+for (auto FeatString : FeatStrings)
+ Features.push_back(FeatString);
+ }
+}
+
+ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
+ ParsedTargetAttr Ret;
+ if (Features == "default")
+return Ret;
+ SmallVector AttrFeatures;
+ Features.split(AttrFeatures, ";");
+ bool FoundArch = false;
+
+ for (auto &Feature : AttrFeatures) {
+Feature = Feature.trim();
+StringRef AttrString = Feature.split("=").second.trim();
+
+if (Feature.startswith("arch=")) {
+ // Override last features
+ Ret.Features.clear();
+ FoundArch = true;
+
+ if (AttrString.startswith("+")) {
+// EXTENSION like arch=+v,+zbb
+SmallVector Exts;
+AttrString.split(Exts, ",");
+for (auto Ext : Exts) {
+ if (Ext.empty())
+continue;
+
+ StringRef ExtName = Ext.substr(1);
+ std::string TargetFeature =
+ llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
+ if (!TargetFeature.empty())
+Ret.Features.push_back(Ext.front() + TargetFeature);
+ else
+Ret.Features.push_back(Ext.str());
+}
+ } else {
+// full-arch-string like arch=rv64gcv
+handleFullArchString(AttrString, Ret.Features);
+ }
+ continue;
+} else if (Feature.startswith("cpu=")) {
+ Ret.CPU = AttrString;
+
+ if (!FoundArch) {
+// Update Features with CPU's features
+StringRef MarchFromCPU = llvm::RISCV::getMArchFromMcpu(Ret.CPU);
+if (MarchFromCPU != "") {
+ Ret.Features.clear();
+ handleFullArchString(MarchFromCPU, Ret.Features);
+}
+ }
+
+ continue;
+} else if (Feature.startswith("tune="))
[clang] [RISCV] Support target attribute for function (PR #65948)
https://github.com/BeMg review_requested https://github.com/llvm/llvm-project/pull/65948 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Support target attribute for function (PR #65948)
BeMg wrote: This pull request move from https://reviews.llvm.org/D151730. And update with lastest spec. 1. When it exist the duplicate target attribute, select the lastest one. 2. arch's features will override cpu's features https://github.com/llvm/llvm-project/pull/65948 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] dc72e8f - [RISCV][NFC] skip non-RISCV target test riscv32-zihintntl.c
Author: Piyou Chen Date: 2023-04-24T23:14:56-07:00 New Revision: dc72e8fe675866b93748d54bc5e04b14c675f476 URL: https://github.com/llvm/llvm-project/commit/dc72e8fe675866b93748d54bc5e04b14c675f476 DIFF: https://github.com/llvm/llvm-project/commit/dc72e8fe675866b93748d54bc5e04b14c675f476.diff LOG: [RISCV][NFC] skip non-RISCV target test riscv32-zihintntl.c Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D149126 Added: Modified: clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c Removed: diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c index 9126e686c4202..5276e486604de 100644 --- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c +++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c @@ -1,3 +1,4 @@ +// REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +experimental-zihintntl -emit-llvm %s -o - \ // RUN: | FileCheck %s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_version (PR #99040)
BeMg wrote: Support `priority` syntax for target_version https://github.com/llvm/llvm-project/pull/99040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_version (PR #99040)
BeMg wrote: stack on https://github.com/llvm/llvm-project/pull/85786 https://github.com/llvm/llvm-project/pull/99040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 395ce72afbf9e4b12fcbfaf9cdbda8921c9ff72a Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 01/16] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticFrontendKinds.td| 4 +
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/include/clang/Sema/SemaRISCV.h | 1 +
clang/lib/AST/ASTContext.cpp | 12 +
clang/lib/CodeGen/CodeGenFunction.cpp | 106 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 35 +++
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++
clang/lib/Sema/SemaRISCV.cpp | 10 +
.../attr-target-clones-riscv-invalid.c| 8 +
clang/test/CodeGen/attr-target-clones-riscv.c | 211 ++
.../CodeGenCXX/attr-target-clones-riscv.cpp | 210 +
.../test/SemaCXX/attr-target-clones-riscv.cpp | 35 +++
14 files changed, 670 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv-invalid.c
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
index 8a1462c670d68f..0c870a1f3f1442 100644
--- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
+++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
@@ -378,4 +378,8 @@ def warn_missing_symbol_graph_dir : Warning<
def err_ast_action_on_llvm_ir : Error<
"cannot apply AST actions to LLVM IR file '%0'">,
DefaultFatal;
+
+def err_os_unsupport_riscv_target_clones : Error<
+ "target_clones is currently only supported on Linux">;
+
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index a58fb5f9792720..f31d88a354ea28 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1496,7 +1496,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/include/clang/Sema/SemaRISCV.h
b/clang/include/clang/Sema/SemaRISCV.h
index d62fca8128b2a3..d7f17797283b86 100644
--- a/clang/include/clang/Sema/SemaRISCV.h
+++ b/clang/include/clang/Sema/SemaRISCV.h
@@ -43,6 +43,7 @@ class SemaRISCV : public SemaBase {
void handleInterruptAttr(Decl *D, const ParsedAttr &AL);
bool isAliasValid(unsigned BuiltinID, llvm::StringRef AliasName);
+ bool isValidFMVExtension(StringRef Ext);
/// Indicate RISC-V vector builtin functions enabled or not.
bool DeclareRVVBuiltins = false;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index b201d201e1ea6a..a4d123219770bb 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -14181,6 +14181,18 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU,
Features);
+} else if (Target->getTriple().isRISCV()) {
+ StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
+ std::vector Features;
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU,
Features);
} else {
std::vector Features;
StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp
b/clang/lib/CodeGen/CodeGenFunction.cpp
index eff8c9f5694084..d625dde684933b 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2877,12 +2877,116 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case
[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
BeMg wrote: ping https://github.com/llvm/llvm-project/pull/106495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/106495
>From e8f472674e0d1e70adcd1d29b8c902f4cd80f188 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 28 Aug 2024 21:15:57 -0700
Subject: [PATCH 1/7] [Clang][RISCV] Recognize unsupport feature by supporting
isValidFeatureName
---
clang/lib/Basic/Targets/RISCV.cpp | 7 +++
clang/lib/Basic/Targets/RISCV.h | 1 +
clang/lib/Sema/SemaDeclAttr.cpp | 15 +++
clang/test/Sema/attr-target-riscv.c | 9 +
4 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b89109e7725d44..9abef57d007468 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -478,3 +478,10 @@ bool RISCVTargetInfo::validateCpuSupports(StringRef
Feature) const {
// __riscv_feature_bits structure.
return -1 != llvm::RISCVISAInfo::getRISCVFeaturesBitsInfo(Feature).second;
}
+
+bool RISCVTargetInfo::isValidFeatureName(StringRef Name) const {
+ if (Name == "__RISCV_TargetAttrNeedOverride")
+return true;
+
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Name);
+}
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 626274b8fc437c..b808ccc8e9cfe9 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -130,6 +130,7 @@ class RISCVTargetInfo : public TargetInfo {
bool supportsCpuSupports() const override { return getTriple().isOSLinux(); }
bool supportsCpuInit() const override { return getTriple().isOSLinux(); }
bool validateCpuSupports(StringRef Feature) const override;
+ bool isValidFeatureName(StringRef Name) const override;
};
class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
public:
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 1e074298ac5289..81cff8d7362ad5 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -2993,10 +2993,17 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
- if (Context.getTargetInfo().getTriple().isRISCV() &&
- ParsedAttrs.Duplicate != "")
-return Diag(LiteralLoc, diag::err_duplicate_target_attribute)
- << Duplicate << None << ParsedAttrs.Duplicate << Target;
+ if (Context.getTargetInfo().getTriple().isRISCV()) {
+if (ParsedAttrs.Duplicate != "")
+ return Diag(LiteralLoc, diag::err_duplicate_target_attribute)
+ << Duplicate << None << ParsedAttrs.Duplicate << Target;
+for (const auto &Feature : ParsedAttrs.Features) {
+ auto CurFeature = StringRef(Feature);
+ if (!CurFeature.starts_with("+") && !CurFeature.starts_with("-"))
+return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
+ << Unsupported << None << AttrStr << Target;
+}
+ }
if (ParsedAttrs.Duplicate != "")
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
diff --git a/clang/test/Sema/attr-target-riscv.c
b/clang/test/Sema/attr-target-riscv.c
index ed4e2915d6c6ef..01d928c1d78e48 100644
--- a/clang/test/Sema/attr-target-riscv.c
+++ b/clang/test/Sema/attr-target-riscv.c
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+notafeature"))) UnsupportFeature(void) {
return 0; }
+
+//expected-warning@+1 {{unsupported 'arch=+zba,zbb' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+zba,zbb"))) WithoutAddSigned(void) { return
0; }
+
+//expected-warning@+1 {{unsupported 'arch=zba' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=zba"))) WithoutAddSigned2(void) { return 0; }
>From ad95a3112c5349ea125d9c8d79cfa2f5e3d1d0a4 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Thu, 29 Aug 2024 00:39:08 -0700
Subject: [PATCH 2/7] Merge handleFullArchString logic, parseArchString will
check whether start with "rv"
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 9abef57d007468..1ab9f19ab7a30c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -388,7 +388,7 @@ static void handleFullArchString(StringRef FullArchStr,
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
// Forward the invalid FullArchStr.
-Features.push_back("+" + FullArchStr.str());
+Features.push_bac
[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+notafeature"))) UnsupportFeature(void) {
return 0; }
+
+//expected-warning@+1 {{unsupported 'arch=+zba,zbb' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+zba,zbb"))) WithoutAddSigned(void) { return
0; }
+
+//expected-warning@+1 {{unsupported 'arch=zba' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=zba"))) WithoutAddSigned2(void) { return 0; }
BeMg wrote:
Add arch=-notafeature testcase
https://github.com/llvm/llvm-project/pull/106495
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[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
@@ -2993,10 +2993,17 @@ bool Sema::checkTargetAttr(SourceLocation LiteralLoc,
StringRef AttrStr) {
return Diag(LiteralLoc, diag::warn_unsupported_target_attribute)
<< Unknown << Tune << ParsedAttrs.Tune << Target;
- if (Context.getTargetInfo().getTriple().isRISCV() &&
- ParsedAttrs.Duplicate != "")
-return Diag(LiteralLoc, diag::err_duplicate_target_attribute)
- << Duplicate << None << ParsedAttrs.Duplicate << Target;
+ if (Context.getTargetInfo().getTriple().isRISCV()) {
+if (ParsedAttrs.Duplicate != "")
+ return Diag(LiteralLoc, diag::err_duplicate_target_attribute)
+ << Duplicate << None << ParsedAttrs.Duplicate << Target;
+for (const auto &Feature : ParsedAttrs.Features) {
+ auto CurFeature = StringRef(Feature);
BeMg wrote:
It works. Updated.
https://github.com/llvm/llvm-project/pull/106495
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[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+notafeature"))) UnsupportFeature(void) {
return 0; }
+
+//expected-warning@+1 {{unsupported 'arch=+zba,zbb' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+zba,zbb"))) WithoutAddSigned(void) { return
0; }
BeMg wrote:
Updated.
https://github.com/llvm/llvm-project/pull/106495
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[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
@@ -4,3 +4,12 @@
int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
//expected-error@+1 {{redefinition of 'foo'}}
int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
+
+//expected-warning@+1 {{unsupported 'notafeature' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+notafeature"))) UnsupportFeature(void) {
return 0; }
+
+//expected-warning@+1 {{unsupported 'arch=+zba,zbb' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=+zba,zbb"))) WithoutAddSigned(void) { return
0; }
+
+//expected-warning@+1 {{unsupported 'arch=zba' in the 'target' attribute
string; 'target' attribute ignored}}
+int __attribute__((target("arch=zba"))) WithoutAddSigned2(void) { return 0; }
BeMg wrote:
Updated.
https://github.com/llvm/llvm-project/pull/106495
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[clang] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote:
> A test case will crash, missing `+` before `zbc`:
>
> ```
> __attribute__((target_clones("default", "arch=+zbb,zbc;priority=-1",
> "priority=-2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo1(void) {
> return 2; }
>
>
> int bar() { return foo1(); }
> ```
>
> ```
> $ clang -cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm foo.c
> clang:
> /home/kitoc/llvm-workspace/llvm-project/llvm/lib/TargetParser/RISCVISAInfo.cpp:455:
> static llvm::Expected >
> llvm::RISCVISAInfo::parseFeatures(unsigned int, const
> std::vector >&): Assertion `ExtName.size() >
> 1 && (ExtName[0] == '+' || ExtName[0] == '-')' failed.
> PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/
> and include the crash backtrace, preprocessed source, and associated run
> script.
> Stack dump:
> 0. Program arguments: ./bin/clang -cc1 -triple riscv64-linux-gnu
> -target-feature +i -emit-llvm attr-target-clones-riscv.c
> 1. attr-target-clones-riscv.c:7:1: current parser token 'int'
> 2. attr-target-clones-riscv.c:4:130: LLVM IR generation of declaration
> 'foo1'
> 3. attr-target-clones-riscv.c:4:130: Generating code for declaration
> 'foo1'
> #0 0x7f4ed63e00d0 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int)
> (/scratch/kitoc/llvm-workspace/build-upstream/bin/../lib/libLLVMSupport.so.20.0git+0x1e00d0)
> ...
> #11 0x7f4eda71a854 llvm::RISCVISAInfo::parseFeatures(unsigned int,
> std::vector,
> std::allocator>, std::allocator std::char_traits, std::allocator>>> const&)
> (/scratch/kitoc/llvm-workspace/build-upstream/bin/../lib/libLLVMTargetParser.so.20.0git+0x3d854)
> #12 0x7f4ed825b8e0
> clang::targets::RISCVTargetInfo::initFeatureMap(llvm::StringMap llvm::MallocAllocator>&, clang::DiagnosticsEngine&, llvm::StringRef,
> std::vector,
> std::allocator>, std::allocator std::char_traits, std::allocator>>> const&) const
> (/scratch/kitoc/llvm-workspace/build-upstream/bin/../lib/libclangBasic.so.20.0git+0x45b8e0)
> ...
> Aborted (core dumped)
> ```
Fixed and add new test.
https://github.com/llvm/llvm-project/pull/85786
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[clang] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: Rename and update the description of err_os_unsupport_riscv_target_clones because not only target clones trigger FMV. https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (PR #106495)
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/106495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RISCVExtensionBitmaskTable
+
+namespace {
+struct LessExtName {
+ bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS,
+ StringRef RHS) {
+return StringRef(LHS.Name) < RHS;
+ }
+ bool
+ operator()(StringRef LHS,
+ const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &RHS) {
+return LHS < StringRef(RHS.Name);
+ }
+};
+} // namespace
+
+static Expected
+getExtensionBitmask(StringRef ExtName) {
+ ArrayRef ExtBitmasks =
+ RISCVExtensionBitmaskTable::ExtensionBitmask;
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
+
+ if (I != ExtBitmasks.end())
+return *I;
+
+ return createStringError("Unsupport extension");
+}
+
+llvm::SmallVector getRequireFeatureBitMask(ArrayRef Exts)
{
+ llvm::SmallVector BitMasks(RISCV::RISCVFeatureBitSize);
+
+ for (auto Ext : Exts) {
+Expected ExtBitmask =
+getExtensionBitmask(Ext);
+assert(ExtBitmask && "This extension doesn't has bitmask.");
BeMg wrote:
Sema check now also verifies whether the extension has already allocated the
bit in the bitmask.
https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
+ raw_ostream &Out) const override;
+ void appendAttributeMangling(StringRef AttrStr,
+ raw_ostream &Out) const override;
};
} // end anonymous namespace
+void RISCVABIInfo::appendAttributeMangling(TargetClonesAttr *Attr,
+ unsigned Index,
+ raw_ostream &Out) const {
+ appendAttributeMangling(Attr->getFeatureStr(Index), Out);
+}
+
+void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr,
+ raw_ostream &Out) const {
+ if (AttrStr == "default") {
+Out << ".default";
+return;
+ }
+
+ Out << '.';
BeMg wrote:
The format will be the function name appended with the sorted feature string,
joined by an underscore.
```
.__...
```
https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ unsigned DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
+
+if (Options[Index].Conditions.Features[0].starts_with("default")) {
+ HasDefault = true;
+ DefaultIndex = Index;
+ continue;
+}
+
+Builder.SetInsertPoint(CurBlock);
+
+std::vector TargetAttrFeats =
+getContext()
+.getTargetInfo()
+.parseTargetAttr(Options[Index].Conditions.Features[0])
+.Features;
+
+if (TargetAttrFeats.empty())
+ continue;
+
+// Two conditions need to be checked for the current version:
BeMg wrote:
Drop the length check and reuse the approach using the `__builtin_support_cpus`.
https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+ CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ cast(RISCVFeaturesBits)->setDSOLocal(true);
+
+ auto LoadFeatureBit = [&](unsigned Index) {
+// Create GEP then load.
+Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
+llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
+ IndexVal};
+Value *Ptr =
+Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+Value *FeaturesBit =
+Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
+return FeaturesBit;
+ };
+
+ SmallVector RequireFeatureBits =
+ llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs);
+ Value *Result = Builder.getTrue();
+ for (unsigned i = 0; i < RequireFeatureBits.size(); i++) {
+if (!RequireFeatureBits[i])
+ continue;
+MaxGroupIDUsed = i;
+Value *Mask = Builder.getInt64(RequireFeatureBits[i]);
+Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask);
+Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
+Result = Builder.CreateAnd(Result, Cmp);
+ }
+
+ return Result;
+}
+
+Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
BeMg wrote:
Droped
https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+ CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ cast(RISCVFeaturesBits)->setDSOLocal(true);
+
+ auto LoadFeatureBit = [&](unsigned Index) {
+// Create GEP then load.
+Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
+llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
+ IndexVal};
+Value *Ptr =
+Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+Value *FeaturesBit =
+Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
+return FeaturesBit;
+ };
+
+ SmallVector RequireFeatureBits =
BeMg wrote:
Now it query the bitpos for only one extension each time.
https://github.com/llvm/llvm-project/pull/85786
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
BeMg wrote:
> This block of repeating code should be factored out as a static helper.
It is standalone help function now.
https://github.com/llvm/llvm-project/pull/85786
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[clang] [compiler-rt] [RISCV][compiler-rt] Update __init_riscv_feature_bits prototype (PR #101472)
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/101472 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 1/6] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/lib/AST/ASTContext.cpp | 9 ++
clang/lib/Basic/Targets/RISCV.cpp | 10 +-
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 23 +++
clang/lib/Sema/SemaDeclAttr.cpp | 22 +++
clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
.../CodeGenCXX/attr-target-clones-riscv.cpp | 136 ++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 19 +++
12 files changed, 462 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
} else {
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
if (I != FeaturesVec.end()) {
std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
@@ -366,6 +366,12 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
return true;
}
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+ if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+ Features.push_back("+__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
bool handleTargetFeatures(std::vector &Features,
DiagnosticsEngine &Diags) override;
+ bool is
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85899
>From 0bbffb92e7f36957c042cab9a67a483571d9b3f9 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH 1/3] [RISCV] Disallow target attribute use in multiversioning
---
clang/lib/Sema/SemaDecl.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 5850cd0ab6b9aa..e543aff77e67ea 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11853,6 +11853,10 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
return false;
+ // Target attribute on RISCV is not used for multiversioning
+ if (NewTA && S.getASTContext().getTargetInfo().getTriple().isRISCV())
+return false;
+
if (!OldDecl || !OldDecl->getAsFunction() ||
OldDecl->getDeclContext()->getRedeclContext() !=
NewFD->getDeclContext()->getRedeclContext()) {
>From f0057a2c65a030fc5afa30dee4b08c71cf3451bd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 1 Apr 2024 23:21:25 -0700
Subject: [PATCH 2/3] Add testcase
---
clang/test/Sema/attr-target-riscv.c | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 clang/test/Sema/attr-target-riscv.c
diff --git a/clang/test/Sema/attr-target-riscv.c
b/clang/test/Sema/attr-target-riscv.c
new file mode 100644
index 00..ed4e2915d6c6ef
--- /dev/null
+++ b/clang/test/Sema/attr-target-riscv.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -fsyntax-only
-verify -std=c2x %s
+
+//expected-note@+1 {{previous definition is here}}
+int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
+//expected-error@+1 {{redefinition of 'foo'}}
+int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
>From 6757bf5e0f857acd3cca8a843a481f6658a5e6c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 7 Apr 2024 22:14:46 -0700
Subject: [PATCH 3/3] Share Triple for AArch64 and RISCV
---
clang/lib/Sema/SemaDecl.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index e543aff77e67ea..547ff30089a7c6 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11849,12 +11849,14 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
return false;
}
+ const llvm::Triple &T = S.getASTContext().getTargetInfo().getTriple();
+
// Target attribute on AArch64 is not used for multiversioning
- if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
+ if (NewTA && T.isAArch64())
return false;
// Target attribute on RISCV is not used for multiversioning
- if (NewTA && S.getASTContext().getTargetInfo().getTriple().isRISCV())
+ if (NewTA && T.isRISCV())
return false;
if (!OldDecl || !OldDecl->getAsFunction() ||
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 01/10] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/lib/AST/ASTContext.cpp | 9 ++
clang/lib/Basic/Targets/RISCV.cpp | 10 +-
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 23 +++
clang/lib/Sema/SemaDeclAttr.cpp | 22 +++
clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
.../CodeGenCXX/attr-target-clones-riscv.cpp | 136 ++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 19 +++
12 files changed, 462 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
} else {
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
if (I != FeaturesVec.end()) {
std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
@@ -366,6 +366,12 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
return true;
}
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+ if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+ Features.push_back("+__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
bool handleTargetFeatures(std::vector &Features,
DiagnosticsEngine &Diags) override;
+ bool
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85899
>From 894c0975638a99c84fde8d1ea5c845e5cdbf32f4 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 18 Mar 2024 05:07:14 -0700
Subject: [PATCH 1/3] [RISCV] Disallow target attribute use in multiversioning
---
clang/lib/Sema/SemaDecl.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 5a23179dfbbf44..0aa0350d5c562f 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11916,6 +11916,10 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
return false;
+ // Target attribute on RISCV is not used for multiversioning
+ if (NewTA && S.getASTContext().getTargetInfo().getTriple().isRISCV())
+return false;
+
if (!OldDecl || !OldDecl->getAsFunction() ||
OldDecl->getDeclContext()->getRedeclContext() !=
NewFD->getDeclContext()->getRedeclContext()) {
>From e6b7a2da5cb6dccd85aa3b7a12bffcc2b4a31270 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Mon, 1 Apr 2024 23:21:25 -0700
Subject: [PATCH 2/3] Add testcase
---
clang/test/Sema/attr-target-riscv.c | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 clang/test/Sema/attr-target-riscv.c
diff --git a/clang/test/Sema/attr-target-riscv.c
b/clang/test/Sema/attr-target-riscv.c
new file mode 100644
index 00..ed4e2915d6c6ef
--- /dev/null
+++ b/clang/test/Sema/attr-target-riscv.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -fsyntax-only
-verify -std=c2x %s
+
+//expected-note@+1 {{previous definition is here}}
+int __attribute__((target("arch=rv64g"))) foo(void) { return 0; }
+//expected-error@+1 {{redefinition of 'foo'}}
+int __attribute__((target("arch=rv64gc"))) foo(void) { return 0; }
>From b9a2a5e3dda4088056da64cf80504a542ff3ddcd Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Sun, 7 Apr 2024 22:14:46 -0700
Subject: [PATCH 3/3] Share Triple for AArch64 and RISCV
---
clang/lib/Sema/SemaDecl.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 0aa0350d5c562f..92d2b2f6120bc9 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -11912,12 +11912,14 @@ static bool CheckMultiVersionFunction(Sema &S,
FunctionDecl *NewFD,
return false;
}
+ const llvm::Triple &T = S.getASTContext().getTargetInfo().getTriple();
+
// Target attribute on AArch64 is not used for multiversioning
- if (NewTA && S.getASTContext().getTargetInfo().getTriple().isAArch64())
+ if (NewTA && T.isAArch64())
return false;
// Target attribute on RISCV is not used for multiversioning
- if (NewTA && S.getASTContext().getTargetInfo().getTriple().isRISCV())
+ if (NewTA && T.isRISCV())
return false;
if (!OldDecl || !OldDecl->getAsFunction() ||
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 239b404203c66ab5336ffdfb45969a50c439a1c0 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 19 Mar 2024 06:22:17 -0700
Subject: [PATCH 01/11] [RISCV][FMV] Support target_clones
---
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/lib/AST/ASTContext.cpp | 9 ++
clang/lib/Basic/Targets/RISCV.cpp | 10 +-
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CodeGenFunction.cpp | 102 -
clang/lib/CodeGen/CodeGenFunction.h | 3 +
clang/lib/CodeGen/CodeGenModule.cpp | 2 +
clang/lib/CodeGen/Targets/RISCV.cpp | 23 +++
clang/lib/Sema/SemaDeclAttr.cpp | 22 +++
clang/test/CodeGen/attr-target-clones-riscv.c | 135 +
.../CodeGenCXX/attr-target-clones-riscv.cpp | 136 ++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 19 +++
12 files changed, 462 insertions(+), 4 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index 374595edd2ce4a..aa48596fbce07d 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1445,7 +1445,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 5a8fae76a43a4d..0fd75e0b36b123 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -13636,6 +13636,15 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Features.insert(Features.begin(),
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
+} else if (Target->getTriple().isRISCV()) {
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
} else {
if (VersionStr.starts_with("arch="))
TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..8e9132c9191a3c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -257,7 +257,7 @@ bool RISCVTargetInfo::initFeatureMap(
// If a target attribute specified a full arch string, override all the ISA
// extension target features.
- const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ const auto I = llvm::find(FeaturesVec, "+__RISCV_TargetAttrNeedOverride");
if (I != FeaturesVec.end()) {
std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
@@ -366,6 +366,12 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
return true;
}
+bool RISCVTargetInfo::isValidFeatureName(StringRef Feature) const {
+ if (Feature.starts_with("__RISCV_TargetAttrNeedOverride"))
+return true;
+ return llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature);
+}
+
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::parseCPU(Name, Is64Bit);
@@ -390,7 +396,7 @@ void RISCVTargetInfo::fillValidTuneCPUList(
static void handleFullArchString(StringRef FullArchStr,
std::vector &Features) {
- Features.push_back("__RISCV_TargetAttrNeedOverride");
+ Features.push_back("+__RISCV_TargetAttrNeedOverride");
auto RII = llvm::RISCVISAInfo::parseArchString(
FullArchStr, /* EnableExperimentalExtension */ true);
if (llvm::errorToBool(RII.takeError())) {
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index bfbdafb682c851..ef8f59185d753c 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -106,6 +106,8 @@ class RISCVTargetInfo : public TargetInfo {
bool handleTargetFeatures(std::vector &Features,
DiagnosticsEngine &Diags) override;
+ bool
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)
https://github.com/BeMg closed https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 48eea6eda33c4e73316fe938a15d8e361039072e Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/2] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the
corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the
compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 301 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 ++
llvm/test/TableGen/riscv-target-def.td| 26 +-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 52 +++
5 files changed, 318 insertions(+), 101 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..8444935bd666d 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ uint64_t Bitmask;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 011edca019fd6..624bd3f408858 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+bits<3> GroupID = groupID;
+bits<64> Bitmask = !shl(1, bitmaskShift);
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 0>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
- "Implements RV{32,64}E (provides 16 rather than 32
GPRs)">;
+ "Implements RV{32,64}E (provides 16 rather than 32
GPRs)">,
+ RISCVExtensionBitmask<0, 1>;
def FeatureStdExtZic64b
: RISCVExtension<"zic64b", 1, 0,
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">,
+ RISCVExtensionBitmask<0, 2>;
def FeatureStdExtZicbom
: RISCVExtension<"zicbom", 1, 0,
- "'Zicbom' (Cache-Block Management Instructions)">;
+ "'Zicbom' (Cache-Block Management Instructions)">,
+ RISCVExtensionBitmask<0, 3>;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
: RISCVExtension<"zicbop", 1, 0,
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
+ "'Zicbop' (Cache-Block Prefetch Instructions)">,
+ RISCVExtensionBitmask<0, 4>;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 5>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
: RISCVExtension<"ziccamoa", 1, 0,
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">,
+ RISCVExtensionBitmask<0, 6>;
def FeatureStdExtZiccif
: RISCVExtension<"ziccif", 1, 0,
- "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">,
+ RISCVExtensionBitmask<0, 7>;
def FeatureStdExtZicclsm
: RISCVExtension<"zicclsm", 1, 0,
- "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtZiccrse
: RISCVExtension<"ziccrse", 1, 0,
-
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: Stack on https://github.com/llvm/llvm-project/pull/94440 https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/BeMg approved this pull request. LGTM. Work fine with current compiler-rt `__init_riscv_feature_bits `/`__riscv_feature_bits ` and qemu with hwprobe support. https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 708c81609c603c5ea820493e92d8c82cf4620d64 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Tue, 23 Jul 2024 19:59:06 -0700
Subject: [PATCH 1/3] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticFrontendKinds.td| 4 +
clang/include/clang/Basic/TargetInfo.h| 3 +-
clang/include/clang/Sema/SemaRISCV.h | 1 +
clang/lib/AST/ASTContext.cpp | 12 +
clang/lib/CodeGen/CGBuiltin.cpp | 64 --
clang/lib/CodeGen/CodeGenFunction.cpp | 106 -
clang/lib/CodeGen/CodeGenFunction.h | 4 +
clang/lib/CodeGen/CodeGenModule.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 35 +++
clang/lib/Sema/SemaDeclAttr.cpp | 30 +++
clang/lib/Sema/SemaRISCV.cpp | 10 +
.../attr-target-clones-riscv-invalid.c| 8 +
clang/test/CodeGen/attr-target-clones-riscv.c | 211 ++
.../CodeGenCXX/attr-target-clones-riscv.cpp | 210 +
.../test/SemaCXX/attr-target-clones-riscv.cpp | 35 +++
.../llvm/TargetParser/RISCVTargetParser.h | 2 +
16 files changed, 717 insertions(+), 23 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv-invalid.c
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
index 12a4617c64d87..b2b63674ecc07 100644
--- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
+++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
@@ -375,4 +375,8 @@ def warn_missing_symbol_graph_dir : Warning<
def err_ast_action_on_llvm_ir : Error<
"cannot apply AST actions to LLVM IR file '%0'">,
DefaultFatal;
+
+def err_os_unsupport_riscv_target_clones : Error<
+ "target_clones is currently only supported on Linux">;
+
}
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index a58fb5f979272..f31d88a354ea2 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1496,7 +1496,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
-return getTriple().isX86() || getTriple().isAArch64();
+return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/include/clang/Sema/SemaRISCV.h
b/clang/include/clang/Sema/SemaRISCV.h
index 48d15c411bddd..9798328361f8e 100644
--- a/clang/include/clang/Sema/SemaRISCV.h
+++ b/clang/include/clang/Sema/SemaRISCV.h
@@ -40,6 +40,7 @@ class SemaRISCV : public SemaBase {
void handleInterruptAttr(Decl *D, const ParsedAttr &AL);
bool isAliasValid(unsigned BuiltinID, StringRef AliasName);
+ bool isValidFMVExtension(StringRef Ext);
/// Indicate RISC-V vector builtin functions enabled or not.
bool DeclareRVVBuiltins = false;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 7af9ea7105bb0..d7147ff02906a 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -14129,6 +14129,18 @@ void
ASTContext::getFunctionFeatureMap(llvm::StringMap &FeatureMap,
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU,
Features);
+} else if (Target->getTriple().isRISCV()) {
+ StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
+ std::vector Features;
+ if (VersionStr != "default") {
+ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU,
Features);
} else {
std::vector Features;
StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a0d03b87ccdc9..6bdaeb655a09a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -63,6 +63,7 @@
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
#include "llvm/TargetParser/
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: > @BeMg Can you rebase over commit > [d1e28e2](https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59)? Now this patch rebase over https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59. Majorly, the diff between origin patch are: 1. Use the getRISCVFeaturesBitPosition function introduced in https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59 in another version `EmitRISCVCpuSupports`. 2. Extract the common part of `EmitRISCVCpuSupports` and create a helper function for it. 3. Remove the __riscv_feature_bits.length check. 4. During the target_clones Sema check, reuse the getRISCVFeaturesBitPosition function to validate the feature. https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
BeMg wrote: > > The proposal can be found at the > > [riscv-non-isa/riscv-c-api-doc#48](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48). > > Please put this in the PR description Updated PR description https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/5] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the
corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the
compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td| 131 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 +
llvm/test/TableGen/riscv-target-def.td| 18 ++-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 37 +
5 files changed, 183 insertions(+), 43 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned BitPosition;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d3cb2aeab41cb..125e9e2f53953 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+int GroupID = groupID;
+int BitPos = bitmaskShift;
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
@@ -78,7 +88,8 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -113,7 +124,8 @@ def FeatureStdExtZicntr
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
+ "'Zicond' (Integer Conditional Operations)">,
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -134,7 +146,8 @@ def HasStdExtZihintpause :
Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -181,7 +194,8 @@ def HasStdExtZmmul :
Predicate<"Subtarget->hasStdExtZmmul()">,
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)",
- [FeatureStdExtZmmul]>;
+ [FeatureStdExtZmmul]>,
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -190,14 +204,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)">;
+ "'A' (Atomic Instructions)">,
+ RISCVExtensionBitmask<0, 0>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
: RISCVExtension<"ztso", 1, 0,
- "'Ztso' (Memory Model - Total Store Order)">;
+ "'Zt
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/6] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the
corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the
compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td| 131 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 +
llvm/test/TableGen/riscv-target-def.td| 18 ++-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 37 +
5 files changed, 183 insertions(+), 43 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned BitPosition;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d3cb2aeab41cb..125e9e2f53953 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+int GroupID = groupID;
+int BitPos = bitmaskShift;
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
@@ -78,7 +88,8 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -113,7 +124,8 @@ def FeatureStdExtZicntr
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
+ "'Zicond' (Integer Conditional Operations)">,
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -134,7 +146,8 @@ def HasStdExtZihintpause :
Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -181,7 +194,8 @@ def HasStdExtZmmul :
Predicate<"Subtarget->hasStdExtZmmul()">,
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)",
- [FeatureStdExtZmmul]>;
+ [FeatureStdExtZmmul]>,
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -190,14 +204,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)">;
+ "'A' (Atomic Instructions)">,
+ RISCVExtensionBitmask<0, 0>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
: RISCVExtension<"ztso", 1, 0,
- "'Ztso' (Memory Model - Total Store Order)">;
+ "'Zt
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg edited https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 38e5bef5d20d7e81170720eb56354c0392f5c902 Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 01/10] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the
corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the
compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td| 131 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 +
llvm/test/TableGen/riscv-target-def.td| 18 ++-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 37 +
5 files changed, 183 insertions(+), 43 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned BitPosition;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d3cb2aeab41cb..125e9e2f53953 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+int GroupID = groupID;
+int BitPos = bitmaskShift;
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
@@ -78,7 +88,8 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -113,7 +124,8 @@ def FeatureStdExtZicntr
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
+ "'Zicond' (Integer Conditional Operations)">,
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -134,7 +146,8 @@ def HasStdExtZihintpause :
Predicate<"Subtarget->hasStdExtZihintpause()">,
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -181,7 +194,8 @@ def HasStdExtZmmul :
Predicate<"Subtarget->hasStdExtZmmul()">,
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)",
- [FeatureStdExtZmmul]>;
+ [FeatureStdExtZmmul]>,
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -190,14 +204,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)">;
+ "'A' (Atomic Instructions)">,
+ RISCVExtensionBitmask<0, 0>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
: RISCVExtension<"ztso", 1, 0,
- "'Ztso' (Memory Model - Total Store Order)">;
+ "'
[clang] [llvm] [RISCV][FMV] Support target_version (PR #99040)
@@ -3127,6 +3142,32 @@ bool Sema::checkTargetClonesAttrString(
/*IncludeLocallyStreaming=*/false))
return Diag(LiteralLoc,
diag::err_sme_streaming_cannot_be_multiversioned);
+} else if (TInfo.getTriple().isRISCV()) {
+ // Suppress warn_target_clone_mixed_values
+ HasCommas = false;
+
+ // Only support arch=+ext,... syntax.
+ if (Str.starts_with("arch=+")) {
+// parseTargetAttr will parse full version string,
+// the following split Cur string is no longer interesting.
BeMg wrote:
For example: version string is `arch=+v,+m,+zbb`
After split Cur string will be {"arch=+v", "+m", "+zbb"}, but parseTargetAttr
accept the `arch=+v,+m,+zbb` as input.
So here it only want to invoke parseTargetAttr once and early quit when second
time.
https://github.com/llvm/llvm-project/pull/99040
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV][FMV] Support target_version (PR #99040)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 4260683c6d589bc5a64ceffd5e409336f81d85eb Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/3] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the
corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the
compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td| 134 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 +
llvm/test/TableGen/riscv-target-def.td| 18 ++-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 37 +
5 files changed, 185 insertions(+), 44 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned BitPosition;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d3cb2aeab41cb..ff6ec42a2e72f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+int GroupID = groupID;
+int BitPos = bitmaskShift;
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
@@ -78,7 +88,8 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -113,7 +124,8 @@ def FeatureStdExtZicntr
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
+ "'Zicond' (Integer Conditional Operations)">,
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -127,14 +139,16 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)">;
+ "'Zihintpause' (Pause Hint)">,
+ RISCVExtensionBitmask<0, 40>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of
FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -181,7 +195,8 @@ def HasStdExtZmmul :
Predicate<"Subtarget->hasStdExtZmmul()">,
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)",
- [FeatureStdExtZmmul]>;
+ [FeatureStdExtZmmul]>,
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -190,14 +205,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (A
[clang] [llvm] [RISCV][FMV] Support target_version (PR #99040)
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/99040
>From 4260683c6d589bc5a64ceffd5e409336f81d85eb Mon Sep 17 00:00:00 2001
From: Piyou Chen
Date: Wed, 5 Jun 2024 01:17:03 -0700
Subject: [PATCH 1/5] [RISCV] Add groupid/bitmask for RISC-V extension
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74.
This patch defines the groupid/bitmask in RISCVFeatures.td and generates the
corresponding table in RISCVTargetParserDef.inc.
The groupid/bitmask of extensions provides an abstraction layer between the
compiler and runtime functions.
---
.../llvm/TargetParser/RISCVTargetParser.h | 8 ++
llvm/lib/Target/RISCV/RISCVFeatures.td| 134 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 32 +
llvm/test/TableGen/riscv-target-def.td| 18 ++-
llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 37 +
5 files changed, 185 insertions(+), 44 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 5b1494efe7bdc..e998bc4ca59ee 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -24,6 +24,14 @@ class Triple;
namespace RISCV {
+namespace RISCVExtensionBitmaskTable {
+struct RISCVExtensionBitmask {
+ const char *Name;
+ unsigned GroupID;
+ unsigned BitPosition;
+};
+} // namespace RISCVExtensionBitmaskTable
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d3cb2aeab41cb..ff6ec42a2e72f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -37,6 +37,15 @@ class RISCVExtension groupID, int bitmaskShift> {
+int GroupID = groupID;
+int BitPos = bitmaskShift;
+}
+
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
class RISCVExperimentalExtension;
+ "'I' (Base Integer Instruction Set)">,
+ RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
: RISCVExtension<"e", 2, 0,
@@ -78,7 +88,8 @@ def HasStdExtZicbop :
Predicate<"Subtarget->hasStdExtZicbop()">,
def FeatureStdExtZicboz
: RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">;
+ "'Zicboz' (Cache-Block Zero Instructions)">,
+ RISCVExtensionBitmask<0, 37>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
@@ -113,7 +124,8 @@ def FeatureStdExtZicntr
def FeatureStdExtZicond
: RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">;
+ "'Zicond' (Integer Conditional Operations)">,
+ RISCVExtensionBitmask<0, 38>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
@@ -127,14 +139,16 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
def FeatureStdExtZihintpause
: RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)">;
+ "'Zihintpause' (Pause Hint)">,
+ RISCVExtensionBitmask<0, 40>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of
FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
: RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">;
+ "'Zihintntl' (Non-Temporal Locality Hints)">,
+ RISCVExtensionBitmask<0, 39>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
@@ -181,7 +195,8 @@ def HasStdExtZmmul :
Predicate<"Subtarget->hasStdExtZmmul()">,
def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)",
- [FeatureStdExtZmmul]>;
+ [FeatureStdExtZmmul]>,
+ RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;
@@ -190,14 +205,16 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
def FeatureStdExtA
: RISCVExtension<"a", 2, 1,
- "'A' (A
[clang] [llvm] [RISCV][FMV] Support target_version (PR #99040)
@@ -0,0 +1,8 @@ +// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS + +// CHECK-UNSUPPORT-OS: error: target_clones is currently only supported on Linux BeMg wrote: Added. https://github.com/llvm/llvm-project/pull/99040 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64_t bitpos;
BeMg wrote:
Does it need `uint64_t` for bit position? I think the value doesn't exceed 63.
https://github.com/llvm/llvm-project/pull/99700
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[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
@@ -62,6 +62,8 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/TargetParser/AArch64TargetParser.h" +#include "llvm/TargetParser/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" BeMg wrote: `RISCVTargetParser.h` can be dropped due to its come from tablegen stuff. https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
BeMg wrote: > * Updating clang tests to exercise this logic. > * Actually running it at all. I did not build compiler-rt, and thus all my > checking was of generated asm/IR. Maybe we could compile the test code with `compiler-rt/lib/builtins/riscv/feature_bits.c` manually. Then we could get rid of copmiler-rt building during running the `__builtin_cpu_init` and `__builtin_cpu_supports` actually. Actually, I tried this patch in my local, and it work well. --- Here is build script for compiler-rt, if you want to build compiler-rt. ``` cmake -DCMAKE_C_COMPILER_TARGET="riscv64-unknown-linux-gnu" \ -DCMAKE_ASM_COMPILER_TARGET="riscv64-unknown-linux-gnu" \ -DCMAKE_AR=./path/to/llvm/install/bin/llvm-ar \ -DCMAKE_C_COMPILER=./path/to/llvm/install/bin/clang \ -DCMAKE_NM=./path/to/llvm/install/bin/llvm-nm \ -DCMAKE_RANLIB=./path/to/llvm/install/bin/llvm-ranlib \ -DCOMPILER_RT_BUILD_BUILTINS=ON \ -DCOMPILER_RT_BUILD_LIBFUZZER=OFF \ -DCOMPILER_RT_BUILD_MEMPROF=OFF \ -DCOMPILER_RT_BUILD_PROFILE=OFF \ -DCOMPILER_RT_BUILD_SANITIZERS=OFF \ -DCOMPILER_RT_BUILD_XRAY=OFF \ -DCOMPILER_RT_DEFAULT_TARGET_ONLY=ON \ -DLLVM_CONFIG_PATH=./path/to/llvm/install/bin/llvm-config \ -G "Ninja" ../compiler-rt ninja # Put the `libclang_rt.builtins-riscv64.a` in correct path cp ./path/to/build/lib/linux/* ./path/to/llvm/install/lib/clang/19/lib/linux ``` ``` # Compile using compiler-rt clang -march=rv64imafd -rtlib=compiler-rt test.c ``` > * Investigate claims from gcc docs that __builtin_cpu_init is called early in > process lifetime with high priority constructor. I did not find this with > some quick searching. https://github.com/llvm/llvm-project/pull/99700 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64_t bitpos;
+};
+
+/// Maps extensions with assigned bit positions within group 0 of
+/// __riscv_features_bits to their respective bit position. At the
+/// moment all extensions are within group 0.
+static RISCVExtBit RISCVGroup0BitPositions[] = {
BeMg wrote:
One reason we choose the `tablegen` approach is trying to maintain the
everything relate to extension (In this case is groupID/bitPos) inside
`RISCVFeatures.td`.
How about land https://github.com/llvm/llvm-project/pull/94440 now, and replace
this struct with tablegen generated `.inc` file? Or maybe we could replace it
after 19.x release?
https://github.com/llvm/llvm-project/pull/99700
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[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver, Options);
+return;
default:
-assert(false && "Only implemented for x86 and AArch64 targets");
+assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+llvm::Function *Resolver, ArrayRef Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ unsigned DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
BeMg wrote:
In other target, it sort the order base on target-defined priority score for
all cpu/extension.
Take Aarch64 as example, it define a table like:
```
// `llvm/lib/Target/AArch64/AArch64FMV.td`
// The last one is score that using to sorting.
def : FMVExtension<"aes", "FEAT_AES", "+fp-armv8,+neon", 150>;
def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>;
def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>;
...
```
And sort it before going to emit the resolver.
```
...
llvm::stable_sort(
Options, [&TI](const CodeGenFunction::MultiVersionResolverOption &LHS,
const CodeGenFunction::MultiVersionResolverOption &RHS) {
return TargetMVPriority(TI, LHS) > TargetMVPriority(TI, RHS);
});
...
static unsigned
TargetMVPriority(const TargetInfo &TI,
const CodeGenFunction::MultiVersionResolverOption &RO) {
unsigned Priority = 0;
unsigned NumFeatures = 0;
for (StringRef Feat : RO.Conditions.Features) {
Priority = std::max(Priority, TI.multiVersionSortPriority(Feat));
NumFeatures++;
}
if (!RO.Conditions.Architecture.empty())
Priority = std::max(
Priority, TI.multiVersionSortPriority(RO.Conditions.Architecture));
Priority += TI.multiVersionFeatureCost() * NumFeatures;
return Priority;
}
```
https://github.com/llvm/llvm-project/pull/85786
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