[llvm] [clang-tools-extra] [clang] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
lukel97 wrote: Oh nice, I'm running into something similar in https://github.com/llvm/llvm-project/pull/71657. Are all these dead ADDIs instructions coming from the backwards local postpass? https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [RISCV] Eliminate dead li after emitting VSETVLIs (PR #65934)
lukel97 wrote: > > Oh nice, I'm running into something similar in #71657. Are all these dead > > ADDIs coming from the backwards local postpass? > > Yes. I believe this PR can address the issue. My suspicion is that these LIs only become dead because the backwards local postpass deletes a vsetvli that had an ADDI AVL. Would it be easier then to just check if they are dead in `doLocalPostpass` rather than keeping around a vector of instructions? I.e. something similar to https://github.com/llvm/llvm-project/pull/71657/commits/8ae868b3825ab5c2d9506c2ca515687d67419b9b https://github.com/llvm/llvm-project/pull/65934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/76942
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector.
NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..64f5f9e9215dcb 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -245,7 +245,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
return std::vector();
}
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
std::vector NonISAExtFeatureVec;
@@ -303,7 +303,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -420,7 +420,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/76962
collectNonISAExtFeature was returning any negative extension features, e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative extensions aren't emitted when calling toFeatureVector(), and
so were considered missing. This is why we see an extra "-zfa" and "-zfb" in
the tests for
the full arch string attributes, even when they are both already present in the
command line flags.
This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead to
check if a feature is an ISA extension.
>From 186bd18fca046b3897b4e011ebba2eb44dd9e813 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 20:48:09 +0700
Subject: [PATCH] [RISCV] Fix collectNonISAExtFeature returning negative
extension features
collectNonISAExtFeature was returning any negative extension features, e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative extensions aren't emitted when calling toFeatureVector(), and
so were considered missing. This is why we see an extra "-zfa" in the tests for
the full arch string attributes, even when -zfa is already present in the
command line flags.
This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead to
check if a feature is an ISA extension.
---
clang/lib/Basic/Targets/RISCV.cpp | 19 ++-
.../CodeGen/RISCV/riscv-func-attr-target.c| 8
2 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..b98cd093bc9b0e 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -237,22 +237,15 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
static std::vector
collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- auto ParseResult =
- llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride);
-
- if (!ParseResult) {
-consumeError(ParseResult.takeError());
-return std::vector();
- }
-
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
-
std::vector NonISAExtFeatureVec;
+ auto IsNonISAExtFeature = [](const std::string &Feature) {
+assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+std::string Ext = Feature.substr(1); // drop the +/-
+return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+ };
llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-[&](const std::string &Feat) {
- return !llvm::is_contained(ImpliedFeatures, Feat);
-});
+IsNonISAExtFeature);
return NonISAExtFeatureVec;
}
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 506acaba687417..759c33a2250600 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -40,8 +40,8 @@ __attribute__((target("cpu=sifive-u54"))) void
testAttrCpuOnly() {}
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa"
}
// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
-// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax,-zfa"
}
-// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
+// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax"
}
+// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax" }
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax,-zbb,-zfa"
}
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax"
}
___
cfe-commits mailin
[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/76962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76962
>From dfaf782113b977c9960358adab88767e23ddbc56 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 20:48:09 +0700
Subject: [PATCH] [RISCV] Fix collectNonISAExtFeature returning negative
extension features
collectNonISAExtFeature was returning any negative extension features, e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative extensions aren't emitted when calling toFeatureVector(), and
so were considered missing. Hence why we still see "-zfa" and "-zfb" in the
tests for the full arch string attributes, even though with a full arch string
we should be overriding the extensions.
This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead to
check if a feature is an ISA extension.
---
clang/lib/Basic/Targets/RISCV.cpp | 19 ++-
.../CodeGen/RISCV/riscv-func-attr-target.c| 8
2 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..b98cd093bc9b0e 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -237,22 +237,15 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
static std::vector
collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- auto ParseResult =
- llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride);
-
- if (!ParseResult) {
-consumeError(ParseResult.takeError());
-return std::vector();
- }
-
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
-
std::vector NonISAExtFeatureVec;
+ auto IsNonISAExtFeature = [](const std::string &Feature) {
+assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+std::string Ext = Feature.substr(1); // drop the +/-
+return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+ };
llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-[&](const std::string &Feat) {
- return !llvm::is_contained(ImpliedFeatures, Feat);
-});
+IsNonISAExtFeature);
return NonISAExtFeatureVec;
}
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 506acaba687417..759c33a2250600 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -40,8 +40,8 @@ __attribute__((target("cpu=sifive-u54"))) void
testAttrCpuOnly() {}
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa"
}
// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
-// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax,-zfa"
}
-// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
+// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax"
}
+// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax" }
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax,-zbb,-zfa"
}
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax"
}
___
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cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
lukel97 wrote: Note that this doesn't fix the issue described in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559. One approach that would build upon this would be to use the entire list of target features including negative extensions when a full arch string is specified. https://github.com/llvm/llvm-project/pull/76962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76962
>From dfaf782113b977c9960358adab88767e23ddbc56 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 20:48:09 +0700
Subject: [PATCH 1/2] [RISCV] Fix collectNonISAExtFeature returning negative
extension features
collectNonISAExtFeature was returning any negative extension features, e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative extensions aren't emitted when calling toFeatureVector(), and
so were considered missing. Hence why we still see "-zfa" and "-zfb" in the
tests for the full arch string attributes, even though with a full arch string
we should be overriding the extensions.
This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead to
check if a feature is an ISA extension.
---
clang/lib/Basic/Targets/RISCV.cpp | 19 ++-
.../CodeGen/RISCV/riscv-func-attr-target.c| 8
2 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..b98cd093bc9b0e 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -237,22 +237,15 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
static std::vector
collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- auto ParseResult =
- llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesNeedOverride);
-
- if (!ParseResult) {
-consumeError(ParseResult.takeError());
-return std::vector();
- }
-
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
-
std::vector NonISAExtFeatureVec;
+ auto IsNonISAExtFeature = [](const std::string &Feature) {
+assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+std::string Ext = Feature.substr(1); // drop the +/-
+return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+ };
llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-[&](const std::string &Feat) {
- return !llvm::is_contained(ImpliedFeatures, Feat);
-});
+IsNonISAExtFeature);
return NonISAExtFeatureVec;
}
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 506acaba687417..759c33a2250600 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -40,8 +40,8 @@ __attribute__((target("cpu=sifive-u54"))) void
testAttrCpuOnly() {}
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa"
}
// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
-// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax,-zfa"
}
-// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
+// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-relax"
}
+// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-relax" }
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax,-zbb,-zfa" }
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax,-zbb,-zfa"
}
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-relax" }
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,-relax"
}
>From 9ab6adf642d71b34280f5b410967c121dbffcc3d Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Fri, 5 Jan 2024 09:40:11 +0700
Subject: [PATCH 2/2] Use StringRef to avoid allocating new std::string
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index b98cd093bc9b0e..59ae12eed94014 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -241,7 +241,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
auto IsNonISAExtFeature = [](co
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/2] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..64f5f9e9215dcb 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -245,7 +245,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
return std::vector();
}
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
std::vector NonISAExtFeatureVec;
@@ -303,7 +303,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -420,7 +420,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
else
llvm_unreachable("XLEN should be 32 or 64.");
-Features.addFeaturesVector(ISAInfo->toFeatureVector());
+Features.addFeaturesVector(ISAInfo->toFeatures());
}
return Features;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..6d267fae5a5dc6 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExten
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/3] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..64f5f9e9215dcb 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -245,7 +245,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
return std::vector();
}
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
std::vector NonISAExtFeatureVec;
@@ -303,7 +303,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -420,7 +420,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
else
llvm_unreachable("XLEN should be 32 or 64.");
-Features.addFeaturesVector(ISAInfo->toFeatureVector());
+Features.addFeaturesVector(ISAInfo->toFeatures());
}
return Features;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..6d267fae5a5dc6 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExten
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/4] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..64f5f9e9215dcb 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -245,7 +245,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
return std::vector();
}
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
std::vector NonISAExtFeatureVec;
@@ -303,7 +303,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -420,7 +420,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
else
llvm_unreachable("XLEN should be 32 or 64.");
-Features.addFeaturesVector(ISAInfo->toFeatureVector());
+Features.addFeaturesVector(ISAInfo->toFeatures());
}
return Features;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..6d267fae5a5dc6 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExten
[clang] [llvm] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/5] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..64f5f9e9215dcb 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -245,7 +245,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
return std::vector();
}
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
std::vector NonISAExtFeatureVec;
@@ -303,7 +303,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -420,7 +420,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
else
llvm_unreachable("XLEN should be 32 or 64.");
-Features.addFeaturesVector(ISAInfo->toFeatureVector());
+Features.addFeaturesVector(ISAInfo->toFeatures());
}
return Features;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..6d267fae5a5dc6 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExten
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
@@ -42,9 +42,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ const auto ISAInfoFeatures = (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false);
+ Features.insert(Features.end(), ISAInfoFeatures.begin(),
+ ISAInfoFeatures.end());
lukel97 wrote:
Argh I was trying to be too clever and forgot that we need to call
Args.MakeArgString, I've just replaced it with the push_back loop again.
https://github.com/llvm/llvm-project/pull/76942
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[clang] [llvm] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
@@ -466,35 +466,35 @@ bool RISCVISAInfo::compareExtension(const std::string
&LHS,
return LHS < RHS;
}
-void RISCVISAInfo::toFeatures(
-std::vector &Features,
-llvm::function_ref StrAlloc,
-bool AddAllExtensions) const {
- for (auto const &Ext : Exts) {
-StringRef ExtName = Ext.first;
-
-if (ExtName == "i")
+std::vector RISCVISAInfo::toFeatures(bool AddAllExtensions,
+ bool IgnoreUnknown) const {
+ std::vector Features;
+ for (const auto &[ExtName, _] : Exts) {
+if (ExtName == "i") // i is not recognized in clang -cc1
lukel97 wrote:
This was just copied from the previous function, but would non-RISCV developers
need to read RISCVISAInfo.cpp? (Still happy to add a link to the spec if you
would prefer)
https://github.com/llvm/llvm-project/pull/76942
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[clang] 2c213c4 - [Clang] Fix reference to sve in rvv driver test comment. NFC
Author: Luke Lau
Date: 2024-01-08T16:04:33+07:00
New Revision: 2c213c45046b78eac48809b013e7a80099607ebb
URL:
https://github.com/llvm/llvm-project/commit/2c213c45046b78eac48809b013e7a80099607ebb
DIFF:
https://github.com/llvm/llvm-project/commit/2c213c45046b78eac48809b013e7a80099607ebb.diff
LOG: [Clang] Fix reference to sve in rvv driver test comment. NFC
Added:
Modified:
clang/test/Driver/riscv-rvv-vector-bits.c
Removed:
diff --git a/clang/test/Driver/riscv-rvv-vector-bits.c
b/clang/test/Driver/riscv-rvv-vector-bits.c
index e92b66c972daf3..24af5f0c73c6ef 100644
--- a/clang/test/Driver/riscv-rvv-vector-bits.c
+++ b/clang/test/Driver/riscv-rvv-vector-bits.c
@@ -44,7 +44,7 @@
// CHECK-BAD-VALUE-ERROR: error: unsupported argument '{{.*}}' to option
'-mrvv-vector-bits='
-// Error if using attribute without -msve-vector-bits= or if using
-msve-vector-bits=+ syntax
+// Error if using attribute without -mrvv-vector-bits= or if using
-mrvv-vector-bits=+ syntax
//
-
// RUN: not %clang -c %s -o /dev/null -target riscv64-linux-gnu \
// RUN: -march=rv64gc_zve64x 2>&1 | FileCheck
--check-prefix=CHECK-NO-FLAG-ERROR %s
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[clang] [RISCV] Fix collectNonISAExtFeature returning negative extension features (PR #76962)
https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/76962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77327
In #77277, we would like to be able to reuse the logic for calculating the
vscale_range in Flang. This is currently in clang::TargetInfo which is quite C
specific, and given that only two targets implement getVScaleRange, it doesn't
seem worthwhile trying to shoehorn clang::TargetInfo into Flang.
This instead moves the logic into llvm/Frontend/Driver where it can be shared
by both (provided that a RISCVISAInfo is passed in: we don't want to have to
ecompute it every time).
>From a8e28b566030434b499d37270d16e7b425aa6f05 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Mon, 8 Jan 2024 22:29:22 +0700
Subject: [PATCH] [Clang][RISCV] Move getVScaleRange logic into
libLLVMFrontendDriver. NFC
In #77277, we would like to be able to reuse the logic for calculating the
vscale_range in Flang. This is currently in clang::TargetInfo which is quite C
specific, and given that only two targets implement getVScaleRange, it doesn't
seem worthwhile trying to shoehorn clang::TargetInfo into Flang.
This instead moves the logic into llvm/Frontend/Driver where it can be shared
by both (provided that a RISCVISAInfo is passed in: we don't want to have to
ecompute it every time).
---
clang/lib/Basic/CMakeLists.txt| 1 +
clang/lib/Basic/Targets/RISCV.cpp | 21 ++---
llvm/include/llvm/Frontend/Driver/RISCV.h | 27 +
llvm/lib/Frontend/Driver/CMakeLists.txt | 1 +
llvm/lib/Frontend/Driver/RISCV.cpp| 37 +++
5 files changed, 69 insertions(+), 18 deletions(-)
create mode 100644 llvm/include/llvm/Frontend/Driver/RISCV.h
create mode 100644 llvm/lib/Frontend/Driver/RISCV.cpp
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 2e218ba7c84cca..8ab960c7212f88 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS
Support
TargetParser
FrontendOpenMP
+ FrontendDriver
)
find_first_existing_vc_file("${LLVM_MAIN_SRC_DIR}" llvm_vc)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..b090a9b167a202 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -15,6 +15,7 @@
#include "clang/Basic/MacroBuilder.h"
#include "clang/Basic/TargetBuiltins.h"
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Frontend/Driver/RISCV.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TargetParser/RISCVTargetParser.h"
#include
@@ -321,24 +322,8 @@ bool RISCVTargetInfo::initFeatureMap(
std::optional>
RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
- // RISCV::RVVBitsPerBlock is 64.
- unsigned VScaleMin = ISAInfo->getMinVLen() / llvm::RISCV::RVVBitsPerBlock;
-
- if (LangOpts.VScaleMin || LangOpts.VScaleMax) {
-// Treat Zvl*b as a lower bound on vscale.
-VScaleMin = std::max(VScaleMin, LangOpts.VScaleMin);
-unsigned VScaleMax = LangOpts.VScaleMax;
-if (VScaleMax != 0 && VScaleMax < VScaleMin)
- VScaleMax = VScaleMin;
-return std::pair(VScaleMin ? VScaleMin : 1, VScaleMax);
- }
-
- if (VScaleMin > 0) {
-unsigned VScaleMax = ISAInfo->getMaxVLen() / llvm::RISCV::RVVBitsPerBlock;
-return std::make_pair(VScaleMin, VScaleMax);
- }
-
- return std::nullopt;
+ return llvm::driver::riscv::getVScaleRange(*ISAInfo, LangOpts.VScaleMin,
+ LangOpts.VScaleMax);
}
/// Return true if has this feature, need to sync with handleTargetFeatures.
diff --git a/llvm/include/llvm/Frontend/Driver/RISCV.h
b/llvm/include/llvm/Frontend/Driver/RISCV.h
new file mode 100644
index 00..1f81f089087b51
--- /dev/null
+++ b/llvm/include/llvm/Frontend/Driver/RISCV.h
@@ -0,0 +1,27 @@
+//===--- RISCV.h *- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines RISC-V frontend logic common to clang and flang
+//
+//===--===//
+
+#ifndef LLVM_FRONTEND_DRIVER_RISCV_H
+#define LLVM_FRONTEND_DRIVER_RISCV_H
+
+#include "llvm/Support/RISCVISAInfo.h"
+#include
+
+namespace llvm::driver::riscv {
+
+std::optional>
+getVScaleRange(const RISCVISAInfo &ISAInfo, unsigned ExplicitMin,
+ unsigned ExplicitMax);
+
+} // namespace llvm::driver::riscv
+
+#endif
diff --git a/llvm/lib/Frontend/Driver/CMakeLists.txt
b/llvm/lib/Frontend/Driver/CMakeLists.txt
index 23de4994a300d8..ac0bc27a248a36 100644
--- a/llvm/lib/Frontend/Driver/CMakeLists.txt
+++ b/llvm/lib/Frontend/Driver/CMakeLists.txt
@@ -1,5 +1,6 @@
add_llvm_component_libra
[clang] [llvm] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From caa25a73dd69268490c89d5e9e91b8d545bce760 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/6] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 6 ++--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 6bc57a83a2d5ae..64f5f9e9215dcb 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -245,7 +245,7 @@ collectNonISAExtFeature(ArrayRef
FeaturesNeedOverride, int XLen) {
return std::vector();
}
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
std::vector NonISAExtFeatureVec;
@@ -303,7 +303,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -420,7 +420,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
else
llvm_unreachable("XLEN should be 32 or 64.");
-Features.addFeaturesVector(ISAInfo->toFeatureVector());
+Features.addFeaturesVector(ISAInfo->toFeatures());
}
return Features;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..6d267fae5a5dc6 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExten
[clang] [llvm] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/76942
>From e0b653a5f81d18155583f6dfd669003b6664a517 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 4 Jan 2024 14:02:39 +0900
Subject: [PATCH 1/6] [RISCV] Deduplicate
RISCVISAInfo::toFeatures/toFeatureVector. NFC
toFeatures and toFeatureVector both output a list of target feature flags, just
with a slightly different interface. toFeatures keeps any unsupported
extensions, and also provides a way to append negative extensions
(AddAllExtensions=true).
This patch combines them into one function, so that a later patch will be be
able to get a std::vector of features that includes all the negative
extensions, which was previously only possible through the StrAlloc interface.
---
clang/lib/Basic/Targets/RISCV.cpp | 4 +--
clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 6 ++--
llvm/include/llvm/Support/RISCVISAInfo.h| 6 ++--
llvm/lib/Object/ELFObjectFile.cpp | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 38 +++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 30 +---
6 files changed, 45 insertions(+), 41 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index 59ae12eed94014..daaa8639ae8358 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -296,7 +296,7 @@ bool RISCVTargetInfo::initFeatureMap(
}
// RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatureVector();
+ std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
// parseFeatures normalizes the feature set by dropping any explicit
// negatives, and non-extension features. We need to preserve the later
@@ -413,7 +413,7 @@ static void handleFullArchString(StringRef FullArchStr,
// Forward the invalid FullArchStr.
Features.push_back("+" + FullArchStr.str());
} else {
-std::vector FeatStrings = (*RII)->toFeatureVector();
+std::vector FeatStrings = (*RII)->toFeatures();
Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index 0717e3b813e1e2..b97224426b916a 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -42,9 +42,9 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ for (std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
+ /*IgnoreUnknown=*/false))
+Features.push_back(Args.MakeArgString(Str));
if (EnableExperimentalExtensions)
Features.push_back(Args.MakeArgString("+experimental"));
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 09c4edd6df60e9..c539448683d368 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -68,9 +68,8 @@ class RISCVISAInfo {
parseFeatures(unsigned XLen, const std::vector &Features);
/// Convert RISC-V ISA info to a feature vector.
- void toFeatures(std::vector &Features,
- llvm::function_ref StrAlloc,
- bool AddAllExtensions) const;
+ std::vector toFeatures(bool AddAllExtensions = false,
+ bool IgnoreUnknown = true) const;
const OrderedExtensionMap &getExtensions() const { return Exts; };
@@ -83,7 +82,6 @@ class RISCVISAInfo {
bool hasExtension(StringRef Ext) const;
std::string toString() const;
- std::vector toFeatureVector() const;
StringRef computeDefaultABI() const;
static bool isSupportedExtensionFeature(StringRef Ext);
diff --git a/llvm/lib/Object/ELFObjectFile.cpp
b/llvm/lib/Object/ELFObjectFile.cpp
index 95c4f9f8545db2..ae21b81c10c82a 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -315,7 +315,7 @@ Expected
ELFObjectFileBase::getRISCVFeatures() const {
else
llvm_unreachable("XLEN should be 32 or 64.");
-Features.addFeaturesVector(ISAInfo->toFeatureVector());
+Features.addFeaturesVector(ISAInfo->toFeatures());
}
return Features;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index a9b7e209915a13..6d267fae5a5dc6 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -466,35 +466,37 @@ bool RISCVISAInfo::compareExtension(const std::string
&LHS,
return LHS < RHS;
}
-void RISCVISAInfo::toFeatures(
-std::vector &Features,
-llvm::function_ref StrAlloc,
-bool AddAllExtensions) const {
+std::vector RISCVISAInfo::toFeatures(bool AddAllExtensions,
+
[llvm] [clang] [RISCV] Deduplicate RISCVISAInfo::toFeatures/toFeatureVector. NFC (PR #76942)
https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/76942 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77426
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.
In initFeatureMap, there are now two code paths:
1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.
Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.
2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH] [RISCV] Overwrite cpu target features for full arch string in
target attribute
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.
In initFeatureMap, there are now two code paths:
1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.
Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.
2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
---
clang/lib/Basic/Targets/RISCV.cpp | 78 +++
.../CodeGen/RISCV/riscv-func-attr-target.c| 8 +-
2 files changed, 30 insertions(+), 56 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..b56c1d465ad77a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,39 +235,6 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
-static std::vector
-collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- std::vector NonISAExtFeatureVec;
-
- auto IsNonISAExtFeature = [](const std::string &Feature) {
-assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
-StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
-return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
- };
- llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-IsNonISAExtFeature);
-
- return NonISAExtFeatureVec;
-}
-
-static std::vector
-resolveTargetAttrOverride(const std::vector &FeaturesVec,
- int XLen) {
- auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
- if (I == FeaturesVec.end())
-return FeaturesVec;
-
- ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
- std::vector NonISAExtFeature =
- collectNonISAExtFeature(FeaturesNeedOverride, XLen);
-
- std::vector ResolvedFeature(++I, FeaturesVec.end());
- ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
- NonISAExtFeature.end());
-
- return ResolvedFeature;
-}
-
bool RISCVTargetInfo::initFeatureMap(
llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector &FeaturesVec) const {
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension target features.
+ const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures = std::vector(std::next(I),
FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string &Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ std::string Ext = Feat
[clang] [llvm] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
lukel97 wrote: > I'm wondering if you considered moving the helper function into RISCVISAInfo? Initially yes, but I ended up backing out of it since it would have been the only bit of "codegen" logic in RISCVISAInfo, and it seemed a shame to pollute it. I also have a feeling that we will need to share more RISC-V specific driver logic between clang and flang eventually, e.g. the logic for `-mrvv-vector-bits` in Clang::AddRISCVTargetArgs. Although I would note that most targets don't need to move code into `libLLVMFrontendDriver`, RISC-V just happens to have quite a lot of RVV specific logic that isn't specific to C. https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/4] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+{"za128rs", RISCVExtensionVersion{1, 0}},
+{"za64rs", RISCVExtensionVersion{1, 0}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", RISCVExtensionVersion{1, 0}},
{"zhinxmin", RISCVExtensionVersion{1, 0}},
+{"zic64b", RISCVExtensionVersion{1, 0}},
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
+{"ziccamoa", RISCVExtensionVersion{1, 0}},
+{"ziccif", RISCVExtensionVersion{1, 0}},
+{"zicclsm", RISCVExtensionVersion{1, 0}},
+{"ziccrse", RISCVExtensionVersion{1, 0}},
{"zicntr", RISCVExtensionVersion{2, 0}},
{"zicsr", RISCVExtensionVersion{2, 0}},
{"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..83
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
lukel97 wrote: @asb I got a response from https://github.com/riscv/riscv-profiles/issues/139, looks like Ziccrse, Ziccamoa, Za64rs, and Za128rs don't imply A. https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/5] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+{"za128rs", RISCVExtensionVersion{1, 0}},
+{"za64rs", RISCVExtensionVersion{1, 0}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", RISCVExtensionVersion{1, 0}},
{"zhinxmin", RISCVExtensionVersion{1, 0}},
+{"zic64b", RISCVExtensionVersion{1, 0}},
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
+{"ziccamoa", RISCVExtensionVersion{1, 0}},
+{"ziccif", RISCVExtensionVersion{1, 0}},
+{"zicclsm", RISCVExtensionVersion{1, 0}},
+{"ziccrse", RISCVExtensionVersion{1, 0}},
{"zicntr", RISCVExtensionVersion{2, 0}},
{"zicsr", RISCVExtensionVersion{2, 0}},
{"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..83
[llvm] [clang] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
lukel97 wrote: > These names will be used in profiles only, but I don't know if we should add > them to RISCVUsage.rst. Good point, I added them in anyway so we're consistent at least. I couldn't find any other "featureless" extensions that we currently support. https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS Support TargetParser FrontendOpenMP + FrontendDriver lukel97 wrote: I agree. I think I'm coming around to the opinion that this is a bit overkill just to avoid duplicating 16 lines of code. I'm also thinking that flang and clang don't need to behave exactly the same in this regard. So we don't necessarily need to keep the two in sync. Thoughts? cc @tschuett https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
@@ -2,6 +2,7 @@ set(LLVM_LINK_COMPONENTS Support TargetParser FrontendOpenMP + FrontendDriver lukel97 wrote: I think the issue with llvmFrontendDriver specifically is that this code wouldn't be called from any of the drivers, it would be called from clangBasic and flangFrontend respectively. Could we create something like llvmFrontendSupport or similar? https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Flang] Support -mrvv-vector-bits flag (PR #77588)
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77588
This patch adds support for the -mrvv-vector-bits flag in the Flang driver, and
translates them to -mvscale-min/-mvscale-max.
The code was copied from the Clang toolchain (similarly to what was done for
AArch64's -msve-vector-bits flag) so it also supports the same
-mrvv-vector-bits=zvl mode.
Note that Flang doesn't yet define the __riscv_v_fixed_vlen macro, so the help
text has been updated to highlight that it's only defined for Clang.
>From 66f47b300afa5f68934c93fed0b16d7a389cf49d Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Wed, 10 Jan 2024 18:22:03 +0700
Subject: [PATCH] [Flang] Support -mrvv-vector-bits flag
This patch adds support for the -mrvv-vector-bits flag in the Flang driver, and
translates them to -mvscale-min/-mvscale-max.
The code was copied from the Clang toolchain (similarly to what was done for
AArch64's -msve-vector-bits flag) so it also supports the same
-mrvv-vector-bits=zvl mode.
Note that Flang doesn't yet define the __riscv_v_fixed_vlen macro, so the help
text has been updated to highlight that it's only defined for Clang.
---
clang/include/clang/Driver/Options.td | 6 ++-
clang/lib/Driver/ToolChains/Flang.cpp | 51 +
clang/lib/Driver/ToolChains/Flang.h | 7 +++
flang/test/Driver/driver-help-hidden.f90| 2 +
flang/test/Driver/driver-help.f90 | 2 +
flang/test/Driver/riscv-rvv-vector-bits.f90 | 51 +
6 files changed, 117 insertions(+), 2 deletions(-)
create mode 100644 flang/test/Driver/riscv-rvv-vector-bits.f90
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index bffdddc28aac60..4de738ef27ae8b 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4585,11 +4585,13 @@ let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group,
+ Visibility<[ClangOption, FlangOption]>,
HelpText<"Specify the size in bits of an RVV vector register. Defaults to "
"the vector length agnostic value of \"scalable\". Accepts power of
"
"2 values between 64 and 65536. Also accepts \"zvl\" "
- "to use the value implied by -march/-mcpu. Value will be reflected "
- "in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">;
+ "to use the value implied by -march/-mcpu. On Clang, value will be "
+ "reflected in __riscv_v_fixed_vlen preprocessor define (RISC-V "
+ "only)">;
def munaligned_access : Flag<["-"], "munaligned-access">, Group,
HelpText<"Allow memory accesses to be unaligned
(AArch32/AArch64/LoongArch/RISC-V only)">;
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp
b/clang/lib/Driver/ToolChains/Flang.cpp
index 41eaad3bbad0a3..ccb9f75e21e558 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "Flang.h"
+#include "Arch/RISCV.h"
#include "CommonArgs.h"
#include "clang/Basic/CodeGenOptions.h"
@@ -14,6 +15,8 @@
#include "llvm/Frontend/Debug/Options.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include
@@ -203,6 +206,51 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args,
}
}
+void Flang::AddRISCVTargetArgs(const ArgList &Args,
+ ArgStringList &CmdArgs) const {
+ const llvm::Triple &Triple = getToolChain().getTriple();
+ // Handle -mrvv-vector-bits=
+ if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
+StringRef Val = A->getValue();
+const Driver &D = getToolChain().getDriver();
+
+// Get minimum VLen from march.
+unsigned MinVLen = 0;
+StringRef Arch = riscv::getRISCVArch(Args, Triple);
+auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
+Arch, /*EnableExperimentalExtensions*/ true);
+// Ignore parsing error.
+if (!errorToBool(ISAInfo.takeError()))
+ MinVLen = (*ISAInfo)->getMinVLen();
+
+// If the value is "zvl", use MinVLen from march. Otherwise, try to parse
+// as integer as long as we have a MinVLen.
+unsigned Bits = 0;
+if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) {
+ Bits = MinVLen;
+} else if (!Val.getAsInteger(10, Bits)) {
+ // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that
+ // at least MinVLen.
+ if (Bits < MinVLen || Bits < llvm::RISCV::RVVBitsPerBlock ||
+ Bits > 65536 || !llvm::isPowerOf2_32(Bits))
+Bits = 0;
+}
+
+// If we got a valid value try to use it.
+if
[llvm] [clang] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/6] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+{"za128rs", RISCVExtensionVersion{1, 0}},
+{"za64rs", RISCVExtensionVersion{1, 0}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", RISCVExtensionVersion{1, 0}},
{"zhinxmin", RISCVExtensionVersion{1, 0}},
+{"zic64b", RISCVExtensionVersion{1, 0}},
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
+{"ziccamoa", RISCVExtensionVersion{1, 0}},
+{"ziccif", RISCVExtensionVersion{1, 0}},
+{"zicclsm", RISCVExtensionVersion{1, 0}},
+{"ziccrse", RISCVExtensionVersion{1, 0}},
{"zicntr", RISCVExtensionVersion{2, 0}},
{"zicsr", RISCVExtensionVersion{2, 0}},
{"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..83
[flang] [clang] [Flang] Support -mrvv-vector-bits flag (PR #77588)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77588
>From 66f47b300afa5f68934c93fed0b16d7a389cf49d Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Wed, 10 Jan 2024 18:22:03 +0700
Subject: [PATCH 1/2] [Flang] Support -mrvv-vector-bits flag
This patch adds support for the -mrvv-vector-bits flag in the Flang driver, and
translates them to -mvscale-min/-mvscale-max.
The code was copied from the Clang toolchain (similarly to what was done for
AArch64's -msve-vector-bits flag) so it also supports the same
-mrvv-vector-bits=zvl mode.
Note that Flang doesn't yet define the __riscv_v_fixed_vlen macro, so the help
text has been updated to highlight that it's only defined for Clang.
---
clang/include/clang/Driver/Options.td | 6 ++-
clang/lib/Driver/ToolChains/Flang.cpp | 51 +
clang/lib/Driver/ToolChains/Flang.h | 7 +++
flang/test/Driver/driver-help-hidden.f90| 2 +
flang/test/Driver/driver-help.f90 | 2 +
flang/test/Driver/riscv-rvv-vector-bits.f90 | 51 +
6 files changed, 117 insertions(+), 2 deletions(-)
create mode 100644 flang/test/Driver/riscv-rvv-vector-bits.f90
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index bffdddc28aac60..4de738ef27ae8b 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4585,11 +4585,13 @@ let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group,
+ Visibility<[ClangOption, FlangOption]>,
HelpText<"Specify the size in bits of an RVV vector register. Defaults to "
"the vector length agnostic value of \"scalable\". Accepts power of
"
"2 values between 64 and 65536. Also accepts \"zvl\" "
- "to use the value implied by -march/-mcpu. Value will be reflected "
- "in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">;
+ "to use the value implied by -march/-mcpu. On Clang, value will be "
+ "reflected in __riscv_v_fixed_vlen preprocessor define (RISC-V "
+ "only)">;
def munaligned_access : Flag<["-"], "munaligned-access">, Group,
HelpText<"Allow memory accesses to be unaligned
(AArch32/AArch64/LoongArch/RISC-V only)">;
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp
b/clang/lib/Driver/ToolChains/Flang.cpp
index 41eaad3bbad0a3..ccb9f75e21e558 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -7,6 +7,7 @@
//===--===//
#include "Flang.h"
+#include "Arch/RISCV.h"
#include "CommonArgs.h"
#include "clang/Basic/CodeGenOptions.h"
@@ -14,6 +15,8 @@
#include "llvm/Frontend/Debug/Options.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Path.h"
+#include "llvm/Support/RISCVISAInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include
@@ -203,6 +206,51 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args,
}
}
+void Flang::AddRISCVTargetArgs(const ArgList &Args,
+ ArgStringList &CmdArgs) const {
+ const llvm::Triple &Triple = getToolChain().getTriple();
+ // Handle -mrvv-vector-bits=
+ if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
+StringRef Val = A->getValue();
+const Driver &D = getToolChain().getDriver();
+
+// Get minimum VLen from march.
+unsigned MinVLen = 0;
+StringRef Arch = riscv::getRISCVArch(Args, Triple);
+auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
+Arch, /*EnableExperimentalExtensions*/ true);
+// Ignore parsing error.
+if (!errorToBool(ISAInfo.takeError()))
+ MinVLen = (*ISAInfo)->getMinVLen();
+
+// If the value is "zvl", use MinVLen from march. Otherwise, try to parse
+// as integer as long as we have a MinVLen.
+unsigned Bits = 0;
+if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) {
+ Bits = MinVLen;
+} else if (!Val.getAsInteger(10, Bits)) {
+ // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that
+ // at least MinVLen.
+ if (Bits < MinVLen || Bits < llvm::RISCV::RVVBitsPerBlock ||
+ Bits > 65536 || !llvm::isPowerOf2_32(Bits))
+Bits = 0;
+}
+
+// If we got a valid value try to use it.
+if (Bits != 0) {
+ unsigned VScaleMin = Bits / llvm::RISCV::RVVBitsPerBlock;
+ CmdArgs.push_back(
+ Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin)));
+ CmdArgs.push_back(
+ Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin)));
+} else if (!Val.equals("scalable")) {
+ // Handle the unsupported values passed to mrvv-vector-bits.
+ D.Diag(diag::err_drv_unsupported_option_argum
[flang] [clang] [Flang] Support -mrvv-vector-bits flag (PR #77588)
https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/77588 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/lukel97 created
https://github.com/llvm/llvm-project/pull/77645
We have two structs for representing the version of an extension in
RISCVISAInfo, with the exact same fields. This patch deduplicates them.
> [!NOTE]
> When renaming the struct, I also dropped the struct's name from the {}
> initializers in the supported extensions lists, rather than adding in the new
> name. I have no strong opinion on this though.
>From 916d4f271982501b7236d60b90c9fa822f7aa2a6 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 11 Jan 2024 00:44:19 +0700
Subject: [PATCH] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC
We have two structs for representing the version of an extension in
RISCVISAInfo, with the exact same fields. This patch deduplicates them.
> [!NOTE]
> When renaming the struct, I also dropped the struct's name from the {}
> initializers in the supported extensions lists, rather than adding in the new
> name. I have no strong opinion on this though.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
llvm/include/llvm/Support/RISCVISAInfo.h| 16 +-
llvm/lib/Support/RISCVISAInfo.cpp | 330 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 76 ++---
4 files changed, 207 insertions(+), 217 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..abd947700a69ab 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -165,7 +165,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro(
Twine("__riscv_", ExtName),
-Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion)));
+Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
}
if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 97f1051b0540a7..46df93d7522602 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -18,11 +18,6 @@
#include
namespace llvm {
-struct RISCVExtensionInfo {
- unsigned MajorVersion;
- unsigned MinorVersion;
-};
-
void riscvExtensionsHelp(StringMap DescMap);
class RISCVISAInfo {
@@ -30,6 +25,12 @@ class RISCVISAInfo {
RISCVISAInfo(const RISCVISAInfo &) = delete;
RISCVISAInfo &operator=(const RISCVISAInfo &) = delete;
+ /// Represents the major and version number components of a RISC-V extension.
+ struct ExtensionVersion {
+unsigned Major;
+unsigned Minor;
+ };
+
static bool compareExtension(const std::string &LHS, const std::string &RHS);
/// Helper class for OrderedExtensionMap.
@@ -41,7 +42,7 @@ class RISCVISAInfo {
/// OrderedExtensionMap is std::map, it's specialized to keep entries
/// in canonical order of extension.
- typedef std::map
+ typedef std::map
OrderedExtensionMap;
RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts)
@@ -104,8 +105,7 @@ class RISCVISAInfo {
OrderedExtensionMap Exts;
- void addExtension(StringRef ExtName, unsigned MajorVersion,
-unsigned MinorVersion);
+ void addExtension(StringRef ExtName, ExtensionVersion Version);
Error checkDependency();
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..86be440addc0e9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -24,16 +24,11 @@
using namespace llvm;
namespace {
-/// Represents the major and version number components of a RISC-V extension
-struct RISCVExtensionVersion {
- unsigned Major;
- unsigned Minor;
-};
struct RISCVSupportedExtension {
const char *Name;
/// Supported version.
- RISCVExtensionVersion Version;
+ RISCVISAInfo::ExtensionVersion Version;
bool operator<(const RISCVSupportedExtension &RHS) const {
return StringRef(Name) < StringRef(RHS.Name);
@@ -50,161 +45,161 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
-{"a", RISCVExtensionVersion{2, 1}},
-{"c", RISCVExtensionVersion{2, 0}},
-{"d", RISCVExtensionVersion{2, 2}},
-{"e", RISCVExtensionVersion{2, 0}},
-{"f", RISCVExtensionVersion{2, 2}},
-{"h", RISCVExtensionVersion{1, 0}},
-{"i", RISCVExtensionVersion{2, 1}},
-{"m", RISCVExtensionVersion{2, 0}},
-
-{"smaia", RISCVExtensionVersion{1, 0}},
-{"ssaia", RISCVExtensionVersion{1, 0}},
-{"svinval", RISCVExtensionVersion{1, 0}},
-{"svnapot", RISCVExtensionVersion{1, 0}},
-{"svpbmt", RISCVExtensionVersion{1, 0}},
-
-{"v", RISCVExtensionVersion{1, 0}},
+{"a", {2, 1}},
+{"c", {2, 0}},
+{"d", {2, 2}},
+{"e", {2, 0}},
+{"f", {2, 2}},
+{"h", {1, 0}},
+{"i", {2, 1}},
+{"m", {2, 0}},
+
+{"smaia", {1, 0}},
+
[llvm] [clang] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/77645 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/77645 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77645
>From 916d4f271982501b7236d60b90c9fa822f7aa2a6 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 11 Jan 2024 00:44:19 +0700
Subject: [PATCH 1/2] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC
We have two structs for representing the version of an extension in
RISCVISAInfo, with the exact same fields. This patch deduplicates them.
> [!NOTE]
> When renaming the struct, I also dropped the struct's name from the {}
> initializers in the supported extensions lists, rather than adding in the new
> name. I have no strong opinion on this though.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
llvm/include/llvm/Support/RISCVISAInfo.h| 16 +-
llvm/lib/Support/RISCVISAInfo.cpp | 330 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 76 ++---
4 files changed, 207 insertions(+), 217 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..abd947700a69ab 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -165,7 +165,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro(
Twine("__riscv_", ExtName),
-Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion)));
+Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
}
if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 97f1051b0540a7..46df93d7522602 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -18,11 +18,6 @@
#include
namespace llvm {
-struct RISCVExtensionInfo {
- unsigned MajorVersion;
- unsigned MinorVersion;
-};
-
void riscvExtensionsHelp(StringMap DescMap);
class RISCVISAInfo {
@@ -30,6 +25,12 @@ class RISCVISAInfo {
RISCVISAInfo(const RISCVISAInfo &) = delete;
RISCVISAInfo &operator=(const RISCVISAInfo &) = delete;
+ /// Represents the major and version number components of a RISC-V extension.
+ struct ExtensionVersion {
+unsigned Major;
+unsigned Minor;
+ };
+
static bool compareExtension(const std::string &LHS, const std::string &RHS);
/// Helper class for OrderedExtensionMap.
@@ -41,7 +42,7 @@ class RISCVISAInfo {
/// OrderedExtensionMap is std::map, it's specialized to keep entries
/// in canonical order of extension.
- typedef std::map
+ typedef std::map
OrderedExtensionMap;
RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts)
@@ -104,8 +105,7 @@ class RISCVISAInfo {
OrderedExtensionMap Exts;
- void addExtension(StringRef ExtName, unsigned MajorVersion,
-unsigned MinorVersion);
+ void addExtension(StringRef ExtName, ExtensionVersion Version);
Error checkDependency();
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..86be440addc0e9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -24,16 +24,11 @@
using namespace llvm;
namespace {
-/// Represents the major and version number components of a RISC-V extension
-struct RISCVExtensionVersion {
- unsigned Major;
- unsigned Minor;
-};
struct RISCVSupportedExtension {
const char *Name;
/// Supported version.
- RISCVExtensionVersion Version;
+ RISCVISAInfo::ExtensionVersion Version;
bool operator<(const RISCVSupportedExtension &RHS) const {
return StringRef(Name) < StringRef(RHS.Name);
@@ -50,161 +45,161 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
-{"a", RISCVExtensionVersion{2, 1}},
-{"c", RISCVExtensionVersion{2, 0}},
-{"d", RISCVExtensionVersion{2, 2}},
-{"e", RISCVExtensionVersion{2, 0}},
-{"f", RISCVExtensionVersion{2, 2}},
-{"h", RISCVExtensionVersion{1, 0}},
-{"i", RISCVExtensionVersion{2, 1}},
-{"m", RISCVExtensionVersion{2, 0}},
-
-{"smaia", RISCVExtensionVersion{1, 0}},
-{"ssaia", RISCVExtensionVersion{1, 0}},
-{"svinval", RISCVExtensionVersion{1, 0}},
-{"svnapot", RISCVExtensionVersion{1, 0}},
-{"svpbmt", RISCVExtensionVersion{1, 0}},
-
-{"v", RISCVExtensionVersion{1, 0}},
+{"a", {2, 1}},
+{"c", {2, 0}},
+{"d", {2, 2}},
+{"e", {2, 0}},
+{"f", {2, 2}},
+{"h", {1, 0}},
+{"i", {2, 1}},
+{"m", {2, 0}},
+
+{"smaia", {1, 0}},
+{"ssaia", {1, 0}},
+{"svinval", {1, 0}},
+{"svnapot", {1, 0}},
+{"svpbmt", {1, 0}},
+
+{"v", {1, 0}},
// vendor-defined ('X') extensions
-{"xcvalu", RISCVExtensionVersion{1, 0}},
-{"xcvbi", RISCVExtensionVersion{1, 0}},
-{"xcvbitmanip", RISCVExtensionVersion{1, 0}},
-{"xcvelw", RISCVExtensionVersion{1, 0}},
-
[llvm] [lld] [clang] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77645
>From 916d4f271982501b7236d60b90c9fa822f7aa2a6 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Thu, 11 Jan 2024 00:44:19 +0700
Subject: [PATCH 1/3] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC
We have two structs for representing the version of an extension in
RISCVISAInfo, with the exact same fields. This patch deduplicates them.
> [!NOTE]
> When renaming the struct, I also dropped the struct's name from the {}
> initializers in the supported extensions lists, rather than adding in the new
> name. I have no strong opinion on this though.
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
llvm/include/llvm/Support/RISCVISAInfo.h| 16 +-
llvm/lib/Support/RISCVISAInfo.cpp | 330 ++--
llvm/unittests/Support/RISCVISAInfoTest.cpp | 76 ++---
4 files changed, 207 insertions(+), 217 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..abd947700a69ab 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -165,7 +165,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro(
Twine("__riscv_", ExtName),
-Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion)));
+Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
}
if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h
b/llvm/include/llvm/Support/RISCVISAInfo.h
index 97f1051b0540a7..46df93d7522602 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -18,11 +18,6 @@
#include
namespace llvm {
-struct RISCVExtensionInfo {
- unsigned MajorVersion;
- unsigned MinorVersion;
-};
-
void riscvExtensionsHelp(StringMap DescMap);
class RISCVISAInfo {
@@ -30,6 +25,12 @@ class RISCVISAInfo {
RISCVISAInfo(const RISCVISAInfo &) = delete;
RISCVISAInfo &operator=(const RISCVISAInfo &) = delete;
+ /// Represents the major and version number components of a RISC-V extension.
+ struct ExtensionVersion {
+unsigned Major;
+unsigned Minor;
+ };
+
static bool compareExtension(const std::string &LHS, const std::string &RHS);
/// Helper class for OrderedExtensionMap.
@@ -41,7 +42,7 @@ class RISCVISAInfo {
/// OrderedExtensionMap is std::map, it's specialized to keep entries
/// in canonical order of extension.
- typedef std::map
+ typedef std::map
OrderedExtensionMap;
RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts)
@@ -104,8 +105,7 @@ class RISCVISAInfo {
OrderedExtensionMap Exts;
- void addExtension(StringRef ExtName, unsigned MajorVersion,
-unsigned MinorVersion);
+ void addExtension(StringRef ExtName, ExtensionVersion Version);
Error checkDependency();
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..86be440addc0e9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -24,16 +24,11 @@
using namespace llvm;
namespace {
-/// Represents the major and version number components of a RISC-V extension
-struct RISCVExtensionVersion {
- unsigned Major;
- unsigned Minor;
-};
struct RISCVSupportedExtension {
const char *Name;
/// Supported version.
- RISCVExtensionVersion Version;
+ RISCVISAInfo::ExtensionVersion Version;
bool operator<(const RISCVSupportedExtension &RHS) const {
return StringRef(Name) < StringRef(RHS.Name);
@@ -50,161 +45,161 @@ static const char *RISCVGImplications[] = {
// NOTE: This table should be sorted alphabetically by extension name.
static const RISCVSupportedExtension SupportedExtensions[] = {
-{"a", RISCVExtensionVersion{2, 1}},
-{"c", RISCVExtensionVersion{2, 0}},
-{"d", RISCVExtensionVersion{2, 2}},
-{"e", RISCVExtensionVersion{2, 0}},
-{"f", RISCVExtensionVersion{2, 2}},
-{"h", RISCVExtensionVersion{1, 0}},
-{"i", RISCVExtensionVersion{2, 1}},
-{"m", RISCVExtensionVersion{2, 0}},
-
-{"smaia", RISCVExtensionVersion{1, 0}},
-{"ssaia", RISCVExtensionVersion{1, 0}},
-{"svinval", RISCVExtensionVersion{1, 0}},
-{"svnapot", RISCVExtensionVersion{1, 0}},
-{"svpbmt", RISCVExtensionVersion{1, 0}},
-
-{"v", RISCVExtensionVersion{1, 0}},
+{"a", {2, 1}},
+{"c", {2, 0}},
+{"d", {2, 2}},
+{"e", {2, 0}},
+{"f", {2, 2}},
+{"h", {1, 0}},
+{"i", {2, 1}},
+{"m", {2, 0}},
+
+{"smaia", {1, 0}},
+{"ssaia", {1, 0}},
+{"svinval", {1, 0}},
+{"svnapot", {1, 0}},
+{"svpbmt", {1, 0}},
+
+{"v", {1, 0}},
// vendor-defined ('X') extensions
-{"xcvalu", RISCVExtensionVersion{1, 0}},
-{"xcvbi", RISCVExtensionVersion{1, 0}},
-{"xcvbitmanip", RISCVExtensionVersion{1, 0}},
-{"xcvelw", RISCVExtensionVersion{1, 0}},
-
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 53993a1f1eaf0f6dc336d45a94b8638c4119ba2e Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 70f531e40b90e6..c5c8f86a72d9d7 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -93,6 +93,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", RISCVExtensionVersion{1, 0}},
{"xventanacondops", RISCVExtensionVersion{1, 0}},
+{"za128rs", RISCVExtensionVersion{1, 0}},
+{"za64rs", RISCVExtensionVersion{1, 0}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"zba", RISCVExtensionVersion{1, 0}},
@@ -121,9 +123,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", RISCVExtensionVersion{1, 0}},
{"zhinxmin", RISCVExtensionVersion{1, 0}},
+{"zic64b", RISCVExtensionVersion{1, 0}},
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
+{"ziccamoa", RISCVExtensionVersion{1, 0}},
+{"ziccif", RISCVExtensionVersion{1, 0}},
+{"zicclsm", RISCVExtensionVersion{1, 0}},
+{"ziccrse", RISCVExtensionVersion{1, 0}},
{"zicntr", RISCVExtensionVersion{2, 0}},
{"zicsr", RISCVExtensionVersion{2, 0}},
{"zifencei", RISCVExtensionVersion{2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index bb7a3291085d43..17ed2a3aa2c57c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..83
[lld] [clang] [llvm] [RISCV] Deduplicate version struct in RISCVISAInfo. NFC (PR #77645)
https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/77645 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From 8de2b22ba2723fccf16ca4d2a863f84fd1b66493 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 390d950486a795..bac7fa1b8f07da 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", {1, 0}},
{"xventanacondops", {1, 0}},
+{"za128rs", {1, 0}},
+{"za64rs", {1, 0}},
{"zawrs", {1, 0}},
{"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", {1, 0}},
{"zhinxmin", {1, 0}},
+{"zic64b", {1, 0}},
{"zicbom", {1, 0}},
{"zicbop", {1, 0}},
{"zicboz", {1, 0}},
+{"ziccamoa", {1, 0}},
+{"ziccif", {1, 0}},
+{"zicclsm", {1, 0}},
+{"ziccrse", {1, 0}},
{"zicntr", {2, 0}},
{"zicsr", {2, 0}},
{"zifencei", {2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 279509575bb52a..1d34fb2c4b5cf6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -86,6 +86,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -510,6 +526,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -554,6 +574,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 9a6e78c09ad8c3..8373ead932a695 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck
--check-prefixes=CHECK,RV64COMBINEINTOZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o -
| FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
; RUN: llc -mtri
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
lukel97 wrote: Rebased on top of 79889fedc57707e99740abc1f48e6c5601d5a3f3 https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Move getVScaleRange logic into libLLVMFrontendDriver. NFC (PR #77327)
lukel97 wrote: Closing for now as deduplication the clang/flang frontend logic most likely requires more thought and discussion https://github.com/llvm/llvm-project/pull/77327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
lukel97 wrote:
> > @4vtomat if the MCPU has a feature but the function explicitly disables it
> > then I think we want the `-`
>
> Why don't we just remove it from feature map?
We also need the negative extensions if the target attribute string is a
complete arch, e.g. `__attribute__((target="arch=rv64i")))`, because any
extensions from mcpu need to be turned off.
https://github.com/llvm/llvm-project/pull/83674
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[clang] [RISCV][FMV] Support target_clones (PR #85786)
lukel97 wrote: Can this land until #85790 lands? https://github.com/llvm/llvm-project/pull/85786 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [libcxxabi] [lldb] [libcxx] [clang] [libc] [lld] [flang] [compiler-rt] [llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,48 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp) &&
+ LT.second.getVectorElementType() != MVT::i1) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+ NumElems * LT.second.getScalarSizeInBits() ==
lukel97 wrote:
Should this be checking that the extracted subvector type is VLEN sized, not
the containing vector type?
https://github.com/llvm/llvm-project/pull/80164
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[lldb] [libcxxabi] [flang] [compiler-rt] [lld] [libc] [llvm] [libcxx] [clang] [clang-tools-extra] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
@@ -326,6 +326,48 @@ InstructionCost
RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
switch (Kind) {
default:
break;
+case TTI::SK_ExtractSubvector:
+ if (isa(SubTp) &&
+ LT.second.getVectorElementType() != MVT::i1) {
+unsigned TpRegs = getRegUsageForType(Tp);
+unsigned NumElems =
+divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+// Whole vector extract - just the vector itself + (possible) vsetvli.
+// TODO: consider adding the cost for vsetvli.
+if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+ NumElems * LT.second.getScalarSizeInBits() ==
+ ST->getRealMinVLen() &&
+ Index % NumElems == 0))
lukel97 wrote:
Should we add some test cases that exercise the exact VLEN path? I presume
we'll need to add another RUN line with `-riscv-v-vector-bits-min=...
-riscv-v-vector-bits-max=...`
https://github.com/llvm/llvm-project/pull/80164
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[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -764,6 +771,58 @@ def FeatureStdExtSmepmp : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true", "'Smepmp' (Enhanced Physical Memory Protection)", []>; +def FeatureStdExtSsccptr +: SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true", + "'Ssccptr' (Main memory supports page table reads)", []>; + +def FeatureStdExtShcounterenvw +: SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true", + "'Shcounterenw' (Support writeable enables for any supproted counter)", []>; +def FeatureStdExtSscounterenvw +: SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true", + "'Sscounterenw' (Support writeable enables for any supproted counter)", []>; + +def FeatureStdExtSsstateen +: SubtargetFeature<"ssstateen", "HasStdExtSsstateen", "true", + "'Ssstateen' (Supervisor-mode view of the state-enable extension)", []>; + +def FeatureStdExtSstc +: SubtargetFeature<"sstc", "HasStdExtSstc", "true", + "'Sstc' (Supervisor-mode timer interrupts)", []>; + +def FeatureStdExtShtvala +: SubtargetFeature<"shtvala", "HasStdExtShtvala", "true", + "'Shtvala' (htval provides all needed values)", []>; +def FeatureStdExtShvstvala +: SubtargetFeature<"shvstvala", "HasStdExtShvstvala", "true", + "'Shvstvala' (vstval provides all needed values)", []>; +def FeatureStdExtSstvala +: SubtargetFeature<"sstvala", "HasStdExtSstvala", "true", + "'Sstvala' (stval provides all needed values)", []>; + +def FeatureStdExtShvstvecd +: SubtargetFeature<"shvstvecd", "HasStdExtShvstvecd", "true", + "'Shvstvecd' (vstvec supports Direct mode)", []>; +def FeatureStdExtSstvecd +: SubtargetFeature<"sstvecd", "HasStdExtSstvecd", "true", + "'Sstvecd' (stvec supports Direct mode)", []>; + +def FeatureStdExtSsu64xl +: SubtargetFeature<"ssu64xl", "HasStdExtSsu64xl", "true", + "'Ssu64xl' (UXLEN=64 supported)", []>; + +def FeaturesStdExtSvade +: SubtargetFeature<"svade", "HasStdExtSvade", "true", + "'Svade' (Raise exceptions on improper A/D bits)", []>; + +def FeaturesStdExtSvadu +: SubtargetFeature<"svadu", "HasStdExtSvadu", "true", + "'Svadu' (Hardware A/D updates)", []>; + +def FeaturesStdExtSvbare +: SubtargetFeature<"svbare", "HasStdExtSvbare", "true", + "'Svbare' $(satp mode Bare supported)", []>; lukel97 wrote: Should this match the description in https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc#glossary-of-isa-extensions "Bare mode virtual-memory translation supported" https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -91,9 +91,24 @@ on support follow. ``E``Supported (`See note <#riscv-rve-note>`__) ``H``Assembly Support ``M``Supported + ``Shcounterenw`` Assembly Support + ``Shgatpa`` Assembly Support + ``Shtvala`` Assembly Support + ``Shvsatpa``Assembly Support lukel97 wrote: Nit, missing a space here https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)
@@ -91,9 +91,24 @@ on support follow. ``E``Supported (`See note <#riscv-rve-note>`__) ``H``Assembly Support ``M``Supported + ``Shcounterenw`` Assembly Support + ``Shgatpa`` Assembly Support + ``Shtvala`` Assembly Support + ``Shvsatpa``Assembly Support + ``Shvstvala``Assembly Support + ``Shvstvecd``Assembly Support ``Smaia``Supported ``Smepmp`` Supported ``Ssaia``Supported + ``Ssccptr`` Assembly Support + ``Sscounterenw`` Assembly Support + ``Sstc`` Assembly Support + ``Sstvala`` Assembly Support + ``Sstvecd`` Assembly Support + ``ssu64xl`` Assembly Support + ``Svade``Assembly Support + ``Svadu``Assembly Support + ``Svbare`` Assembly Support lukel97 wrote: Should these link to the #riscv-profiles-extensions-note like with the Z extensions from the profiles spec? https://github.com/llvm/llvm-project/pull/79399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/2] [RISCV] Overwrite cpu target features for full arch
string in target attribute
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.
In initFeatureMap, there are now two code paths:
1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.
Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.
2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
---
clang/lib/Basic/Targets/RISCV.cpp | 78 +++
.../CodeGen/RISCV/riscv-func-attr-target.c| 8 +-
2 files changed, 30 insertions(+), 56 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..b56c1d465ad77a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,39 +235,6 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
-static std::vector
-collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- std::vector NonISAExtFeatureVec;
-
- auto IsNonISAExtFeature = [](const std::string &Feature) {
-assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
-StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
-return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
- };
- llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-IsNonISAExtFeature);
-
- return NonISAExtFeatureVec;
-}
-
-static std::vector
-resolveTargetAttrOverride(const std::vector &FeaturesVec,
- int XLen) {
- auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
- if (I == FeaturesVec.end())
-return FeaturesVec;
-
- ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
- std::vector NonISAExtFeature =
- collectNonISAExtFeature(FeaturesNeedOverride, XLen);
-
- std::vector ResolvedFeature(++I, FeaturesVec.end());
- ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
- NonISAExtFeature.end());
-
- return ResolvedFeature;
-}
-
bool RISCVTargetInfo::initFeatureMap(
llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector &FeaturesVec) const {
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension target features.
+ const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures = std::vector(std::next(I),
FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string &Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ std::string Ext = Feature.substr(1); // drop the +/-
+ return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+ std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+ }
+
+ // Otherwise, parse the features and add any implied extensions.
+ std::vector AllFeatures = FeaturesVec;
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
if (!ParseResult) {
std::string Buffer;
llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -295,21 +279,9 @@ bool RISCVTargetInfo::initFeatureMap(
return false;
}
- // RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
-
- // parseFeatures normalizes the feature set by dropping any explicit
- // negatives, and non-extension features. We need
[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/3] [RISCV] Overwrite cpu target features for full arch
string in target attribute
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.
In initFeatureMap, there are now two code paths:
1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.
Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.
2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
---
clang/lib/Basic/Targets/RISCV.cpp | 78 +++
.../CodeGen/RISCV/riscv-func-attr-target.c| 8 +-
2 files changed, 30 insertions(+), 56 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..b56c1d465ad77a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,39 +235,6 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
-static std::vector
-collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- std::vector NonISAExtFeatureVec;
-
- auto IsNonISAExtFeature = [](const std::string &Feature) {
-assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
-StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
-return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
- };
- llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-IsNonISAExtFeature);
-
- return NonISAExtFeatureVec;
-}
-
-static std::vector
-resolveTargetAttrOverride(const std::vector &FeaturesVec,
- int XLen) {
- auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
- if (I == FeaturesVec.end())
-return FeaturesVec;
-
- ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
- std::vector NonISAExtFeature =
- collectNonISAExtFeature(FeaturesNeedOverride, XLen);
-
- std::vector ResolvedFeature(++I, FeaturesVec.end());
- ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
- NonISAExtFeature.end());
-
- return ResolvedFeature;
-}
-
bool RISCVTargetInfo::initFeatureMap(
llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector &FeaturesVec) const {
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension target features.
+ const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures = std::vector(std::next(I),
FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string &Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ std::string Ext = Feature.substr(1); // drop the +/-
+ return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+ std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+ }
+
+ // Otherwise, parse the features and add any implied extensions.
+ std::vector AllFeatures = FeaturesVec;
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
if (!ParseResult) {
std::string Buffer;
llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -295,21 +279,9 @@ bool RISCVTargetInfo::initFeatureMap(
return false;
}
- // RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
-
- // parseFeatures normalizes the feature set by dropping any explicit
- // negatives, and non-extension features. We need
[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension target features.
+ const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures(std::next(I), FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](StringRef Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ StringRef Ext = Feature.substr(1); // drop the +/-
+ return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+ std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+ }
+
+ // Otherwise, parse the features and add any implied extensions.
+ std::vector AllFeatures = FeaturesVec;
lukel97 wrote:
FeaturesVec is a const reference argument so we can't mutate it unfortunately.
Is there another way to avoid the copy here?
https://github.com/llvm/llvm-project/pull/77426
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[clang] [RISCV] Overwrite cpu target features for full arch string in target attribute (PR #77426)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77426
>From 0fadce20076015fbb28d449a2b3086f2e4261604 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 15:32:15 +0700
Subject: [PATCH 1/4] [RISCV] Overwrite cpu target features for full arch
string in target attribute
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue described
in https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch string is specified, a "full" list of extensions is now passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes any
negative features that disable ISA extensions.
In initFeatureMap, there are now two code paths:
1. If the arch string was overriden, use the "full" list of override features,
only adding back any non-isa features that were specified.
Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have the
features for rv64i, not a mix of both.
2. Otherwise, parse and *append* the list of implied features. By appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
---
clang/lib/Basic/Targets/RISCV.cpp | 78 +++
.../CodeGen/RISCV/riscv-func-attr-target.c| 8 +-
2 files changed, 30 insertions(+), 56 deletions(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index daaa8639ae8358..b56c1d465ad77a 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -235,39 +235,6 @@ ArrayRef
RISCVTargetInfo::getTargetBuiltins() const {
clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
}
-static std::vector
-collectNonISAExtFeature(ArrayRef FeaturesNeedOverride, int XLen) {
- std::vector NonISAExtFeatureVec;
-
- auto IsNonISAExtFeature = [](const std::string &Feature) {
-assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
-StringRef Ext = StringRef(Feature).drop_front(); // drop the +/-
-return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
- };
- llvm::copy_if(FeaturesNeedOverride, std::back_inserter(NonISAExtFeatureVec),
-IsNonISAExtFeature);
-
- return NonISAExtFeatureVec;
-}
-
-static std::vector
-resolveTargetAttrOverride(const std::vector &FeaturesVec,
- int XLen) {
- auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
- if (I == FeaturesVec.end())
-return FeaturesVec;
-
- ArrayRef FeaturesNeedOverride(&*FeaturesVec.begin(), &*I);
- std::vector NonISAExtFeature =
- collectNonISAExtFeature(FeaturesNeedOverride, XLen);
-
- std::vector ResolvedFeature(++I, FeaturesVec.end());
- ResolvedFeature.insert(ResolvedFeature.end(), NonISAExtFeature.begin(),
- NonISAExtFeature.end());
-
- return ResolvedFeature;
-}
-
bool RISCVTargetInfo::initFeatureMap(
llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector &FeaturesVec) const {
@@ -281,10 +248,27 @@ bool RISCVTargetInfo::initFeatureMap(
Features["32bit"] = true;
}
- std::vector NewFeaturesVec =
- resolveTargetAttrOverride(FeaturesVec, XLen);
+ // If a target attribute specified a full arch string, override all the ISA
+ // extension target features.
+ const auto I = llvm::find(FeaturesVec, "__RISCV_TargetAttrNeedOverride");
+ if (I != FeaturesVec.end()) {
+std::vector OverrideFeatures = std::vector(std::next(I),
FeaturesVec.end());
+
+// Add back any non ISA extension features, e.g. +relax.
+auto IsNonISAExtFeature = [](const std::string &Feature) {
+ assert(Feature.size() > 1 && (Feature[0] == '+' || Feature[0] == '-'));
+ std::string Ext = Feature.substr(1); // drop the +/-
+ return !llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext);
+};
+llvm::copy_if(llvm::make_range(FeaturesVec.begin(), I),
+ std::back_inserter(OverrideFeatures), IsNonISAExtFeature);
- auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, NewFeaturesVec);
+return TargetInfo::initFeatureMap(Features, Diags, CPU, OverrideFeatures);
+ }
+
+ // Otherwise, parse the features and add any implied extensions.
+ std::vector AllFeatures = FeaturesVec;
+ auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
if (!ParseResult) {
std::string Buffer;
llvm::raw_string_ostream OutputErrMsg(Buffer);
@@ -295,21 +279,9 @@ bool RISCVTargetInfo::initFeatureMap(
return false;
}
- // RISCVISAInfo makes implications for ISA features
- std::vector ImpliedFeatures = (*ParseResult)->toFeatures();
-
- // parseFeatures normalizes the feature set by dropping any explicit
- // negatives, and non-extension features. We need
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From fb8eebe1c7f5b4dec812c64d9a2572a98d59bdb8 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1eca..8c9eb1bddb3cb5 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", {1, 0}},
{"xventanacondops", {1, 0}},
+{"za128rs", {1, 0}},
+{"za64rs", {1, 0}},
{"zawrs", {1, 0}},
{"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", {1, 0}},
{"zhinxmin", {1, 0}},
+{"zic64b", {1, 0}},
{"zicbom", {1, 0}},
{"zicbop", {1, 0}},
{"zicboz", {1, 0}},
+{"ziccamoa", {1, 0}},
+{"ziccif", {1, 0}},
+{"zicclsm", {1, 0}},
+{"ziccrse", {1, 0}},
{"zicntr", {2, 0}},
{"zicsr", {2, 0}},
{"zifencei", {2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982..1946f2253fa6c0 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -93,6 +93,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -517,6 +533,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -561,6 +581,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d1..3e55e0fb4e6861 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck
--check-prefixes=CHECK,RV64COMBINEINTOZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o -
| FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
; RUN: llc -mtri
[clang] 9d6e189 - [RISCV] Use regexp to check negative extensions in test. NFC
Author: Luke Lau
Date: 2024-01-18T21:47:06+07:00
New Revision: 9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64
URL:
https://github.com/llvm/llvm-project/commit/9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64
DIFF:
https://github.com/llvm/llvm-project/commit/9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64.diff
LOG: [RISCV] Use regexp to check negative extensions in test. NFC
Everytime an extension is added, this test will need to have the negative
extension appended to multiple CHECK lines where we're overriding the arch.
This is quite time consuming since it needs to be in the right order, so this
replaces the explicit list of negative extensions with a regexp instead.
Added:
Modified:
clang/test/CodeGen/RISCV/riscv-func-attr-target.c
Removed:
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index 54a0aad8a18b43..7d3362e84e7588 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -40,8 +40,9 @@ __attribute__((target("cpu=sifive-u54"))) void
testAttrCpuOnly() {}
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa"
}
// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
-// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-h,-relax,-smaia,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b"
}
-// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-relax,-smaia,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b"
}
+// Make sure we append negative features if we override the arch
+// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
+// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zicond,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-relax,-sma
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 updated
https://github.com/llvm/llvm-project/pull/77458
>From d22817bcd7ea7ab5763cb4da58552ce6930d4b73 Mon Sep 17 00:00:00 2001
From: Luke Lau
Date: Tue, 9 Jan 2024 19:42:10 +0700
Subject: [PATCH 1/7] [RISCV] Add support for new unprivileged extensions
defined in profiles spec
This adds minimal support for 7 new extensions that were defined as a part of
the RISC-V Profiles specification here:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
As stated in the specification, these extensions don't add any new features but
describe existing features. So this patch only adds parsing and subtarget
features.
---
llvm/lib/Support/RISCVISAInfo.cpp | 7 +++
llvm/lib/Target/RISCV/RISCVFeatures.td | 26 ++
llvm/test/CodeGen/RISCV/attributes.ll | 14 ++
3 files changed, 47 insertions(+)
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index d991878a5f1ecac..8c9eb1bddb3cb52 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -88,6 +88,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xtheadvdot", {1, 0}},
{"xventanacondops", {1, 0}},
+{"za128rs", {1, 0}},
+{"za64rs", {1, 0}},
{"zawrs", {1, 0}},
{"zba", {1, 0}},
@@ -116,9 +118,14 @@ static const RISCVSupportedExtension SupportedExtensions[]
= {
{"zhinx", {1, 0}},
{"zhinxmin", {1, 0}},
+{"zic64b", {1, 0}},
{"zicbom", {1, 0}},
{"zicbop", {1, 0}},
{"zicboz", {1, 0}},
+{"ziccamoa", {1, 0}},
+{"ziccif", {1, 0}},
+{"zicclsm", {1, 0}},
+{"ziccrse", {1, 0}},
{"zicntr", {2, 0}},
{"zicsr", {2, 0}},
{"zifencei", {2, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa334c69ddc982b..1946f2253fa6c07 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -93,6 +93,22 @@ def HasStdExtZifencei :
Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of
FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
+def FeatureStdExtZiccamoa
+: SubtargetFeature<"ziccamoa", "HasStdExtZiccamoa", "true",
+ "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+
+def FeatureStdExtZiccif
+: SubtargetFeature<"ziccif", "HasStdExtZiccif", "true",
+ "'Ziccif' (Main Memory Supports Instruction Fetch with
Atomicity Requirement)">;
+
+def FeatureStdExtZicclsm
+: SubtargetFeature<"zicclsm", "HasStdExtZicclsm", "true",
+ "'Zicclsm' (Main Memory Supports Misaligned
Loads/Stores)">;
+
+def FeatureStdExtZiccrse
+: SubtargetFeature<"ziccrse", "HasStdExtZiccrse", "true",
+ "'Ziccrse' (Main Memory Supports Forward Progress on
LR/SC Sequences)">;
+
def FeatureStdExtZicntr
: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
"'Zicntr' (Base Counters and Timers)",
@@ -517,6 +533,10 @@ def HasStdExtZfhOrZvfh
"'Zfh' (Half-Precision Floating-Point) or "
"'Zvfh' (Vector Half-Precision
Floating-Point)">;
+def FeatureStdExtZic64b
+: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
+ "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+
def FeatureStdExtZicbom
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
"'Zicbom' (Cache-Block Management Instructions)">;
@@ -561,6 +581,12 @@ def HasStdExtZtso :
Predicate<"Subtarget->hasStdExtZtso()">,
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
+def FeatureStdExtZa164rs : SubtargetFeature<"za64rs", "HasStdExtZa64rs",
"true",
+"'Za64rs' (Reservation Set Size of
at Most 64 Bytes)">;
+
+def FeatureStdExtZa128rs : SubtargetFeature<"za128rs", "HasStdExtZa128rs",
"true",
+"'Za128rs' (Reservation Set Size
of at Most 128 Bytes)">;
+
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
"'Zawrs' (Wait on Reservation Set)">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 60ef404ac345d15..3e55e0fb4e6861e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -130,6 +130,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck
--check-prefixes=CHECK,RV64COMBINEINTOZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o -
| FileCheck --check-prefixes=CHECK,RV64COMBINEINTOZKN %s
; RUN: llc
[llvm] [clang] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
lukel97 wrote: Rebased on top of 9d6e189ee8a93b9bc65a2b317961d8d1f63e3f64 which should fix the pre-merge check test failure https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add support for new unprivileged extensions defined in profiles spec (PR #77458)
https://github.com/lukel97 closed https://github.com/llvm/llvm-project/pull/77458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote: Hi, I'm no longer able to compile SPEC CPU 2017 after this due to an error in 510.parest_r: ``` /cpu2017/benchspec/CPU/510.parest_r/src/source/fe/fe_tools.cc:2020:15: error: partial ordering for explicit instantiation of 'back_interpolate' is ambiguous 2020 | void FETools::back_interpolate<3> | ^ /cpu2017/benchspec/CPU/510.parest_r/src/source/fe/fe_tools.cc:1167:10: note: explicit instantiation candidate function 'dealii::FETools::back_interpolate<3, dealii::Vector, dealii::Vector, 3>' template here [with dim = 3, InVector = dealii::Vector, OutVector = dealii::Vector, spacedim = 3] 1167 | FETools::back_interpolate(const DoFHandler &dof1, | ^ /cpu2017/benchspec/CPU/510.parest_r/src/source/fe/fe_tools.cc:1219:10: note: explicit instantiation candidate function 'dealii::FETools::back_interpolate<3, dealii::DoFHandler, dealii::Vector, dealii::Vector, 3>' template here [with dim = 3, DH = dealii::DoFHandler, InVector = dealii::Vector, OutVector = dealii::Vector, spacedim = 3] 1219 | FETools::back_interpolate(const DH &dof1, | ^ ``` I think it's based off this https://github.com/dealii/dealii/blob/master/source/fe/fe_tools.cc, but unfortunately what SPEC is using seems to be quite out of date. I can try plugging this into creduce and see if it gives a reproducer. I'm not a C++ expert by any means so maybe this error is correct. Is there a flag that could be used to workaround this? https://github.com/llvm/llvm-project/pull/100692 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote:
@mizvekov
I'm not sure if it's possible to share SPEC sources due to the license, but
creduce was able to get it down to this which passed with -fsyntax-only before
aa7497a.
```c++
template class a;
template class b;
class c {
template
void h(const a &, const e &, const b &, f &);
template class i, class e, class f, int g>
void h(const i &, e, const b &, f);
};
template class a;
template class b;
template
void c::h(const a &, const e &, const b &, f &) {}
template void c::h(const a<3> &, const float &, const b<3> &, float &);
```
https://github.com/llvm/llvm-project/pull/100692
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[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote:
Here's the version without the rename pass
```c++
template class DoFHandler;
template class FiniteElement;
class FETools {
template
void back_interpolate(const DoFHandler &, const InVector &,
const FiniteElement &, OutVector &);
template class DH, class InVector, class OutVector,
int spacedim>
void back_interpolate(const DH &, InVector,
const FiniteElement &, OutVector);
};
template class DoFHandler;
template class FiniteElement;
template
void FETools::back_interpolate(const DoFHandler &,
const InVector &,
const FiniteElement &,
OutVector &) {}
template void FETools::back_interpolate(const DoFHandler<3> &, const double &,
const FiniteElement<3> &, double &);
```
https://github.com/llvm/llvm-project/pull/100692
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[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote: I just checked and gcc-13 is able to build that SPEC benchmark fine, so I think you're right there's probably some macro somewhere. I'll go digging for around for it. https://github.com/llvm/llvm-project/pull/100692 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote: I did a bit of grepping but I couldn't find any obvious macro. But I realised that gcc actually does accept the reproducer, when compiled with `-std=gnu++98`: https://compiler-explorer.com/z/zsGY6xbh5 This flag is set when compiling SPEC, and seems to be where clang differs. https://github.com/llvm/llvm-project/pull/100692 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote: I tried out #94981 and -fno-relaxed-template-template-args and can confirm both fix it. I'm now running into a separate LoopVectorizer crash, but I made it out of the frontend :) Using -fno-relaxed-template-template-args should be fine, in llvm-test-suite we already do something similar for another benchmark by passing -fdelayed-template-parsing, so I'll go ahead and open up a pull request there to add the flag. Thanks for all your help so far in finding a way around this! https://github.com/llvm/llvm-project/pull/100692 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libcxx] [llvm] Reapply "[Clang] Implement resolution for CWG1835 (#92957)" (PR #98547)
lukel97 wrote: I'm also seeing a error when building the 510.parest_r benchmark from SPEC CPU 2017 https://github.com/llvm/llvm-project/pull/98547 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-tools-extra] Reapply "[Clang][Sema] Diagnose class member access expressions naming non-existent members of the current instantiation prior to instantiation in the absence of dependent
lukel97 wrote: Hi, this seems to uncover an unfortunate error in xalan-c https://github.com/apache/xalan-c/blob/c326619da4813acfc845c2830d904a4860f9afe1/src/xalanc/XMLSupport/XalanOtherEncodingWriter.hpp#L323 which is present in one of the SPEC CPU 2017 benchmarks (and prevents SPEC CPU 2017 from being built) The error in xalan-c looks to be real since I can't find any definition of `m_isPresentable`, so I don't think this is an issue with this patch per say. Thought I'd flag this anyway in case others are running into the same issue. https://github.com/llvm/llvm-project/pull/90152 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Gate unratified profiles behind -menable-experimental-extensions (PR #92167)
https://github.com/lukel97 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/92167 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] check deduction consistency when partial ordering function templates (PR #100692)
lukel97 wrote: > > I tried out #94981 and -fno-relaxed-template-template-args and can confirm > > both fix it. I'm now running into a separate LoopVectorizer crash, but I > > made it out of the frontend :) > > Using -fno-relaxed-template-template-args should be fine, in > > llvm-test-suite we already do something similar for another benchmark by > > passing -fdelayed-template-parsing, so I'll go ahead and open up a pull > > request there to add the flag. > > Thanks for all your help so far in finding a way around this! > > It should work without any flags now, can you confirm? I can confirm I'm able to build SPEC without the flag now. https://github.com/llvm/llvm-project/pull/100692 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [emacs][clang-format] Add elisp API for clang-format on git diffs (PR #112792)
@@ -205,14 +288,60 @@ uses the function `buffer-file-name'." (delete-file temp-file) (when (buffer-name temp-buffer) (kill-buffer temp-buffer) +;;;###autoload +(defun clang-format-git-diffs (&optional style assume-file-name) lukel97 wrote: I think the term diff would be more consistent with existing emacs functions e.g. vc-diff, diff-delete-trailing-whitespace etc. https://github.com/llvm/llvm-project/pull/112792 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [emacs][clang-format] Add elisp API for clang-format on git diffs (PR #112792)
@@ -146,18 +146,104 @@ is a zero-based file offset, assuming ‘utf-8-unix’ coding." (lambda (byte &optional _quality _coding-system) (byte-to-position (1+ byte) -;;;###autoload -(defun clang-format-region (start end &optional style assume-file-name) - "Use clang-format to format the code between START and END according to STYLE. -If called interactively uses the region or the current statement if there is no -no active region. If no STYLE is given uses `clang-format-style'. Use -ASSUME-FILE-NAME to locate a style config file, if no ASSUME-FILE-NAME is given -uses the function `buffer-file-name'." - (interactive - (if (use-region-p) - (list (region-beginning) (region-end)) - (list (point) (point +(defun clang-format--vc-diff-get-diff-lines (file-orig file-new) + "Return all line regions that contain diffs between FILE-ORIG and +FILE-NEW. If there is no diff ‘nil’ is returned. Otherwise the +return is a ‘list’ of lines in the format ‘--lines=:’ +which can be passed directly to ‘clang-format’." + ;; Use temporary buffer for output of diff. + (with-temp-buffer +;; We could use diff.el:diff-no-select here. The reason we don't +;; is diff-no-select requires extra copies on the buffers which +;; induces noticeable slowdowns, especially on larger files. +(let ((status (call-process + diff-command + nil + (current-buffer) + nil + ;; Binary diff has different behaviors that we + ;; aren't interested in. + "-a" + ;; Print new lines in file-new formatted as + ;; "--lines= " + "--changed-group-format=%(N=0?:--lines=%dF:%dM )" + ;; Don't print anything for unchanged lines + "--unchanged-group-format=" lukel97 wrote: Hey sorry for the delay, I'm not very well versed in elisp unfortunately. But this looks really useful and I would definitely use it. I tried this out locally though on macOS and it looks like BSD diff doesn't have `--unchanged-group-format`. Is this needed for the rest of it to work? This isn't a blocking comment btw, we can always tell people to just install diffutils. https://github.com/llvm/llvm-project/pull/112792 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Mark pointer masking extensions as non-experimental (PR #113618)
@@ -26,5 +26,5 @@ entry:
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
declare @llvm.masked.gather.nxv4i32.nxv4p0(, i32 immarg, , ) #1
-attributes #0 = {
"target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-experimental-smmpm,-experimental-smnpm,-experimental-ssctr,-experimental-ssnpm,-experimental-sspm,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b"
}
+attributes #0 = {
"target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-smmpm,-smnpm,-experimental-ssctr,-ssnpm,-sspm,-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b"
}
lukel97 wrote:
We don't, this was just copied over from the issue in
https://github.com/llvm/llvm-project/issues/107950, we can definitely tidy it up
https://github.com/llvm/llvm-project/pull/113618
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[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)
@@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, FeaturePostRAScheduler]>; +def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", + NoSchedModel, + [Feature64Bit, lukel97 wrote: You can include all the RVA23U64 features with a !listconcat, similar to what the other processors have done with RVA22U64 https://github.com/llvm/llvm-project/pull/115100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [emacs][clang-format] Add elisp API for clang-format on git diffs (PR #112792)
lukel97 wrote: Just a heads up I've been using this locally for a bit now and it's been great, thanks for working on this. Haven't run into any issues so far. https://github.com/llvm/llvm-project/pull/112792 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [emacs][clang-format] Add elisp API for clang-format on git diffs (PR #112792)
https://github.com/lukel97 approved this pull request. Apologies for the delay on this again. However I tried it out locally and it now seems to work on macOS, thanks for fixing that! I really can't speak much for the elisp, but we don't have many reviewers for the emacs stuff and this feature would be really handy to have. So LGTM, if it needs more review I think it can be done post-commit :) https://github.com/llvm/llvm-project/pull/112792 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][CodeGen] Fix metadata when vectorization is disabled by pragma (PR #135163)
@@ -194,7 +194,7 @@ void for_test_scalable(int *List, int Length) {
}
}
-// Verify for loop is performing scalable vectorization
+// Verify for loop is NOT performing vectorization because the width is 1
lukel97 wrote:
> If taking the intent of the original implementation, then it appears to not
> vectorize the loop.
Yeah I think that makes sense, i.e. we should disable vectorization if
`(Attrs.VectorizeEnable == LoopAttributes::Disable || (Attrs.VectorizeWidth ==
1 && Attrs.VectorizeScalable != LoopAttributes:: Enable))`.
We should probably also update this bit in the docs to be explicit about it:
> Specifying a **non-scalable** width/count of 1 disables the optimization, and
> is equivalent to vectorize(disable) or interleave(disable).
https://github.com/llvm/llvm-project/pull/135163
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[clang] [clang][CodeGen] Fix metadata when vectorization is disabled by pragma (PR #135163)
https://github.com/lukel97 approved this pull request. Thanks, LGTM. Though this is a part of the code that I'm not familiar with so probably best to wait for another LGTM https://github.com/llvm/llvm-project/pull/135163 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
