[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-07-15 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:10
 /// This file describes the RISC-V instructions from the standard 'V' Vector
 /// extension, version 0.10.
 /// This version is still experimental as the 'V' extension hasn't been

khchen wrote:
> Do we need to update 0.10 to 1.0-rc?
> If the answer is yes, I think maybe we also need to update the clang part 
> (ex. arch parsing, predefine macro) in follow-up patches.
> 
> 
Maybe update it after finishing all changes in 1.0-rc?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105690/new/

https://reviews.llvm.org/D105690

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-07-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D106518#2895445 , @craig.topper 
wrote:

> Why do they need to be disabled? Doesn’t the spec define them to truncate?

In the 1.0-rc1, 18.2: The V extension supports all vector load and store 
instructions (Section Vector Loads and Stores), except the V extension does not 
support EEW=64 for index values when XLEN=32.

I think this means that all index instruction with eew=64 is only supported in 
RV64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-07-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:693
+let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
+RequiredExtensions = ["Xlen64"] in {
+def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>;

jrtc27 wrote:
> Xlen64 is not an extension. Nor is RV64I, even, it is a base ISA, but that 
> would at least be somewhat defensible. In fact, Xlen64 would be parsed as a 
> valid non-standard extension called "Xlen" with major version 64 and minor 
> version 0, just like any other Xfoo.
So change Xlen64 to RV64 or create a new field of RVVBuiltin to describle it? 
Which one do you think is better?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-07-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105690/new/

https://reviews.llvm.org/D105690

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-07-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:555
 
+defvar Xlen32EEWList = [["8", "(Log2EEW:3)"],
+["16", "(Log2EEW:4)"],

frasercrmck wrote:
> jrtc27 wrote:
> > Ignoring whether the change is actually correct, this should be capitalised 
> > as XLen32EEWList, but really this should actually be RV32 not XLen32 as 
> > that's not a term we use.
> While we're here I'm wondering whether a top-level 
> `Xlen32EEWList`/`RV32EEWList` is conveying the wrong thing. It's only the 
> loads and stores that have a different EEW list on RV32, isn't it?
Yes, only for index load/store, we should add the macro to the generated header 
to make `EEW=64` just available on RV64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-07-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: llvm/test/MC/RISCV/rvv/aliases.s:86
+# NO-ALIAS: vfwredusum.vs v8, v4, v20, v0.t  # encoding: [0x57,0x14,0x4a,0xc4]
+vfwredusum.vs v8, v4, v20, v0.t

kito-cheng wrote:
> I guess you want to verify `vfredsum.vs`  and `vfwredsum.vs` here?
Yes, but because the `Emit` of the InstAlias is set to 0, the printing priority 
of alias is lower than instruction, It just print the mnemonic of the 
instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105690/new/

https://reviews.llvm.org/D105690

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-07-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: llvm/test/MC/RISCV/rvv/aliases.s:86
+# NO-ALIAS: vfwredusum.vs v8, v4, v20, v0.t  # encoding: [0x57,0x14,0x4a,0xc4]
+vfwredusum.vs v8, v4, v20, v0.t

craig.topper wrote:
> jacquesguan wrote:
> > kito-cheng wrote:
> > > I guess you want to verify `vfredsum.vs`  and `vfwredsum.vs` here?
> > Yes, but because the `Emit` of the InstAlias is set to 0, the printing 
> > priority of alias is lower than instruction, It just print the mnemonic of 
> > the instruction.
> Don't you want to use the alias `vfredsum.vs` as input and verify you get the 
> non-alias `vfredusum.vs` back?
Yes, you are right, I do not notice using wrong input, thank you.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105690/new/

https://reviews.llvm.org/D105690

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-07-23 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:680
   foreach type = TypeList in {
-foreach eew_list = EEWList in {
+foreach eew_list = Xlen32EEWList in {
   defvar eew = eew_list[0];

HsiangKai wrote:
> There is no need to define `Xlen32EEWList`. You could use `EEWList[0-2]` for 
> the purpose.
Done, thank you.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

2022-02-07 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: eopXD, kito-cheng.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya.
jacquesguan requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

This revision recover the implication between Zve* extensions and the V 
extension.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119210

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,43 +34,43 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl32b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl64b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl128b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl256b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl512b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl1024b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl2048b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl4096b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl8192b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl16384b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl32768b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0

[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

2022-02-13 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D119210#3318348 , @eopXD wrote:

> Kindly reverse ping.
> May you land this change?

OK, right now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119210/new/

https://reviews.llvm.org/D119210

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

2022-02-13 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbfb4c0c37078: [RISCV] Recover the implication between Zve* 
extensions and the V extension. (authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119210/new/

https://reviews.llvm.org/D119210

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,43 +34,43 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl32b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl64b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl128b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl256b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl512b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl1024b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl2048b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl4096b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl8192b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl16384b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl32768b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl65536b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl204

[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

2021-08-01 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105690/new/

https://reviews.llvm.org/D105690

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-08-01 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-08-01 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:179
const std::vector &IntrinsicTypes,
-   StringRef RequiredExtension, unsigned NF);
+   const std::vector RequiredExtensions, unsigned NF);
   ~RVVIntrinsic() = default;

craig.topper wrote:
> RequiredExtensions should be a reference
Done, thanks.



Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:349
+  if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
+errs() << "The V extension does not support EEW=64 for index values "
+  "when XLEN=32\n";

craig.topper wrote:
> This would just print a message to stderr but wouldn't fail the program. 
> Probably should use report_fatal_error. Or we could let the caller go to 
> SelectCode which would also trigger a "Cannot select" fatal error.
Done, thanks.



Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:430
+  if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
+errs() << "The V extension does not support EEW=64 for index values "
+  "when XLEN=32\n";

craig.topper wrote:
> Same as above
Done, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D105626: [RISCV][Clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins

2021-07-08 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added a reviewer: craig.topper.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
jacquesguan requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Add extension macro __riscv_zvlsseg to enable Zvlsseg builtins only with target 
feature Zvlsseg.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105626

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -141,6 +141,7 @@
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvamo = 1 << 4,
+  Zvlsseg = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -784,6 +785,8 @@
   }
   if (RequiredExtension == "Zvamo")
 RISCVExtensions |= RISCVExtension::Zvamo;
+  if (RequiredExtension == "Zvlsseg")
+RISCVExtensions |= RISCVExtension::Zvlsseg;
 
   // Init OutputType and InputTypes
   OutputType = OutInTypes[0];
@@ -1237,6 +1240,8 @@
 OS << LS << "defined(__riscv_zfh)";
   if (Extents & RISCVExtension::Zvamo)
 OS << LS << "defined(__riscv_zvamo)";
+  if (Extents & RISCVExtension::Zvlsseg)
+OS << LS << "defined(__riscv_zvlsseg)";
   OS << "\n";
   return true;
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s 
\
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s 
\
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s 
\
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s 
\
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -di

[PATCH] D105626: [RISCV][Clang] Add macro __riscv_zvlsseg for RVV Zvlsseg builtins

2021-07-08 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 357408.
jacquesguan added a comment.

Add target feature zvlsseg for rvv-intrinsics/vlsegff.c


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105626/new/

https://reviews.llvm.org/D105626

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -141,6 +141,7 @@
   D = 1 << 2,
   Zfh = 1 << 3,
   Zvamo = 1 << 4,
+  Zvlsseg = 1 << 5,
 };
 
 // TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -784,6 +785,8 @@
   }
   if (RequiredExtension == "Zvamo")
 RISCVExtensions |= RISCVExtension::Zvamo;
+  if (RequiredExtension == "Zvlsseg")
+RISCVExtensions |= RISCVExtension::Zvlsseg;
 
   // Init OutputType and InputTypes
   OutputType = OutInTypes[0];
@@ -1237,6 +1240,8 @@
 OS << LS << "defined(__riscv_zfh)";
   if (Extents & RISCVExtension::Zvamo)
 OS << LS << "defined(__riscv_zvamo)";
+  if (Extents & RISCVExtension::Zvlsseg)
+OS << LS << "defined(__riscv_zvlsseg)";
   OS << "\n";
   return true;
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include 
 
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
@@ -2,12 +2,14 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
-// RUN:   -disable-O0-optnone -fallow-half-arguments-and-returns -emit-llvm %s \
-// RUN:   -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
+// RUN:   -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN:   -fallow-half-arguments-and-returns -emit-llvm %s -o - \
+// RUN:   | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.
Herald added a subscriber: wangpc.

ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 541904.
jacquesguan added a comment.

Address comment and rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -373,7 +373,7 @@
   RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
   EXPECT_EQ(Exts.size(), 2UL);
   EXPECT_EQ(Exts.count("zihintntl"), 1U);
-  auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izihintntl0p2", true);
+  auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izihintntl1p0", true);
   ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
   RISCVISAInfo::OrderedExtensionMap Exts2 = (*MaybeISAInfo2)->getExtensions();
   EXPECT_EQ(Exts2.size(), 2UL);
@@ -481,13 +481,13 @@
   RISCVISAInfo::parseArchString("rv64im_zihintntl", true, false);
   ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded());
   EXPECT_THAT((*MaybeISAInfo1)->toFeatureVector(),
-  ElementsAre("+m", "+experimental-zihintntl"));
+  ElementsAre("+m", "+zihintntl"));
 
   auto MaybeISAInfo2 = RISCVISAInfo::parseArchString(
   "rv32e_zihintntl_xventanacondops", true, false);
   ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
   EXPECT_THAT((*MaybeISAInfo2)->toFeatureVector(),
-  ElementsAre("+e", "+experimental-zihintntl", "+xventanacondops"));
+  ElementsAre("+e", "+zihintntl", "+xventanacondops"));
 }
 
 TEST(ToFeatureVector, UnsupportedExtensionsAreDropped) {
Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked 2 inline comments as done.
jacquesguan added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:151
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
 // CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
 

BeMg wrote:
> The CHECK-ZIHINTNTL-EXT also need update.
Done, thanks.



Comment at: llvm/docs/RISCVUsage.rst:214
+``zihintntl``
   LLVM implements the `0.2 draft specification 
`__.
 

BeMg wrote:
> zihintntl could add into `table:: Ratified Extensions by Status`, and be 
> removed this from the Experimental Extensions section.
Done, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 542290.
jacquesguan marked 2 inline comments as done.
jacquesguan added a comment.

rebase main and address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D151547#4514424 , @asb wrote:

> I remain concerned about exposing the intrinsics if they're not yet agreed as 
> finalised. I see there is now a PR to add them to riscv-c-api doc 
> https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47
>
> I'd be OK with merging this now if the intrinsics were temporarily removed, 
> or logic were added to gate them in some way (though we don't have precedent 
> on the best way to do this I don't think). Otherwise, I'd rather wait until 
> the intrinsics are agreed.

I saw that https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is 
basically agreed and close to merge, I think we could wait it to avoid repeat 
patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-07-25 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is already merged, any 
more advice about this patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157584: [clang][Sema] Skip access check on arrays of zero-length element

2023-08-10 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan accepted this revision.
jacquesguan added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157584/new/

https://reviews.llvm.org/D157584

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh or Zfhmin is available

2023-08-11 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck, luke.
Herald added subscribers: s.egerton, simoncook.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added subscribers: cfe-commits, wangpc.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157693

Files:
  clang/docs/LanguageExtensions.rst


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -812,6 +812,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh or Zfhmin is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -812,6 +812,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh or Zfhmin is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh or Zfhmin is available

2023-08-11 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 549311.
jacquesguan added a comment.

remove zfmin


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157693/new/

https://reviews.llvm.org/D157693

Files:
  clang/docs/LanguageExtensions.rst


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -812,6 +812,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -812,6 +812,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh is available

2023-08-13 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 549779.
jacquesguan added a comment.

Add Zhinx.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157693/new/

https://reviews.llvm.org/D157693

Files:
  clang/docs/LanguageExtensions.rst


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -814,6 +814,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh or Zhinx is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -814,6 +814,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh or Zhinx is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh or Zhinx is available

2023-08-13 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added inline comments.



Comment at: clang/docs/LanguageExtensions.rst:815
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh is available)
 

craig.topper wrote:
> Zhinx also
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157693/new/

https://reviews.llvm.org/D157693

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D157693: [clang][doc] Mark _Float16 is support natively when Zfh or Zhinx is available

2023-08-13 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
jacquesguan marked an inline comment as done.
Closed by commit rG9d0cf88e7086: [clang][doc] Mark _Float16 is support natively 
when Zfh or Zhinx is available (authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157693/new/

https://reviews.llvm.org/D157693

Files:
  clang/docs/LanguageExtensions.rst


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -814,6 +814,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh or Zhinx is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM


Index: clang/docs/LanguageExtensions.rst
===
--- clang/docs/LanguageExtensions.rst
+++ clang/docs/LanguageExtensions.rst
@@ -814,6 +814,7 @@
   * AMDGPU (natively)
   * SPIR (natively)
   * X86 (if SSE2 is available; natively if AVX512-FP16 is also available)
+  * RISC-V (natively if Zfh or Zhinx is available)
 
 * ``__bf16`` is supported on the following targets (currently never natively):
   * 32-bit ARM
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158045: [clang][SVE] Rename isVLSTBuiltinType, NFC

2023-08-15 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: DavidTruby, efriedma, peterwaller-arm, 
paulwalker-arm, bsmith, c-rhodes, sdesmalen, rsandifo-arm, ctetreau, 
cameron.mcinally, aaron.ballman.
Herald added a subscriber: psnobl.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Since we also have VLST for rvv now, it is not clear to keep using 
`isVLSTBuiltinType`, so I added prefix SVE to it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158045

Files:
  clang/include/clang/AST/Type.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/Type.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaType.cpp

Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -8363,7 +8363,7 @@
   }
 
   // Attribute can only be attached to a single SVE vector or predicate type.
-  if (!CurType->isVLSTBuiltinType()) {
+  if (!CurType->isSVEVLSTBuiltinType()) {
 S.Diag(Attr.getLoc(), diag::err_attribute_invalid_sve_type)
 << Attr << CurType;
 Attr.setInvalid();
Index: clang/lib/Sema/SemaExprCXX.cpp
===
--- clang/lib/Sema/SemaExprCXX.cpp
+++ clang/lib/Sema/SemaExprCXX.cpp
@@ -6305,7 +6305,7 @@
 
 static bool isValidSizelessVectorForConditionalCondition(ASTContext &Ctx,
  QualType CondTy) {
-  if (!CondTy->isVLSTBuiltinType())
+  if (!CondTy->isSVEVLSTBuiltinType())
 return false;
   const QualType EltTy =
   cast(CondTy.getCanonicalType())->getSveEltType(Ctx);
@@ -6417,10 +6417,10 @@
 
   QualType LHSType = LHS.get()->getType();
   const auto *LHSBT =
-  LHSType->isVLSTBuiltinType() ? LHSType->getAs() : nullptr;
+  LHSType->isSVEVLSTBuiltinType() ? LHSType->getAs() : nullptr;
   QualType RHSType = RHS.get()->getType();
   const auto *RHSBT =
-  RHSType->isVLSTBuiltinType() ? RHSType->getAs() : nullptr;
+  RHSType->isSVEVLSTBuiltinType() ? RHSType->getAs() : nullptr;
 
   QualType ResultType;
 
@@ -6462,7 +6462,7 @@
 RHS = ImpCastExprToType(RHS.get(), ResultType, CK_VectorSplat);
   }
 
-  assert(!ResultType.isNull() && ResultType->isVLSTBuiltinType() &&
+  assert(!ResultType.isNull() && ResultType->isSVEVLSTBuiltinType() &&
  "Result should have been a vector type");
   auto *ResultBuiltinTy = ResultType->castAs();
   QualType ResultElementTy = ResultBuiltinTy->getSveEltType(Context);
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -14827,7 +14827,7 @@
 
   // Strip vector types.
   if (isa(Source)) {
-if (Target->isVLSTBuiltinType() &&
+if (Target->isSVEVLSTBuiltinType() &&
 (S.Context.areCompatibleSveTypes(QualType(Target, 0),
  QualType(Source, 0)) ||
  S.Context.areLaxCompatibleSveTypes(QualType(Target, 0),
@@ -14878,7 +14878,7 @@
   const BuiltinType *TargetBT = dyn_cast(Target);
 
   // Strip SVE vector types
-  if (SourceBT && SourceBT->isVLSTBuiltinType()) {
+  if (SourceBT && SourceBT->isSVEVLSTBuiltinType()) {
 // Need the original target type for vector type checks
 const Type *OriginalTarget = S.Context.getCanonicalType(T).getTypePtr();
 // Handle conversion from scalable to fixed when msve-vector-bits is
@@ -14897,7 +14897,7 @@
 Source = SourceBT->getSveEltType(S.Context).getTypePtr();
   }
 
-  if (TargetBT && TargetBT->isVLSTBuiltinType())
+  if (TargetBT && TargetBT->isSVEVLSTBuiltinType())
 Target = TargetBT->getSveEltType(S.Context).getTypePtr();
 
   // If the source is floating point...
Index: clang/lib/CodeGen/CGExprScalar.cpp
===
--- clang/lib/CodeGen/CGExprScalar.cpp
+++ clang/lib/CodeGen/CGExprScalar.cpp
@@ -1798,7 +1798,7 @@
   // careful, because the base of a vector subscript is occasionally an rvalue,
   // so we can't get it as an lvalue.
   if (!E->getBase()->getType()->isVectorType() &&
-  !E->getBase()->getType()->isVLSTBuiltinType())
+  !E->getBase()->getType()->isSVEVLSTBuiltinType())
 return EmitLoadOfLValue(E);
 
   // Handle the vector case.  The base must be a vector, the index must be an
@@ -4858,7 +4858,7 @@
   }
 
   if (condExpr->getType()->isVectorType() ||
-  condExpr->getType()->isVLSTBuiltinType()) {
+  condExpr->getType()->isSVEVLSTBuiltinType()) {
 CGF.incrementProfileCounter(E);
 
 llvm::Value *CondV = CGF.EmitScalarExpr(condExpr);
Index: clang/lib/AST/Type.cpp
===
--- clang/lib/AST/Type.cpp
+++ cla

[PATCH] D158045: [clang][SVE] Rename isVLSTBuiltinType, NFC

2023-08-15 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 550627.
jacquesguan added a comment.

fix compile


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158045/new/

https://reviews.llvm.org/D158045

Files:
  clang/include/clang/AST/Type.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/Type.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaType.cpp

Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -8363,7 +8363,7 @@
   }
 
   // Attribute can only be attached to a single SVE vector or predicate type.
-  if (!CurType->isVLSTBuiltinType()) {
+  if (!CurType->isSVEVLSTBuiltinType()) {
 S.Diag(Attr.getLoc(), diag::err_attribute_invalid_sve_type)
 << Attr << CurType;
 Attr.setInvalid();
Index: clang/lib/Sema/SemaExprCXX.cpp
===
--- clang/lib/Sema/SemaExprCXX.cpp
+++ clang/lib/Sema/SemaExprCXX.cpp
@@ -6305,7 +6305,7 @@
 
 static bool isValidSizelessVectorForConditionalCondition(ASTContext &Ctx,
  QualType CondTy) {
-  if (!CondTy->isVLSTBuiltinType())
+  if (!CondTy->isSVEVLSTBuiltinType())
 return false;
   const QualType EltTy =
   cast(CondTy.getCanonicalType())->getSveEltType(Ctx);
@@ -6417,10 +6417,10 @@
 
   QualType LHSType = LHS.get()->getType();
   const auto *LHSBT =
-  LHSType->isVLSTBuiltinType() ? LHSType->getAs() : nullptr;
+  LHSType->isSVEVLSTBuiltinType() ? LHSType->getAs() : nullptr;
   QualType RHSType = RHS.get()->getType();
   const auto *RHSBT =
-  RHSType->isVLSTBuiltinType() ? RHSType->getAs() : nullptr;
+  RHSType->isSVEVLSTBuiltinType() ? RHSType->getAs() : nullptr;
 
   QualType ResultType;
 
@@ -6462,7 +6462,7 @@
 RHS = ImpCastExprToType(RHS.get(), ResultType, CK_VectorSplat);
   }
 
-  assert(!ResultType.isNull() && ResultType->isVLSTBuiltinType() &&
+  assert(!ResultType.isNull() && ResultType->isSVEVLSTBuiltinType() &&
  "Result should have been a vector type");
   auto *ResultBuiltinTy = ResultType->castAs();
   QualType ResultElementTy = ResultBuiltinTy->getSveEltType(Context);
Index: clang/lib/Sema/SemaExpr.cpp
===
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -5945,7 +5945,7 @@
 if (Combined != MemberQuals)
   ResultType = Context.getQualifiedType(ResultType, Combined);
   } else if (LHSTy->isBuiltinType() &&
- LHSTy->getAs()->isVLSTBuiltinType()) {
+ LHSTy->getAs()->isSVEVLSTBuiltinType()) {
 const BuiltinType *BTy = LHSTy->getAs();
 if (BTy->isSVEBool())
   return ExprError(Diag(LLoc, diag::err_subscript_svbool_t)
@@ -10934,7 +10934,7 @@
 assert(!isa(VT) &&
"ExtVectorTypes should not be handled here!");
 VectorEltTy = VT->getElementType();
-  } else if (VectorTy->isVLSTBuiltinType()) {
+  } else if (VectorTy->isSVEVLSTBuiltinType()) {
 VectorEltTy =
 VectorTy->castAs()->getSveEltType(S.getASTContext());
   } else {
@@ -11297,25 +11297,25 @@
   if (Context.hasSameType(LHSType, RHSType))
 return LHSType;
 
-  if (LHSType->isVLSTBuiltinType() && !RHSType->isVLSTBuiltinType()) {
+  if (LHSType->isSVEVLSTBuiltinType() && !RHSType->isSVEVLSTBuiltinType()) {
 if (!tryGCCVectorConvertAndSplat(*this, &RHS, &LHS))
   return LHSType;
   }
-  if (RHSType->isVLSTBuiltinType() && !LHSType->isVLSTBuiltinType()) {
+  if (RHSType->isSVEVLSTBuiltinType() && !LHSType->isSVEVLSTBuiltinType()) {
 if (LHS.get()->isLValue() ||
 !tryGCCVectorConvertAndSplat(*this, &LHS, &RHS))
   return RHSType;
   }
 
-  if ((!LHSType->isVLSTBuiltinType() && !LHSType->isRealType()) ||
-  (!RHSType->isVLSTBuiltinType() && !RHSType->isRealType())) {
+  if ((!LHSType->isSVEVLSTBuiltinType() && !LHSType->isRealType()) ||
+  (!RHSType->isSVEVLSTBuiltinType() && !RHSType->isRealType())) {
 Diag(Loc, diag::err_typecheck_vector_not_convertable_non_scalar)
 << LHSType << RHSType << LHS.get()->getSourceRange()
 << RHS.get()->getSourceRange();
 return QualType();
   }
 
-  if (LHSType->isVLSTBuiltinType() && RHSType->isVLSTBuiltinType() &&
+  if (LHSType->isSVEVLSTBuiltinType() && RHSType->isSVEVLSTBuiltinType() &&
   Context.getBuiltinVectorTypeInfo(LHSBuiltinTy).EC !=
   Context.getBuiltinVectorTypeInfo(RHSBuiltinTy).EC) {
 Diag(Loc, diag::err_typecheck_vector_lengths_not_equal)
@@ -11324,11 +11324,11 @@
 return QualType();
   }
 
-  if (LHSType->isVLSTBuiltinType() || RHSType->isVLSTBuiltinType()) {
-QualType Scalar = LHSType->isVLSTBuiltinType() ? RHSType : LHSType;
-QualType Vector = LHSType->isVLSTBuiltinType() ? LH

[PATCH] D158045: [clang][SVE] Rename isVLSTBuiltinType, NFC

2023-08-16 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 550967.
jacquesguan added a comment.

rename to isSveVLSBuiltinType.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158045/new/

https://reviews.llvm.org/D158045

Files:
  clang/include/clang/AST/Type.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/Type.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaType.cpp

Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -8363,7 +8363,7 @@
   }
 
   // Attribute can only be attached to a single SVE vector or predicate type.
-  if (!CurType->isVLSTBuiltinType()) {
+  if (!CurType->isSveVLSBuiltinType()) {
 S.Diag(Attr.getLoc(), diag::err_attribute_invalid_sve_type)
 << Attr << CurType;
 Attr.setInvalid();
Index: clang/lib/Sema/SemaExprCXX.cpp
===
--- clang/lib/Sema/SemaExprCXX.cpp
+++ clang/lib/Sema/SemaExprCXX.cpp
@@ -6305,7 +6305,7 @@
 
 static bool isValidSizelessVectorForConditionalCondition(ASTContext &Ctx,
  QualType CondTy) {
-  if (!CondTy->isVLSTBuiltinType())
+  if (!CondTy->isSveVLSBuiltinType())
 return false;
   const QualType EltTy =
   cast(CondTy.getCanonicalType())->getSveEltType(Ctx);
@@ -6417,10 +6417,10 @@
 
   QualType LHSType = LHS.get()->getType();
   const auto *LHSBT =
-  LHSType->isVLSTBuiltinType() ? LHSType->getAs() : nullptr;
+  LHSType->isSveVLSBuiltinType() ? LHSType->getAs() : nullptr;
   QualType RHSType = RHS.get()->getType();
   const auto *RHSBT =
-  RHSType->isVLSTBuiltinType() ? RHSType->getAs() : nullptr;
+  RHSType->isSveVLSBuiltinType() ? RHSType->getAs() : nullptr;
 
   QualType ResultType;
 
@@ -6462,7 +6462,7 @@
 RHS = ImpCastExprToType(RHS.get(), ResultType, CK_VectorSplat);
   }
 
-  assert(!ResultType.isNull() && ResultType->isVLSTBuiltinType() &&
+  assert(!ResultType.isNull() && ResultType->isSveVLSBuiltinType() &&
  "Result should have been a vector type");
   auto *ResultBuiltinTy = ResultType->castAs();
   QualType ResultElementTy = ResultBuiltinTy->getSveEltType(Context);
Index: clang/lib/Sema/SemaExpr.cpp
===
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -5945,7 +5945,7 @@
 if (Combined != MemberQuals)
   ResultType = Context.getQualifiedType(ResultType, Combined);
   } else if (LHSTy->isBuiltinType() &&
- LHSTy->getAs()->isVLSTBuiltinType()) {
+ LHSTy->getAs()->isSveVLSBuiltinType()) {
 const BuiltinType *BTy = LHSTy->getAs();
 if (BTy->isSVEBool())
   return ExprError(Diag(LLoc, diag::err_subscript_svbool_t)
@@ -10934,7 +10934,7 @@
 assert(!isa(VT) &&
"ExtVectorTypes should not be handled here!");
 VectorEltTy = VT->getElementType();
-  } else if (VectorTy->isVLSTBuiltinType()) {
+  } else if (VectorTy->isSveVLSBuiltinType()) {
 VectorEltTy =
 VectorTy->castAs()->getSveEltType(S.getASTContext());
   } else {
@@ -11297,25 +11297,25 @@
   if (Context.hasSameType(LHSType, RHSType))
 return LHSType;
 
-  if (LHSType->isVLSTBuiltinType() && !RHSType->isVLSTBuiltinType()) {
+  if (LHSType->isSveVLSBuiltinType() && !RHSType->isSveVLSBuiltinType()) {
 if (!tryGCCVectorConvertAndSplat(*this, &RHS, &LHS))
   return LHSType;
   }
-  if (RHSType->isVLSTBuiltinType() && !LHSType->isVLSTBuiltinType()) {
+  if (RHSType->isSveVLSBuiltinType() && !LHSType->isSveVLSBuiltinType()) {
 if (LHS.get()->isLValue() ||
 !tryGCCVectorConvertAndSplat(*this, &LHS, &RHS))
   return RHSType;
   }
 
-  if ((!LHSType->isVLSTBuiltinType() && !LHSType->isRealType()) ||
-  (!RHSType->isVLSTBuiltinType() && !RHSType->isRealType())) {
+  if ((!LHSType->isSveVLSBuiltinType() && !LHSType->isRealType()) ||
+  (!RHSType->isSveVLSBuiltinType() && !RHSType->isRealType())) {
 Diag(Loc, diag::err_typecheck_vector_not_convertable_non_scalar)
 << LHSType << RHSType << LHS.get()->getSourceRange()
 << RHS.get()->getSourceRange();
 return QualType();
   }
 
-  if (LHSType->isVLSTBuiltinType() && RHSType->isVLSTBuiltinType() &&
+  if (LHSType->isSveVLSBuiltinType() && RHSType->isSveVLSBuiltinType() &&
   Context.getBuiltinVectorTypeInfo(LHSBuiltinTy).EC !=
   Context.getBuiltinVectorTypeInfo(RHSBuiltinTy).EC) {
 Diag(Loc, diag::err_typecheck_vector_lengths_not_equal)
@@ -11324,11 +11324,11 @@
 return QualType();
   }
 
-  if (LHSType->isVLSTBuiltinType() || RHSType->isVLSTBuiltinType()) {
-QualType Scalar = LHSType->isVLSTBuiltinType() ? RHSType : LHSType;
-QualType Vector = LHSType->isVLSTBuiltinType()

[PATCH] D158045: [clang][SVE] Rename isVLSTBuiltinType, NFC

2023-08-16 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D158045#4592331 , @paulwalker-arm 
wrote:

> I'd hope there are common code paths where `isVLSTBuiltinType` would still be 
> useful but I guess this step is required to make that happen anyway.
>
> If you permit a minor request can the new name please be 
> `isSveVLSBuiltinType` to match the case used by the related `getSveEltType` 
> function and the extra `T` in the old name has always bugged me.

Yes, I am working on a patch to implement clang vector language support for rvv 
just like we have on sve. Most part we could reuse `isVLSTBuiltinType` that 
contains VLST of both sve and rvv.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158045/new/

https://reviews.llvm.org/D158045

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158045: [clang][SVE] Rename isVLSTBuiltinType, NFC

2023-08-16 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG28741a23c9fc: [clang][SVE] Rename isVLSTBuiltinType, NFC 
(authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158045/new/

https://reviews.llvm.org/D158045

Files:
  clang/include/clang/AST/Type.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/Type.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaType.cpp

Index: clang/lib/Sema/SemaType.cpp
===
--- clang/lib/Sema/SemaType.cpp
+++ clang/lib/Sema/SemaType.cpp
@@ -8363,7 +8363,7 @@
   }
 
   // Attribute can only be attached to a single SVE vector or predicate type.
-  if (!CurType->isVLSTBuiltinType()) {
+  if (!CurType->isSveVLSBuiltinType()) {
 S.Diag(Attr.getLoc(), diag::err_attribute_invalid_sve_type)
 << Attr << CurType;
 Attr.setInvalid();
Index: clang/lib/Sema/SemaExprCXX.cpp
===
--- clang/lib/Sema/SemaExprCXX.cpp
+++ clang/lib/Sema/SemaExprCXX.cpp
@@ -6305,7 +6305,7 @@
 
 static bool isValidSizelessVectorForConditionalCondition(ASTContext &Ctx,
  QualType CondTy) {
-  if (!CondTy->isVLSTBuiltinType())
+  if (!CondTy->isSveVLSBuiltinType())
 return false;
   const QualType EltTy =
   cast(CondTy.getCanonicalType())->getSveEltType(Ctx);
@@ -6417,10 +6417,10 @@
 
   QualType LHSType = LHS.get()->getType();
   const auto *LHSBT =
-  LHSType->isVLSTBuiltinType() ? LHSType->getAs() : nullptr;
+  LHSType->isSveVLSBuiltinType() ? LHSType->getAs() : nullptr;
   QualType RHSType = RHS.get()->getType();
   const auto *RHSBT =
-  RHSType->isVLSTBuiltinType() ? RHSType->getAs() : nullptr;
+  RHSType->isSveVLSBuiltinType() ? RHSType->getAs() : nullptr;
 
   QualType ResultType;
 
@@ -6462,7 +6462,7 @@
 RHS = ImpCastExprToType(RHS.get(), ResultType, CK_VectorSplat);
   }
 
-  assert(!ResultType.isNull() && ResultType->isVLSTBuiltinType() &&
+  assert(!ResultType.isNull() && ResultType->isSveVLSBuiltinType() &&
  "Result should have been a vector type");
   auto *ResultBuiltinTy = ResultType->castAs();
   QualType ResultElementTy = ResultBuiltinTy->getSveEltType(Context);
Index: clang/lib/Sema/SemaExpr.cpp
===
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -5945,7 +5945,7 @@
 if (Combined != MemberQuals)
   ResultType = Context.getQualifiedType(ResultType, Combined);
   } else if (LHSTy->isBuiltinType() &&
- LHSTy->getAs()->isVLSTBuiltinType()) {
+ LHSTy->getAs()->isSveVLSBuiltinType()) {
 const BuiltinType *BTy = LHSTy->getAs();
 if (BTy->isSVEBool())
   return ExprError(Diag(LLoc, diag::err_subscript_svbool_t)
@@ -10934,7 +10934,7 @@
 assert(!isa(VT) &&
"ExtVectorTypes should not be handled here!");
 VectorEltTy = VT->getElementType();
-  } else if (VectorTy->isVLSTBuiltinType()) {
+  } else if (VectorTy->isSveVLSBuiltinType()) {
 VectorEltTy =
 VectorTy->castAs()->getSveEltType(S.getASTContext());
   } else {
@@ -11297,25 +11297,25 @@
   if (Context.hasSameType(LHSType, RHSType))
 return LHSType;
 
-  if (LHSType->isVLSTBuiltinType() && !RHSType->isVLSTBuiltinType()) {
+  if (LHSType->isSveVLSBuiltinType() && !RHSType->isSveVLSBuiltinType()) {
 if (!tryGCCVectorConvertAndSplat(*this, &RHS, &LHS))
   return LHSType;
   }
-  if (RHSType->isVLSTBuiltinType() && !LHSType->isVLSTBuiltinType()) {
+  if (RHSType->isSveVLSBuiltinType() && !LHSType->isSveVLSBuiltinType()) {
 if (LHS.get()->isLValue() ||
 !tryGCCVectorConvertAndSplat(*this, &LHS, &RHS))
   return RHSType;
   }
 
-  if ((!LHSType->isVLSTBuiltinType() && !LHSType->isRealType()) ||
-  (!RHSType->isVLSTBuiltinType() && !RHSType->isRealType())) {
+  if ((!LHSType->isSveVLSBuiltinType() && !LHSType->isRealType()) ||
+  (!RHSType->isSveVLSBuiltinType() && !RHSType->isRealType())) {
 Diag(Loc, diag::err_typecheck_vector_not_convertable_non_scalar)
 << LHSType << RHSType << LHS.get()->getSourceRange()
 << RHS.get()->getSourceRange();
 return QualType();
   }
 
-  if (LHSType->isVLSTBuiltinType() && RHSType->isVLSTBuiltinType() &&
+  if (LHSType->isSveVLSBuiltinType() && RHSType->isSveVLSBuiltinType() &&
   Context.getBuiltinVectorTypeInfo(LHSBuiltinTy).EC !=
   Context.getBuiltinVectorTypeInfo(RHSBuiltinTy).EC) {
 Diag(Loc, diag::err_typecheck_vector_lengths_not_equal)
@@ -11324,11 +11324,11 @@
 return QualType();
   }
 
-  if (LHSType->isVLSTBuiltinType() || RHSType->isVLSTBuiltinType()) {
-QualType Scalar = LHSType->isVLSTBuiltinType() ? RHSTy

[PATCH] D157130: [RISCV] Check type size for lax conversions between RVV builtin types and VectorType::RVVFixedLengthDataVector.

2023-08-20 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan accepted this revision.
jacquesguan added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157130/new/

https://reviews.llvm.org/D157130

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-20 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:14906
+// specified
+if (S.Context.areCompatibleRVVTypes(QualType(OriginalTarget, 0),
+QualType(Source, 0)) ||

craig.topper wrote:
> Why do we need this, but SVE doesn't?
Merged with the former sve function.



Comment at: clang/lib/Sema/SemaExpr.cpp:12294
 
+  if ((LHSBuiltinTy && LHSBuiltinTy->isSVEBool()) ||
+  (RHSBuiltinTy && RHSBuiltinTy->isSVEBool())) {

craig.topper wrote:
> This code looks identical to the code above it.
Removed.



Comment at: clang/lib/Sema/SemaExpr.cpp:16322
   break;
-else if (resultType->isSveVLSBuiltinType()) // SVE vectors allow + and -
+else if (resultType->isVLSBuiltinType()) // SVE vectors allow + and -
   break;

craig.topper wrote:
> Update "SVE" to mention "RVV" too?
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158259/new/

https://reviews.llvm.org/D158259

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:90
+//
+vfloat32m1_t add_f32(vfloat32m1_t a, vfloat32m1_t b) {
+  return a + b;

Jim wrote:
> Do we support operation for vfloat16 here?
Thanks to point it. I added fp16 vector cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158259/new/

https://reviews.llvm.org/D158259

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-08-23 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 552622.
jacquesguan added a comment.
Herald added subscribers: wangpc, sunshaoce.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -655,6 +655,7 @@
 for (auto RequiredFeature : RequiredFeatures) {
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,18 +4,18 @@
 // REQUIRES: riscv-registered-target
 #include 
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
-  vfloat16m1_t f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
+  vfloat16m1_t f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  (void)f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+  (void)f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  return f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+  return f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 }
 
-vfloat16m1x2_t bar() { /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
-  vfloat16m1x2_t f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+vfloat16m1x2_t bar() { /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
+  vfloat16m1x2_t f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  (void)f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+  (void)f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  return f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+  return f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison,  [[

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang

2023-08-23 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG654fa9a7e898: [RISCV] Add Zvfhmin extension for clang 
(authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -653,6 +653,7 @@
 for (auto RequiredFeature : RequiredFeatures) {
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,18 +4,18 @@
 // REQUIRES: riscv-registered-target
 #include 
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
-  vfloat16m1_t f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
+  vfloat16m1_t f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  (void)f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+  (void)f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  return f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+  return f16m1; /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 }
 
-vfloat16m1x2_t bar() { /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
-  vfloat16m1x2_t f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+vfloat16m1x2_t bar() { /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
+  vfloat16m1x2_t f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  (void)f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+  (void)f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 
-  return f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh' extension}} */
+  return f16m1x2; /* expected-error {{RISC-V type 'vfloat16m1x2_t' (aka '__rvv_float16m1x2_t') requires the 'zvfh or zvfhmin' extension}} */
 }
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHE

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-08-09 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 548848.
jacquesguan added a comment.

rebase and add release note.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 #

[PATCH] D151547: [RISCV] Remove experimental for zihintntl

2023-08-10 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 548903.
jacquesguan added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN: |

[PATCH] D157586: [clang][AVR] Restrict IntMaxType to 16-bit signed integer

2023-08-10 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan accepted this revision.
jacquesguan added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157586/new/

https://reviews.llvm.org/D157586

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151547: [RISCV] Remove experimental for zihintntl

2023-08-10 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf808788487ab: [RISCV] Remove experimental for zihintntl 
(authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/CodeGen/RISCV/prefetch.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s

Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl,+c < %s 2>&1 | FileCheck %s
 
 c.ntl.p1 1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 c.ntl.pall 2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zihintntl-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntl-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntl-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl -riscv-no-aliases -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \
+# RUN: llvm-mc -fil

[PATCH] D151869: [RISCV] Enable more builtin for zvfhmin without zvfh

2023-09-07 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4d2536c82fc4: [RISCV] Enable more builtin for zvfhmin 
without zvfh (authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151869/new/

https://reviews.llvm.org/D151869

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -9,7 +9,7 @@
 
 // CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
 // CHECK-ZVFHMIN-NEXT:  entry:
-// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 7, i64 [[VL:%.*]])
 // CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
 //
 vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
@@ -25,3 +25,192 @@
 vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
   return __riscv_vfwcvt_f(src, vl);
 }
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vle.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) {
+  return __riscv_vle16_v_f16m1(base, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vse16_v_f16m1(_Float16 *base, vfloat16m1_t value, size_t vl) {
+  return __riscv_vse16_v_f16m1(base, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vlse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vlse.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vlse16_v_f16m1(const _Float16 *base, ptrdiff_t bstride, size_t vl) {
+  return __riscv_vlse16_v_f16m1(base, bstride, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsse16_v_f16m1(_Float16 *base, ptrdiff_t bstride, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsse16_v_f16m1(base, bstride, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vluxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vluxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+  return __riscv_vluxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsuxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsuxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsuxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vloxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vloxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+  return __riscv_vloxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsoxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsoxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsoxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsoxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16ff_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0
+// CHECK-ZVFHMIN-NEXT:[[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1
+/

[PATCH] D151869: [RISCV] Support more builtin for zvfhmin.

2023-08-24 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 553051.
jacquesguan added a comment.
Herald added subscribers: wangpc, sunshaoce.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151869/new/

https://reviews.llvm.org/D151869

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -9,7 +9,7 @@
 
 // CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
 // CHECK-ZVFHMIN-NEXT:  entry:
-// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 7, i64 [[VL:%.*]])
 // CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
 //
 vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
@@ -25,3 +25,192 @@
 vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
   return __riscv_vfwcvt_f(src, vl);
 }
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vle.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) {
+  return __riscv_vle16_v_f16m1(base, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vse16_v_f16m1(_Float16 *base, vfloat16m1_t value, size_t vl) {
+  return __riscv_vse16_v_f16m1(base, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vlse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vlse.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vlse16_v_f16m1(const _Float16 *base, ptrdiff_t bstride, size_t vl) {
+  return __riscv_vlse16_v_f16m1(base, bstride, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsse16_v_f16m1(_Float16 *base, ptrdiff_t bstride, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsse16_v_f16m1(base, bstride, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vluxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vluxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+  return __riscv_vluxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsuxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsuxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsuxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vloxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vloxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+  return __riscv_vloxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsoxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsoxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsoxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsoxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16ff_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0
+// CHECK-ZVFHMIN-NEXT:[[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1
+// CHECK-ZVFHMIN-NEXT:store i64 [[TMP2]], ptr [[NEW_VL:%.*]], align 8
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP1

[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-09-06 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added a comment.

ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158259/new/

https://reviews.llvm.org/D158259

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151869: [RISCV] Enable more builtin for zvfhmin without zvfh

2023-09-07 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151869/new/

https://reviews.llvm.org/D151869

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D145659: [clang] Add AVR specific inline assembly escaped characters

2023-03-15 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan accepted this revision.
jacquesguan added a comment.
This revision is now accepted and ready to land.

LGTM.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145659/new/

https://reviews.llvm.org/D145659

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D145659: [clang] Add AVR specific inline assembly escaped characters

2023-03-12 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/lib/Basic/Targets/AVR.cpp:433
+AVRTargetInfo::handleAsmEscapedChar(char EscChar) const {
+  char C;
+  switch (EscChar) {

redundant variable?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145659/new/

https://reviews.llvm.org/D145659

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-25 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 525494.
jacquesguan added a comment.

Split into 2 revisions and address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td

Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -472,6 +472,11 @@
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
 
+def FeatureStdExtZvfhmin
+: SubtargetFeature<"experimental-zvfhmin", "HasStdExtZvfhmin", "true",
+   "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+   [FeatureStdExtZve32f]>;
+
 def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
 
 def HasStdExtZfhOrZvfh
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -152,6 +152,7 @@
 {"zvfbfmin", RISCVExtensionVersion{0, 6}},
 {"zvfbfwma", RISCVExtensionVersion{0, 6}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+{"zvfhmin", RISCVExtensionVersion{0, 1}},
 {"ztso", RISCVExtensionVersion{0, 1}},
 
 // vector crypto
@@ -943,6 +944,7 @@
 static const char *ImpliedExtsZvfbfmin[] = {"zve32f"};
 static const char *ImpliedExtsZvfbfwma[] = {"zve32f"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
+static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
 static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
 "zvkt"};
 static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
@@ -1004,6 +1006,7 @@
 {{"zvfbfmin"}, {ImpliedExtsZvfbfmin}},
 {{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
 {{"zvfh"}, {ImpliedExtsZvfh}},
+{{"zvfhmin"}, {ImpliedExtsZvfhmin}},
 {{"zvkn"}, {ImpliedExtsZvkn}},
 {{"zvkng"}, {ImpliedExtsZvkng}},
 {{"zvknhb"}, {ImpliedExtsZvknhb}},
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -645,6 +645,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,5 +4,5 @@
 // REQUIRES: riscv-registered-target
 #include 
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 } /* expected-warning {{non-void function does not return a value}}*/
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f1

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-25 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked 8 inline comments as done.
jacquesguan added a comment.

https://reviews.llvm.org/D151414 this is the backend part.




Comment at: clang/include/clang/Basic/riscv_vector.td:1856
   def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
-  def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+  let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;

michaelmaitland wrote:
> michaelmaitland wrote:
> > In general, I believe that `vfwcvt_f_f_v` and `vfncvt_f_f_w` do not require 
> > Zvfhmin or Zvfh. The only time that these intrinsics require Zvfhmin or 
> > Zvfh is when the operands to these intrinsics have EEW=16.
> The semantics for `RequiredFeatures` is `Features required to enable for this 
> builtin.` Since not all types in the range require the ZvfhminOrZvfh feature, 
> it may make sense to do some refactoring:
> 
> I think two possible solutions are:
>   1. to split def of `vfwcvt_f_f_v` and `vfncvt_f_f_w ` by type_range and the 
> type range `x` uses the RequiredFeatures
>   2. Use different required features for different type ranges (i.e. 
> RequiredFeatures is a list of lists where the outer list is for each type in 
> the range, and the inner list is the RequiredFeature for that type.)
I split it into 2 definations.



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c:15
+
+
+

michaelmaitland wrote:
> Do we need a test that checks calls to `__riscv_vfwcvt_f` and 
> `__riscv_vfncvt_f` using type `vfloat16m1_t` without zvfh nor zvfhmin lead to 
> the expected error asking for `zvfh or zvfhmin`?
fp16 vector type check is in `Sema/riscv-vector-float16-check.c`.




Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1018
 
+if (VT.getVectorElementType() == MVT::f16 &&
+!Subtarget.hasVInstructionsF16()) {

craig.topper wrote:
> This needs to be below `By default everything must be expanded.`
Fixed in https://reviews.llvm.org/D151414.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2096
   case MVT::f16:
-return Subtarget.hasVInstructionsF16();
+return Subtarget.hasVInstructionsF16Mininal();
   case MVT::f32:

craig.topper wrote:
> Is this correct? This function is called by 
> `RISCVTargetTransformInfo::isLegalToVectorizeReduction`, 
> `isLegalMaskedLoadStore`, `isLegalMaskedGatherScatter`.
Fixed in https://reviews.llvm.org/D151414.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162
+  bool hasVInstructionsF16Mininal() const {
+return HasStdExtZvfhmin || HasStdExtZvfh;
+  }

craig.topper wrote:
> Doesn't HasStdExtZvfh already imply HasStdExtZvfhmin?
The v spec doesn't metion this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-25 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked 5 inline comments as done.
jacquesguan added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:162
+  bool hasVInstructionsF16Mininal() const {
+return HasStdExtZvfhmin || HasStdExtZvfh;
+  }

craig.topper wrote:
> michaelmaitland wrote:
> > michaelmaitland wrote:
> > > jacquesguan wrote:
> > > > craig.topper wrote:
> > > > > Doesn't HasStdExtZvfh already imply HasStdExtZvfhmin?
> > > > The v spec doesn't metion this.
> > > I think the spec conveys this when it says `The Zvfhmin extension depends 
> > > on the Zve32f extension.`
> > My mistake, that says `Zve32f`, not `Zvfh`. However, the spec does say:
> > 
> > `When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and 
> > vfncvt.f.f.w instructions become defined when SEW=16` and also says `When 
> > the Zvfh extension is implemented, all instructions in Sections Vector 
> > Floating-Point Instructions.` Since `vfwcvt.f.f.v and vfncvt.f.f.w` are 
> > part of `Vector Floating-Point Instructions` section, this is how it is 
> > implied.
> It's implemented in LLVM by this patch https://reviews.llvm.org/D150016
This patch make Zvfh imply **Zfhmin ** not **Zvfhmin**. I think the relation 
between Zvfh and Zvfhmin is just like the relation between Zfh and Zfhmin. Now 
Zfh doesn't imply Zfhmin, so I keep Zvfh not imply Zvfhmin.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-05-26 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, jdoerfert, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, 
arichardson.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Since zihintntl is ratified now, we could remove the experimental prefix and 
change its version to 1.0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151547

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
  llvm/test/CodeGen/RISCV/nontemporal.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zihintntl-invalid.s
  llvm/test/MC/RISCV/rv32zihintntl-valid.s
  llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
  llvm/test/MC/RISCV/rv32zihintntlc-valid.s
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -375,7 +375,7 @@
   RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions();
   EXPECT_EQ(Exts.size(), 2UL);
   EXPECT_EQ(Exts.count("zihintntl"), 1U);
-  auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izihintntl0p2", true);
+  auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izihintntl1p0", true);
   ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
   RISCVISAInfo::OrderedExtensionMap Exts2 = (*MaybeISAInfo2)->getExtensions();
   EXPECT_EQ(Exts2.size(), 2UL);
@@ -454,13 +454,13 @@
   RISCVISAInfo::parseArchString("rv64im_zihintntl", true, false);
   ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded());
   EXPECT_THAT((*MaybeISAInfo1)->toFeatureVector(),
-  ElementsAre("+m", "+experimental-zihintntl"));
+  ElementsAre("+m", "+zihintntl"));
 
   auto MaybeISAInfo2 = RISCVISAInfo::parseArchString(
   "rv32e_zihintntl_xventanacondops", true, false);
   ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded());
   EXPECT_THAT((*MaybeISAInfo2)->toFeatureVector(),
-  ElementsAre("+e", "+experimental-zihintntl", "+xventanacondops"));
+  ElementsAre("+e", "+zihintntl", "+xventanacondops"));
 }
 
 TEST(ToFeatureVector, UnsupportedExtensionsAreDropped) {
Index: llvm/test/MC/RISCV/rv32zihintntlc-valid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-valid.s
+++ llvm/test/MC/RISCV/rv32zihintntlc-valid.s
@@ -1,15 +1,15 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl,+c -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zihintntl,+c -show-encoding \
 # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl,+c < %s \
-# RUN: | llvm-objdump --mattr=+experimental-zihintntl,+c -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \
+# RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \
 # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
-# RUN: not llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
+# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s
 
 # CHECK-ASM-AND-OBJ: ntl.p1
 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00]
Index: llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
===
--- llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
+++ llvm

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

2023-05-29 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D151547#4375613 , @asb wrote:

> Thanks for the patch.
>
> Is the __riscv_ntl_* interface finalised and agreed? I'm wary of repeating 
> the mistake we made with the V extension where we exposed intrinsics that 
> weren't yet finalised.

I don't find any information about these two intrinsics, where do they be 
proposed?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151547/new/

https://reviews.llvm.org/D151547

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-30 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D150253#4381435 , @craig.topper 
wrote:

> We need to support reinterpret intrinsics so that we can load/store bf16 
> values.

Sorry, I don't understand your comment well. I think that change you mentioned 
should not be included into this revision which only support zvfhmin for clang.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-30 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D150253#4382884 , @craig.topper 
wrote:

> Do we need to enable these intrinsics for Zvfhmin?
>
>   vfloat16mf4_t __riscv_vle16_v_f16mf4 (const float16_t *base, size_t vl);
>   vfloat16mf2_t __riscv_vle16_v_f16mf2 (const float16_t *base, size_t vl);
>   vfloat16m1_t __riscv_vle16_v_f16m1 (const float16_t *base, size_t vl);
>   vfloat16m2_t __riscv_vle16_v_f16m2 (const float16_t *base, size_t vl);
>   vfloat16m4_t __riscv_vle16_v_f16m4 (const float16_t *base, size_t vl);
>   vfloat16m8_t __riscv_vle16_v_f16m8 (const float16_t *base, size_t vl);
>
> Similar for all the other load/store intrinsics?
>
> Also all the vreinterpret intrinsics.
>
> And `__riscv_vmerge_vvm_f16*` and `__riscv_vmv_v_v_f16*`
>
> They can be a separate patch.

Yes, I will create a new patch to do that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-30 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 526872.
jacquesguan added a comment.

Address a comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td

Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -472,6 +472,11 @@
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
 
+def FeatureStdExtZvfhmin
+: SubtargetFeature<"experimental-zvfhmin", "HasStdExtZvfhmin", "true",
+   "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+   [FeatureStdExtZve32f]>;
+
 def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
 
 def HasStdExtZfhOrZvfh
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -152,6 +152,7 @@
 {"zvfbfmin", RISCVExtensionVersion{0, 6}},
 {"zvfbfwma", RISCVExtensionVersion{0, 6}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+{"zvfhmin", RISCVExtensionVersion{0, 1}},
 {"ztso", RISCVExtensionVersion{0, 1}},
 
 // vector crypto
@@ -943,6 +944,7 @@
 static const char *ImpliedExtsZvfbfmin[] = {"zve32f"};
 static const char *ImpliedExtsZvfbfwma[] = {"zve32f"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
+static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
 static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
 "zvkt"};
 static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
@@ -1004,6 +1006,7 @@
 {{"zvfbfmin"}, {ImpliedExtsZvfbfmin}},
 {{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
 {{"zvfh"}, {ImpliedExtsZvfh}},
+{{"zvfhmin"}, {ImpliedExtsZvfhmin}},
 {{"zvkn"}, {ImpliedExtsZvkn}},
 {{"zvkng"}, {ImpliedExtsZvkng}},
 {{"zvknhb"}, {ImpliedExtsZvknhb}},
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,5 +4,5 @@
 // REQUIRES: riscv-registered-target
 #include 
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 } /* expected-warning {{non-void function does not return a value}}*/
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NE

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-05-30 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG35a0079238ce: [RISCV] Add Zvfhmin extension for clang. 
(authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td

Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -472,6 +472,11 @@
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
 
+def FeatureStdExtZvfhmin
+: SubtargetFeature<"experimental-zvfhmin", "HasStdExtZvfhmin", "true",
+   "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+   [FeatureStdExtZve32f]>;
+
 def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
 
 def HasStdExtZfhOrZvfh
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -152,6 +152,7 @@
 {"zvfbfmin", RISCVExtensionVersion{0, 6}},
 {"zvfbfwma", RISCVExtensionVersion{0, 6}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
+{"zvfhmin", RISCVExtensionVersion{0, 1}},
 {"ztso", RISCVExtensionVersion{0, 1}},
 
 // vector crypto
@@ -943,6 +944,7 @@
 static const char *ImpliedExtsZvfbfmin[] = {"zve32f"};
 static const char *ImpliedExtsZvfbfwma[] = {"zve32f"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
+static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
 static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
 "zvkt"};
 static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
@@ -1004,6 +1006,7 @@
 {{"zvfbfmin"}, {ImpliedExtsZvfbfmin}},
 {{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
 {{"zvfh"}, {ImpliedExtsZvfh}},
+{{"zvfhmin"}, {ImpliedExtsZvfhmin}},
 {{"zvkn"}, {ImpliedExtsZvkn}},
 {{"zvkng"}, {ImpliedExtsZvkng}},
 {{"zvknhb"}, {ImpliedExtsZvknhb}},
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,5 +4,5 @@
 // REQUIRES: riscv-registered-target
 #include 
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 } /* expected-warning {{non-void function does not return a value}}*/
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t s

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-06-01 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 527312.
jacquesguan added a comment.

Update dependency.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/test/Sema/riscv-vector-float16-check.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,5 +4,5 @@
 // REQUIRES: riscv-registered-target
 #include 
 
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
 } /* expected-warning {{non-void function does not return a value}}*/
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
+  return __riscv_vfwcvt_f(src, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVF %s
+
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfhmin -emit-llvm-only %s 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-ZVFHMIN-ERR
+
+#include 
+
+// CHECK-ZVF-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-ZVF-NEXT:  entry:
+// CHECK-ZVF-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64( poison,  [[OP1:%.*]],  [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVF-NEXT:ret  [[TMP0]]
+//
+
+// CHECK-ZVFHMIN-ERR: no matching function for call to '__riscv_vfadd'
+
+vfloat16m1_t test_vfadd_vv_f16m1(vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+  return __riscv_vfadd(op1, op2, vl);
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -195,6 +195,8 @@
   const TargetInfo &TI = Context.getTargetInfo();
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
+  bool HasZvfh = TI.hasFeature("experimental-zvfh");
+

[PATCH] D151869: [RISCV] Support more builtin for zvfhmin.

2023-06-01 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck, 
michaelmaitland.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, arichardson.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

This patch enables some fp16 vector type builtins that don't use fp arithmetic 
instruction for zvfhmin.
Include following builtins:

  vector load/store,
  vector reinterpret,
  vmerge_vvm,
  vmv_v.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151869

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -25,3 +25,208 @@
 vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
   return __riscv_vfwcvt_f(src, vl);
 }
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vle.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) {
+  return __riscv_vle16_v_f16m1(base, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vse16_v_f16m1(_Float16 *base, vfloat16m1_t value, size_t vl) {
+  return __riscv_vse16_v_f16m1(base, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vlse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vlse.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vlse16_v_f16m1(const _Float16 *base, ptrdiff_t bstride, size_t vl) {
+  return __riscv_vlse16_v_f16m1(base, bstride, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsse16_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsse.nxv4f16.i64( [[VALUE:%.*]], ptr [[BASE:%.*]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsse16_v_f16m1(_Float16 *base, ptrdiff_t bstride, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsse16_v_f16m1(base, bstride, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vluxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vluxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+  return __riscv_vluxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsuxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsuxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsuxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vloxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64( poison, ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vloxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+  return __riscv_vloxei32_v_f16m1(base, bindex, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vsoxei32_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:call void @llvm.riscv.vsoxei.nxv4f16.nxv4i32.i64( [[VALUE:%.*]], ptr [[BASE:%.*]],  [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret void
+//
+void test_vsoxei32_v_f16m1(_Float16 *base, vuint32m2_t bindex, vfloat16m1_t value, size_t vl) {
+  return __riscv_vsoxei32_v_f16m1(base, bindex, value, vl);
+}
+
+// CHECK-ZVFHMIN-LABEL: @test_vle16ff_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4f16.i64( poison, ptr [[BASE:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:[[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0
+// CHECK-ZVFHMIN-NEXT:[[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1
+//

[PATCH] D150253: [RISCV] Add Zvfhmin extension for clang.

2023-06-01 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2219
+  def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
+  let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {

eopXD wrote:
> craig.topper wrote:
> > eopXD wrote:
> > > I think using `ZvfhminOrZvfh` is not accurate here. By the v-spec:
> > > 
> > > > When the Zvfhmin extension is implemented, the vfwcvt.f.f.v and 
> > > > vfncvt.f.f.w instructions become defined when SEW=16. 
> > > > The Zvfh extension depends on the Zve32f and Zfhmin extensions.
> > > 
> > > I think making it `let RequiredFeatures = ["Zvfhmin"]` would be clearer.
> > Note that the spec says Zfhmin(no v) not Zvfhmin. 
> My mistake. I suspect this is an oversight of the v-spec, just created an 
> issue for this.
> 
> https://github.com/riscv/riscv-v-spec/issues/885
Thanks for comment. I think that v-spec is in accordance with the scalar spec 
to some degree. Since `zfh` doesn't imply `zfhmin`, I don't think they will let 
`zvfh` imply `zvfhmin`.



Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c:15
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);

eopXD wrote:
> This test case is already covered.
> 
> https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvt.c#L356
Yes, but this test is for zvfhmin. `vfncvt.c` contains other convert cases not 
enable for zvfhmin so we can't just add a zvfhmin check.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150021: [RISCV] Make zve32f imply F and zve64d imply D.

2023-05-06 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan accepted this revision.
jacquesguan added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150021/new/

https://reviews.llvm.org/D150021

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-10 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, evandro, apazos, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, 
arichardson.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

This patch adds the Zvfhmin extension for clang and llvm RISCV target.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td

Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -446,6 +446,11 @@
   "'V' (Vector Extension for Application Processors), 'Zve32f', "
   "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
 
+def FeatureStdExtZvfhmin
+: SubtargetFeature<"experimental-zvfhmin", "HasStdExtZvfhmin", "true",
+   "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+   [FeatureStdExtZve32f]>;
+
 def FeatureStdExtZvfh
 : SubtargetFeature<"experimental-zvfh", "HasStdExtZvfh", "true",
"'Zvfh' (Vector Half-Precision Floating-Point)",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -148,6 +148,7 @@
 {"zcmt", RISCVExtensionVersion{1, 0}},
 {"zfa", RISCVExtensionVersion{0, 2}},
 {"zicond", RISCVExtensionVersion{1, 0}},
+{"zvfhmin", RISCVExtensionVersion{0, 1}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
 {"ztso", RISCVExtensionVersion{0, 1}},
 
@@ -936,6 +937,7 @@
 static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
 static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
+static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
 static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
 "zvkt"};
@@ -994,6 +996,7 @@
 {{"zve64d"}, {ImpliedExtsZve64d}},
 {{"zve64f"}, {ImpliedExtsZve64f}},
 {{"zve64x"}, {ImpliedExtsZve64x}},
+{{"zvfhmin"}, {ImpliedExtsZvfhmin}},
 {{"zvfh"}, {ImpliedExtsZvfh}},
 {{"zvkn"}, {ImpliedExtsZvkn}},
 {{"zvkng"}, {ImpliedExtsZvkng}},
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -target-feature +experimental-zvfhmin -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include 
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64( poison,  [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT:ret  [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+  return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT:  entry:
+// CHECK-ZVFHMIN-NEXT:[[TMP0:%.*]

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-15 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

To enable specific EEW for specific insturction in instruction selection, I 
will create some parent revisions. Here is the first one. 
https://reviews.llvm.org/D150550


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-15 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D150253#4343699 , @craig.topper 
wrote:

> In D150253#4341545 , @jacquesguan 
> wrote:
>
>> To enable specific EEW for specific insturction in instruction selection, I 
>> will create some parent revisions. Here is the first one. 
>> https://reviews.llvm.org/D150550
>
> @michaelmaitland was also going to be working on supporting Zvfhmin for 
> SiFive. Maybe we can split up and share some of the work?

Yes, in order to avoid duplicate work.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 523688.
jacquesguan added a comment.

make f16 vector type legal for Zvfhmin, add predicates to enable 2 convert 
pattern.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll

Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
@@ -3,6 +3,10 @@
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
 declare  @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
   ,
   ,
Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
 
 declare  @llvm.vp.fptrunc.nxv2f16.nxv2f32(, , i32)
 
Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
@@ -3,6 +3,10 @@
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
 
 define  @vfptrunc_nxv1f32_nxv1f16( %va) {
 ;
Index: llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
 
 declare  @llvm.vp.fpext.nxv2f32.nxv2f16(, , i32)
 
Index: llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
@@ -3,6 +3,10 @@
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
 ; RUN: -verify-mac

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

@michaelmaitland , I update this revision with my local branch. May you have a 
look and see what missed compared with you version?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D150253: [RISCV] Add Zvfhmin extension.

2023-05-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 523696.
jacquesguan added a comment.

Fix indention.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150253/new/

https://reviews.llvm.org/D150253

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/Sema.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd.ll
  llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
  llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll

Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
@@ -3,6 +3,10 @@
 ; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
 ; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
 declare  @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
   ,
   ,
Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
 
 declare  @llvm.vp.fptrunc.nxv2f16.nxv2f32(, , i32)
 
Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
@@ -3,6 +3,10 @@
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
 
 define  @vfptrunc_nxv1f32_nxv1f16( %va) {
 ;
Index: llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
 
 declare  @llvm.vp.fpext.nxv2f32.nxv2f16(, , i32)
 
Index: llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
===
--- llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
@@ -3,6 +3,10 @@
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
 ; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,

[PATCH] D148908: [Driver][NFC] Simplify code.

2023-04-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
Herald added a project: All.
jacquesguan requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148908

Files:
  clang/lib/Driver/Driver.cpp


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -4095,16 +4095,15 @@
 
   Current = NewCurrent;
 
-  // Use the current host action in any of the offloading actions, if
-  // required.
-  if (!UseNewOffloadingDriver)
-if (OffloadBuilder->addHostDependenceToDeviceActions(Current, 
InputArg))
-  break;
-
   // Try to build the offloading actions and add the result as a dependency
   // to the host.
   if (UseNewOffloadingDriver)
 Current = BuildOffloadingActions(C, Args, I, Current);
+  // Use the current host action in any of the offloading actions, if
+  // required.
+  else if (OffloadBuilder->addHostDependenceToDeviceActions(Current,
+InputArg))
+break;
 
   if (Current->getType() == types::TY_Nothing)
 break;


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -4095,16 +4095,15 @@
 
   Current = NewCurrent;
 
-  // Use the current host action in any of the offloading actions, if
-  // required.
-  if (!UseNewOffloadingDriver)
-if (OffloadBuilder->addHostDependenceToDeviceActions(Current, InputArg))
-  break;
-
   // Try to build the offloading actions and add the result as a dependency
   // to the host.
   if (UseNewOffloadingDriver)
 Current = BuildOffloadingActions(C, Args, I, Current);
+  // Use the current host action in any of the offloading actions, if
+  // required.
+  else if (OffloadBuilder->addHostDependenceToDeviceActions(Current,
+InputArg))
+break;
 
   if (Current->getType() == types::TY_Nothing)
 break;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D148908: [Driver][NFC] Simplify code.

2023-04-22 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8e3a5a965a14: [Driver][NFC] Simplify code. (authored by 
jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148908/new/

https://reviews.llvm.org/D148908

Files:
  clang/lib/Driver/Driver.cpp


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -4095,16 +4095,15 @@
 
   Current = NewCurrent;
 
-  // Use the current host action in any of the offloading actions, if
-  // required.
-  if (!UseNewOffloadingDriver)
-if (OffloadBuilder->addHostDependenceToDeviceActions(Current, 
InputArg))
-  break;
-
   // Try to build the offloading actions and add the result as a dependency
   // to the host.
   if (UseNewOffloadingDriver)
 Current = BuildOffloadingActions(C, Args, I, Current);
+  // Use the current host action in any of the offloading actions, if
+  // required.
+  else if (OffloadBuilder->addHostDependenceToDeviceActions(Current,
+InputArg))
+break;
 
   if (Current->getType() == types::TY_Nothing)
 break;


Index: clang/lib/Driver/Driver.cpp
===
--- clang/lib/Driver/Driver.cpp
+++ clang/lib/Driver/Driver.cpp
@@ -4095,16 +4095,15 @@
 
   Current = NewCurrent;
 
-  // Use the current host action in any of the offloading actions, if
-  // required.
-  if (!UseNewOffloadingDriver)
-if (OffloadBuilder->addHostDependenceToDeviceActions(Current, InputArg))
-  break;
-
   // Try to build the offloading actions and add the result as a dependency
   // to the host.
   if (UseNewOffloadingDriver)
 Current = BuildOffloadingActions(C, Args, I, Current);
+  // Use the current host action in any of the offloading actions, if
+  // required.
+  else if (OffloadBuilder->addHostDependenceToDeviceActions(Current,
+InputArg))
+break;
 
   if (Current->getType() == types::TY_Nothing)
 break;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117854: [RISCV] Refactor Zve* extensions.

2022-01-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 402166.
jacquesguan added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h

Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -179,13 +179,19 @@
   }
 
   // Vector codegen related methods.
-  bool hasVInstructions() const { return HasStdExtZve32x; }
-  bool hasVInstructionsI64() const { return HasStdExtZve64x; }
-  bool hasVInstructionsF16() const { return HasStdExtZve32f && HasStdExtZfh; }
+  bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; }
+  bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; }
+  bool hasVInstructionsF16() const {
+return HasStdExtV || (HasStdExtZve32f && HasStdExtZfh);
+  }
   // FIXME: Consider Zfinx in the future
-  bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
+  bool hasVInstructionsF32() const {
+return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
+  }
   // FIXME: Consider Zdinx in the future
-  bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; }
+  bool hasVInstructionsF64() const {
+return HasStdExtV || (HasStdExtZve64d && HasStdExtD);
+  }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
   unsigned getMaxInterleaveFactor() const {
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -193,21 +193,21 @@
 def FeatureStdExtV
 : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
"'V' (Vector Extension for Application Processors)",
-   [FeatureStdExtZvl128b, FeatureStdExtZve64d, FeatureStdExtF, FeatureStdExtD]>;
+   [FeatureStdExtZvl128b, FeatureStdExtF, FeatureStdExtD]>;
 
 def HasVInstructions: Predicate<"Subtarget->hasVInstructions()">,
   AssemblerPredicate<
-  (any_of FeatureStdExtZve32x),
+  (any_of FeatureStdExtZve32x, FeatureStdExtV),
   "'V' (Vector Extension for Application Processors), 'Zve32x' or "
   "'Zve64x' (Vector Extensions for Embedded Processors)">;
 def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
   AssemblerPredicate<
-  (any_of FeatureStdExtZve64x),
+  (any_of FeatureStdExtZve64x, FeatureStdExtV),
   "'V' (Vector Extension for Application Processors) or 'Zve64x' "
   "(Vector Extensions for Embedded Processors)">;
 def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
   AssemblerPredicate<
-  (any_of FeatureStdExtZve32f),
+  (any_of FeatureStdExtZve32f, FeatureStdExtV),
   "'V' (Vector Extension for Application Processors), 'Zve32f', "
   "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -688,9 +688,11 @@
   bool HasE = Exts.count("e") == 1;
   bool HasD = Exts.count("d") == 1;
   bool HasF = Exts.count("f") == 1;
-  bool HasVector = Exts.count("zve32x") == 1;
+  bool HasZve32x = Exts.count("zve32x") == 1;
   bool HasZve32f = Exts.count("zve32f") == 1;
   bool HasZve64d = Exts.count("zve64d") == 1;
+  bool HasV = Exts.count("v") == 1;
+  bool HasVector = HasZve32x || HasV;
   bool HasZvl = MinVLen != 0;
 
   if (HasE && !IsRv32)
@@ -730,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -853,6 +855,11 @@
   ExtName.getAsInteger(10, ZveELen);
   MaxELen = std::max(MaxELen, ZveELen);
 }
+if (ExtName == "v") {
+  MaxELenFp = 64;
+  MaxELen = 64;
+  return;
+}
   }
 }
 
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1024,7 +1024,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET

[PATCH] D117854: [RISCV] Refactor Zve* extensions.

2022-01-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D117854#3261659 , @craig.topper 
wrote:

> In D117854#3261618 , @eopXD wrote:
>
>> A question that bothers me is that we need to specify a specific feature to 
>> enable the TARGET_BUILTIN for rvv, if we are removing the “subset” 
>> relationship here, how can V enable the builtin-s?
>
> If I remember right "experimental-zve32x|experimental-v" should be valid 
> syntax. Though I'm not sure the string is used at all because of how the 
> clang_builtin_alias used by the header works.

I modified the `RISCVISAInfo` and make this revision works for Clang.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117854: [RISCV] Refactor Zve* extensions.

2022-01-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 402173.
jacquesguan added a comment.
Herald added a subscriber: jdoerfert.

Fix test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
 
 .attribute arch, "rv32iv0p10zvl16384b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b

[PATCH] D117920: [RISCV] Decouple V and Zve64*

2022-01-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

I did some similar change in my revision https://reviews.llvm.org/D117854.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117920/new/

https://reviews.llvm.org/D117920

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D117854#3263206 , @eopXD wrote:

> Maybe change the title to address more specifically of what this patch does?

Done, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 402184.
jacquesguan added a comment.

Address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
 
 .attribute arch, "rv32iv0p10zvl16384b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
+# CHECK

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3978
   for (StringRef F : ReqFeatures) {
-if (TI.hasFeature(F))
-  continue;
-
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (F == "64bit")
-  F = "RV64";
-
-// Convert features like "zbr" and "experimental-zbr" to "Zbr".
-F.consume_front("experimental-");
-std::string FeatureStr = F.str();
-FeatureStr[0] = std::toupper(FeatureStr[0]);
+SmallVector ReqOpFeatures;
+F.split(ReqOpFeatures, '|');

craig.topper wrote:
> Is this change testable?
Done, I add a test case `clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c` 
to test this.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:697
   bool HasZvl = MinVLen != 0;
 
   if (HasE && !IsRv32)

craig.topper wrote:
> Should we check that Zve and V are not specified together?
Done.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 402188.
jacquesguan added a comment.

Fix test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute  5, "rv32i2p0_zba1p0"
@@ -75,43 +75,43 @@
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
 
 .attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
 
 .attribute arch, "rv32iv0p10zvl16384b0p10"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
+# CHECK:

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-23 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 402385.
jacquesguan added a comment.
Herald added a subscriber: pcwang-thead.

Address comment


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,43 +34,43 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl32b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl64b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl128b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl256b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl512b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl1024b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl2048b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl4096b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl8192b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl16384b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl32768b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl65536b"
-# CHECK: attribute

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-23 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 402401.
jacquesguan added a comment.

Rebase main


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,43 +34,43 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl32b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl64b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl128b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl256b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl512b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl1024b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl2048b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl4096b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl8192b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl16384b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl32768b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl65536b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve3

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

2022-01-23 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGba16e3c31f66: [RISCV] Decouple Zve* extensions and the V 
extension. (authored by jacquesguan).

Changed prior to commit:
  https://reviews.llvm.org/D117854?vs=402401&id=402404#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117854/new/

https://reviews.llvm.org/D117854

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb-error.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -34,43 +34,43 @@
 # CHECK: attribute  5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32iv"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl32b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl64b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl128b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl256b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl512b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl1024b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl2048b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl4096b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ivzvl8192b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl16384b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
 
 .attribute arch, "rv32ivzvl32768b"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_v

[PATCH] D118015: [RISCV][NFC] Rename RequiredExtensions to RequiredFeatures.

2022-01-23 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck, 
HsiangKai, khchen, benshi001.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
jacquesguan requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

The field 'RequiredExtensions' is used to specify the constraint for rvv 
builtin, and it contains something which is not a sub-extension or extension 
such as 'RV64'. So the word 'extension' is not accurate now, 'feature' seems 
better.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118015

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -179,7 +179,7 @@
bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &Types,
const std::vector &IntrinsicTypes,
-   const std::vector &RequiredExtensions, unsigned NF);
+   const std::vector &RequiredFeatures, unsigned NF);
   ~RVVIntrinsic() = default;
 
   StringRef getBuiltinName() const { return BuiltinName; }
@@ -772,7 +772,7 @@
bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &OutInTypes,
const std::vector &NewIntrinsicTypes,
-   const std::vector &RequiredExtensions,
+   const std::vector &RequiredFeatures,
unsigned NF)
 : IRName(IRName), IsMask(IsMask), HasVL(HasVL), HasPolicy(HasPolicy),
   HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef),
@@ -805,8 +805,8 @@
 if (T->isVector(64))
   RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
-  for (auto Extension : RequiredExtensions) {
-if (Extension == "RV64")
+  for (auto Feature : RequiredFeatures) {
+if (Feature == "RV64")
   RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
@@ -1154,8 +1154,8 @@
 StringRef ManualCodegenMask = R->getValueAsString("ManualCodegenMask");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
-std::vector RequiredExtensions =
-R->getValueAsListOfStrings("RequiredExtensions");
+std::vector RequiredFeatures =
+R->getValueAsListOfStrings("RequiredFeatures");
 StringRef IRName = R->getValueAsString("IRName");
 StringRef IRNameMask = R->getValueAsString("IRNameMask");
 unsigned NF = R->getValueAsInt("NF");
@@ -1223,7 +1223,7 @@
 Name, SuffixStr, MangledName, MangledSuffixStr, IRName,
 /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL, HasPolicy,
 HasNoMaskedOverloaded, HasAutoDef, ManualCodegen, Types.getValue(),
-IntrinsicTypes, RequiredExtensions, NF));
+IntrinsicTypes, RequiredFeatures, NF));
 if (HasMask) {
   // Create a mask intrinsic
   Optional MaskTypes =
@@ -1232,7 +1232,7 @@
   Name, SuffixStr, MangledName, MangledSuffixStr, IRNameMask,
   /*IsMask=*/true, HasMaskedOffOperand, HasVL, HasPolicy,
   HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask,
-  MaskTypes.getValue(), IntrinsicTypes, RequiredExtensions, NF));
+  MaskTypes.getValue(), IntrinsicTypes, RequiredFeatures, NF));
 }
   } // end for Log2LMULList
 }   // end for TypeRange
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -215,8 +215,8 @@
   // an automatic definition in header is emitted.
   string HeaderCode = "";
 
-  // Sub extension of vector spec.
-  list RequiredExtensions = [];
+  // Features required to enable for this builtin.
+  list RequiredFeatures = [];
 
   // Number of fields for Load/Store Segment instructions.
   int NF = 1;
@@ -720,7 +720,7 @@
 defvar eew64 = "64";
 defvar eew64_type = "(Log2EEW:6)";
 let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
-RequiredExtensions = ["RV64"] in {
+RequiredFeatures = ["RV64"] in {
 def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>;
   if !not(IsFloat.val) then {
 def: RVVBuiltin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
@@ -819,7 +819,7 @@
 d

[PATCH] D118015: [RISCV][NFC] Rename RequiredExtensions to RequiredFeatures.

2022-01-24 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9ea3dfa5d015: [RISCV][NFC] Rename RequiredExtensions to 
RequiredFeatures. (authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118015/new/

https://reviews.llvm.org/D118015

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -179,7 +179,7 @@
bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &Types,
const std::vector &IntrinsicTypes,
-   const std::vector &RequiredExtensions, unsigned NF);
+   const std::vector &RequiredFeatures, unsigned NF);
   ~RVVIntrinsic() = default;
 
   StringRef getBuiltinName() const { return BuiltinName; }
@@ -772,7 +772,7 @@
bool HasNoMaskedOverloaded, bool HasAutoDef,
StringRef ManualCodegen, const RVVTypes &OutInTypes,
const std::vector &NewIntrinsicTypes,
-   const std::vector &RequiredExtensions,
+   const std::vector &RequiredFeatures,
unsigned NF)
 : IRName(IRName), IsMask(IsMask), HasVL(HasVL), HasPolicy(HasPolicy),
   HasNoMaskedOverloaded(HasNoMaskedOverloaded), HasAutoDef(HasAutoDef),
@@ -805,8 +805,8 @@
 if (T->isVector(64))
   RISCVPredefinedMacros |= RISCVPredefinedMacro::VectorMaxELen64;
   }
-  for (auto Extension : RequiredExtensions) {
-if (Extension == "RV64")
+  for (auto Feature : RequiredFeatures) {
+if (Feature == "RV64")
   RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64;
   }
 
@@ -1154,8 +1154,8 @@
 StringRef ManualCodegenMask = R->getValueAsString("ManualCodegenMask");
 std::vector IntrinsicTypes =
 R->getValueAsListOfInts("IntrinsicTypes");
-std::vector RequiredExtensions =
-R->getValueAsListOfStrings("RequiredExtensions");
+std::vector RequiredFeatures =
+R->getValueAsListOfStrings("RequiredFeatures");
 StringRef IRName = R->getValueAsString("IRName");
 StringRef IRNameMask = R->getValueAsString("IRNameMask");
 unsigned NF = R->getValueAsInt("NF");
@@ -1223,7 +1223,7 @@
 Name, SuffixStr, MangledName, MangledSuffixStr, IRName,
 /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL, HasPolicy,
 HasNoMaskedOverloaded, HasAutoDef, ManualCodegen, Types.getValue(),
-IntrinsicTypes, RequiredExtensions, NF));
+IntrinsicTypes, RequiredFeatures, NF));
 if (HasMask) {
   // Create a mask intrinsic
   Optional MaskTypes =
@@ -1232,7 +1232,7 @@
   Name, SuffixStr, MangledName, MangledSuffixStr, IRNameMask,
   /*IsMask=*/true, HasMaskedOffOperand, HasVL, HasPolicy,
   HasNoMaskedOverloaded, HasAutoDef, ManualCodegenMask,
-  MaskTypes.getValue(), IntrinsicTypes, RequiredExtensions, NF));
+  MaskTypes.getValue(), IntrinsicTypes, RequiredFeatures, NF));
 }
   } // end for Log2LMULList
 }   // end for TypeRange
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -215,8 +215,8 @@
   // an automatic definition in header is emitted.
   string HeaderCode = "";
 
-  // Sub extension of vector spec.
-  list RequiredExtensions = [];
+  // Features required to enable for this builtin.
+  list RequiredFeatures = [];
 
   // Number of fields for Load/Store Segment instructions.
   int NF = 1;
@@ -720,7 +720,7 @@
 defvar eew64 = "64";
 defvar eew64_type = "(Log2EEW:6)";
 let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
-RequiredExtensions = ["RV64"] in {
+RequiredFeatures = ["RV64"] in {
 def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>;
   if !not(IsFloat.val) then {
 def: RVVBuiltin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
@@ -819,7 +819,7 @@
 defvar eew64 = "64";
 defvar eew64_type = "(Log2EEW:6)";
 let Name = op # eew64  # "_v", IRName = op, IRNameMask = op # "_mask",
-RequiredExtensions = ["RV64"]  in  {
+RequiredFeatures = ["RV64"]  in  {
   def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
   if !not(IsFloat.val) then {
 def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;


Index: clang/utils/TableGen/RISCVVEmitter.cpp

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

2022-01-26 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, eopXD, asb, luismarques, 
frasercrmck, HsiangKai, khchen, benshi001.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
jacquesguan requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

According to the v spec, there is no include relationship or dependency among 
the Zve* extensions. For exmaple, we do not need to implement Zve64x for 
Zve64f, these two are indepedent extensions. This patch decouple all Zve* 
extensions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118225

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/test/Preprocessor/riscv-target-features.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -76,16 +76,16 @@
 # CHECK: attribute  5, "rv32i2p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32ifzve32f"
-# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zvl32b1p0"
 
 .attribute arch, "rv32izve64x"
-# CHECK: attribute  5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifzve64f"
-# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zve64f1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifdzve64d"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_zve64d1p0_zvl32b1p0_zvl64b1p0"
 
 ## Experimental extensions require version string to be explicitly specified
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -202,18 +202,29 @@
   }
 
   // Vector codegen related methods.
-  bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; }
-  bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; }
+  bool hasZve() const {
+return HasStdExtZve32x || HasStdExtZve32f || HasStdExtZve64x ||
+   HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZve64() const {
+return HasStdExtZve64x || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZvef() const {
+return HasStdExtZve32f || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZved() const { return HasStdExtZve64d; }
+  bool hasVInstructions() const { return HasStdExtV || hasZve(); }
+  bool hasVInstructionsI64() const { return HasStdExtV || hasZve64(); }
   bool hasVInstructionsF16() const {
-return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh;
+return HasStdExtZfh && (HasStdExtV || hasZvef());
   }
   // FIXME: Consider Zfinx in the future
   bool hasVInstructionsF32() const {
-return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
+return HasStdExtV || (hasZvef() && HasStdExtF);
   }
   // FIXME: Consider Zdinx in the future
   bool hasVInstructionsF64() const {
-return HasStdExtV || (HasStdExtZve64d && HasStdExtD);
+return HasStdExtV || (hasZved() && HasStdExtD);
   }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -299,24 +299,24 @@
 : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
-   [FeatureStdExtZve32x]>;
+   [FeatureStdExtZvl32b]>;
 
 def FeatureStdExtZve64x
 : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
"'Zve64x' (Vector Extensions for Embedded Processors "
-   "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+   "with maximal 64 EEW)", [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64f
 : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
"'Zve64f' (Vector E

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

2022-01-26 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

In D118225#3272071 , @eopXD wrote:

> Not sure if this simplifies things. Users and the compiler  can use the macro 
> `__riscv_v_elen` and `__riscv_v_elen_fp` to do things to the vector-related 
> target feature.
>
> Other than that I don't hold any strong objection to this refactoring.

This patch is similar with https://reviews.llvm.org/D117854. I think these five 
Zve* extensions are independent, we do not need to implement Zve32x for Zve64x, 
even all instructions of Zve32x is subset of instructions of Zve64x, same with 
other dependencies.
Current implemention of Zve* with depedency make some unclear. For example, in 
`clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c`, the error message shows 
that the buitin only needs Zve32x or V  extension to be enable. But actually, 
if we just implement Zve64x, these builtins should work as well. These error 
messages is kind of confusing if we make Zve* extensions has depedent 
relationship.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118225/new/

https://reviews.llvm.org/D118225

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

2022-01-26 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 403503.
jacquesguan added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118225/new/

https://reviews.llvm.org/D118225

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/test/Preprocessor/riscv-target-features.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -76,16 +76,16 @@
 # CHECK: attribute  5, "rv32i2p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32ifzve32f"
-# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zvl32b1p0"
 
 .attribute arch, "rv32izve64x"
-# CHECK: attribute  5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifzve64f"
-# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zve64f1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifdzve64d"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_zve64d1p0_zvl32b1p0_zvl64b1p0"
 
 ## Experimental extensions require version string to be explicitly specified
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -202,18 +202,29 @@
   }
 
   // Vector codegen related methods.
-  bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; }
-  bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; }
+  bool hasZve() const {
+return HasStdExtZve32x || HasStdExtZve32f || HasStdExtZve64x ||
+   HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZve64() const {
+return HasStdExtZve64x || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZvef() const {
+return HasStdExtZve32f || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZved() const { return HasStdExtZve64d; }
+  bool hasVInstructions() const { return HasStdExtV || hasZve(); }
+  bool hasVInstructionsI64() const { return HasStdExtV || hasZve64(); }
   bool hasVInstructionsF16() const {
-return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh;
+return HasStdExtZfh && (HasStdExtV || hasZvef());
   }
   // FIXME: Consider Zfinx in the future
   bool hasVInstructionsF32() const {
-return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
+return HasStdExtV || (hasZvef() && HasStdExtF);
   }
   // FIXME: Consider Zdinx in the future
   bool hasVInstructionsF64() const {
-return HasStdExtV || (HasStdExtZve64d && HasStdExtD);
+return HasStdExtV || (hasZved() && HasStdExtD);
   }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -299,24 +299,24 @@
 : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
-   [FeatureStdExtZve32x]>;
+   [FeatureStdExtZvl32b]>;
 
 def FeatureStdExtZve64x
 : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
"'Zve64x' (Vector Extensions for Embedded Processors "
-   "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+   "with maximal 64 EEW)", [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64f
 : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
-   [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+   [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64d
 : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
-   [FeatureStdExtZve64f]>;
+   [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtV
 : SubtargetFeature<"v", "HasStdExtV", "true",
Index: llvm/lib/Support/RISCVISAInfo.cpp
==

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

2022-01-26 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:747
   // Could not implement Zve* extension and the V extension at the same time.
-  if (HasZve32x && HasV)
+  if (HasZve && HasV)
 return createStringError(

craig.topper wrote:
> Now we need to check if multiple Zve extensions are specified at the same 
> time?
Done


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118225/new/

https://reviews.llvm.org/D118225

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

2022-01-27 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan updated this revision to Diff 403858.
jacquesguan added a comment.

Update code


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118225/new/

https://reviews.llvm.org/D118225

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
  clang/test/Preprocessor/riscv-target-features.c
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -76,16 +76,16 @@
 # CHECK: attribute  5, "rv32i2p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32ifzve32f"
-# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zvl32b1p0"
 
 .attribute arch, "rv32izve64x"
-# CHECK: attribute  5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifzve64f"
-# CHECK: attribute  5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_zve64f1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifdzve64d"
-# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute  5, "rv32i2p0_f2p0_d2p0_zve64d1p0_zvl32b1p0_zvl64b1p0"
 
 ## Experimental extensions require version string to be explicitly specified
 
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -202,18 +202,29 @@
   }
 
   // Vector codegen related methods.
-  bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; }
-  bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; }
+  bool hasZve() const {
+return HasStdExtZve32x || HasStdExtZve32f || HasStdExtZve64x ||
+   HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZve64() const {
+return HasStdExtZve64x || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZvef() const {
+return HasStdExtZve32f || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZved() const { return HasStdExtZve64d; }
+  bool hasVInstructions() const { return HasStdExtV || hasZve(); }
+  bool hasVInstructionsI64() const { return HasStdExtV || hasZve64(); }
   bool hasVInstructionsF16() const {
-return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh;
+return HasStdExtZfh && (HasStdExtV || hasZvef());
   }
   // FIXME: Consider Zfinx in the future
   bool hasVInstructionsF32() const {
-return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
+return HasStdExtV || (hasZvef() && HasStdExtF);
   }
   // FIXME: Consider Zdinx in the future
   bool hasVInstructionsF64() const {
-return HasStdExtV || (HasStdExtZve64d && HasStdExtD);
+return HasStdExtV || (hasZved() && HasStdExtD);
   }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
Index: llvm/lib/Target/RISCV/RISCV.td
===
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -305,24 +305,24 @@
 : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
"'Zve32f' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW and F extension)",
-   [FeatureStdExtZve32x]>;
+   [FeatureStdExtZvl32b]>;
 
 def FeatureStdExtZve64x
 : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
"'Zve64x' (Vector Extensions for Embedded Processors "
-   "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+   "with maximal 64 EEW)", [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64f
 : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
"'Zve64f' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW and F extension)",
-   [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+   [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64d
 : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
"'Zve64d' (Vector Extensions for Embedded Processors "
"with maximal 64 EEW, F and D extension)",
-   [FeatureStdExtZve64f]>;
+   [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtV
 : SubtargetFeature<"v", "HasStdExtV", "true",
Index: llvm/lib/Support/RISCVISAInfo.cpp
===

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2022-01-06 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

ping


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2022-01-07 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5475
 
+  if (IndexVT.getVectorElementType() == MVT::i64 && XLenVT == MVT::i32) {
+report_fatal_error("The V extension does not support EEW=64 for index "

craig.topper wrote:
> Can we truncate the index to nvxXi32 instead of erroring? Would that allow us 
> to preserve more test cases?
Done, thanks.



Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:1033
 
-define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(i64* %base, <8 x i8> %idxs, 
<8 x i1> %m, <8 x i64> %passthru) {
-; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i64:

craig.topper wrote:
> Can these test cases be preserved in an rv64 only test?
Done, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info

2021-12-19 Thread Jianjian Guan via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9c11e9528683: [Clang][RISCV] Fix upper bound of RISC-V V 
type in debug info (authored by jacquesguan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115430/new/

https://reviews.llvm.org/D115430

Files:
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/test/CodeGen/RISCV/riscv-v-debuginfo.c


Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -9,7 +9,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, 
DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t 
arg_2) {
   __rvv_int16mf2_t ret;
@@ -17,7 +17,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, 
DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t 
arg_2) {
   __rvv_int32mf2_t ret;
@@ -25,4 +25,4 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, 
DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, 
DW_OP_minus))
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -768,7 +768,7 @@
   }
 
   // Element count = (VLENB / SEW) x LMUL
-  SmallVector Expr(
+  SmallVector Expr(
   // The DW_OP_bregx operation has two operands: a register which is
   // specified by an unsigned LEB128 number, followed by a signed 
LEB128
   // offset.
@@ -782,6 +782,8 @@
 Expr.push_back(llvm::dwarf::DW_OP_div);
   else
 Expr.push_back(llvm::dwarf::DW_OP_mul);
+  // Element max index = count - 1
+  Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
   auto *LowerBound =
   llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(


Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===
--- clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -9,7 +9,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) {
   __rvv_int16mf2_t ret;
@@ -17,7 +17,7 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
 
 __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) {
   __rvv_int32mf2_t ret;
@@ -25,4 +25,4 @@
 }
 
 // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
-// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus))
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -768,7 +768,7 @@
   }
 
   // Element count = (VLENB / SEW) x LMUL
-  SmallVector Expr(
+  SmallVector Expr(
   // The DW_OP_bregx operation has two operands: a register which is
   // specified by an unsigned LEB128 number, followed by a signed LEB128
   // offset.
@@ -782,6 +782,8 @@
 Expr.push_back(llvm::dwarf::DW_OP_div);
   else
 Expr.push_back(llvm::dwarf::DW_OP_mul);
+  // Element max index = count - 1
+  Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus});
 
   auto *LowerBound =
   llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info

2021-12-19 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

Sorry, I should use --author="Luhaocong " in my 
git command, and I will pay attention next time to land revision that created 
by other one.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115430/new/

https://reviews.llvm.org/D115430

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

2021-12-21 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan added a comment.

Ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D111597: [RISCV][Clang] Fix RISCV vector header comment.

2021-10-11 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan created this revision.
jacquesguan added reviewers: HsiangKai, khchen, craig.topper.
Herald added subscribers: achieveartificialintelligence, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb.
jacquesguan requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

Fix wrong comment for macro endif.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111597

Files:
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1035,7 +1035,7 @@
 
   OS << "\n#ifdef __cplusplus\n";
   OS << "}\n";
-  OS << "#endif // __riscv_vector\n";
+  OS << "#endif // __cplusplus\n";
   OS << "#endif // __RISCV_VECTOR_H\n";
 }
 


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1035,7 +1035,7 @@
 
   OS << "\n#ifdef __cplusplus\n";
   OS << "}\n";
-  OS << "#endif // __riscv_vector\n";
+  OS << "#endif // __cplusplus\n";
   OS << "#endif // __RISCV_VECTOR_H\n";
 }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits