jacquesguan updated this revision to Diff 527312.
jacquesguan added a comment.
Update dependency.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150253/new/
https://reviews.llvm.org/D150253
Files:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
clang/test/Sema/riscv-vector-float16-check.c
clang/utils/TableGen/RISCVVEmitter.cpp
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===================================================================
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
.Case("RV64", RVV_REQ_RV64)
.Case("FullMultiply", RVV_REQ_FullMultiply)
+ .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
.Case("Xsfvcp", RVV_REQ_Xsfvcp)
.Default(RVV_REQ_None);
assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/Sema/riscv-vector-float16-check.c
===================================================================
--- clang/test/Sema/riscv-vector-float16-check.c
+++ clang/test/Sema/riscv-vector-float16-check.c
@@ -4,5 +4,5 @@
// REQUIRES: riscv-registered-target
#include <riscv_vector.h>
-vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh' extension}} */
+vfloat16m1_t foo() { /* expected-error {{RISC-V type 'vfloat16m1_t' (aka '__rvv_float16m1_t') requires the 'zvfh or zvfhmin' extension}} */
} /* expected-warning {{non-void function does not return a value}}*/
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -target-feature +experimental-zvfhmin -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include <riscv_vector.h>
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+ return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT: ret <vscale x 4 x float> [[TMP0]]
+//
+vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
+ return __riscv_vfwcvt_f(src, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
@@ -0,0 +1,24 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-ZVF %s
+
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -target-feature +experimental-zvfhmin -emit-llvm-only %s 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CHECK-ZVFHMIN-ERR
+
+#include <riscv_vector.h>
+
+// CHECK-ZVF-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-ZVF-NEXT: entry:
+// CHECK-ZVF-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVF-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+
+// CHECK-ZVFHMIN-ERR: no matching function for call to '__riscv_vfadd'
+
+vfloat16m1_t test_vfadd_vv_f16m1(vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+ return __riscv_vfadd(op1, op2, vl);
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===================================================================
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -195,6 +195,8 @@
const TargetInfo &TI = Context.getTargetInfo();
bool HasRV64 = TI.hasFeature("64bit");
bool HasFullMultiply = TI.hasFeature("v");
+ bool HasZvfh = TI.hasFeature("experimental-zvfh");
+ bool HasZvfhminOrZvfh = TI.hasFeature("experimental-zvfhmin") || HasZvfh;
auto ConstructRVVIntrinsics = [&](ArrayRef<RVVIntrinsicRecord> Recs,
IntrinsicKind K) {
@@ -257,6 +259,16 @@
!HasFullMultiply)
continue;
+ if (BaseType == BasicType::Float16) {
+ if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) ==
+ RVV_REQ_ZvfhminOrZvfh) {
+ if (!HasZvfhminOrZvfh)
+ continue;
+ } else if (!HasZvfh) {
+ continue;
+ }
+ }
+
// Expanded with different LMUL.
for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
Index: clang/lib/Sema/Sema.cpp
===================================================================
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2044,9 +2044,10 @@
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
- !TI.hasFeature("experimental-zvfh"))
+ !TI.hasFeature("experimental-zvfh") &&
+ !TI.hasFeature("experimental-zvfhmin"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD)
- << Ty << "zvfh";
+ << Ty << "zvfh or zvfhmin";
if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve32f";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===================================================================
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -470,7 +470,8 @@
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_FullMultiply = 1 << 1,
- RVV_REQ_Xsfvcp = 1 << 2,
+ RVV_REQ_ZvfhminOrZvfh = 1 << 2,
+ RVV_REQ_Xsfvcp = 1 << 3,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
};
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -2215,7 +2215,13 @@
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
- def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+ def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+ def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
+ let Name = "vfwcvt_f_f_v";
+ let IRName = "vfwcvt_f_f_v";
+ let MaskedIRName = "vfwcvt_f_f_v_mask";
+ }
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -2226,7 +2232,13 @@
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">;
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
- def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
+ def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "f", "vfncvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+ def vfncvt_f_f_w_fp16 : RVVConvBuiltin<"v", "vw", "x", "vfncvt_f"> {
+ let Name = "vfncvt_f_f_w";
+ let IRName = "vfncvt_f_f_w";
+ let MaskedIRName = "vfncvt_f_f_w_mask";
+ }
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
}
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