jacquesguan updated this revision to Diff 523696.
jacquesguan added a comment.
Fix indention.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150253/new/
https://reviews.llvm.org/D150253
Files:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfadd.ll
llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
Index: llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
@@ -3,6 +3,10 @@
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(
<vscale x 1 x float>,
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v,+m -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 2 x half> @llvm.vp.fptrunc.nxv2f16.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
Index: llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
@@ -3,6 +3,10 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) {
;
Index: llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
Index: llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
@@ -3,6 +3,10 @@
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x float> @vfpext_nxv1f16_nxv1f32(<vscale x 1 x half> %va) {
;
Index: llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
@@ -3,6 +3,10 @@
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(
<vscale x 1 x half>,
<vscale x 1 x float>,
Index: llvm/test/CodeGen/RISCV/rvv/vfadd.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vfadd.ll
+++ llvm/test/CodeGen/RISCV/rvv/vfadd.ll
@@ -7,6 +7,13 @@
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN: -target-abi=ilp32d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN
+; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfhmin \
+; RUN: -target-abi=lp64d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN
+
+; ZVFMIN: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfadd
+
declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
<vscale x 1 x half>,
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
@@ -1,6 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+
declare <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float>, <2 x i1>, i32)
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfhmin,+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
declare <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half>, <2 x i1>, i32)
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -158,6 +158,9 @@
// Vector codegen related methods.
bool hasVInstructions() const { return HasStdExtZve32x; }
bool hasVInstructionsI64() const { return HasStdExtZve64x; }
+ bool hasVInstructionsF16Mininal() const {
+ return HasStdExtZvfhmin || HasStdExtZvfh;
+ }
bool hasVInstructionsF16() const { return HasStdExtZvfh; }
// FIXME: Consider Zfinx in the future
bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2150,8 +2150,9 @@
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
- GetVTypePredicates<fwti>.Predicates) in
+ let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Mininal],
+ !listconcat(GetVTypePredicates<fvti>.Predicates,
+ GetVTypePredicates<fwti>.Predicates)) in
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
(fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
@@ -2179,22 +2180,25 @@
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
- GetVTypePredicates<fwti>.Predicates) in {
- def : Pat<(fvti.Vector (any_riscv_fpround_vl
- (fwti.Vector fwti.RegClass:$rs1),
- (fwti.Mask V0), VLOpFrag)),
- (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK")
- (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
- (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
+ // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
+ let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Mininal],
+ !listconcat(GetVTypePredicates<fvti>.Predicates,
+ GetVTypePredicates<fwti>.Predicates)) in
+ def : Pat<(fvti.Vector (any_riscv_fpround_vl
+ (fwti.Vector fwti.RegClass:$rs1),
+ (fwti.Mask V0), VLOpFrag)),
+ (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK")
+ (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
+ (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
+ let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
+ GetVTypePredicates<fwti>.Predicates) in
def : Pat<(fvti.Vector (any_riscv_fncvt_rod_vl
(fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask V0), VLOpFrag)),
(!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK")
(fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
(fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TA_MA)>;
- }
}
// 14. Vector Reduction Operations
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1185,8 +1185,9 @@
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
- GetVTypePredicates<fwti>.Predicates) in
+ let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Mininal],
+ !listconcat(GetVTypePredicates<fvti>.Predicates,
+ GetVTypePredicates<fwti>.Predicates)) in
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
fwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -5416,11 +5416,13 @@
{
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
- GetVTypePredicates<fwti>.Predicates) in
- defm : VPatConversionTA<intrinsic, instruction, "V",
- fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
- fvti.LMul, fwti.RegClass, fvti.RegClass>;
+ // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
+ let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Mininal],
+ !listconcat(GetVTypePredicates<fvti>.Predicates,
+ GetVTypePredicates<fwti>.Predicates)) in
+ defm : VPatConversionTA<intrinsic, instruction, "V",
+ fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
+ fvti.LMul, fwti.RegClass, fvti.RegClass>;
}
}
@@ -5450,8 +5452,9 @@
}
}
-multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
- foreach fvtiToFWti = AllWidenableFloatVectors in
+multiclass VPatConversionVF_WF <string intrinsic, string instruction,
+ list<VTypeInfoToWide> wlist = AllWidenableFloatVectors> {
+ foreach fvtiToFWti = wlist in
{
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
@@ -6677,7 +6680,16 @@
defm : VPatConversionVI_WF<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F">;
defm : VPatConversionVF_WI <"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU">;
defm : VPatConversionVF_WI <"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X">;
-defm : VPatConversionVF_WF<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F">;
+defvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors,
+ !ne(fvtiToFWti.Vti.Scalar, f16));
+defm : VPatConversionVF_WF<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
+ WidenableFloatVectorsExceptF16>;
+// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
+defvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors,
+ !eq(fvtiToFWti.Vti.Scalar, f16));
+let Predicates = [HasVInstructionsF16Mininal] in
+defm : VPatConversionVF_WF<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
+ F16WidenableFloatVectors>;
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F">;
//===----------------------------------------------------------------------===//
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -179,7 +179,7 @@
addRegClassForRVV(VT);
}
- if (Subtarget.hasVInstructionsF16())
+ if (Subtarget.hasVInstructionsF16Mininal())
for (MVT VT : F16VecVTs)
addRegClassForRVV(VT);
@@ -852,6 +852,12 @@
continue;
SetCommonVFPActions(VT);
}
+ } else if (Subtarget.hasVInstructionsF16Mininal()) {
+ for (MVT VT : F16VecVTs) {
+ setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
+ setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
+ // TODO: make others promote?
+ }
}
if (Subtarget.hasVInstructionsF32()) {
@@ -1009,6 +1015,14 @@
if (!useRVVForFixedLengthVectorVT(VT))
continue;
+ if (VT.getVectorElementType() == MVT::f16 &&
+ !Subtarget.hasVInstructionsF16()) {
+ setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
+ setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
+ // TODO: make others promote?
+ continue;
+ }
+
// By default everything must be expanded.
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op)
setOperationAction(Op, VT, Expand);
@@ -2079,7 +2093,7 @@
case MVT::i64:
return Subtarget.hasVInstructionsI64();
case MVT::f16:
- return Subtarget.hasVInstructionsF16();
+ return Subtarget.hasVInstructionsF16Mininal();
case MVT::f32:
return Subtarget.hasVInstructionsF32();
case MVT::f64:
@@ -2144,7 +2158,7 @@
return false;
break;
case MVT::f16:
- if (!Subtarget.hasVInstructionsF16())
+ if (!Subtarget.hasVInstructionsF16Mininal())
return false;
break;
case MVT::f32:
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -456,8 +456,18 @@
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
+def FeatureStdExtZvfhmin
+ : SubtargetFeature<"experimental-zvfhmin", "HasStdExtZvfhmin", "true",
+ "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
+ [FeatureStdExtZve32f]>;
+
def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
+def HasVInstructionsF16Mininal : Predicate<"Subtarget->hasVInstructionsF16Mininal()">,
+ AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
+ "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
+ "'Zvfh' (Vector Half-Precision Floating-Point)">;
+
def HasStdExtZfhOrZvfh
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -149,6 +149,7 @@
{"zfa", RISCVExtensionVersion{0, 2}},
{"zicond", RISCVExtensionVersion{1, 0}},
{"zvfh", RISCVExtensionVersion{0, 1}},
+ {"zvfhmin", RISCVExtensionVersion{0, 1}},
{"ztso", RISCVExtensionVersion{0, 1}},
// vector crypto
@@ -937,6 +938,7 @@
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
+static const char *ImpliedExtsZvfhmin[] = {"zve32f"};
static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
"zvkt"};
static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
@@ -995,6 +997,7 @@
{{"zve64f"}, {ImpliedExtsZve64f}},
{{"zve64x"}, {ImpliedExtsZve64x}},
{{"zvfh"}, {ImpliedExtsZvfh}},
+ {{"zvfhmin"}, {ImpliedExtsZvfhmin}},
{{"zvkn"}, {ImpliedExtsZvkn}},
{{"zvkng"}, {ImpliedExtsZvkng}},
{{"zvknhb"}, {ImpliedExtsZvknhb}},
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===================================================================
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
RVVRequire RequireExt = StringSwitch<RVVRequire>(RequiredFeature)
.Case("RV64", RVV_REQ_RV64)
.Case("FullMultiply", RVV_REQ_FullMultiply)
+ .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
.Case("Xsfvcp", RVV_REQ_Xsfvcp)
.Default(RVV_REQ_None);
assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -target-feature +experimental-zvfhmin -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-ZVFHMIN %s
+
+#include <riscv_vector.h>
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfncvt_f_f_w_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32.i64(<vscale x 4 x half> poison, <vscale x 4 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+vfloat16m1_t test_vfncvt_f_f_w_f16m1(vfloat32m2_t src, size_t vl) {
+ return __riscv_vfncvt_f(src, vl);
+}
+
+
+// CHECK-ZVFHMIN-LABEL: @test_vfwcvt_f_f_v_f16m1(
+// CHECK-ZVFHMIN-NEXT: entry:
+// CHECK-ZVFHMIN-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16.i64(<vscale x 4 x float> poison, <vscale x 4 x half> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVFHMIN-NEXT: ret <vscale x 4 x float> [[TMP0]]
+//
+vfloat32m2_t test_vfwcvt_f_f_v_f16m1(vfloat16m1_t src, size_t vl) {
+ return __riscv_vfwcvt_f(src, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-ZVF %s
+
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN: -target-feature +experimental-zvfhmin -emit-llvm-only %s 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CHECK-ZVFHMIN-ERR
+
+#include <riscv_vector.h>
+
+
+
+
+// CHECK-ZVF-LABEL: @test_vfadd_vv_f16m1(
+// CHECK-ZVF-NEXT: entry:
+// CHECK-ZVF-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> poison, <vscale x 4 x half> [[OP1:%.*]], <vscale x 4 x half> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-ZVF-NEXT: ret <vscale x 4 x half> [[TMP0]]
+//
+
+// CHECK-ZVFHMIN-ERR: no matching function for call to '__riscv_vfadd'
+
+vfloat16m1_t test_vfadd_vv_f16m1(vfloat16m1_t op1, vfloat16m1_t op2, size_t vl) {
+ return __riscv_vfadd(op1, op2, vl);
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===================================================================
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -191,6 +191,9 @@
const TargetInfo &TI = Context.getTargetInfo();
bool HasRV64 = TI.hasFeature("64bit");
bool HasFullMultiply = TI.hasFeature("v");
+ bool HasZvfh = TI.hasFeature("experimental-zvfh");
+ bool HasZvfhminOrZvfh = TI.hasFeature("experimental-zvfhmin") ||
+ TI.hasFeature("experimental-zvfh");
auto ConstructRVVIntrinsics = [&](ArrayRef<RVVIntrinsicRecord> Recs,
IntrinsicKind K) {
@@ -252,6 +255,16 @@
!HasFullMultiply)
continue;
+ if (BaseType == BasicType::Float16) {
+ if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) ==
+ RVV_REQ_ZvfhminOrZvfh) {
+ if (!HasZvfhminOrZvfh)
+ continue;
+ } else if (!HasZvfh) {
+ continue;
+ }
+ }
+
// Expanded with different LMUL.
for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
Index: clang/lib/Sema/Sema.cpp
===================================================================
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -2044,9 +2044,9 @@
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
- !TI.hasFeature("experimental-zvfh"))
- Diag(Loc, diag::err_riscv_type_requires_extension, FD)
- << Ty << "zvfh";
+ !TI.hasFeature("experimental-zvfh") &&
+ !TI.hasFeature("experimental-zvfhmin"))
+ Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zvfh";
if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve32f";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===================================================================
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -462,7 +462,8 @@
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_FullMultiply = 1 << 1,
- RVV_REQ_Xsfvcp = 1 << 2,
+ RVV_REQ_ZvfhminOrZvfh = 1 << 2,
+ RVV_REQ_Xsfvcp = 1 << 3,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
};
Index: clang/include/clang/Basic/riscv_vector.td
===================================================================
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1853,7 +1853,8 @@
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
- def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+ def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -1864,7 +1865,8 @@
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">;
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
- def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+ def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
}
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