[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/102285
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc created 
https://github.com/llvm/llvm-project/pull/95427

Syntacore SCR3 is a microcontroller-class processor core. Overview: 
https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

>From 1449d6ba48779051f19dcf9160aaa40599e2750e Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Fri, 31 May 2024 16:10:28 +0300
Subject: [PATCH] [RISCV] Add scheduling model for Syntacore SCR3

Syntacore SCR3 is a microcontroller-class processor core.
Overview: https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

Co-authored-by: Dmitrii Petrov 
---
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCV.td|   1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  21 ++
 .../Target/RISCV/RISCVSchedSyntacoreSCR3.td   | 266 ++
 .../RISCV/SyntacoreSCR/SCR3-dmaadmaa.s|  91 ++
 .../llvm-mca/RISCV/SyntacoreSCR/SCR3-.s   |  57 
 6 files changed, 440 insertions(+), 4 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-dmaadmaa.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-.s

diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 5362c6f882c25..90dbd3ef37342 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, syntacore-scr3-rv64, veyron-v1, 
xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, 
sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, syntacore-scr3-rv64, 
veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 09f496574d64a..d96fafbe60807 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -51,6 +51,7 @@ include "RISCVSchedSiFive7.td"
 include "RISCVSchedSiFiveP400.td"
 include "RISCVSchedSiFiveP600.td"
 include "RISCVSchedSyntacoreSCR1.td"
+include "RISCVSchedSyntacoreSCR3.td"
 include "RISCVSchedXiangShanNanHu.td"
 
 
//===--===//
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..822af1c6dcbbc 100644
--- a/llvm/lib/Target/RISCV/RI

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc updated 
https://github.com/llvm/llvm-project/pull/95427

>From 1449d6ba48779051f19dcf9160aaa40599e2750e Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Fri, 31 May 2024 16:10:28 +0300
Subject: [PATCH 1/2] [RISCV] Add scheduling model for Syntacore SCR3

Syntacore SCR3 is a microcontroller-class processor core.
Overview: https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

Co-authored-by: Dmitrii Petrov 
---
 clang/test/Misc/target-invalid-cpu-note.c |   8 +-
 llvm/lib/Target/RISCV/RISCV.td|   1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  |  21 ++
 .../Target/RISCV/RISCVSchedSyntacoreSCR3.td   | 266 ++
 .../RISCV/SyntacoreSCR/SCR3-dmaadmaa.s|  91 ++
 .../llvm-mca/RISCV/SyntacoreSCR/SCR3-.s   |  57 
 6 files changed, 440 insertions(+), 4 deletions(-)
 create mode 100644 llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR3.td
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-dmaadmaa.s
 create mode 100644 llvm/test/tools/llvm-mca/RISCV/SyntacoreSCR/SCR3-.s

diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 5362c6f882c25..90dbd3ef37342 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, syntacore-scr3-rv64, veyron-v1, 
xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, 
sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, 
generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, syntacore-scr3-rv64, 
veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 09f496574d64a..d96fafbe60807 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -51,6 +51,7 @@ include "RISCVSchedSiFive7.td"
 include "RISCVSchedSiFiveP400.td"
 include "RISCVSchedSiFiveP600.td"
 include "RISCVSchedSyntacoreSCR1.td"
+include "RISCVSchedSyntacoreSCR3.td"
 include "RISCVSchedXiangShanNanHu.td"
 
 
//===--===//
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb0452..822af1c6dcbbc 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : 
RISCVProcessorModel<"syntacore-scr1-max",
   FeatureStdExtC],
 

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Anton Sidorenko via cfe-commits]

asi-sc wrote:

It'd be great if someone outside of Syntacore would have a quick look at this 
patch too.

https://github.com/llvm/llvm-project/pull/95427
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Anton Sidorenko via cfe-commits]

@@ -0,0 +1,266 @@
+//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- 
tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+
+// This model covers SYNTACORE_SCR3_RV32IMC and SYNTACORE_RV64IMAC
+// configurations (syntacore-scr3-rv32/64).
+// Overview: https://syntacore.com/products/scr3
+
+// SCR3 is single-issue in-order processor
+class SyntacoreSCR3Model : SchedMachineModel {
+  let MicroOpBufferSize = 0;
+  let IssueWidth = 1;
+  let LoadLatency = 2;
+  let MispredictPenalty = 3;
+  let CompleteModel = 0;
+  let UnsupportedFeatures = [HasStdExtD, HasStdExtZbkb, HasStdExtZbkc, 
HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVInstructions];
+}
+
+// Branching
+multiclass SCR3_Branching {
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+}
+
+// Single-cycle integer arithmetic and logic
+multiclass SCR3_IntALU {
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+  def : WriteRes;
+}
+
+// Integer multiplication
+multiclass SCR3_IntMul {
+  let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Integer division
+multiclass SCR3_IntDiv {
+  let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Load/store instructions on SCR3 have latency 2
+multiclass SCR3_Memory {
+  let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Atomic memory
+multiclass SCR3_AtomicMemory {
+  let Latency = 20 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+  }
+}
+
+// Others
+multiclass SCR3_Other {
+  def : WriteRes;
+  def : WriteRes;
+
+  def : InstRW<[WriteIALU], (instrs COPY)>;
+}
+
+
+multiclass SCR3_Unsupported {
+  defm : UnsupportedSchedSFB;
+  defm : UnsupportedSchedV;
+  defm : UnsupportedSchedXsfvcp;
+  defm : UnsupportedSchedZabha;
+  defm : UnsupportedSchedZba;
+  defm : UnsupportedSchedZbb;
+  defm : UnsupportedSchedZbc;
+  defm : UnsupportedSchedZbs;
+  defm : UnsupportedSchedZbkb;
+  defm : UnsupportedSchedZbkx;
+  defm : UnsupportedSchedZfa;
+  defm : UnsupportedSchedZfh;
+  defm : UnsupportedSchedZvk;
+
+  let Unsupported = true in {

asi-sc wrote:

Created https://github.com/llvm/llvm-project/pull/95948 to introduce these 
classes.

https://github.com/llvm/llvm-project/pull/95427
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc created 
https://github.com/llvm/llvm-project/pull/95953

Syntacore SCR3 is a microcontroller-class processor core. Overview: 
https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

>From 75c4b0d1deb57fb22f9b2446aa8b368c662c38b8 Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Tue, 18 Jun 2024 19:40:54 +0300
Subject: [PATCH] [RISCV] Add Syntacore SCR3 processor definition

Syntacore SCR3 is a microcontroller-class processor core.
Overview: https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

Co-authored-by: Dmitrii Petrov 
---
 clang/test/Driver/riscv-cpus.c| 18 ++
 clang/test/Misc/target-invalid-cpu-note.c |  8 
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 21 +
 4 files changed, 44 insertions(+), 4 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 41c257bc559ed..e809cbb32fea2 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
+// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv64 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV64 %s
+// MCPU-SYNTACORE-SCR3-RV64: "-target-cpu" "syntacore-scr3-rv64"
+// MCPU-SYNTACORE-SCR3-RV64: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV64: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV64: "-target-abi" "lp64"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s
+// MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 59d3aaa122dbe..1a9063ee5a257 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, 
xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, 
sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-on

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc updated 
https://github.com/llvm/llvm-project/pull/95953

>From 75c4b0d1deb57fb22f9b2446aa8b368c662c38b8 Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Tue, 18 Jun 2024 19:40:54 +0300
Subject: [PATCH 1/2] [RISCV] Add Syntacore SCR3 processor definition

Syntacore SCR3 is a microcontroller-class processor core.
Overview: https://syntacore.com/products/scr3
This PR introduces two CPUs:
  * 'syntacore-scr3-rv32' which is rv32imc
  * 'syntacore-scr3-rv64' which is rv64imac

Co-authored-by: Dmitrii Petrov 
---
 clang/test/Driver/riscv-cpus.c| 18 ++
 clang/test/Misc/target-invalid-cpu-note.c |  8 
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 21 +
 4 files changed, 44 insertions(+), 4 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 41c257bc559ed..e809cbb32fea2 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
+// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv64 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV64 %s
+// MCPU-SYNTACORE-SCR3-RV64: "-target-cpu" "syntacore-scr3-rv64"
+// MCPU-SYNTACORE-SCR3-RV64: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV64: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV64: "-target-abi" "lp64"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s
+// MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 59d3aaa122dbe..1a9063ee5a257 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, 
xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, 
sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, 
sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, 
rocket-rv64, sifive-p450, sifive-p

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Anton Sidorenko via cfe-commits]

@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"

asi-sc wrote:

Addressed.

https://github.com/llvm/llvm-project/pull/95953
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Anton Sidorenko via cfe-commits]

@@ -358,3 +358,21 @@
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 
-march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
+// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-feature" "+zicsr" "-target-feature" 
"+zifencei"
+// MCPU-SYNTACORE-SCR3-RV32: "-target-abi" "ilp32"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
+// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"

asi-sc wrote:

This just copies the checks many processors do (rocket, veyron, 
xiangshan-nanhu, etc)

https://github.com/llvm/llvm-project/pull/95953
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR3 processor definition (PR #95953)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed https://github.com/llvm/llvm-project/pull/95953
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc created 
https://github.com/llvm/llvm-project/pull/101321

Syntacore SCR4 is a microcontroller-class processor core that has much in 
common with SCR3. The most significant difference for compilers is F and D 
extensions support. Overview: https://syntacore.com/products/scr4

Two CPUs are added:
  * 'syntacore-scr4-rv32' -- rv32imfdc
  * 'syntacore-scr4-rv64' -- rv64imafdc

Scheduling model will be added in a separate PR.
-

>From 833727a9f23fff71695f4d2a5e7ee3e58ab5449a Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Wed, 3 Jul 2024 19:31:47 +0300
Subject: [PATCH] [RISCV] Add Syntacore SCR4 RV32/64 processors definition

Syntacore SCR4 is a microcontroller-class processor core that has much in common
with SCR3. The most significant difference for compilers is F and D extensions
support. Overview: https://syntacore.com/products/scr4

Two CPUs are added:
  * 'syntacore-scr4-rv32' -- rv32imfdc
  * 'syntacore-scr4-rv64' -- rv64imafdc

-

Co-authored-by: Dmitrii Petrov 
Co-authored-by: Anton Afanasyev 
---
 clang/test/Driver/riscv-cpus.c| 27 +++
 clang/test/Misc/target-invalid-cpu-note.c |  8 +++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 25 +
 4 files changed, 57 insertions(+), 4 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 26bcda6468dd2..7a885cde76d6a 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -381,3 +381,30 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s
 // MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr4-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR4-RV32 %s
+// MCPU-SYNTACORE-SCR4-RV32: "-target-cpu" "syntacore-scr4-rv32"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR4-RV32-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr4-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV32 %s
+// MTUNE-SYNTACORE-SCR4-RV32: "-tune-cpu" "syntacore-scr4-rv32"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr4-rv64 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR4-RV64 %s
+// MCPU-SYNTACORE-SCR4-RV64: "-target-cpu" "syntacore-scr4-rv64"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR4-RV64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr4-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV64 %s
+// MTUNE-SYNTACORE-SCR4-RV64: "-tune-cpu" "syntacore-scr4-rv64"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index e0757b69242a8..b87bced18cb2b 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
syntacore-scr4-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc edited 
https://github.com/llvm/llvm-project/pull/101321
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Anton Sidorenko via cfe-commits]

@@ -106,6 +106,7 @@ Changes to the RISC-V Backend
 * `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
   the required alignment space with a sequence of `0x0` bytes (the requested
   fill value) rather than NOPs.
+* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``

asi-sc wrote:

Hm, actually not sure. It looks like a change to RISC-V backend (which is 
propagated to the driver) and previously we mentioned such changes in llvm 
release notes e.g. 
https://github.com/llvm/llvm-project/blob/release/18.x/llvm/docs/ReleaseNotes.rst#changes-to-the-risc-v-backend
 or 
https://github.com/llvm/llvm-project/blob/release/19.x/llvm/docs/ReleaseNotes.rst#changes-to-the-risc-v-backend
 .  Although I don't have a strong opinion on this matter.

https://github.com/llvm/llvm-project/pull/101321
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR4 RV32/64 processors definition (PR #101321)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/101321
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc created 
https://github.com/llvm/llvm-project/pull/102285

Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V processor core.
Overview: https://syntacore.com/products/scr5

Scheduling model will be added in a subsequent PR.

Co-authored-by: Dmitrii Petrov 
Co-authored-by: Anton Afanasyev 

>From 4c433796397d7393aefba63489d3e915949b172a Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Thu, 4 Jul 2024 18:09:26 +0300
Subject: [PATCH] [RISCV] Add Syntacore SCR5 RV32/64 processors definition

Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V processor core.
Overview: https://syntacore.com/products/scr5

Co-authored-by: Dmitrii Petrov 
Co-authored-by: Anton Afanasyev 
---
 clang/test/Driver/riscv-cpus.c| 28 +++
 clang/test/Misc/target-invalid-cpu-note.c |  8 +++
 llvm/docs/ReleaseNotes.rst|  2 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 26 +
 4 files changed, 59 insertions(+), 5 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 7a885cde76d6ae..29b646fcf300ad 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -408,3 +408,31 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr4-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV64 %s
 // MTUNE-SYNTACORE-SCR4-RV64: "-tune-cpu" "syntacore-scr4-rv64"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV32 %s
+// MCPU-SYNTACORE-SCR5-RV32: "-target-cpu" "syntacore-scr5-rv32"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr5-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV32 %s
+// MTUNE-SYNTACORE-SCR5-RV32: "-tune-cpu" "syntacore-scr5-rv32"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV64 %s
+// MCPU-SYNTACORE-SCR5-RV64: "-target-cpu" "syntacore-scr5-rv64"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
+// MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index b87bced18cb2b4..77f781a1f9415e 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,16 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
syntacore-scr4-rv32{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
syntacore-scr4-rv32, syntacore-scr5-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, 
sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, 
syntacore-scr4-rv64, syntacore-scr5-rv64, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --ch

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

[Anton Sidorenko via cfe-commits]

@@ -378,6 +378,32 @@ def SYNTACORE_SCR4_RV64 : 
RISCVProcessorModel<"syntacore-scr4-rv64",
FeatureStdExtC],
   [TuneNoDefaultUnroll, 
FeaturePostRAScheduler]>;
 
+def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
+  NoSchedModel,
+  [Feature32Bit,
+   FeatureStdExtI,
+   FeatureStdExtZicsr,
+   FeatureStdExtZifencei,
+   FeatureStdExtM,
+   FeatureStdExtA,

asi-sc wrote:

> The documentation says A and F are both optional

SCR5 is a highly configurable core, but we'd like to support the default 
configuration in the compiler which has A, F, D extensions.

> It is weird to me because D always depends on F.

Thanks for noticing, it's a typo. I'll report it. 


https://github.com/llvm/llvm-project/pull/102285
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] full support for riscv_rvv_vector_bits attribute (PR #100110)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/100110
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc updated 
https://github.com/llvm/llvm-project/pull/102285

>From aeae8cfd59de3e0898e3e70882dc1ef566d6f021 Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Thu, 4 Jul 2024 18:09:26 +0300
Subject: [PATCH] [RISCV] Add Syntacore SCR5 RV32/64 processors definition

Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V processor core.
Overview: https://syntacore.com/products/scr5

Co-authored-by: Dmitrii Petrov 
Co-authored-by: Anton Afanasyev 
---
 clang/test/Driver/riscv-cpus.c| 28 +++
 clang/test/Misc/target-invalid-cpu-note.c |  9 
 llvm/docs/ReleaseNotes.rst|  2 +-
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 26 +
 4 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 29687ac4e1c83e..2fa5b1753745f8 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -459,3 +459,31 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr4-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV64 %s
 // MTUNE-SYNTACORE-SCR4-RV64: "-tune-cpu" "syntacore-scr4-rv64"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv32 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV32 %s
+// MCPU-SYNTACORE-SCR5-RV32: "-target-cpu" "syntacore-scr5-rv32"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-abi" "ilp32d"
+
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr5-rv32 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV32 %s
+// MTUNE-SYNTACORE-SCR5-RV32: "-tune-cpu" "syntacore-scr5-rv32"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV64 %s
+// MCPU-SYNTACORE-SCR5-RV64: "-target-cpu" "syntacore-scr5-rv64"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
+// MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 249bea2311549f..b1783f3917a350 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -81,17 +81,16 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
syntacore-scr4-rv32{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, 
syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, 
syntacore-scr4-rv32, syntacore-scr5-rv32{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, 
sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, 
syntacore-scr3-rv64, syntacore-scr4-rv64, syntacore-scr5-rv64, veyron-v1, 
xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, 
rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sif

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc created 
https://github.com/llvm/llvm-project/pull/108406

Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core.
The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march.
Overview: https://syntacore.com/products/scr7

Scheduling model will be added in a subsequent PR.

>From 0c2925d18e8e4312a16d081c1c97d3298b85e8d4 Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Mon, 2 Sep 2024 13:25:39 +0300
Subject: [PATCH] [RISCV] Add Syntacore SCR7 processor definition

Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core.
The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march.
Overview: https://syntacore.com/products/scr7

Scheduling model will be added in a subsequent PR.

Co-authored-by: Dmitrii Petrov 
Co-authored-by: Anton Afanasyev 
Co-authored-by: Elena Lepilkina 
---
 clang/test/Driver/riscv-cpus.c| 25 +++
 .../test/Misc/target-invalid-cpu-note/riscv.c |  2 ++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 19 ++
 4 files changed, 47 insertions(+)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 481eaae9153e86..79256e402c0b74 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -502,3 +502,28 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
 // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr7 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR7 %s
+// MCPU-SYNTACORE-SCR7: "-target-cpu" "syntacore-scr7"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
+// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 96d3cefd434d78..7bbf3574af3c35 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -40,6 +40,7 @@
 // RISCV64-SAME: {{^}}, syntacore-scr3-rv64
 // RISCV64-SAME: {{^}}, syntacore-scr4-rv64
 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64
+// RISCV64-SAME: {{^}}, syntacore-scr7
 // RISCV64-SAME: {{^}}, veyron-v1
 // RISCV64-SAME: {{^}}, xiangshan-nanhu
 // RISCV64-SAME: {{$}}
@@ -85,6 +86,7 @@
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
+// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
 // TUNE-RISCV64-SAME: {{^}}, generic
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 52456896f2fc6c..6df4c37b092432 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -123,6 +123,7 @@ Changes to the RISC-V Backend
   largely untested.
 * The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
 * Added ``Smctr`` and ``Ssctr`` extensions.
+* ``-mcpu=syntacore-scr7`` was added.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index d4ec5ecc6489c1..c4e1a1457e8d30 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -383,6 +383,25 @@ def SYNTACORE_SCR5_RV64 : 
RISCVProcessorModel<"syntacore-scr5-rv64",
FeatureStdExtC],
   [TuneNoDefaultUnroll, 
FeaturePostRAScheduler]>;
 
+def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
+  NoSchedModel,
+  [Feature64Bit,
+

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

[Anton Sidorenko via cfe-commits]

@@ -502,3 +502,28 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
 // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr7 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR7 %s
+// MCPU-SYNTACORE-SCR7: "-target-cpu" "syntacore-scr7"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-abi" "lp64d"

asi-sc wrote:

Thanks for catching this! Addressed.

https://github.com/llvm/llvm-project/pull/108406
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc updated 
https://github.com/llvm/llvm-project/pull/108406

>From 0c2925d18e8e4312a16d081c1c97d3298b85e8d4 Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Mon, 2 Sep 2024 13:25:39 +0300
Subject: [PATCH 1/2] [RISCV] Add Syntacore SCR7 processor definition

Syntacore SCR7 is a high-performance Linux-capable RISC-V processor core.
The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march.
Overview: https://syntacore.com/products/scr7

Scheduling model will be added in a subsequent PR.

Co-authored-by: Dmitrii Petrov 
Co-authored-by: Anton Afanasyev 
Co-authored-by: Elena Lepilkina 
---
 clang/test/Driver/riscv-cpus.c| 25 +++
 .../test/Misc/target-invalid-cpu-note/riscv.c |  2 ++
 llvm/docs/ReleaseNotes.rst|  1 +
 llvm/lib/Target/RISCV/RISCVProcessors.td  | 19 ++
 4 files changed, 47 insertions(+)

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 481eaae9153e86..79256e402c0b74 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -502,3 +502,28 @@
 
 // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
 // MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr7 | 
FileCheck -check-prefix=MCPU-SYNTACORE-SCR7 %s
+// MCPU-SYNTACORE-SCR7: "-target-cpu" "syntacore-scr7"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh"
+// MCPU-SYNTACORE-SCR7-SAME: "-target-abi" "lp64d"
+
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | 
FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
+// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c 
b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 96d3cefd434d78..7bbf3574af3c35 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -40,6 +40,7 @@
 // RISCV64-SAME: {{^}}, syntacore-scr3-rv64
 // RISCV64-SAME: {{^}}, syntacore-scr4-rv64
 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64
+// RISCV64-SAME: {{^}}, syntacore-scr7
 // RISCV64-SAME: {{^}}, veyron-v1
 // RISCV64-SAME: {{^}}, xiangshan-nanhu
 // RISCV64-SAME: {{$}}
@@ -85,6 +86,7 @@
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
+// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
 // TUNE-RISCV64-SAME: {{^}}, generic
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 52456896f2fc6c..6df4c37b092432 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -123,6 +123,7 @@ Changes to the RISC-V Backend
   largely untested.
 * The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
 * Added ``Smctr`` and ``Ssctr`` extensions.
+* ``-mcpu=syntacore-scr7`` was added.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td 
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index d4ec5ecc6489c1..c4e1a1457e8d30 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -383,6 +383,25 @@ def SYNTACORE_SCR5_RV64 : 
RISCVProcessorModel<"syntacore-scr5-rv64",
FeatureStdExtC],
   [TuneNoDefaultUnroll, 
FeaturePostRAScheduler]>;
 
+def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
+  NoSchedModel,
+  [Feature64Bit,
+   FeatureStdExtI,
+   FeatureStdExtZicsr,
+   FeatureStdExtZifencei,
+  

[clang] [llvm] [RISCV] Add Syntacore SCR7 processor definition (PR #108406)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/108406
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Revert "[Clang] Fix name lookup for dependent bases (#114978)" (PR #117727)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc created 
https://github.com/llvm/llvm-project/pull/117727

This reverts commit 486644723038555a224fd09d462bb5099e64809e as requested by 
the commit author.

Buildbots fail:
* https://lab.llvm.org/buildbot/#/builders/164/builds/4945
* https://lab.llvm.org/buildbot/#/builders/52/builds/4021

>From 7501e1cb92371d7082aa4e98ebe990d8f86bafe2 Mon Sep 17 00:00:00 2001
From: Anton Sidorenko 
Date: Tue, 26 Nov 2024 18:30:38 +0300
Subject: [PATCH] Revert "[Clang] Fix name lookup for dependent bases
 (#114978)"

This reverts commit 486644723038555a224fd09d462bb5099e64809e as requested by
the commit author.

Buildbots fail:
* https://lab.llvm.org/buildbot/#/builders/164/builds/4945
* https://lab.llvm.org/buildbot/#/builders/52/builds/4021
---
 clang/docs/ReleaseNotes.rst  |  3 --
 clang/lib/AST/CXXInheritance.cpp | 18 
 clang/test/CXX/drs/cwg5xx.cpp| 48 ++--
 clang/www/cxx_dr_status.html |  2 +-
 4 files changed, 9 insertions(+), 62 deletions(-)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index c4086a5bcbf368..6c40e48e2f49b3 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -279,9 +279,6 @@ Resolutions to C++ Defect Reports
   by default.
   (`CWG2521: User-defined literals and reserved identifiers 
`_).
 
-- Fix name lookup for a dependent base class that is the current 
instantiation.  
-  (`CWG591: When a dependent base class is the current instantiation 
`_).
-
 C Language Changes
 --
 
diff --git a/clang/lib/AST/CXXInheritance.cpp b/clang/lib/AST/CXXInheritance.cpp
index 10b8d524ff8978..aefc06e9197cfb 100644
--- a/clang/lib/AST/CXXInheritance.cpp
+++ b/clang/lib/AST/CXXInheritance.cpp
@@ -134,7 +134,7 @@ bool CXXRecordDecl::forallBases(ForallBasesCallback 
BaseMatches) const {
 return false;
 
   CXXRecordDecl *Base =
-  cast_if_present(Ty->getDecl()->getDefinition());
+cast_or_null(Ty->getDecl()->getDefinition());
   if (!Base ||
   (Base->isDependentContext() &&
!Base->isCurrentInstantiation(Record))) {
@@ -169,21 +169,13 @@ bool CXXBasePaths::lookupInBases(ASTContext &Context,
 QualType BaseType =
 Context.getCanonicalType(BaseSpec.getType()).getUnqualifiedType();
 
-bool isCurrentInstantiation = isa(BaseType);
-if (!isCurrentInstantiation) {
-  if (auto *BaseRecord = cast_if_present(
-  BaseSpec.getType()->getAsRecordDecl()))
-isCurrentInstantiation = BaseRecord->isDependentContext() &&
- BaseRecord->isCurrentInstantiation(Record);
-}
 // C++ [temp.dep]p3:
 //   In the definition of a class template or a member of a class template,
 //   if a base class of the class template depends on a template-parameter,
 //   the base class scope is not examined during unqualified name lookup
 //   either at the point of definition of the class template or member or
 //   during an instantiation of the class tem- plate or member.
-if (!LookupInDependent &&
-(BaseType->isDependentType() && !isCurrentInstantiation))
+if (!LookupInDependent && BaseType->isDependentType())
   continue;
 
 // Determine whether we need to visit this base class at all,
@@ -251,8 +243,9 @@ bool CXXBasePaths::lookupInBases(ASTContext &Context,
 return FoundPath;
   }
 } else if (VisitBase) {
-  CXXRecordDecl *BaseRecord = nullptr;
+  CXXRecordDecl *BaseRecord;
   if (LookupInDependent) {
+BaseRecord = nullptr;
 const TemplateSpecializationType *TST =
 BaseSpec.getType()->getAs();
 if (!TST) {
@@ -271,7 +264,8 @@ bool CXXBasePaths::lookupInBases(ASTContext &Context,
 BaseRecord = nullptr;
 }
   } else {
-BaseRecord = 
cast(BaseSpec.getType()->getAsRecordDecl());
+BaseRecord = cast(
+BaseSpec.getType()->castAs()->getDecl());
   }
   if (BaseRecord &&
   lookupInBases(Context, BaseRecord, BaseMatches, LookupInDependent)) {
diff --git a/clang/test/CXX/drs/cwg5xx.cpp b/clang/test/CXX/drs/cwg5xx.cpp
index 0d53a9d07d76de..ed0c7159dfc889 100644
--- a/clang/test/CXX/drs/cwg5xx.cpp
+++ b/clang/test/CXX/drs/cwg5xx.cpp
@@ -1178,61 +1178,17 @@ namespace cwg590 { // cwg590: yes
   template typename A::B::C A::B::C::f(A::B::C) {}
 }
 
-namespace cwg591 { // cwg591: yes
+namespace cwg591 { // cwg591: no
   template struct A {
 typedef int M;
 struct B {
   typedef void M;
   struct C;
-  struct D;
-};
-  };
-
-  template struct G {
-struct B {
-  typedef int M;
-  struct C {
-typedef void M;
-struct D;
-  };
-};
-  };
-
-  template struct H {
-template struct B {
-  typedef int M;
-  template struct C {
-typedef void M;
-s

[clang] Revert "[Clang] Fix name lookup for dependent bases (#114978)" (PR #117727)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/117727
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang] Fix name lookup for dependent bases (PR #114978)

[Anton Sidorenko via cfe-commits]

asi-sc wrote:

@vbe-sc , reverted as you asked me offline 
https://github.com/llvm/llvm-project/pull/117727 . Feel free to create a new PR 
which includes the original commit and the fix for problem.

https://github.com/llvm/llvm-project/pull/114978
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (PR #114014)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/114014
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Reapply "[clang] Fix name lookup for dependent bases" (PR #118003)

[Anton Sidorenko via cfe-commits]

https://github.com/asi-sc closed 
https://github.com/llvm/llvm-project/pull/118003
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits