================
@@ -378,6 +378,32 @@ def SYNTACORE_SCR4_RV64 :
RISCVProcessorModel<"syntacore-scr4-rv64",
FeatureStdExtC],
[TuneNoDefaultUnroll,
FeaturePostRAScheduler]>;
+def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
----------------
asi-sc wrote:
> The documentation says A and F are both optional
SCR5 is a highly configurable core, but we'd like to support the default
configuration in the compiler which has A, F, D extensions.
> It is weird to me because D always depends on F.
Thanks for noticing, it's a typo. I'll report it.
https://github.com/llvm/llvm-project/pull/102285
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